1 /*******************************************************************************
3 Copyright (c) 2001-2003, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 *******************************************************************************/
34 /*$FreeBSD: src/sys/dev/em/if_em_hw.c,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/
35 /*$DragonFly: src/sys/dev/netif/em/if_em_hw.c,v 1.2 2003/06/17 04:28:25 dillon Exp $*/
37 * Shared functions for accessing and configuring the MAC
40 #include <dev/em/if_em_hw.h>
42 static int32_t em_set_phy_type(struct em_hw *hw);
43 static void em_phy_init_script(struct em_hw *hw);
44 static int32_t em_setup_fiber_link(struct em_hw *hw);
45 static int32_t em_setup_copper_link(struct em_hw *hw);
46 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
47 static int32_t em_config_mac_to_phy(struct em_hw *hw);
48 static int32_t em_force_mac_fc(struct em_hw *hw);
49 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
50 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
51 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count);
52 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
53 static int32_t em_phy_reset_dsp(struct em_hw *hw);
54 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
55 uint16_t words, uint16_t *data);
56 static int32_t em_write_eeprom_microwire(struct em_hw *hw,
57 uint16_t offset, uint16_t words,
59 static int32_t em_spi_eeprom_ready(struct em_hw *hw);
60 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
61 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
62 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count);
63 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
64 static int32_t em_acquire_eeprom(struct em_hw *hw);
65 static void em_release_eeprom(struct em_hw *hw);
66 static void em_standby_eeprom(struct em_hw *hw);
67 static int32_t em_id_led_init(struct em_hw * hw);
71 /******************************************************************************
72 * Set the phy type member in the hw struct.
74 * hw - Struct containing variables accessed by shared code
75 *****************************************************************************/
77 em_set_phy_type(struct em_hw *hw)
79 DEBUGFUNC("em_set_phy_type");
82 case M88E1000_E_PHY_ID:
83 case M88E1000_I_PHY_ID:
84 case M88E1011_I_PHY_ID:
85 hw->phy_type = em_phy_m88;
87 case IGP01E1000_I_PHY_ID:
88 hw->phy_type = em_phy_igp;
91 /* Should never have loaded on this device */
92 hw->phy_type = em_phy_undefined;
93 return -E1000_ERR_PHY_TYPE;
99 /******************************************************************************
100 * IGP phy init script - initializes the GbE PHY
102 * hw - Struct containing variables accessed by shared code
103 *****************************************************************************/
105 em_phy_init_script(struct em_hw *hw)
107 DEBUGFUNC("em_phy_init_script");
109 if(hw->phy_init_script) {
112 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000);
113 em_write_phy_reg(hw,0x0000,0x0140);
116 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F95);
117 em_write_phy_reg(hw,0x0015,0x0001);
119 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F71);
120 em_write_phy_reg(hw,0x0011,0xBD21);
122 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F79);
123 em_write_phy_reg(hw,0x0019,0x0018);
125 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F30);
126 em_write_phy_reg(hw,0x0010,0x1600);
128 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F31);
129 em_write_phy_reg(hw,0x0011,0x0014);
131 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F32);
132 em_write_phy_reg(hw,0x0012,0x161C);
134 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F94);
135 em_write_phy_reg(hw,0x0014,0x0003);
137 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F96);
138 em_write_phy_reg(hw,0x0016,0x003F);
140 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x2010);
141 em_write_phy_reg(hw,0x0010,0x0008);
143 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000);
144 em_write_phy_reg(hw,0x0000,0x3300);
148 /******************************************************************************
149 * Set the mac type member in the hw struct.
151 * hw - Struct containing variables accessed by shared code
152 *****************************************************************************/
154 em_set_mac_type(struct em_hw *hw)
156 DEBUGFUNC("em_set_mac_type");
158 switch (hw->device_id) {
159 case E1000_DEV_ID_82542:
160 switch (hw->revision_id) {
161 case E1000_82542_2_0_REV_ID:
162 hw->mac_type = em_82542_rev2_0;
164 case E1000_82542_2_1_REV_ID:
165 hw->mac_type = em_82542_rev2_1;
168 /* Invalid 82542 revision ID */
169 return -E1000_ERR_MAC_TYPE;
172 case E1000_DEV_ID_82543GC_FIBER:
173 case E1000_DEV_ID_82543GC_COPPER:
174 hw->mac_type = em_82543;
176 case E1000_DEV_ID_82544EI_COPPER:
177 case E1000_DEV_ID_82544EI_FIBER:
178 case E1000_DEV_ID_82544GC_COPPER:
179 case E1000_DEV_ID_82544GC_LOM:
180 hw->mac_type = em_82544;
182 case E1000_DEV_ID_82540EM:
183 case E1000_DEV_ID_82540EM_LOM:
184 case E1000_DEV_ID_82540EP:
185 case E1000_DEV_ID_82540EP_LOM:
186 case E1000_DEV_ID_82540EP_LP:
187 hw->mac_type = em_82540;
189 case E1000_DEV_ID_82545EM_COPPER:
190 case E1000_DEV_ID_82545EM_FIBER:
191 hw->mac_type = em_82545;
193 case E1000_DEV_ID_82546EB_COPPER:
194 case E1000_DEV_ID_82546EB_FIBER:
195 case E1000_DEV_ID_82546EB_QUAD_COPPER:
196 hw->mac_type = em_82546;
198 case E1000_DEV_ID_82541EI:
199 case E1000_DEV_ID_82541EP:
200 hw->mac_type = em_82541;
202 case E1000_DEV_ID_82547EI:
203 hw->mac_type = em_82547;
206 /* Should never have loaded on this device */
207 return -E1000_ERR_MAC_TYPE;
211 return E1000_SUCCESS;
213 /******************************************************************************
214 * Reset the transmit and receive units; mask and clear all interrupts.
216 * hw - Struct containing variables accessed by shared code
217 *****************************************************************************/
219 em_reset_hw(struct em_hw *hw)
227 DEBUGFUNC("em_reset_hw");
229 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
230 if(hw->mac_type == em_82542_rev2_0) {
231 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
232 em_pci_clear_mwi(hw);
235 /* Clear interrupt mask to stop board from generating interrupts */
236 DEBUGOUT("Masking off all interrupts\n");
237 E1000_WRITE_REG(hw, IMC, 0xffffffff);
239 /* Disable the Transmit and Receive units. Then delay to allow
240 * any pending transactions to complete before we hit the MAC with
243 E1000_WRITE_REG(hw, RCTL, 0);
244 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
245 E1000_WRITE_FLUSH(hw);
247 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
248 hw->tbi_compatibility_on = FALSE;
250 /* Delay to allow any outstanding PCI transactions to complete before
251 * resetting the device
255 /* Issue a global reset to the MAC. This will reset the chip's
256 * transmit, receive, DMA, and link units. It will not effect
257 * the current PCI configuration. The global reset bit is self-
258 * clearing, and should clear within a microsecond.
260 DEBUGOUT("Issuing a global reset to MAC\n");
261 ctrl = E1000_READ_REG(hw, CTRL);
263 /* Must reset the PHY before resetting the MAC */
264 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
265 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
269 switch(hw->mac_type) {
275 /* These controllers can't ack the 64-bit write when issuing the
276 * reset, so use IO-mapping as a workaround to issue the reset */
277 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
280 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
284 /* Force a reload from the EEPROM if necessary */
285 if(hw->mac_type < em_82540) {
286 /* Wait for reset to complete */
288 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
289 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
290 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
291 E1000_WRITE_FLUSH(hw);
292 /* Wait for EEPROM reload */
295 /* Wait for EEPROM reload (it happens automatically) */
297 /* Dissable HW ARPs on ASF enabled adapters */
298 manc = E1000_READ_REG(hw, MANC);
299 manc &= ~(E1000_MANC_ARP_EN);
300 E1000_WRITE_REG(hw, MANC, manc);
303 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
304 em_phy_init_script(hw);
306 /* Configure activity LED after PHY reset */
307 led_ctrl = E1000_READ_REG(hw, LEDCTL);
308 led_ctrl &= IGP_ACTIVITY_LED_MASK;
309 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
310 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
313 /* Clear interrupt mask to stop board from generating interrupts */
314 DEBUGOUT("Masking off all interrupts\n");
315 E1000_WRITE_REG(hw, IMC, 0xffffffff);
317 /* Clear any pending interrupt events. */
318 icr = E1000_READ_REG(hw, ICR);
320 /* If MWI was previously enabled, reenable it. */
321 if(hw->mac_type == em_82542_rev2_0) {
322 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
327 /******************************************************************************
328 * Performs basic configuration of the adapter.
330 * hw - Struct containing variables accessed by shared code
332 * Assumes that the controller has previously been reset and is in a
333 * post-reset uninitialized state. Initializes the receive address registers,
334 * multicast table, and VLAN filter table. Calls routines to setup link
335 * configuration and flow control settings. Clears all on-chip counters. Leaves
336 * the transmit and receive units disabled and uninitialized.
337 *****************************************************************************/
339 em_init_hw(struct em_hw *hw)
341 uint32_t ctrl, status;
344 uint16_t pcix_cmd_word;
345 uint16_t pcix_stat_hi_word;
349 DEBUGFUNC("em_init_hw");
351 /* Initialize Identification LED */
352 ret_val = em_id_led_init(hw);
354 DEBUGOUT("Error Initializing Identification LED\n");
358 /* Set the Media Type and exit with error if it is not valid. */
359 if(hw->mac_type != em_82543) {
360 /* tbi_compatibility is only valid on 82543 */
361 hw->tbi_compatibility_en = FALSE;
364 if(hw->mac_type >= em_82543) {
365 status = E1000_READ_REG(hw, STATUS);
366 if(status & E1000_STATUS_TBIMODE) {
367 hw->media_type = em_media_type_fiber;
368 /* tbi_compatibility not valid on fiber */
369 hw->tbi_compatibility_en = FALSE;
371 hw->media_type = em_media_type_copper;
374 /* This is an 82542 (fiber only) */
375 hw->media_type = em_media_type_fiber;
378 /* Disabling VLAN filtering. */
379 DEBUGOUT("Initializing the IEEE VLAN\n");
380 E1000_WRITE_REG(hw, VET, 0);
384 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
385 if(hw->mac_type == em_82542_rev2_0) {
386 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
387 em_pci_clear_mwi(hw);
388 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
389 E1000_WRITE_FLUSH(hw);
393 /* Setup the receive address. This involves initializing all of the Receive
394 * Address Registers (RARs 0 - 15).
396 em_init_rx_addrs(hw);
398 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
399 if(hw->mac_type == em_82542_rev2_0) {
400 E1000_WRITE_REG(hw, RCTL, 0);
401 E1000_WRITE_FLUSH(hw);
403 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
407 /* Zero out the Multicast HASH table */
408 DEBUGOUT("Zeroing the MTA\n");
409 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
410 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
412 /* Set the PCI priority bit correctly in the CTRL register. This
413 * determines if the adapter gives priority to receives, or if it
414 * gives equal priority to transmits and receives.
416 if(hw->dma_fairness) {
417 ctrl = E1000_READ_REG(hw, CTRL);
418 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
421 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
422 if(hw->bus_type == em_bus_type_pcix) {
423 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
424 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
425 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
426 PCIX_COMMAND_MMRBC_SHIFT;
427 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
428 PCIX_STATUS_HI_MMRBC_SHIFT;
429 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
430 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
431 if(cmd_mmrbc > stat_mmrbc) {
432 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
433 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
434 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
438 /* Call a subroutine to configure the link and setup flow control. */
439 ret_val = em_setup_link(hw);
441 /* Set the transmit descriptor write-back policy */
442 if(hw->mac_type > em_82544) {
443 ctrl = E1000_READ_REG(hw, TXDCTL);
444 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
445 E1000_WRITE_REG(hw, TXDCTL, ctrl);
448 /* Clear all of the statistics registers (clear on read). It is
449 * important that we do this after we have tried to establish link
450 * because the symbol error count will increment wildly if there
453 em_clear_hw_cntrs(hw);
458 /******************************************************************************
459 * Configures flow control and link settings.
461 * hw - Struct containing variables accessed by shared code
463 * Determines which flow control settings to use. Calls the apropriate media-
464 * specific link configuration function. Configures the flow control settings.
465 * Assuming the adapter has a valid link partner, a valid link should be
466 * established. Assumes the hardware has previously been reset and the
467 * transmitter and receiver are not enabled.
468 *****************************************************************************/
470 em_setup_link(struct em_hw *hw)
474 uint16_t eeprom_data;
476 DEBUGFUNC("em_setup_link");
478 /* Read and store word 0x0F of the EEPROM. This word contains bits
479 * that determine the hardware's default PAUSE (flow control) mode,
480 * a bit that determines whether the HW defaults to enabling or
481 * disabling auto-negotiation, and the direction of the
482 * SW defined pins. If there is no SW over-ride of the flow
483 * control setting, then the variable hw->fc will
484 * be initialized based on a value in the EEPROM.
486 if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
487 DEBUGOUT("EEPROM Read Error\n");
488 return -E1000_ERR_EEPROM;
491 if(hw->fc == em_fc_default) {
492 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
494 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
495 EEPROM_WORD0F_ASM_DIR)
496 hw->fc = em_fc_tx_pause;
501 /* We want to save off the original Flow Control configuration just
502 * in case we get disconnected and then reconnected into a different
503 * hub or switch with different Flow Control capabilities.
505 if(hw->mac_type == em_82542_rev2_0)
506 hw->fc &= (~em_fc_tx_pause);
508 if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
509 hw->fc &= (~em_fc_rx_pause);
511 hw->original_fc = hw->fc;
513 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
515 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
516 * polarity value for the SW controlled pins, and setup the
517 * Extended Device Control reg with that info.
518 * This is needed because one of the SW controlled pins is used for
519 * signal detection. So this should be done before em_setup_pcs_link()
520 * or em_phy_setup() is called.
522 if(hw->mac_type == em_82543) {
523 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
525 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
528 /* Call the necessary subroutine to configure the link. */
529 ret_val = (hw->media_type == em_media_type_fiber) ?
530 em_setup_fiber_link(hw) :
531 em_setup_copper_link(hw);
533 /* Initialize the flow control address, type, and PAUSE timer
534 * registers to their default values. This is done even if flow
535 * control is disabled, because it does not hurt anything to
536 * initialize these registers.
538 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
540 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
541 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
542 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
543 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
545 /* Set the flow control receive threshold registers. Normally,
546 * these registers will be set to a default threshold that may be
547 * adjusted later by the driver's runtime code. However, if the
548 * ability to transmit pause frames in not enabled, then these
549 * registers will be set to 0.
551 if(!(hw->fc & em_fc_tx_pause)) {
552 E1000_WRITE_REG(hw, FCRTL, 0);
553 E1000_WRITE_REG(hw, FCRTH, 0);
555 /* We need to set up the Receive Threshold high and low water marks
556 * as well as (optionally) enabling the transmission of XON frames.
558 if(hw->fc_send_xon) {
559 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
560 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
562 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
563 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
569 /******************************************************************************
570 * Sets up link for a fiber based adapter
572 * hw - Struct containing variables accessed by shared code
574 * Manipulates Physical Coding Sublayer functions in order to configure
575 * link. Assumes the hardware has been previously reset and the transmitter
576 * and receiver are not enabled.
577 *****************************************************************************/
579 em_setup_fiber_link(struct em_hw *hw)
588 DEBUGFUNC("em_setup_fiber_link");
590 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
591 * set when the optics detect a signal. On older adapters, it will be
592 * cleared when there is a signal
594 ctrl = E1000_READ_REG(hw, CTRL);
595 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
598 /* Take the link out of reset */
599 ctrl &= ~(E1000_CTRL_LRST);
601 em_config_collision_dist(hw);
603 /* Check for a software override of the flow control settings, and setup
604 * the device accordingly. If auto-negotiation is enabled, then software
605 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
606 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
607 * auto-negotiation is disabled, then software will have to manually
608 * configure the two flow control enable bits in the CTRL register.
610 * The possible values of the "fc" parameter are:
611 * 0: Flow control is completely disabled
612 * 1: Rx flow control is enabled (we can receive pause frames, but
613 * not send pause frames).
614 * 2: Tx flow control is enabled (we can send pause frames but we do
615 * not support receiving pause frames).
616 * 3: Both Rx and TX flow control (symmetric) are enabled.
620 /* Flow control is completely disabled by a software over-ride. */
621 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
624 /* RX Flow control is enabled and TX Flow control is disabled by a
625 * software over-ride. Since there really isn't a way to advertise
626 * that we are capable of RX Pause ONLY, we will advertise that we
627 * support both symmetric and asymmetric RX PAUSE. Later, we will
628 * disable the adapter's ability to send PAUSE frames.
630 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
633 /* TX Flow control is enabled, and RX Flow control is disabled, by a
634 * software over-ride.
636 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
639 /* Flow control (both RX and TX) is enabled by a software over-ride. */
640 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
643 DEBUGOUT("Flow control param set incorrectly\n");
644 return -E1000_ERR_CONFIG;
648 /* Since auto-negotiation is enabled, take the link out of reset (the link
649 * will be in reset, because we previously reset the chip). This will
650 * restart auto-negotiation. If auto-neogtiation is successful then the
651 * link-up status bit will be set and the flow control enable bits (RFCE
652 * and TFCE) will be set according to their negotiated value.
654 DEBUGOUT("Auto-negotiation enabled\n");
656 E1000_WRITE_REG(hw, TXCW, txcw);
657 E1000_WRITE_REG(hw, CTRL, ctrl);
658 E1000_WRITE_FLUSH(hw);
663 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
664 * indication in the Device Status Register. Time-out if a link isn't
665 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
666 * less than 500 milliseconds even if the other end is doing it in SW).
668 if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
669 DEBUGOUT("Looking for Link\n");
670 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
672 status = E1000_READ_REG(hw, STATUS);
673 if(status & E1000_STATUS_LU) break;
675 if(i == (LINK_UP_TIMEOUT / 10)) {
676 /* AutoNeg failed to achieve a link, so we'll call
677 * em_check_for_link. This routine will force the link up if we
678 * detect a signal. This will allow us to communicate with
679 * non-autonegotiating link partners.
681 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
682 hw->autoneg_failed = 1;
683 ret_val = em_check_for_link(hw);
685 DEBUGOUT("Error while checking for link\n");
688 hw->autoneg_failed = 0;
690 hw->autoneg_failed = 0;
691 DEBUGOUT("Valid Link Found\n");
694 DEBUGOUT("No Signal Detected\n");
699 /******************************************************************************
700 * Detects which PHY is present and the speed and duplex
702 * hw - Struct containing variables accessed by shared code
703 ******************************************************************************/
705 em_setup_copper_link(struct em_hw *hw)
713 DEBUGFUNC("em_setup_copper_link");
715 ctrl = E1000_READ_REG(hw, CTRL);
716 /* With 82543, we need to force speed and duplex on the MAC equal to what
717 * the PHY speed and duplex configuration is. In addition, we need to
718 * perform a hardware reset on the PHY to take it out of reset.
720 if(hw->mac_type > em_82543) {
721 ctrl |= E1000_CTRL_SLU;
722 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
723 E1000_WRITE_REG(hw, CTRL, ctrl);
725 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
726 E1000_WRITE_REG(hw, CTRL, ctrl);
730 /* Make sure we have a valid PHY */
731 ret_val = em_detect_gig_phy(hw);
733 DEBUGOUT("Error, did not detect valid phy.\n");
736 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
738 if (hw->phy_type == em_phy_igp) {
740 ret_val = em_phy_reset(hw);
742 DEBUGOUT("Error Resetting the PHY\n");
746 /* Wait 10ms for MAC to configure PHY from eeprom settings */
749 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) {
750 DEBUGOUT("PHY Write Error\n");
751 return -E1000_ERR_PHY;
754 /* Configure activity LED after PHY reset */
755 led_ctrl = E1000_READ_REG(hw, LEDCTL);
756 led_ctrl &= IGP_ACTIVITY_LED_MASK;
757 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
758 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
760 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
761 /* Disable SmartSpeed */
762 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
764 DEBUGOUT("PHY Read Error\n");
765 return -E1000_ERR_PHY;
767 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
768 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
770 DEBUGOUT("PHY Write Error\n");
771 return -E1000_ERR_PHY;
773 /* Set auto Master/Slave resolution process */
774 if(em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data) < 0) {
775 DEBUGOUT("PHY Read Error\n");
776 return -E1000_ERR_PHY;
778 phy_data &= ~CR_1000T_MS_ENABLE;
779 if(em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data) < 0) {
780 DEBUGOUT("PHY Write Error\n");
781 return -E1000_ERR_PHY;
785 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) {
786 DEBUGOUT("PHY Read Error\n");
787 return -E1000_ERR_PHY;
790 /* Force MDI for IGP PHY */
791 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
792 IGP01E1000_PSCR_FORCE_MDI_MDIX);
796 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) {
797 DEBUGOUT("PHY Write Error\n");
798 return -E1000_ERR_PHY;
802 /* Enable CRS on TX. This must be set for half-duplex operation. */
803 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
804 DEBUGOUT("PHY Read Error\n");
805 return -E1000_ERR_PHY;
807 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
810 * MDI/MDI-X = 0 (default)
811 * 0 - Auto for all speeds
814 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
816 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
820 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
823 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
826 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
830 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
835 * disable_polarity_correction = 0 (default)
836 * Automatic Correction for Reversed Cable Polarity
840 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
841 if(hw->disable_polarity_correction == 1)
842 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
843 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
844 DEBUGOUT("PHY Write Error\n");
845 return -E1000_ERR_PHY;
848 /* Force TX_CLK in the Extended PHY Specific Control Register
851 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
852 DEBUGOUT("PHY Read Error\n");
853 return -E1000_ERR_PHY;
855 phy_data |= M88E1000_EPSCR_TX_CLK_25;
857 if (hw->phy_revision < M88E1011_I_REV_4) {
858 /* Configure Master and Slave downshift values */
859 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
860 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
861 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
862 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
863 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
865 DEBUGOUT("PHY Write Error\n");
866 return -E1000_ERR_PHY;
870 /* SW Reset the PHY so all changes take effect */
871 ret_val = em_phy_reset(hw);
873 DEBUGOUT("Error Resetting the PHY\n");
879 * autoneg = 1 (default)
880 * PHY will advertise value(s) parsed from
881 * autoneg_advertised and fc
883 * PHY will be set to 10H, 10F, 100H, or 100F
884 * depending on value parsed from forced_speed_duplex.
887 /* Is autoneg enabled? This is enabled by default or by software override.
888 * If so, call em_phy_setup_autoneg routine to parse the
889 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
890 * user should have provided a speed/duplex override. If so, then call
891 * em_phy_force_speed_duplex to parse and set this up.
894 /* Perform some bounds checking on the hw->autoneg_advertised
895 * parameter. If this variable is zero, then set it to the default.
897 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
899 /* If autoneg_advertised is zero, we assume it was not defaulted
900 * by the calling code so we set to advertise full capability.
902 if(hw->autoneg_advertised == 0)
903 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
905 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
906 ret_val = em_phy_setup_autoneg(hw);
908 DEBUGOUT("Error Setting up Auto-Negotiation\n");
911 DEBUGOUT("Restarting Auto-Neg\n");
913 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
914 * the Auto Neg Restart bit in the PHY control register.
916 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
917 DEBUGOUT("PHY Read Error\n");
918 return -E1000_ERR_PHY;
920 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
921 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
922 DEBUGOUT("PHY Write Error\n");
923 return -E1000_ERR_PHY;
926 /* Does the user want to wait for Auto-Neg to complete here, or
927 * check at a later time (for example, callback routine).
929 if(hw->wait_autoneg_complete) {
930 ret_val = em_wait_autoneg(hw);
932 DEBUGOUT("Error while waiting for autoneg to complete\n");
936 hw->get_link_status = TRUE;
938 DEBUGOUT("Forcing speed and duplex\n");
939 ret_val = em_phy_force_speed_duplex(hw);
941 DEBUGOUT("Error Forcing Speed and Duplex\n");
946 /* Check link status. Wait up to 100 microseconds for link to become
949 for(i = 0; i < 10; i++) {
950 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
951 DEBUGOUT("PHY Read Error\n");
952 return -E1000_ERR_PHY;
954 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
955 DEBUGOUT("PHY Read Error\n");
956 return -E1000_ERR_PHY;
958 if(phy_data & MII_SR_LINK_STATUS) {
959 /* We have link, so we need to finish the config process:
960 * 1) Set up the MAC to the current PHY speed/duplex
961 * if we are on 82543. If we
962 * are on newer silicon, we only need to configure
963 * collision distance in the Transmit Control Register.
964 * 2) Set up flow control on the MAC to that established with
967 if(hw->mac_type >= em_82544) {
968 em_config_collision_dist(hw);
970 ret_val = em_config_mac_to_phy(hw);
972 DEBUGOUT("Error configuring MAC to PHY settings\n");
976 ret_val = em_config_fc_after_link_up(hw);
978 DEBUGOUT("Error Configuring Flow Control\n");
981 DEBUGOUT("Valid link established!!!\n");
987 DEBUGOUT("Unable to establish link!!!\n");
991 /******************************************************************************
992 * Configures PHY autoneg and flow control advertisement settings
994 * hw - Struct containing variables accessed by shared code
995 ******************************************************************************/
997 em_phy_setup_autoneg(struct em_hw *hw)
999 uint16_t mii_autoneg_adv_reg;
1000 uint16_t mii_1000t_ctrl_reg;
1002 DEBUGFUNC("em_phy_setup_autoneg");
1004 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1005 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
1006 DEBUGOUT("PHY Read Error\n");
1007 return -E1000_ERR_PHY;
1010 /* Read the MII 1000Base-T Control Register (Address 9). */
1011 if(em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
1012 DEBUGOUT("PHY Read Error\n");
1013 return -E1000_ERR_PHY;
1016 /* Need to parse both autoneg_advertised and fc and set up
1017 * the appropriate PHY registers. First we will parse for
1018 * autoneg_advertised software override. Since we can advertise
1019 * a plethora of combinations, we need to check each bit
1023 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1024 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1025 * the 1000Base-T Control Register (Address 9).
1027 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1028 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1030 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1032 /* Do we want to advertise 10 Mb Half Duplex? */
1033 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1034 DEBUGOUT("Advertise 10mb Half duplex\n");
1035 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1038 /* Do we want to advertise 10 Mb Full Duplex? */
1039 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1040 DEBUGOUT("Advertise 10mb Full duplex\n");
1041 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1044 /* Do we want to advertise 100 Mb Half Duplex? */
1045 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1046 DEBUGOUT("Advertise 100mb Half duplex\n");
1047 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1050 /* Do we want to advertise 100 Mb Full Duplex? */
1051 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1052 DEBUGOUT("Advertise 100mb Full duplex\n");
1053 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1056 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1057 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1058 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1061 /* Do we want to advertise 1000 Mb Full Duplex? */
1062 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1063 DEBUGOUT("Advertise 1000mb Full duplex\n");
1064 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1067 /* Check for a software override of the flow control settings, and
1068 * setup the PHY advertisement registers accordingly. If
1069 * auto-negotiation is enabled, then software will have to set the
1070 * "PAUSE" bits to the correct value in the Auto-Negotiation
1071 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1073 * The possible values of the "fc" parameter are:
1074 * 0: Flow control is completely disabled
1075 * 1: Rx flow control is enabled (we can receive pause frames
1076 * but not send pause frames).
1077 * 2: Tx flow control is enabled (we can send pause frames
1078 * but we do not support receiving pause frames).
1079 * 3: Both Rx and TX flow control (symmetric) are enabled.
1080 * other: No software override. The flow control configuration
1081 * in the EEPROM is used.
1084 case em_fc_none: /* 0 */
1085 /* Flow control (RX & TX) is completely disabled by a
1086 * software over-ride.
1088 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1090 case em_fc_rx_pause: /* 1 */
1091 /* RX Flow control is enabled, and TX Flow control is
1092 * disabled, by a software over-ride.
1094 /* Since there really isn't a way to advertise that we are
1095 * capable of RX Pause ONLY, we will advertise that we
1096 * support both symmetric and asymmetric RX PAUSE. Later
1097 * (in em_config_fc_after_link_up) we will disable the
1098 *hw's ability to send PAUSE frames.
1100 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1102 case em_fc_tx_pause: /* 2 */
1103 /* TX Flow control is enabled, and RX Flow control is
1104 * disabled, by a software over-ride.
1106 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1107 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1109 case em_fc_full: /* 3 */
1110 /* Flow control (both RX and TX) is enabled by a software
1113 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1116 DEBUGOUT("Flow control param set incorrectly\n");
1117 return -E1000_ERR_CONFIG;
1120 if(em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
1121 DEBUGOUT("PHY Write Error\n");
1122 return -E1000_ERR_PHY;
1125 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1127 if(em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
1128 DEBUGOUT("PHY Write Error\n");
1129 return -E1000_ERR_PHY;
1134 /******************************************************************************
1135 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1137 * hw - Struct containing variables accessed by shared code
1138 ******************************************************************************/
1140 em_phy_force_speed_duplex(struct em_hw *hw)
1144 uint16_t mii_ctrl_reg;
1145 uint16_t mii_status_reg;
1149 DEBUGFUNC("em_phy_force_speed_duplex");
1151 /* Turn off Flow control if we are forcing speed and duplex. */
1152 hw->fc = em_fc_none;
1154 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1156 /* Read the Device Control Register. */
1157 ctrl = E1000_READ_REG(hw, CTRL);
1159 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1160 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1161 ctrl &= ~(DEVICE_SPEED_MASK);
1163 /* Clear the Auto Speed Detect Enable bit. */
1164 ctrl &= ~E1000_CTRL_ASDE;
1166 /* Read the MII Control Register. */
1167 if(em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
1168 DEBUGOUT("PHY Read Error\n");
1169 return -E1000_ERR_PHY;
1172 /* We need to disable autoneg in order to force link and duplex. */
1174 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1176 /* Are we forcing Full or Half Duplex? */
1177 if(hw->forced_speed_duplex == em_100_full ||
1178 hw->forced_speed_duplex == em_10_full) {
1179 /* We want to force full duplex so we SET the full duplex bits in the
1180 * Device and MII Control Registers.
1182 ctrl |= E1000_CTRL_FD;
1183 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1184 DEBUGOUT("Full Duplex\n");
1186 /* We want to force half duplex so we CLEAR the full duplex bits in
1187 * the Device and MII Control Registers.
1189 ctrl &= ~E1000_CTRL_FD;
1190 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1191 DEBUGOUT("Half Duplex\n");
1194 /* Are we forcing 100Mbps??? */
1195 if(hw->forced_speed_duplex == em_100_full ||
1196 hw->forced_speed_duplex == em_100_half) {
1197 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1198 ctrl |= E1000_CTRL_SPD_100;
1199 mii_ctrl_reg |= MII_CR_SPEED_100;
1200 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1201 DEBUGOUT("Forcing 100mb ");
1203 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1204 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1205 mii_ctrl_reg |= MII_CR_SPEED_10;
1206 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1207 DEBUGOUT("Forcing 10mb ");
1210 em_config_collision_dist(hw);
1212 /* Write the configured values back to the Device Control Reg. */
1213 E1000_WRITE_REG(hw, CTRL, ctrl);
1215 if (hw->phy_type == em_phy_m88) {
1216 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
1217 DEBUGOUT("PHY Read Error\n");
1218 return -E1000_ERR_PHY;
1221 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1222 * forced whenever speed are duplex are forced.
1224 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1225 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
1226 DEBUGOUT("PHY Write Error\n");
1227 return -E1000_ERR_PHY;
1229 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1231 /* Need to reset the PHY or these changes will be ignored */
1232 mii_ctrl_reg |= MII_CR_RESET;
1234 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1235 * forced whenever speed or duplex are forced.
1237 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) {
1238 DEBUGOUT("PHY Read Error\n");
1239 return -E1000_ERR_PHY;
1242 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1243 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1245 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) {
1246 DEBUGOUT("PHY Write Error\n");
1247 return -E1000_ERR_PHY;
1251 /* Write back the modified PHY MII control register. */
1252 if(em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
1253 DEBUGOUT("PHY Write Error\n");
1254 return -E1000_ERR_PHY;
1258 /* The wait_autoneg_complete flag may be a little misleading here.
1259 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1260 * But we do want to delay for a period while forcing only so we
1261 * don't generate false No Link messages. So we will wait here
1262 * only if the user has set wait_autoneg_complete to 1, which is
1265 if(hw->wait_autoneg_complete) {
1266 /* We will wait for autoneg to complete. */
1267 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1270 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1271 for(i = PHY_FORCE_TIME; i > 0; i--) {
1272 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1275 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1276 DEBUGOUT("PHY Read Error\n");
1277 return -E1000_ERR_PHY;
1279 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1280 DEBUGOUT("PHY Read Error\n");
1281 return -E1000_ERR_PHY;
1283 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1286 if(i == 0) { /* We didn't get link */
1287 /* Reset the DSP and wait again for link. */
1289 ret_val = em_phy_reset_dsp(hw);
1291 DEBUGOUT("Error Resetting PHY DSP\n");
1295 /* This loop will early-out if the link condition has been met. */
1296 for(i = PHY_FORCE_TIME; i > 0; i--) {
1297 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1299 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1302 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1303 DEBUGOUT("PHY Read Error\n");
1304 return -E1000_ERR_PHY;
1306 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1307 DEBUGOUT("PHY Read Error\n");
1308 return -E1000_ERR_PHY;
1313 if (hw->phy_type == em_phy_m88) {
1314 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1315 * Extended PHY Specific Control Register to 25MHz clock. This value
1316 * defaults back to a 2.5MHz clock when the PHY is reset.
1318 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
1319 DEBUGOUT("PHY Read Error\n");
1320 return -E1000_ERR_PHY;
1322 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1323 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
1324 DEBUGOUT("PHY Write Error\n");
1325 return -E1000_ERR_PHY;
1328 /* In addition, because of the s/w reset above, we need to enable CRS on
1329 * TX. This must be set for both full and half duplex operation.
1331 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
1332 DEBUGOUT("PHY Read Error\n");
1333 return -E1000_ERR_PHY;
1335 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1336 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
1337 DEBUGOUT("PHY Write Error\n");
1338 return -E1000_ERR_PHY;
1344 /******************************************************************************
1345 * Sets the collision distance in the Transmit Control register
1347 * hw - Struct containing variables accessed by shared code
1349 * Link should have been established previously. Reads the speed and duplex
1350 * information from the Device Status register.
1351 ******************************************************************************/
1353 em_config_collision_dist(struct em_hw *hw)
1357 DEBUGFUNC("em_config_collision_dist");
1359 tctl = E1000_READ_REG(hw, TCTL);
1361 tctl &= ~E1000_TCTL_COLD;
1362 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1364 E1000_WRITE_REG(hw, TCTL, tctl);
1365 E1000_WRITE_FLUSH(hw);
1368 /******************************************************************************
1369 * Sets MAC speed and duplex settings to reflect the those in the PHY
1371 * hw - Struct containing variables accessed by shared code
1372 * mii_reg - data to write to the MII control register
1374 * The contents of the PHY register containing the needed information need to
1376 ******************************************************************************/
1378 em_config_mac_to_phy(struct em_hw *hw)
1383 DEBUGFUNC("em_config_mac_to_phy");
1385 /* Read the Device Control Register and set the bits to Force Speed
1388 ctrl = E1000_READ_REG(hw, CTRL);
1389 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1390 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1392 /* Set up duplex in the Device Control and Transmit Control
1393 * registers depending on negotiated values.
1395 if (hw->phy_type == em_phy_igp) {
1396 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0) {
1397 DEBUGOUT("PHY Read Error\n");
1398 return -E1000_ERR_PHY;
1400 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1401 else ctrl &= ~E1000_CTRL_FD;
1403 em_config_collision_dist(hw);
1405 /* Set up speed in the Device Control register depending on
1406 * negotiated values.
1408 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1409 IGP01E1000_PSSR_SPEED_1000MBPS)
1410 ctrl |= E1000_CTRL_SPD_1000;
1411 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1412 IGP01E1000_PSSR_SPEED_100MBPS)
1413 ctrl |= E1000_CTRL_SPD_100;
1415 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
1416 DEBUGOUT("PHY Read Error\n");
1417 return -E1000_ERR_PHY;
1419 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1420 else ctrl &= ~E1000_CTRL_FD;
1422 em_config_collision_dist(hw);
1424 /* Set up speed in the Device Control register depending on
1425 * negotiated values.
1427 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1428 ctrl |= E1000_CTRL_SPD_1000;
1429 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1430 ctrl |= E1000_CTRL_SPD_100;
1432 /* Write the configured values back to the Device Control Reg. */
1433 E1000_WRITE_REG(hw, CTRL, ctrl);
1437 /******************************************************************************
1438 * Forces the MAC's flow control settings.
1440 * hw - Struct containing variables accessed by shared code
1442 * Sets the TFCE and RFCE bits in the device control register to reflect
1443 * the adapter settings. TFCE and RFCE need to be explicitly set by
1444 * software when a Copper PHY is used because autonegotiation is managed
1445 * by the PHY rather than the MAC. Software must also configure these
1446 * bits when link is forced on a fiber connection.
1447 *****************************************************************************/
1449 em_force_mac_fc(struct em_hw *hw)
1453 DEBUGFUNC("em_force_mac_fc");
1455 /* Get the current configuration of the Device Control Register */
1456 ctrl = E1000_READ_REG(hw, CTRL);
1458 /* Because we didn't get link via the internal auto-negotiation
1459 * mechanism (we either forced link or we got link via PHY
1460 * auto-neg), we have to manually enable/disable transmit an
1461 * receive flow control.
1463 * The "Case" statement below enables/disable flow control
1464 * according to the "hw->fc" parameter.
1466 * The possible values of the "fc" parameter are:
1467 * 0: Flow control is completely disabled
1468 * 1: Rx flow control is enabled (we can receive pause
1469 * frames but not send pause frames).
1470 * 2: Tx flow control is enabled (we can send pause frames
1471 * frames but we do not receive pause frames).
1472 * 3: Both Rx and TX flow control (symmetric) is enabled.
1473 * other: No other values should be possible at this point.
1478 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1480 case em_fc_rx_pause:
1481 ctrl &= (~E1000_CTRL_TFCE);
1482 ctrl |= E1000_CTRL_RFCE;
1484 case em_fc_tx_pause:
1485 ctrl &= (~E1000_CTRL_RFCE);
1486 ctrl |= E1000_CTRL_TFCE;
1489 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1492 DEBUGOUT("Flow control param set incorrectly\n");
1493 return -E1000_ERR_CONFIG;
1496 /* Disable TX Flow Control for 82542 (rev 2.0) */
1497 if(hw->mac_type == em_82542_rev2_0)
1498 ctrl &= (~E1000_CTRL_TFCE);
1500 E1000_WRITE_REG(hw, CTRL, ctrl);
1504 /******************************************************************************
1505 * Configures flow control settings after link is established
1507 * hw - Struct containing variables accessed by shared code
1509 * Should be called immediately after a valid link has been established.
1510 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1511 * and autonegotiation is enabled, the MAC flow control settings will be set
1512 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1513 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1514 *****************************************************************************/
1516 em_config_fc_after_link_up(struct em_hw *hw)
1519 uint16_t mii_status_reg;
1520 uint16_t mii_nway_adv_reg;
1521 uint16_t mii_nway_lp_ability_reg;
1525 DEBUGFUNC("em_config_fc_after_link_up");
1527 /* Check for the case where we have fiber media and auto-neg failed
1528 * so we had to force link. In this case, we need to force the
1529 * configuration of the MAC to match the "fc" parameter.
1531 if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
1532 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
1533 ret_val = em_force_mac_fc(hw);
1535 DEBUGOUT("Error forcing flow control settings\n");
1540 /* Check for the case where we have copper media and auto-neg is
1541 * enabled. In this case, we need to check and see if Auto-Neg
1542 * has completed, and if so, how the PHY and link partner has
1543 * flow control configured.
1545 if((hw->media_type == em_media_type_copper) && hw->autoneg) {
1546 /* Read the MII Status Register and check to see if AutoNeg
1547 * has completed. We read this twice because this reg has
1548 * some "sticky" (latched) bits.
1550 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1551 DEBUGOUT("PHY Read Error \n");
1552 return -E1000_ERR_PHY;
1554 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1555 DEBUGOUT("PHY Read Error \n");
1556 return -E1000_ERR_PHY;
1559 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1560 /* The AutoNeg process has completed, so we now need to
1561 * read both the Auto Negotiation Advertisement Register
1562 * (Address 4) and the Auto_Negotiation Base Page Ability
1563 * Register (Address 5) to determine how flow control was
1566 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
1567 DEBUGOUT("PHY Read Error\n");
1568 return -E1000_ERR_PHY;
1570 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
1571 DEBUGOUT("PHY Read Error\n");
1572 return -E1000_ERR_PHY;
1575 /* Two bits in the Auto Negotiation Advertisement Register
1576 * (Address 4) and two bits in the Auto Negotiation Base
1577 * Page Ability Register (Address 5) determine flow control
1578 * for both the PHY and the link partner. The following
1579 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1580 * 1999, describes these PAUSE resolution bits and how flow
1581 * control is determined based upon these settings.
1582 * NOTE: DC = Don't Care
1584 * LOCAL DEVICE | LINK PARTNER
1585 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1586 *-------|---------|-------|---------|--------------------
1587 * 0 | 0 | DC | DC | em_fc_none
1588 * 0 | 1 | 0 | DC | em_fc_none
1589 * 0 | 1 | 1 | 0 | em_fc_none
1590 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1591 * 1 | 0 | 0 | DC | em_fc_none
1592 * 1 | DC | 1 | DC | em_fc_full
1593 * 1 | 1 | 0 | 0 | em_fc_none
1594 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1597 /* Are both PAUSE bits set to 1? If so, this implies
1598 * Symmetric Flow Control is enabled at both ends. The
1599 * ASM_DIR bits are irrelevant per the spec.
1601 * For Symmetric Flow Control:
1603 * LOCAL DEVICE | LINK PARTNER
1604 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1605 *-------|---------|-------|---------|--------------------
1606 * 1 | DC | 1 | DC | em_fc_full
1609 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1610 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1611 /* Now we need to check if the user selected RX ONLY
1612 * of pause frames. In this case, we had to advertise
1613 * FULL flow control because we could not advertise RX
1614 * ONLY. Hence, we must now check to see if we need to
1615 * turn OFF the TRANSMISSION of PAUSE frames.
1617 if(hw->original_fc == em_fc_full) {
1618 hw->fc = em_fc_full;
1619 DEBUGOUT("Flow Control = FULL.\r\n");
1621 hw->fc = em_fc_rx_pause;
1622 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1625 /* For receiving PAUSE frames ONLY.
1627 * LOCAL DEVICE | LINK PARTNER
1628 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1629 *-------|---------|-------|---------|--------------------
1630 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1633 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1634 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1635 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1636 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1637 hw->fc = em_fc_tx_pause;
1638 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1640 /* For transmitting PAUSE frames ONLY.
1642 * LOCAL DEVICE | LINK PARTNER
1643 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1644 *-------|---------|-------|---------|--------------------
1645 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1648 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1649 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1650 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1651 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1652 hw->fc = em_fc_rx_pause;
1653 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1655 /* Per the IEEE spec, at this point flow control should be
1656 * disabled. However, we want to consider that we could
1657 * be connected to a legacy switch that doesn't advertise
1658 * desired flow control, but can be forced on the link
1659 * partner. So if we advertised no flow control, that is
1660 * what we will resolve to. If we advertised some kind of
1661 * receive capability (Rx Pause Only or Full Flow Control)
1662 * and the link partner advertised none, we will configure
1663 * ourselves to enable Rx Flow Control only. We can do
1664 * this safely for two reasons: If the link partner really
1665 * didn't want flow control enabled, and we enable Rx, no
1666 * harm done since we won't be receiving any PAUSE frames
1667 * anyway. If the intent on the link partner was to have
1668 * flow control enabled, then by us enabling RX only, we
1669 * can at least receive pause frames and process them.
1670 * This is a good idea because in most cases, since we are
1671 * predominantly a server NIC, more times than not we will
1672 * be asked to delay transmission of packets than asking
1673 * our link partner to pause transmission of frames.
1675 else if(hw->original_fc == em_fc_none ||
1676 hw->original_fc == em_fc_tx_pause) {
1677 hw->fc = em_fc_none;
1678 DEBUGOUT("Flow Control = NONE.\r\n");
1680 hw->fc = em_fc_rx_pause;
1681 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1684 /* Now we need to do one last check... If we auto-
1685 * negotiated to HALF DUPLEX, flow control should not be
1686 * enabled per IEEE 802.3 spec.
1688 em_get_speed_and_duplex(hw, &speed, &duplex);
1690 if(duplex == HALF_DUPLEX)
1691 hw->fc = em_fc_none;
1693 /* Now we call a subroutine to actually force the MAC
1694 * controller to use the correct flow control settings.
1696 ret_val = em_force_mac_fc(hw);
1698 DEBUGOUT("Error forcing flow control settings\n");
1702 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1708 /******************************************************************************
1709 * Checks to see if the link status of the hardware has changed.
1711 * hw - Struct containing variables accessed by shared code
1713 * Called by any function that needs to check the link status of the adapter.
1714 *****************************************************************************/
1716 em_check_for_link(struct em_hw *hw)
1725 uint16_t lp_capability;
1727 DEBUGFUNC("em_check_for_link");
1729 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1730 * set when the optics detect a signal. On older adapters, it will be
1731 * cleared when there is a signal
1733 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
1736 ctrl = E1000_READ_REG(hw, CTRL);
1737 status = E1000_READ_REG(hw, STATUS);
1738 rxcw = E1000_READ_REG(hw, RXCW);
1740 /* If we have a copper PHY then we only want to go out to the PHY
1741 * registers to see if Auto-Neg has completed and/or if our link
1742 * status has changed. The get_link_status flag will be set if we
1743 * receive a Link Status Change interrupt or we have Rx Sequence
1746 if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
1747 /* First we want to see if the MII Status Register reports
1748 * link. If so, then we want to get the current speed/duplex
1750 * Read the register twice since the link bit is sticky.
1752 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1753 DEBUGOUT("PHY Read Error\n");
1754 return -E1000_ERR_PHY;
1756 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1757 DEBUGOUT("PHY Read Error\n");
1758 return -E1000_ERR_PHY;
1761 if(phy_data & MII_SR_LINK_STATUS) {
1762 hw->get_link_status = FALSE;
1763 /* Check if there was DownShift, must be checked immediately after
1765 em_check_downshift(hw);
1768 /* No link detected */
1772 /* If we are forcing speed/duplex, then we simply return since
1773 * we have already determined whether we have link or not.
1775 if(!hw->autoneg) return -E1000_ERR_CONFIG;
1777 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
1778 * have Si on board that is 82544 or newer, Auto
1779 * Speed Detection takes care of MAC speed/duplex
1780 * configuration. So we only need to configure Collision
1781 * Distance in the MAC. Otherwise, we need to force
1782 * speed/duplex on the MAC to the current PHY speed/duplex
1785 if(hw->mac_type >= em_82544)
1786 em_config_collision_dist(hw);
1788 ret_val = em_config_mac_to_phy(hw);
1790 DEBUGOUT("Error configuring MAC to PHY settings\n");
1795 /* Configure Flow Control now that Auto-Neg has completed. First, we
1796 * need to restore the desired flow control settings because we may
1797 * have had to re-autoneg with a different link partner.
1799 ret_val = em_config_fc_after_link_up(hw);
1801 DEBUGOUT("Error configuring flow control\n");
1805 /* At this point we know that we are on copper and we have
1806 * auto-negotiated link. These are conditions for checking the link
1807 * parter capability register. We use the link partner capability to
1808 * determine if TBI Compatibility needs to be turned on or off. If
1809 * the link partner advertises any speed in addition to Gigabit, then
1810 * we assume that they are GMII-based, and TBI compatibility is not
1811 * needed. If no other speeds are advertised, we assume the link
1812 * partner is TBI-based, and we turn on TBI Compatibility.
1814 if(hw->tbi_compatibility_en) {
1815 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
1816 DEBUGOUT("PHY Read Error\n");
1817 return -E1000_ERR_PHY;
1819 if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1820 NWAY_LPAR_10T_FD_CAPS |
1821 NWAY_LPAR_100TX_HD_CAPS |
1822 NWAY_LPAR_100TX_FD_CAPS |
1823 NWAY_LPAR_100T4_CAPS)) {
1824 /* If our link partner advertises anything in addition to
1825 * gigabit, we do not need to enable TBI compatibility.
1827 if(hw->tbi_compatibility_on) {
1828 /* If we previously were in the mode, turn it off. */
1829 rctl = E1000_READ_REG(hw, RCTL);
1830 rctl &= ~E1000_RCTL_SBP;
1831 E1000_WRITE_REG(hw, RCTL, rctl);
1832 hw->tbi_compatibility_on = FALSE;
1835 /* If TBI compatibility is was previously off, turn it on. For
1836 * compatibility with a TBI link partner, we will store bad
1837 * packets. Some frames have an additional byte on the end and
1838 * will look like CRC errors to to the hardware.
1840 if(!hw->tbi_compatibility_on) {
1841 hw->tbi_compatibility_on = TRUE;
1842 rctl = E1000_READ_REG(hw, RCTL);
1843 rctl |= E1000_RCTL_SBP;
1844 E1000_WRITE_REG(hw, RCTL, rctl);
1849 /* If we don't have link (auto-negotiation failed or link partner cannot
1850 * auto-negotiate), the cable is plugged in (we have signal), and our
1851 * link partner is not trying to auto-negotiate with us (we are receiving
1852 * idles or data), we need to force link up. We also need to give
1853 * auto-negotiation time to complete, in case the cable was just plugged
1854 * in. The autoneg_failed flag does this.
1856 else if((hw->media_type == em_media_type_fiber) &&
1857 (!(status & E1000_STATUS_LU)) &&
1858 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
1859 (!(rxcw & E1000_RXCW_C))) {
1860 if(hw->autoneg_failed == 0) {
1861 hw->autoneg_failed = 1;
1864 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
1866 /* Disable auto-negotiation in the TXCW register */
1867 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
1869 /* Force link-up and also force full-duplex. */
1870 ctrl = E1000_READ_REG(hw, CTRL);
1871 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1872 E1000_WRITE_REG(hw, CTRL, ctrl);
1874 /* Configure Flow Control after forcing link up. */
1875 ret_val = em_config_fc_after_link_up(hw);
1877 DEBUGOUT("Error configuring flow control\n");
1881 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
1882 * auto-negotiation in the TXCW register and disable forced link in the
1883 * Device Control register in an attempt to auto-negotiate with our link
1886 else if((hw->media_type == em_media_type_fiber) &&
1887 (ctrl & E1000_CTRL_SLU) &&
1888 (rxcw & E1000_RXCW_C)) {
1889 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
1890 E1000_WRITE_REG(hw, TXCW, hw->txcw);
1891 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
1896 /******************************************************************************
1897 * Detects the current speed and duplex settings of the hardware.
1899 * hw - Struct containing variables accessed by shared code
1900 * speed - Speed of the connection
1901 * duplex - Duplex setting of the connection
1902 *****************************************************************************/
1904 em_get_speed_and_duplex(struct em_hw *hw,
1910 DEBUGFUNC("em_get_speed_and_duplex");
1912 if(hw->mac_type >= em_82543) {
1913 status = E1000_READ_REG(hw, STATUS);
1914 if(status & E1000_STATUS_SPEED_1000) {
1915 *speed = SPEED_1000;
1916 DEBUGOUT("1000 Mbs, ");
1917 } else if(status & E1000_STATUS_SPEED_100) {
1919 DEBUGOUT("100 Mbs, ");
1922 DEBUGOUT("10 Mbs, ");
1925 if(status & E1000_STATUS_FD) {
1926 *duplex = FULL_DUPLEX;
1927 DEBUGOUT("Full Duplex\r\n");
1929 *duplex = HALF_DUPLEX;
1930 DEBUGOUT(" Half Duplex\r\n");
1933 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
1934 *speed = SPEED_1000;
1935 *duplex = FULL_DUPLEX;
1939 /******************************************************************************
1940 * Blocks until autoneg completes or times out (~4.5 seconds)
1942 * hw - Struct containing variables accessed by shared code
1943 ******************************************************************************/
1945 em_wait_autoneg(struct em_hw *hw)
1950 DEBUGFUNC("em_wait_autoneg");
1951 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
1953 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1954 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1955 /* Read the MII Status Register and wait for Auto-Neg
1956 * Complete bit to be set.
1958 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1959 DEBUGOUT("PHY Read Error\n");
1960 return -E1000_ERR_PHY;
1962 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1963 DEBUGOUT("PHY Read Error\n");
1964 return -E1000_ERR_PHY;
1966 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
1974 /******************************************************************************
1975 * Raises the Management Data Clock
1977 * hw - Struct containing variables accessed by shared code
1978 * ctrl - Device control register's current value
1979 ******************************************************************************/
1981 em_raise_mdi_clk(struct em_hw *hw,
1984 /* Raise the clock input to the Management Data Clock (by setting the MDC
1985 * bit), and then delay 2 microseconds.
1987 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
1988 E1000_WRITE_FLUSH(hw);
1992 /******************************************************************************
1993 * Lowers the Management Data Clock
1995 * hw - Struct containing variables accessed by shared code
1996 * ctrl - Device control register's current value
1997 ******************************************************************************/
1999 em_lower_mdi_clk(struct em_hw *hw,
2002 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2003 * bit), and then delay 2 microseconds.
2005 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2006 E1000_WRITE_FLUSH(hw);
2010 /******************************************************************************
2011 * Shifts data bits out to the PHY
2013 * hw - Struct containing variables accessed by shared code
2014 * data - Data to send out to the PHY
2015 * count - Number of bits to shift out
2017 * Bits are shifted out in MSB to LSB order.
2018 ******************************************************************************/
2020 em_shift_out_mdi_bits(struct em_hw *hw,
2027 /* We need to shift "count" number of bits out to the PHY. So, the value
2028 * in the "data" parameter will be shifted out to the PHY one bit at a
2029 * time. In order to do this, "data" must be broken down into bits.
2032 mask <<= (count - 1);
2034 ctrl = E1000_READ_REG(hw, CTRL);
2036 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2037 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2040 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2041 * then raising and lowering the Management Data Clock. A "0" is
2042 * shifted out to the PHY by setting the MDIO bit to "0" and then
2043 * raising and lowering the clock.
2045 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2046 else ctrl &= ~E1000_CTRL_MDIO;
2048 E1000_WRITE_REG(hw, CTRL, ctrl);
2049 E1000_WRITE_FLUSH(hw);
2053 em_raise_mdi_clk(hw, &ctrl);
2054 em_lower_mdi_clk(hw, &ctrl);
2060 /******************************************************************************
2061 * Shifts data bits in from the PHY
2063 * hw - Struct containing variables accessed by shared code
2065 * Bits are shifted in in MSB to LSB order.
2066 ******************************************************************************/
2068 em_shift_in_mdi_bits(struct em_hw *hw)
2074 /* In order to read a register from the PHY, we need to shift in a total
2075 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2076 * to avoid contention on the MDIO pin when a read operation is performed.
2077 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2078 * by raising the input to the Management Data Clock (setting the MDC bit),
2079 * and then reading the value of the MDIO bit.
2081 ctrl = E1000_READ_REG(hw, CTRL);
2083 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2084 ctrl &= ~E1000_CTRL_MDIO_DIR;
2085 ctrl &= ~E1000_CTRL_MDIO;
2087 E1000_WRITE_REG(hw, CTRL, ctrl);
2088 E1000_WRITE_FLUSH(hw);
2090 /* Raise and Lower the clock before reading in the data. This accounts for
2091 * the turnaround bits. The first clock occurred when we clocked out the
2092 * last bit of the Register Address.
2094 em_raise_mdi_clk(hw, &ctrl);
2095 em_lower_mdi_clk(hw, &ctrl);
2097 for(data = 0, i = 0; i < 16; i++) {
2099 em_raise_mdi_clk(hw, &ctrl);
2100 ctrl = E1000_READ_REG(hw, CTRL);
2101 /* Check to see if we shifted in a "1". */
2102 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2103 em_lower_mdi_clk(hw, &ctrl);
2106 em_raise_mdi_clk(hw, &ctrl);
2107 em_lower_mdi_clk(hw, &ctrl);
2112 /*****************************************************************************
2113 * Reads the value from a PHY register
2115 * hw - Struct containing variables accessed by shared code
2116 * reg_addr - address of the PHY register to read
2117 ******************************************************************************/
2119 em_read_phy_reg(struct em_hw *hw,
2125 const uint32_t phy_addr = 1;
2127 DEBUGFUNC("em_read_phy_reg");
2129 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2130 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2131 return -E1000_ERR_PARAM;
2134 if(hw->mac_type > em_82543) {
2135 /* Set up Op-code, Phy Address, and register address in the MDI
2136 * Control register. The MAC will take care of interfacing with the
2137 * PHY to retrieve the desired data.
2139 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2140 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2141 (E1000_MDIC_OP_READ));
2143 E1000_WRITE_REG(hw, MDIC, mdic);
2145 /* Poll the ready bit to see if the MDI read completed */
2146 for(i = 0; i < 64; i++) {
2148 mdic = E1000_READ_REG(hw, MDIC);
2149 if(mdic & E1000_MDIC_READY) break;
2151 if(!(mdic & E1000_MDIC_READY)) {
2152 DEBUGOUT("MDI Read did not complete\n");
2153 return -E1000_ERR_PHY;
2155 if(mdic & E1000_MDIC_ERROR) {
2156 DEBUGOUT("MDI Error\n");
2157 return -E1000_ERR_PHY;
2159 *phy_data = (uint16_t) mdic;
2161 /* We must first send a preamble through the MDIO pin to signal the
2162 * beginning of an MII instruction. This is done by sending 32
2163 * consecutive "1" bits.
2165 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2167 /* Now combine the next few fields that are required for a read
2168 * operation. We use this method instead of calling the
2169 * em_shift_out_mdi_bits routine five different times. The format of
2170 * a MII read instruction consists of a shift out of 14 bits and is
2171 * defined as follows:
2172 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2173 * followed by a shift in of 18 bits. This first two bits shifted in
2174 * are TurnAround bits used to avoid contention on the MDIO pin when a
2175 * READ operation is performed. These two bits are thrown away
2176 * followed by a shift in of 16 bits which contains the desired data.
2178 mdic = ((reg_addr) | (phy_addr << 5) |
2179 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2181 em_shift_out_mdi_bits(hw, mdic, 14);
2183 /* Now that we've shifted out the read command to the MII, we need to
2184 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2187 *phy_data = em_shift_in_mdi_bits(hw);
2192 /******************************************************************************
2193 * Writes a value to a PHY register
2195 * hw - Struct containing variables accessed by shared code
2196 * reg_addr - address of the PHY register to write
2197 * data - data to write to the PHY
2198 ******************************************************************************/
2200 em_write_phy_reg(struct em_hw *hw,
2206 const uint32_t phy_addr = 1;
2208 DEBUGFUNC("em_write_phy_reg");
2210 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2211 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2212 return -E1000_ERR_PARAM;
2215 if(hw->mac_type > em_82543) {
2216 /* Set up Op-code, Phy Address, register address, and data intended
2217 * for the PHY register in the MDI Control register. The MAC will take
2218 * care of interfacing with the PHY to send the desired data.
2220 mdic = (((uint32_t) phy_data) |
2221 (reg_addr << E1000_MDIC_REG_SHIFT) |
2222 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2223 (E1000_MDIC_OP_WRITE));
2225 E1000_WRITE_REG(hw, MDIC, mdic);
2227 /* Poll the ready bit to see if the MDI read completed */
2228 for(i = 0; i < 64; i++) {
2230 mdic = E1000_READ_REG(hw, MDIC);
2231 if(mdic & E1000_MDIC_READY) break;
2233 if(!(mdic & E1000_MDIC_READY)) {
2234 DEBUGOUT("MDI Write did not complete\n");
2235 return -E1000_ERR_PHY;
2238 /* We'll need to use the SW defined pins to shift the write command
2239 * out to the PHY. We first send a preamble to the PHY to signal the
2240 * beginning of the MII instruction. This is done by sending 32
2241 * consecutive "1" bits.
2243 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2245 /* Now combine the remaining required fields that will indicate a
2246 * write operation. We use this method instead of calling the
2247 * em_shift_out_mdi_bits routine for each field in the command. The
2248 * format of a MII write instruction is as follows:
2249 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2251 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2252 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2254 mdic |= (uint32_t) phy_data;
2256 em_shift_out_mdi_bits(hw, mdic, 32);
2262 /******************************************************************************
2263 * Returns the PHY to the power-on reset state
2265 * hw - Struct containing variables accessed by shared code
2266 ******************************************************************************/
2268 em_phy_hw_reset(struct em_hw *hw)
2270 uint32_t ctrl, ctrl_ext;
2273 DEBUGFUNC("em_phy_hw_reset");
2275 DEBUGOUT("Resetting Phy...\n");
2277 if(hw->mac_type > em_82543) {
2278 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2279 * bit. Then, take it out of reset.
2281 ctrl = E1000_READ_REG(hw, CTRL);
2282 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2283 E1000_WRITE_FLUSH(hw);
2285 E1000_WRITE_REG(hw, CTRL, ctrl);
2286 E1000_WRITE_FLUSH(hw);
2288 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2289 * bit to put the PHY into reset. Then, take it out of reset.
2291 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2292 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2293 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2294 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2295 E1000_WRITE_FLUSH(hw);
2297 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2298 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2299 E1000_WRITE_FLUSH(hw);
2303 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2304 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) {
2305 DEBUGOUT("PHY Write Error\n");
2309 /* Configure activity LED after PHY reset */
2310 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2311 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2312 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2313 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2317 /******************************************************************************
2320 * hw - Struct containing variables accessed by shared code
2322 * Sets bit 15 of the MII Control regiser
2323 ******************************************************************************/
2325 em_phy_reset(struct em_hw *hw)
2329 DEBUGFUNC("em_phy_reset");
2331 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
2332 DEBUGOUT("PHY Read Error\n");
2333 return -E1000_ERR_PHY;
2335 phy_data |= MII_CR_RESET;
2336 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
2337 DEBUGOUT("PHY Write Error\n");
2338 return -E1000_ERR_PHY;
2341 if (hw->phy_type == em_phy_igp) {
2342 em_phy_init_script(hw);
2347 /******************************************************************************
2348 * Probes the expected PHY address for known PHY IDs
2350 * hw - Struct containing variables accessed by shared code
2351 ******************************************************************************/
2353 em_detect_gig_phy(struct em_hw *hw)
2355 uint16_t phy_id_high, phy_id_low;
2356 boolean_t match = FALSE;
2357 int32_t phy_init_status;
2359 DEBUGFUNC("em_detect_gig_phy");
2361 /* Read the PHY ID Registers to identify which PHY is onboard. */
2362 if(em_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
2363 DEBUGOUT("PHY Read Error\n");
2364 return -E1000_ERR_PHY;
2366 hw->phy_id = (uint32_t) (phy_id_high << 16);
2368 if(em_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
2369 DEBUGOUT("PHY Read Error\n");
2370 return -E1000_ERR_PHY;
2372 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2373 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2375 switch(hw->mac_type) {
2377 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2380 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2385 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2389 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2392 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2393 return -E1000_ERR_CONFIG;
2395 phy_init_status = em_set_phy_type(hw);
2397 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2398 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2401 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2402 return -E1000_ERR_PHY;
2405 /******************************************************************************
2406 * Resets the PHY's DSP
2408 * hw - Struct containing variables accessed by shared code
2409 ******************************************************************************/
2411 em_phy_reset_dsp(struct em_hw *hw)
2413 int32_t ret_val = -E1000_ERR_PHY;
2414 DEBUGFUNC("em_phy_reset_dsp");
2417 if(em_write_phy_reg(hw, 29, 0x001d) < 0) break;
2418 if(em_write_phy_reg(hw, 30, 0x00c1) < 0) break;
2419 if(em_write_phy_reg(hw, 30, 0x0000) < 0) break;
2423 if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
2427 /******************************************************************************
2428 * Get PHY information from various PHY registers for igp PHY only.
2430 * hw - Struct containing variables accessed by shared code
2431 * phy_info - PHY information structure
2432 ******************************************************************************/
2434 em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
2436 uint16_t phy_data, polarity, min_length, max_length, average;
2438 DEBUGFUNC("em_phy_igp_get_info");
2440 /* The downshift status is checked only once, after link is established,
2441 * and it stored in the hw->speed_downgraded parameter. */
2442 phy_info->downshift = hw->speed_downgraded;
2444 /* IGP01E1000 does not need to support it. */
2445 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
2447 /* IGP01E1000 always correct polarity reversal */
2448 phy_info->polarity_correction = em_polarity_reversal_enabled;
2450 /* Check polarity status */
2451 if(em_check_polarity(hw, &polarity) < 0)
2452 return -E1000_ERR_PHY;
2454 phy_info->cable_polarity = polarity;
2456 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0)
2457 return -E1000_ERR_PHY;
2459 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2460 IGP01E1000_PSSR_MDIX_SHIFT;
2462 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2463 IGP01E1000_PSSR_SPEED_1000MBPS) {
2464 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2465 if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0)
2466 return -E1000_ERR_PHY;
2468 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2469 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2470 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2471 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2473 /* Get cable length */
2474 if(em_get_cable_length(hw, &min_length, &max_length) < 0)
2475 return -E1000_ERR_PHY;
2477 /* transalte to old method */
2478 average = (max_length + min_length) / 2;
2480 if(average <= em_igp_cable_length_50)
2481 phy_info->cable_length = em_cable_length_50;
2482 else if(average <= em_igp_cable_length_80)
2483 phy_info->cable_length = em_cable_length_50_80;
2484 else if(average <= em_igp_cable_length_110)
2485 phy_info->cable_length = em_cable_length_80_110;
2486 else if(average <= em_igp_cable_length_140)
2487 phy_info->cable_length = em_cable_length_110_140;
2489 phy_info->cable_length = em_cable_length_140;
2492 return E1000_SUCCESS;
2495 /******************************************************************************
2496 * Get PHY information from various PHY registers fot m88 PHY only.
2498 * hw - Struct containing variables accessed by shared code
2499 * phy_info - PHY information structure
2500 ******************************************************************************/
2502 em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
2504 uint16_t phy_data, polarity;
2506 DEBUGFUNC("em_phy_m88_get_info");
2508 /* The downshift status is checked only once, after link is established,
2509 * and it stored in the hw->speed_downgraded parameter. */
2510 phy_info->downshift = hw->speed_downgraded;
2512 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
2513 return -E1000_ERR_PHY;
2515 phy_info->extended_10bt_distance =
2516 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2517 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2518 phy_info->polarity_correction =
2519 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2520 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2522 /* Check polarity status */
2523 if(em_check_polarity(hw, &polarity) < 0)
2524 return -E1000_ERR_PHY;
2526 phy_info->cable_polarity = polarity;
2528 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
2529 return -E1000_ERR_PHY;
2531 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2532 M88E1000_PSSR_MDIX_SHIFT;
2534 if(phy_data & M88E1000_PSSR_1000MBS) {
2535 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2536 * are only valid at 1000 Mbps
2538 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2539 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2541 if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0)
2542 return -E1000_ERR_PHY;
2544 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2545 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2547 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2548 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2551 return E1000_SUCCESS;
2554 /******************************************************************************
2555 * Get PHY information from various PHY registers
2557 * hw - Struct containing variables accessed by shared code
2558 * phy_info - PHY information structure
2559 ******************************************************************************/
2561 em_phy_get_info(struct em_hw *hw,
2562 struct em_phy_info *phy_info)
2566 DEBUGFUNC("em_phy_get_info");
2568 phy_info->cable_length = em_cable_length_undefined;
2569 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
2570 phy_info->cable_polarity = em_rev_polarity_undefined;
2571 phy_info->downshift = em_downshift_undefined;
2572 phy_info->polarity_correction = em_polarity_reversal_undefined;
2573 phy_info->mdix_mode = em_auto_x_mode_undefined;
2574 phy_info->local_rx = em_1000t_rx_status_undefined;
2575 phy_info->remote_rx = em_1000t_rx_status_undefined;
2577 if(hw->media_type != em_media_type_copper) {
2578 DEBUGOUT("PHY info is only valid for copper media\n");
2579 return -E1000_ERR_CONFIG;
2582 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2583 DEBUGOUT("PHY Read Error\n");
2584 return -E1000_ERR_PHY;
2586 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2587 DEBUGOUT("PHY Read Error\n");
2588 return -E1000_ERR_PHY;
2590 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2591 DEBUGOUT("PHY info is only valid if link is up\n");
2592 return -E1000_ERR_CONFIG;
2595 if (hw->phy_type == em_phy_igp)
2596 return em_phy_igp_get_info(hw, phy_info);
2598 return em_phy_m88_get_info(hw, phy_info);
2602 em_validate_mdi_setting(struct em_hw *hw)
2604 DEBUGFUNC("em_validate_mdi_settings");
2606 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2607 DEBUGOUT("Invalid MDI setting detected\n");
2609 return -E1000_ERR_CONFIG;
2615 /******************************************************************************
2616 * Sets up eeprom variables in the hw struct. Must be called after mac_type
2619 * hw - Struct containing variables accessed by shared code
2620 *****************************************************************************/
2622 em_init_eeprom_params(struct em_hw *hw)
2624 struct em_eeprom_info *eeprom = &hw->eeprom;
2625 uint32_t eecd = E1000_READ_REG(hw, EECD);
2626 uint16_t eeprom_size;
2628 DEBUGFUNC("em_init_eeprom_params");
2630 switch (hw->mac_type) {
2631 case em_82542_rev2_0:
2632 case em_82542_rev2_1:
2635 eeprom->type = em_eeprom_microwire;
2636 eeprom->word_size = 64;
2637 eeprom->opcode_bits = 3;
2638 eeprom->address_bits = 6;
2639 eeprom->delay_usec = 50;
2644 eeprom->type = em_eeprom_microwire;
2645 eeprom->opcode_bits = 3;
2646 eeprom->delay_usec = 50;
2647 if(eecd & E1000_EECD_SIZE) {
2648 eeprom->word_size = 256;
2649 eeprom->address_bits = 8;
2651 eeprom->word_size = 64;
2652 eeprom->address_bits = 6;
2658 if (eecd & E1000_EECD_TYPE) {
2659 eeprom->type = em_eeprom_spi;
2660 eeprom->opcode_bits = 8;
2661 eeprom->delay_usec = 1;
2662 if (eecd & E1000_EECD_ADDR_BITS) {
2663 eeprom->page_size = 32;
2664 eeprom->address_bits = 16;
2666 eeprom->page_size = 8;
2667 eeprom->address_bits = 8;
2670 eeprom->type = em_eeprom_microwire;
2671 eeprom->opcode_bits = 3;
2672 eeprom->delay_usec = 50;
2673 if (eecd & E1000_EECD_ADDR_BITS) {
2674 eeprom->word_size = 256;
2675 eeprom->address_bits = 8;
2677 eeprom->word_size = 64;
2678 eeprom->address_bits = 6;
2684 if (eeprom->type == em_eeprom_spi) {
2685 eeprom->word_size = 64;
2686 if (em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
2687 eeprom_size &= EEPROM_SIZE_MASK;
2689 switch (eeprom_size) {
2690 case EEPROM_SIZE_16KB:
2691 eeprom->word_size = 8192;
2693 case EEPROM_SIZE_8KB:
2694 eeprom->word_size = 4096;
2696 case EEPROM_SIZE_4KB:
2697 eeprom->word_size = 2048;
2699 case EEPROM_SIZE_2KB:
2700 eeprom->word_size = 1024;
2702 case EEPROM_SIZE_1KB:
2703 eeprom->word_size = 512;
2705 case EEPROM_SIZE_512B:
2706 eeprom->word_size = 256;
2708 case EEPROM_SIZE_128B:
2710 eeprom->word_size = 64;
2717 /******************************************************************************
2718 * Raises the EEPROM's clock input.
2720 * hw - Struct containing variables accessed by shared code
2721 * eecd - EECD's current value
2722 *****************************************************************************/
2724 em_raise_ee_clk(struct em_hw *hw,
2727 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
2728 * wait <delay> microseconds.
2730 *eecd = *eecd | E1000_EECD_SK;
2731 E1000_WRITE_REG(hw, EECD, *eecd);
2732 E1000_WRITE_FLUSH(hw);
2733 usec_delay(hw->eeprom.delay_usec);
2736 /******************************************************************************
2737 * Lowers the EEPROM's clock input.
2739 * hw - Struct containing variables accessed by shared code
2740 * eecd - EECD's current value
2741 *****************************************************************************/
2743 em_lower_ee_clk(struct em_hw *hw,
2746 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
2747 * wait 50 microseconds.
2749 *eecd = *eecd & ~E1000_EECD_SK;
2750 E1000_WRITE_REG(hw, EECD, *eecd);
2751 E1000_WRITE_FLUSH(hw);
2752 usec_delay(hw->eeprom.delay_usec);
2755 /******************************************************************************
2756 * Shift data bits out to the EEPROM.
2758 * hw - Struct containing variables accessed by shared code
2759 * data - data to send to the EEPROM
2760 * count - number of bits to shift out
2761 *****************************************************************************/
2763 em_shift_out_ee_bits(struct em_hw *hw,
2767 struct em_eeprom_info *eeprom = &hw->eeprom;
2771 /* We need to shift "count" bits out to the EEPROM. So, value in the
2772 * "data" parameter will be shifted out to the EEPROM one bit at a time.
2773 * In order to do this, "data" must be broken down into bits.
2775 mask = 0x01 << (count - 1);
2776 eecd = E1000_READ_REG(hw, EECD);
2777 if (eeprom->type == em_eeprom_microwire) {
2778 eecd &= ~E1000_EECD_DO;
2779 } else if (eeprom->type == em_eeprom_spi) {
2780 eecd |= E1000_EECD_DO;
2783 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2784 * and then raising and then lowering the clock (the SK bit controls
2785 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
2786 * by setting "DI" to "0" and then raising and then lowering the clock.
2788 eecd &= ~E1000_EECD_DI;
2791 eecd |= E1000_EECD_DI;
2793 E1000_WRITE_REG(hw, EECD, eecd);
2794 E1000_WRITE_FLUSH(hw);
2796 usec_delay(eeprom->delay_usec);
2798 em_raise_ee_clk(hw, &eecd);
2799 em_lower_ee_clk(hw, &eecd);
2805 /* We leave the "DI" bit set to "0" when we leave this routine. */
2806 eecd &= ~E1000_EECD_DI;
2807 E1000_WRITE_REG(hw, EECD, eecd);
2810 /******************************************************************************
2811 * Shift data bits in from the EEPROM
2813 * hw - Struct containing variables accessed by shared code
2814 *****************************************************************************/
2816 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count)
2822 /* In order to read a register from the EEPROM, we need to shift 'count'
2823 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
2824 * input to the EEPROM (setting the SK bit), and then reading the value of
2825 * the "DO" bit. During this "shifting in" process the "DI" bit should
2829 eecd = E1000_READ_REG(hw, EECD);
2831 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
2834 for(i = 0; i < count; i++) {
2836 em_raise_ee_clk(hw, &eecd);
2838 eecd = E1000_READ_REG(hw, EECD);
2840 eecd &= ~(E1000_EECD_DI);
2841 if(eecd & E1000_EECD_DO)
2844 em_lower_ee_clk(hw, &eecd);
2850 /******************************************************************************
2851 * Prepares EEPROM for access
2853 * hw - Struct containing variables accessed by shared code
2855 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
2856 * function should be called before issuing a command to the EEPROM.
2857 *****************************************************************************/
2859 em_acquire_eeprom(struct em_hw *hw)
2861 struct em_eeprom_info *eeprom = &hw->eeprom;
2864 DEBUGFUNC("em_acquire_eeprom");
2866 eecd = E1000_READ_REG(hw, EECD);
2868 /* Request EEPROM Access */
2869 if(hw->mac_type > em_82544) {
2870 eecd |= E1000_EECD_REQ;
2871 E1000_WRITE_REG(hw, EECD, eecd);
2872 eecd = E1000_READ_REG(hw, EECD);
2873 while((!(eecd & E1000_EECD_GNT)) &&
2874 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
2877 eecd = E1000_READ_REG(hw, EECD);
2879 if(!(eecd & E1000_EECD_GNT)) {
2880 eecd &= ~E1000_EECD_REQ;
2881 E1000_WRITE_REG(hw, EECD, eecd);
2882 DEBUGOUT("Could not acquire EEPROM grant\n");
2883 return -E1000_ERR_EEPROM;
2887 /* Setup EEPROM for Read/Write */
2889 if (eeprom->type == em_eeprom_microwire) {
2890 /* Clear SK and DI */
2891 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
2892 E1000_WRITE_REG(hw, EECD, eecd);
2895 eecd |= E1000_EECD_CS;
2896 E1000_WRITE_REG(hw, EECD, eecd);
2897 } else if (eeprom->type == em_eeprom_spi) {
2898 /* Clear SK and CS */
2899 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2900 E1000_WRITE_REG(hw, EECD, eecd);
2904 return E1000_SUCCESS;
2907 /******************************************************************************
2908 * Returns EEPROM to a "standby" state
2910 * hw - Struct containing variables accessed by shared code
2911 *****************************************************************************/
2913 em_standby_eeprom(struct em_hw *hw)
2915 struct em_eeprom_info *eeprom = &hw->eeprom;
2918 eecd = E1000_READ_REG(hw, EECD);
2920 if(eeprom->type == em_eeprom_microwire) {
2921 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2922 E1000_WRITE_REG(hw, EECD, eecd);
2923 E1000_WRITE_FLUSH(hw);
2924 usec_delay(eeprom->delay_usec);
2927 eecd |= E1000_EECD_SK;
2928 E1000_WRITE_REG(hw, EECD, eecd);
2929 E1000_WRITE_FLUSH(hw);
2930 usec_delay(eeprom->delay_usec);
2933 eecd |= E1000_EECD_CS;
2934 E1000_WRITE_REG(hw, EECD, eecd);
2935 E1000_WRITE_FLUSH(hw);
2936 usec_delay(eeprom->delay_usec);
2939 eecd &= ~E1000_EECD_SK;
2940 E1000_WRITE_REG(hw, EECD, eecd);
2941 E1000_WRITE_FLUSH(hw);
2942 usec_delay(eeprom->delay_usec);
2943 } else if(eeprom->type == em_eeprom_spi) {
2944 /* Toggle CS to flush commands */
2945 eecd |= E1000_EECD_CS;
2946 E1000_WRITE_REG(hw, EECD, eecd);
2947 E1000_WRITE_FLUSH(hw);
2948 usec_delay(eeprom->delay_usec);
2949 eecd &= ~E1000_EECD_CS;
2950 E1000_WRITE_REG(hw, EECD, eecd);
2951 E1000_WRITE_FLUSH(hw);
2952 usec_delay(eeprom->delay_usec);
2956 /******************************************************************************
2957 * Terminates a command by inverting the EEPROM's chip select pin
2959 * hw - Struct containing variables accessed by shared code
2960 *****************************************************************************/
2962 em_release_eeprom(struct em_hw *hw)
2966 DEBUGFUNC("em_release_eeprom");
2968 eecd = E1000_READ_REG(hw, EECD);
2970 if (hw->eeprom.type == em_eeprom_spi) {
2971 eecd |= E1000_EECD_CS; /* Pull CS high */
2972 eecd &= ~E1000_EECD_SK; /* Lower SCK */
2974 E1000_WRITE_REG(hw, EECD, eecd);
2976 usec_delay(hw->eeprom.delay_usec);
2977 } else if(hw->eeprom.type == em_eeprom_microwire) {
2978 /* cleanup eeprom */
2980 /* CS on Microwire is active-high */
2981 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
2983 E1000_WRITE_REG(hw, EECD, eecd);
2985 /* Rising edge of clock */
2986 eecd |= E1000_EECD_SK;
2987 E1000_WRITE_REG(hw, EECD, eecd);
2988 E1000_WRITE_FLUSH(hw);
2989 usec_delay(hw->eeprom.delay_usec);
2991 /* Falling edge of clock */
2992 eecd &= ~E1000_EECD_SK;
2993 E1000_WRITE_REG(hw, EECD, eecd);
2994 E1000_WRITE_FLUSH(hw);
2995 usec_delay(hw->eeprom.delay_usec);
2998 /* Stop requesting EEPROM access */
2999 if(hw->mac_type > em_82544) {
3000 eecd &= ~E1000_EECD_REQ;
3001 E1000_WRITE_REG(hw, EECD, eecd);
3005 /******************************************************************************
3006 * Reads a 16 bit word from the EEPROM.
3008 * hw - Struct containing variables accessed by shared code
3009 *****************************************************************************/
3011 em_spi_eeprom_ready(struct em_hw *hw)
3013 uint16_t retry_count = 0;
3014 uint8_t spi_stat_reg;
3016 DEBUGFUNC("em_spi_eeprom_ready");
3018 /* Read "Status Register" repeatedly until the LSB is cleared. The
3019 * EEPROM will signal that the command has been completed by clearing
3020 * bit 0 of the internal status register. If it's not cleared within
3021 * 5 milliseconds, then error out.
3025 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3026 hw->eeprom.opcode_bits);
3027 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
3028 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3034 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3036 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3037 * only 0-5mSec on 5V devices)
3039 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3040 DEBUGOUT("SPI EEPROM Status error\n");
3041 return -E1000_ERR_EEPROM;
3044 return E1000_SUCCESS;
3047 /******************************************************************************
3048 * Reads a 16 bit word from the EEPROM.
3050 * hw - Struct containing variables accessed by shared code
3051 * offset - offset of word in the EEPROM to read
3052 * data - word read from the EEPROM
3053 * words - number of words to read
3054 *****************************************************************************/
3056 em_read_eeprom(struct em_hw *hw,
3061 struct em_eeprom_info *eeprom = &hw->eeprom;
3064 DEBUGFUNC("em_read_eeprom");
3066 /* A check for invalid values: offset too large, too many words, and not
3069 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3071 DEBUGOUT("\"words\" parameter out of bounds\n");
3072 return -E1000_ERR_EEPROM;
3075 /* Prepare the EEPROM for reading */
3076 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
3077 return -E1000_ERR_EEPROM;
3079 if(eeprom->type == em_eeprom_spi) {
3080 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3082 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3084 em_standby_eeprom(hw);
3086 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3087 if((eeprom->address_bits == 8) && (offset >= 128))
3088 read_opcode |= EEPROM_A8_OPCODE_SPI;
3090 /* Send the READ command (opcode + addr) */
3091 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3092 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3094 else if(eeprom->type == em_eeprom_microwire) {
3095 /* Send the READ command (opcode + addr) */
3096 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3097 eeprom->opcode_bits);
3098 em_shift_out_ee_bits(hw, offset, eeprom->address_bits);
3101 /* Read the data. The address of the eeprom internally increments with
3102 * each word (microwire) or byte (spi) being read, saving on the overhead
3103 * of eeprom setup and tear-down. The address counter will roll over if
3104 * reading beyond the size of the eeprom, thus allowing the entire memory
3105 * to be read starting from any offset. */
3106 for (i = 0; i < words; i++) {
3107 uint16_t word_in = em_shift_in_ee_bits(hw, 16);
3108 if (eeprom->type == em_eeprom_spi)
3109 word_in = (word_in >> 8) | (word_in << 8);
3113 /* End this read operation */
3114 em_release_eeprom(hw);
3119 /******************************************************************************
3120 * Verifies that the EEPROM has a valid checksum
3122 * hw - Struct containing variables accessed by shared code
3124 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3125 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3127 *****************************************************************************/
3129 em_validate_eeprom_checksum(struct em_hw *hw)
3131 uint16_t checksum = 0;
3132 uint16_t i, eeprom_data;
3134 DEBUGFUNC("em_validate_eeprom_checksum");
3136 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3137 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3138 DEBUGOUT("EEPROM Read Error\n");
3139 return -E1000_ERR_EEPROM;
3141 checksum += eeprom_data;
3144 if(checksum == (uint16_t) EEPROM_SUM) {
3147 DEBUGOUT("EEPROM Checksum Invalid\n");
3148 return -E1000_ERR_EEPROM;
3152 /******************************************************************************
3153 * Calculates the EEPROM checksum and writes it to the EEPROM
3155 * hw - Struct containing variables accessed by shared code
3157 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3158 * Writes the difference to word offset 63 of the EEPROM.
3159 *****************************************************************************/
3161 em_update_eeprom_checksum(struct em_hw *hw)
3163 uint16_t checksum = 0;
3164 uint16_t i, eeprom_data;
3166 DEBUGFUNC("em_update_eeprom_checksum");
3168 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3169 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3170 DEBUGOUT("EEPROM Read Error\n");
3171 return -E1000_ERR_EEPROM;
3173 checksum += eeprom_data;
3175 checksum = (uint16_t) EEPROM_SUM - checksum;
3176 if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3177 DEBUGOUT("EEPROM Write Error\n");
3178 return -E1000_ERR_EEPROM;
3183 /******************************************************************************
3184 * Parent function for writing words to the different EEPROM types.
3186 * hw - Struct containing variables accessed by shared code
3187 * offset - offset within the EEPROM to be written to
3188 * words - number of words to write
3189 * data - 16 bit word to be written to the EEPROM
3191 * If em_update_eeprom_checksum is not called after this function, the
3192 * EEPROM will most likely contain an invalid checksum.
3193 *****************************************************************************/
3195 em_write_eeprom(struct em_hw *hw,
3200 struct em_eeprom_info *eeprom = &hw->eeprom;
3203 DEBUGFUNC("em_write_eeprom");
3205 /* A check for invalid values: offset too large, too many words, and not
3208 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3210 DEBUGOUT("\"words\" parameter out of bounds\n");
3211 return -E1000_ERR_EEPROM;
3214 /* Prepare the EEPROM for writing */
3215 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
3216 return -E1000_ERR_EEPROM;
3218 if(eeprom->type == em_eeprom_microwire)
3219 status = em_write_eeprom_microwire(hw, offset, words, data);
3221 status = em_write_eeprom_spi(hw, offset, words, data);
3223 /* Done with writing */
3224 em_release_eeprom(hw);
3229 /******************************************************************************
3230 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3232 * hw - Struct containing variables accessed by shared code
3233 * offset - offset within the EEPROM to be written to
3234 * words - number of words to write
3235 * data - pointer to array of 8 bit words to be written to the EEPROM
3237 *****************************************************************************/
3239 em_write_eeprom_spi(struct em_hw *hw,
3244 struct em_eeprom_info *eeprom = &hw->eeprom;
3247 DEBUGFUNC("em_write_eeprom_spi");
3249 while (widx < words) {
3250 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3252 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3254 em_standby_eeprom(hw);
3256 /* Send the WRITE ENABLE command (8 bit opcode ) */
3257 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3258 eeprom->opcode_bits);
3260 em_standby_eeprom(hw);
3262 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3263 if((eeprom->address_bits == 8) && (offset >= 128))
3264 write_opcode |= EEPROM_A8_OPCODE_SPI;
3266 /* Send the Write command (8-bit opcode + addr) */
3267 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3269 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3270 eeprom->address_bits);
3274 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3275 while (widx < words) {
3276 uint16_t word_out = data[widx];
3277 word_out = (word_out >> 8) | (word_out << 8);
3278 em_shift_out_ee_bits(hw, word_out, 16);
3281 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3282 * operation, while the smaller eeproms are capable of an 8-byte
3283 * PAGE WRITE operation. Break the inner loop to pass new address
3285 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3286 em_standby_eeprom(hw);
3292 return E1000_SUCCESS;
3295 /******************************************************************************
3296 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3298 * hw - Struct containing variables accessed by shared code
3299 * offset - offset within the EEPROM to be written to
3300 * words - number of words to write
3301 * data - pointer to array of 16 bit words to be written to the EEPROM
3303 *****************************************************************************/
3305 em_write_eeprom_microwire(struct em_hw *hw,
3310 struct em_eeprom_info *eeprom = &hw->eeprom;
3312 uint16_t words_written = 0;
3315 DEBUGFUNC("em_write_eeprom_microwire");
3317 /* Send the write enable command to the EEPROM (3-bit opcode plus
3318 * 6/8-bit dummy address beginning with 11). It's less work to include
3319 * the 11 of the dummy address as part of the opcode than it is to shift
3320 * it over the correct number of bits for the address. This puts the
3321 * EEPROM into write/erase mode.
3323 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3324 (uint16_t)(eeprom->opcode_bits + 2));
3326 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3328 /* Prepare the EEPROM */
3329 em_standby_eeprom(hw);
3331 while (words_written < words) {
3332 /* Send the Write command (3-bit opcode + addr) */
3333 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3334 eeprom->opcode_bits);
3336 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3337 eeprom->address_bits);
3340 em_shift_out_ee_bits(hw, data[words_written], 16);
3342 /* Toggle the CS line. This in effect tells the EEPROM to execute
3343 * the previous command.
3345 em_standby_eeprom(hw);
3347 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3348 * signal that the command has been completed by raising the DO signal.
3349 * If DO does not go high in 10 milliseconds, then error out.
3351 for(i = 0; i < 200; i++) {
3352 eecd = E1000_READ_REG(hw, EECD);
3353 if(eecd & E1000_EECD_DO) break;
3357 DEBUGOUT("EEPROM Write did not complete\n");
3358 return -E1000_ERR_EEPROM;
3361 /* Recover from write */
3362 em_standby_eeprom(hw);
3367 /* Send the write disable command to the EEPROM (3-bit opcode plus
3368 * 6/8-bit dummy address beginning with 10). It's less work to include
3369 * the 10 of the dummy address as part of the opcode than it is to shift
3370 * it over the correct number of bits for the address. This takes the
3371 * EEPROM out of write/erase mode.
3373 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3374 (uint16_t)(eeprom->opcode_bits + 2));
3376 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3381 /******************************************************************************
3382 * Reads the adapter's part number from the EEPROM
3384 * hw - Struct containing variables accessed by shared code
3385 * part_num - Adapter's part number
3386 *****************************************************************************/
3388 em_read_part_num(struct em_hw *hw,
3391 uint16_t offset = EEPROM_PBA_BYTE_1;
3392 uint16_t eeprom_data;
3394 DEBUGFUNC("em_read_part_num");
3396 /* Get word 0 from EEPROM */
3397 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3398 DEBUGOUT("EEPROM Read Error\n");
3399 return -E1000_ERR_EEPROM;
3401 /* Save word 0 in upper half of part_num */
3402 *part_num = (uint32_t) (eeprom_data << 16);
3404 /* Get word 1 from EEPROM */
3405 if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3406 DEBUGOUT("EEPROM Read Error\n");
3407 return -E1000_ERR_EEPROM;
3409 /* Save word 1 in lower half of part_num */
3410 *part_num |= eeprom_data;
3415 /******************************************************************************
3416 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3417 * second function of dual function devices
3419 * hw - Struct containing variables accessed by shared code
3420 *****************************************************************************/
3422 em_read_mac_addr(struct em_hw * hw)
3425 uint16_t eeprom_data, i;
3427 DEBUGFUNC("em_read_mac_addr");
3429 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3431 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3432 DEBUGOUT("EEPROM Read Error\n");
3433 return -E1000_ERR_EEPROM;
3435 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3436 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3438 if((hw->mac_type == em_82546) &&
3439 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3440 if(hw->perm_mac_addr[5] & 0x01)
3441 hw->perm_mac_addr[5] &= ~(0x01);
3443 hw->perm_mac_addr[5] |= 0x01;
3445 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3446 hw->mac_addr[i] = hw->perm_mac_addr[i];
3450 /******************************************************************************
3451 * Initializes receive address filters.
3453 * hw - Struct containing variables accessed by shared code
3455 * Places the MAC address in receive address register 0 and clears the rest
3456 * of the receive addresss registers. Clears the multicast table. Assumes
3457 * the receiver is in reset when the routine is called.
3458 *****************************************************************************/
3460 em_init_rx_addrs(struct em_hw *hw)
3466 DEBUGFUNC("em_init_rx_addrs");
3468 /* Setup the receive address. */
3469 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3470 addr_low = (hw->mac_addr[0] |
3471 (hw->mac_addr[1] << 8) |
3472 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
3474 addr_high = (hw->mac_addr[4] |
3475 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
3477 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
3478 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
3480 /* Zero out the other 15 receive addresses. */
3481 DEBUGOUT("Clearing RAR[1-15]\n");
3482 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3483 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3484 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3488 /******************************************************************************
3489 * Updates the MAC's list of multicast addresses.
3491 * hw - Struct containing variables accessed by shared code
3492 * mc_addr_list - the list of new multicast addresses
3493 * mc_addr_count - number of addresses
3494 * pad - number of bytes between addresses in the list
3496 * The given list replaces any existing list. Clears the last 15 receive
3497 * address registers and the multicast table. Uses receive address registers
3498 * for the first 15 multicast addresses, and hashes the rest into the
3500 *****************************************************************************/
3502 em_mc_addr_list_update(struct em_hw *hw,
3503 uint8_t *mc_addr_list,
3504 uint32_t mc_addr_count,
3507 uint32_t hash_value;
3509 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
3511 DEBUGFUNC("em_mc_addr_list_update");
3513 /* Set the new number of MC addresses that we are being requested to use. */
3514 hw->num_mc_addrs = mc_addr_count;
3516 /* Clear RAR[1-15] */
3517 DEBUGOUT(" Clearing RAR[1-15]\n");
3518 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3519 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3520 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3524 DEBUGOUT(" Clearing MTA\n");
3525 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3526 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3529 /* Add the new addresses */
3530 for(i = 0; i < mc_addr_count; i++) {
3531 DEBUGOUT(" Adding the multicast addresses:\n");
3532 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3533 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3534 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3535 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3536 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3537 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3538 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3540 hash_value = em_hash_mc_addr(hw,
3542 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3544 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3546 /* Place this multicast address in the RAR if there is room, *
3547 * else put it in the MTA
3549 if(rar_used_count < E1000_RAR_ENTRIES) {
3551 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3555 em_mta_set(hw, hash_value);
3558 DEBUGOUT("MC Update Complete\n");
3561 /******************************************************************************
3562 * Hashes an address to determine its location in the multicast table
3564 * hw - Struct containing variables accessed by shared code
3565 * mc_addr - the multicast address to hash
3566 *****************************************************************************/
3568 em_hash_mc_addr(struct em_hw *hw,
3571 uint32_t hash_value = 0;
3573 /* The portion of the address that is used for the hash table is
3574 * determined by the mc_filter_type setting.
3576 switch (hw->mc_filter_type) {
3577 /* [0] [1] [2] [3] [4] [5]
3582 /* [47:36] i.e. 0x563 for above example address */
3583 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
3586 /* [46:35] i.e. 0xAC6 for above example address */
3587 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
3590 /* [45:34] i.e. 0x5D8 for above example address */
3591 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
3594 /* [43:32] i.e. 0x634 for above example address */
3595 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
3599 hash_value &= 0xFFF;
3603 /******************************************************************************
3604 * Sets the bit in the multicast table corresponding to the hash value.
3606 * hw - Struct containing variables accessed by shared code
3607 * hash_value - Multicast address hash value
3608 *****************************************************************************/
3610 em_mta_set(struct em_hw *hw,
3611 uint32_t hash_value)
3613 uint32_t hash_bit, hash_reg;
3617 /* The MTA is a register array of 128 32-bit registers.
3618 * It is treated like an array of 4096 bits. We want to set
3619 * bit BitArray[hash_value]. So we figure out what register
3620 * the bit is in, read it, OR in the new bit, then write
3621 * back the new value. The register is determined by the
3622 * upper 7 bits of the hash value and the bit within that
3623 * register are determined by the lower 5 bits of the value.
3625 hash_reg = (hash_value >> 5) & 0x7F;
3626 hash_bit = hash_value & 0x1F;
3628 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
3630 mta |= (1 << hash_bit);
3632 /* If we are on an 82544 and we are trying to write an odd offset
3633 * in the MTA, save off the previous entry before writing and
3634 * restore the old value after writing.
3636 if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
3637 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
3638 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3639 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
3641 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3645 /******************************************************************************
3646 * Puts an ethernet address into a receive address register.
3648 * hw - Struct containing variables accessed by shared code
3649 * addr - Address to put into receive address register
3650 * index - Receive address register to write
3651 *****************************************************************************/
3653 em_rar_set(struct em_hw *hw,
3657 uint32_t rar_low, rar_high;
3659 /* HW expects these in little endian so we reverse the byte order
3660 * from network order (big endian) to little endian
3662 rar_low = ((uint32_t) addr[0] |
3663 ((uint32_t) addr[1] << 8) |
3664 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
3666 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
3668 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
3669 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
3672 /******************************************************************************
3673 * Writes a value to the specified offset in the VLAN filter table.
3675 * hw - Struct containing variables accessed by shared code
3676 * offset - Offset in VLAN filer table to write
3677 * value - Value to write into VLAN filter table
3678 *****************************************************************************/
3680 em_write_vfta(struct em_hw *hw,
3686 if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
3687 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
3688 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
3689 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
3691 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
3695 /******************************************************************************
3696 * Clears the VLAN filer table
3698 * hw - Struct containing variables accessed by shared code
3699 *****************************************************************************/
3701 em_clear_vfta(struct em_hw *hw)
3705 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
3706 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
3710 em_id_led_init(struct em_hw * hw)
3713 const uint32_t ledctl_mask = 0x000000FF;
3714 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
3715 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
3716 uint16_t eeprom_data, i, temp;
3717 const uint16_t led_mask = 0x0F;
3719 DEBUGFUNC("em_id_led_init");
3721 if(hw->mac_type < em_82540) {
3726 ledctl = E1000_READ_REG(hw, LEDCTL);
3727 hw->ledctl_default = ledctl;
3728 hw->ledctl_mode1 = hw->ledctl_default;
3729 hw->ledctl_mode2 = hw->ledctl_default;
3731 if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
3732 DEBUGOUT("EEPROM Read Error\n");
3733 return -E1000_ERR_EEPROM;
3735 if((eeprom_data== ID_LED_RESERVED_0000) ||
3736 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
3737 for(i = 0; i < 4; i++) {
3738 temp = (eeprom_data >> (i << 2)) & led_mask;
3740 case ID_LED_ON1_DEF2:
3741 case ID_LED_ON1_ON2:
3742 case ID_LED_ON1_OFF2:
3743 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
3744 hw->ledctl_mode1 |= ledctl_on << (i << 3);
3746 case ID_LED_OFF1_DEF2:
3747 case ID_LED_OFF1_ON2:
3748 case ID_LED_OFF1_OFF2:
3749 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
3750 hw->ledctl_mode1 |= ledctl_off << (i << 3);
3757 case ID_LED_DEF1_ON2:
3758 case ID_LED_ON1_ON2:
3759 case ID_LED_OFF1_ON2:
3760 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
3761 hw->ledctl_mode2 |= ledctl_on << (i << 3);
3763 case ID_LED_DEF1_OFF2:
3764 case ID_LED_ON1_OFF2:
3765 case ID_LED_OFF1_OFF2:
3766 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
3767 hw->ledctl_mode2 |= ledctl_off << (i << 3);
3777 /******************************************************************************
3778 * Prepares SW controlable LED for use and saves the current state of the LED.
3780 * hw - Struct containing variables accessed by shared code
3781 *****************************************************************************/
3783 em_setup_led(struct em_hw *hw)
3787 DEBUGFUNC("em_setup_led");
3789 switch(hw->device_id) {
3790 case E1000_DEV_ID_82542:
3791 case E1000_DEV_ID_82543GC_FIBER:
3792 case E1000_DEV_ID_82543GC_COPPER:
3793 case E1000_DEV_ID_82544EI_COPPER:
3794 case E1000_DEV_ID_82544EI_FIBER:
3795 case E1000_DEV_ID_82544GC_COPPER:
3796 case E1000_DEV_ID_82544GC_LOM:
3797 /* No setup necessary */
3799 case E1000_DEV_ID_82545EM_FIBER:
3800 case E1000_DEV_ID_82546EB_FIBER:
3801 ledctl = E1000_READ_REG(hw, LEDCTL);
3802 /* Save current LEDCTL settings */
3803 hw->ledctl_default = ledctl;
3805 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
3806 E1000_LEDCTL_LED0_BLINK |
3807 E1000_LEDCTL_LED0_MODE_MASK);
3808 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
3809 E1000_WRITE_REG(hw, LEDCTL, ledctl);
3811 case E1000_DEV_ID_82540EP:
3812 case E1000_DEV_ID_82540EP_LOM:
3813 case E1000_DEV_ID_82540EP_LP:
3814 case E1000_DEV_ID_82540EM:
3815 case E1000_DEV_ID_82540EM_LOM:
3816 case E1000_DEV_ID_82545EM_COPPER:
3817 case E1000_DEV_ID_82546EB_COPPER:
3818 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3819 case E1000_DEV_ID_82541EI:
3820 case E1000_DEV_ID_82541EP:
3821 case E1000_DEV_ID_82547EI:
3822 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
3825 DEBUGOUT("Invalid device ID\n");
3826 return -E1000_ERR_CONFIG;
3831 /******************************************************************************
3832 * Restores the saved state of the SW controlable LED.
3834 * hw - Struct containing variables accessed by shared code
3835 *****************************************************************************/
3837 em_cleanup_led(struct em_hw *hw)
3839 DEBUGFUNC("em_cleanup_led");
3841 switch(hw->device_id) {
3842 case E1000_DEV_ID_82542:
3843 case E1000_DEV_ID_82543GC_FIBER:
3844 case E1000_DEV_ID_82543GC_COPPER:
3845 case E1000_DEV_ID_82544EI_COPPER:
3846 case E1000_DEV_ID_82544EI_FIBER:
3847 case E1000_DEV_ID_82544GC_COPPER:
3848 case E1000_DEV_ID_82544GC_LOM:
3849 /* No cleanup necessary */
3851 case E1000_DEV_ID_82540EP:
3852 case E1000_DEV_ID_82540EP_LOM:
3853 case E1000_DEV_ID_82540EP_LP:
3854 case E1000_DEV_ID_82540EM:
3855 case E1000_DEV_ID_82540EM_LOM:
3856 case E1000_DEV_ID_82545EM_COPPER:
3857 case E1000_DEV_ID_82545EM_FIBER:
3858 case E1000_DEV_ID_82546EB_COPPER:
3859 case E1000_DEV_ID_82546EB_FIBER:
3860 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3861 case E1000_DEV_ID_82541EI:
3862 case E1000_DEV_ID_82541EP:
3863 case E1000_DEV_ID_82547EI:
3864 /* Restore LEDCTL settings */
3865 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
3868 DEBUGOUT("Invalid device ID\n");
3869 return -E1000_ERR_CONFIG;
3874 /******************************************************************************
3875 * Turns on the software controllable LED
3877 * hw - Struct containing variables accessed by shared code
3878 *****************************************************************************/
3880 em_led_on(struct em_hw *hw)
3884 DEBUGFUNC("em_led_on");
3886 switch(hw->device_id) {
3887 case E1000_DEV_ID_82542:
3888 case E1000_DEV_ID_82543GC_FIBER:
3889 case E1000_DEV_ID_82543GC_COPPER:
3890 case E1000_DEV_ID_82544EI_FIBER:
3891 ctrl = E1000_READ_REG(hw, CTRL);
3892 /* Set SW Defineable Pin 0 to turn on the LED */
3893 ctrl |= E1000_CTRL_SWDPIN0;
3894 ctrl |= E1000_CTRL_SWDPIO0;
3895 E1000_WRITE_REG(hw, CTRL, ctrl);
3897 case E1000_DEV_ID_82544EI_COPPER:
3898 case E1000_DEV_ID_82544GC_COPPER:
3899 case E1000_DEV_ID_82544GC_LOM:
3900 case E1000_DEV_ID_82545EM_FIBER:
3901 case E1000_DEV_ID_82546EB_FIBER:
3902 ctrl = E1000_READ_REG(hw, CTRL);
3903 /* Clear SW Defineable Pin 0 to turn on the LED */
3904 ctrl &= ~E1000_CTRL_SWDPIN0;
3905 ctrl |= E1000_CTRL_SWDPIO0;
3906 E1000_WRITE_REG(hw, CTRL, ctrl);
3908 case E1000_DEV_ID_82540EP:
3909 case E1000_DEV_ID_82540EP_LOM:
3910 case E1000_DEV_ID_82540EP_LP:
3911 case E1000_DEV_ID_82540EM:
3912 case E1000_DEV_ID_82540EM_LOM:
3913 case E1000_DEV_ID_82545EM_COPPER:
3914 case E1000_DEV_ID_82546EB_COPPER:
3915 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3916 case E1000_DEV_ID_82541EI:
3917 case E1000_DEV_ID_82541EP:
3918 case E1000_DEV_ID_82547EI:
3919 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
3922 DEBUGOUT("Invalid device ID\n");
3923 return -E1000_ERR_CONFIG;
3928 /******************************************************************************
3929 * Turns off the software controllable LED
3931 * hw - Struct containing variables accessed by shared code
3932 *****************************************************************************/
3934 em_led_off(struct em_hw *hw)
3938 DEBUGFUNC("em_led_off");
3940 switch(hw->device_id) {
3941 case E1000_DEV_ID_82542:
3942 case E1000_DEV_ID_82543GC_FIBER:
3943 case E1000_DEV_ID_82543GC_COPPER:
3944 case E1000_DEV_ID_82544EI_FIBER:
3945 ctrl = E1000_READ_REG(hw, CTRL);
3946 /* Clear SW Defineable Pin 0 to turn off the LED */
3947 ctrl &= ~E1000_CTRL_SWDPIN0;
3948 ctrl |= E1000_CTRL_SWDPIO0;
3949 E1000_WRITE_REG(hw, CTRL, ctrl);
3951 case E1000_DEV_ID_82544EI_COPPER:
3952 case E1000_DEV_ID_82544GC_COPPER:
3953 case E1000_DEV_ID_82544GC_LOM:
3954 case E1000_DEV_ID_82545EM_FIBER:
3955 case E1000_DEV_ID_82546EB_FIBER:
3956 ctrl = E1000_READ_REG(hw, CTRL);
3957 /* Set SW Defineable Pin 0 to turn off the LED */
3958 ctrl |= E1000_CTRL_SWDPIN0;
3959 ctrl |= E1000_CTRL_SWDPIO0;
3960 E1000_WRITE_REG(hw, CTRL, ctrl);
3962 case E1000_DEV_ID_82540EP:
3963 case E1000_DEV_ID_82540EP_LOM:
3964 case E1000_DEV_ID_82540EP_LP:
3965 case E1000_DEV_ID_82540EM:
3966 case E1000_DEV_ID_82540EM_LOM:
3967 case E1000_DEV_ID_82545EM_COPPER:
3968 case E1000_DEV_ID_82546EB_COPPER:
3969 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3970 case E1000_DEV_ID_82541EI:
3971 case E1000_DEV_ID_82541EP:
3972 case E1000_DEV_ID_82547EI:
3973 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
3976 DEBUGOUT("Invalid device ID\n");
3977 return -E1000_ERR_CONFIG;
3982 /******************************************************************************
3983 * Clears all hardware statistics counters.
3985 * hw - Struct containing variables accessed by shared code
3986 *****************************************************************************/
3988 em_clear_hw_cntrs(struct em_hw *hw)
3990 volatile uint32_t temp;
3992 temp = E1000_READ_REG(hw, CRCERRS);
3993 temp = E1000_READ_REG(hw, SYMERRS);
3994 temp = E1000_READ_REG(hw, MPC);
3995 temp = E1000_READ_REG(hw, SCC);
3996 temp = E1000_READ_REG(hw, ECOL);
3997 temp = E1000_READ_REG(hw, MCC);
3998 temp = E1000_READ_REG(hw, LATECOL);
3999 temp = E1000_READ_REG(hw, COLC);
4000 temp = E1000_READ_REG(hw, DC);
4001 temp = E1000_READ_REG(hw, SEC);
4002 temp = E1000_READ_REG(hw, RLEC);
4003 temp = E1000_READ_REG(hw, XONRXC);
4004 temp = E1000_READ_REG(hw, XONTXC);
4005 temp = E1000_READ_REG(hw, XOFFRXC);
4006 temp = E1000_READ_REG(hw, XOFFTXC);
4007 temp = E1000_READ_REG(hw, FCRUC);
4008 temp = E1000_READ_REG(hw, PRC64);
4009 temp = E1000_READ_REG(hw, PRC127);
4010 temp = E1000_READ_REG(hw, PRC255);
4011 temp = E1000_READ_REG(hw, PRC511);
4012 temp = E1000_READ_REG(hw, PRC1023);
4013 temp = E1000_READ_REG(hw, PRC1522);
4014 temp = E1000_READ_REG(hw, GPRC);
4015 temp = E1000_READ_REG(hw, BPRC);
4016 temp = E1000_READ_REG(hw, MPRC);
4017 temp = E1000_READ_REG(hw, GPTC);
4018 temp = E1000_READ_REG(hw, GORCL);
4019 temp = E1000_READ_REG(hw, GORCH);
4020 temp = E1000_READ_REG(hw, GOTCL);
4021 temp = E1000_READ_REG(hw, GOTCH);
4022 temp = E1000_READ_REG(hw, RNBC);
4023 temp = E1000_READ_REG(hw, RUC);
4024 temp = E1000_READ_REG(hw, RFC);
4025 temp = E1000_READ_REG(hw, ROC);
4026 temp = E1000_READ_REG(hw, RJC);
4027 temp = E1000_READ_REG(hw, TORL);
4028 temp = E1000_READ_REG(hw, TORH);
4029 temp = E1000_READ_REG(hw, TOTL);
4030 temp = E1000_READ_REG(hw, TOTH);
4031 temp = E1000_READ_REG(hw, TPR);
4032 temp = E1000_READ_REG(hw, TPT);
4033 temp = E1000_READ_REG(hw, PTC64);
4034 temp = E1000_READ_REG(hw, PTC127);
4035 temp = E1000_READ_REG(hw, PTC255);
4036 temp = E1000_READ_REG(hw, PTC511);
4037 temp = E1000_READ_REG(hw, PTC1023);
4038 temp = E1000_READ_REG(hw, PTC1522);
4039 temp = E1000_READ_REG(hw, MPTC);
4040 temp = E1000_READ_REG(hw, BPTC);
4042 if(hw->mac_type < em_82543) return;
4044 temp = E1000_READ_REG(hw, ALGNERRC);
4045 temp = E1000_READ_REG(hw, RXERRC);
4046 temp = E1000_READ_REG(hw, TNCRS);
4047 temp = E1000_READ_REG(hw, CEXTERR);
4048 temp = E1000_READ_REG(hw, TSCTC);
4049 temp = E1000_READ_REG(hw, TSCTFC);
4051 if(hw->mac_type <= em_82544) return;
4053 temp = E1000_READ_REG(hw, MGTPRC);
4054 temp = E1000_READ_REG(hw, MGTPDC);
4055 temp = E1000_READ_REG(hw, MGTPTC);
4058 /******************************************************************************
4059 * Resets Adaptive IFS to its default state.
4061 * hw - Struct containing variables accessed by shared code
4063 * Call this after em_init_hw. You may override the IFS defaults by setting
4064 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4065 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4066 * before calling this function.
4067 *****************************************************************************/
4069 em_reset_adaptive(struct em_hw *hw)
4071 DEBUGFUNC("em_reset_adaptive");
4073 if(hw->adaptive_ifs) {
4074 if(!hw->ifs_params_forced) {
4075 hw->current_ifs_val = 0;
4076 hw->ifs_min_val = IFS_MIN;
4077 hw->ifs_max_val = IFS_MAX;
4078 hw->ifs_step_size = IFS_STEP;
4079 hw->ifs_ratio = IFS_RATIO;
4081 hw->in_ifs_mode = FALSE;
4082 E1000_WRITE_REG(hw, AIT, 0);
4084 DEBUGOUT("Not in Adaptive IFS mode!\n");
4088 /******************************************************************************
4089 * Called during the callback/watchdog routine to update IFS value based on
4090 * the ratio of transmits to collisions.
4092 * hw - Struct containing variables accessed by shared code
4093 * tx_packets - Number of transmits since last callback
4094 * total_collisions - Number of collisions since last callback
4095 *****************************************************************************/
4097 em_update_adaptive(struct em_hw *hw)
4099 DEBUGFUNC("em_update_adaptive");
4101 if(hw->adaptive_ifs) {
4102 if((hw->collision_delta * hw->ifs_ratio) >
4103 hw->tx_packet_delta) {
4104 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4105 hw->in_ifs_mode = TRUE;
4106 if(hw->current_ifs_val < hw->ifs_max_val) {
4107 if(hw->current_ifs_val == 0)
4108 hw->current_ifs_val = hw->ifs_min_val;
4110 hw->current_ifs_val += hw->ifs_step_size;
4111 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4115 if((hw->in_ifs_mode == TRUE) &&
4116 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4117 hw->current_ifs_val = 0;
4118 hw->in_ifs_mode = FALSE;
4119 E1000_WRITE_REG(hw, AIT, 0);
4123 DEBUGOUT("Not in Adaptive IFS mode!\n");
4127 /******************************************************************************
4128 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4130 * hw - Struct containing variables accessed by shared code
4131 * frame_len - The length of the frame in question
4132 * mac_addr - The Ethernet destination address of the frame in question
4133 *****************************************************************************/
4135 em_tbi_adjust_stats(struct em_hw *hw,
4136 struct em_hw_stats *stats,
4142 /* First adjust the frame length. */
4144 /* We need to adjust the statistics counters, since the hardware
4145 * counters overcount this packet as a CRC error and undercount
4146 * the packet as a good packet
4148 /* This packet should not be counted as a CRC error. */
4150 /* This packet does count as a Good Packet Received. */
4153 /* Adjust the Good Octets received counters */
4154 carry_bit = 0x80000000 & stats->gorcl;
4155 stats->gorcl += frame_len;
4156 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4157 * Received Count) was one before the addition,
4158 * AND it is zero after, then we lost the carry out,
4159 * need to add one to Gorch (Good Octets Received Count High).
4160 * This could be simplified if all environments supported
4163 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4165 /* Is this a broadcast or multicast? Check broadcast first,
4166 * since the test for a multicast frame will test positive on
4167 * a broadcast frame.
4169 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4170 /* Broadcast packet */
4172 else if(*mac_addr & 0x01)
4173 /* Multicast packet */
4176 if(frame_len == hw->max_frame_size) {
4177 /* In this case, the hardware has overcounted the number of
4184 /* Adjust the bin counters when the extra byte put the frame in the
4185 * wrong bin. Remember that the frame_len was adjusted above.
4187 if(frame_len == 64) {
4190 } else if(frame_len == 127) {
4193 } else if(frame_len == 255) {
4196 } else if(frame_len == 511) {
4199 } else if(frame_len == 1023) {
4202 } else if(frame_len == 1522) {
4207 /******************************************************************************
4208 * Gets the current PCI bus type, speed, and width of the hardware
4210 * hw - Struct containing variables accessed by shared code
4211 *****************************************************************************/
4213 em_get_bus_info(struct em_hw *hw)
4217 if(hw->mac_type < em_82543) {
4218 hw->bus_type = em_bus_type_unknown;
4219 hw->bus_speed = em_bus_speed_unknown;
4220 hw->bus_width = em_bus_width_unknown;
4224 status = E1000_READ_REG(hw, STATUS);
4225 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4226 em_bus_type_pcix : em_bus_type_pci;
4228 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4229 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
4230 em_bus_speed_66 : em_bus_speed_120;
4231 } else if(hw->bus_type == em_bus_type_pci) {
4232 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4233 em_bus_speed_66 : em_bus_speed_33;
4235 switch (status & E1000_STATUS_PCIX_SPEED) {
4236 case E1000_STATUS_PCIX_SPEED_66:
4237 hw->bus_speed = em_bus_speed_66;
4239 case E1000_STATUS_PCIX_SPEED_100:
4240 hw->bus_speed = em_bus_speed_100;
4242 case E1000_STATUS_PCIX_SPEED_133:
4243 hw->bus_speed = em_bus_speed_133;
4246 hw->bus_speed = em_bus_speed_reserved;
4250 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4251 em_bus_width_64 : em_bus_width_32;
4253 /******************************************************************************
4254 * Reads a value from one of the devices registers using port I/O (as opposed
4255 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4257 * hw - Struct containing variables accessed by shared code
4258 * offset - offset to read from
4259 *****************************************************************************/
4261 em_read_reg_io(struct em_hw *hw,
4264 uint32_t io_addr = hw->io_base;
4265 uint32_t io_data = hw->io_base + 4;
4267 em_io_write(hw, io_addr, offset);
4268 return em_io_read(hw, io_data);
4271 /******************************************************************************
4272 * Writes a value to one of the devices registers using port I/O (as opposed to
4273 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4275 * hw - Struct containing variables accessed by shared code
4276 * offset - offset to write to
4277 * value - value to write
4278 *****************************************************************************/
4280 em_write_reg_io(struct em_hw *hw,
4284 uint32_t io_addr = hw->io_base;
4285 uint32_t io_data = hw->io_base + 4;
4287 em_io_write(hw, io_addr, offset);
4288 em_io_write(hw, io_data, value);
4292 /******************************************************************************
4293 * Estimates the cable length.
4295 * hw - Struct containing variables accessed by shared code
4296 * min_length - The estimated minimum length
4297 * max_length - The estimated maximum length
4299 * returns: E1000_SUCCESS / -E1000_ERR_XXX
4301 * This function always returns a ranged length (minimum & maximum).
4302 * So for M88 phy's, this function interprets the one value returned from the
4303 * register to the minimum and maximum range.
4304 * For IGP phy's, the function calculates the range by the AGC registers.
4305 *****************************************************************************/
4307 em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
4308 uint16_t *max_length)
4310 uint16_t agc_value = 0;
4311 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4312 uint16_t i, phy_data;
4314 DEBUGFUNC("em_get_cable_length");
4316 *min_length = *max_length = 0;
4318 /* Use old method for Phy older than IGP */
4319 if(hw->phy_type == em_phy_m88) {
4320 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
4321 return -E1000_ERR_PHY;
4323 /* Convert the enum value to ranged values */
4324 switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4325 M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
4326 case em_cable_length_50:
4328 *max_length = em_igp_cable_length_50;
4330 case em_cable_length_50_80:
4331 *min_length = em_igp_cable_length_50;
4332 *max_length = em_igp_cable_length_80;
4334 case em_cable_length_80_110:
4335 *min_length = em_igp_cable_length_80;
4336 *max_length = em_igp_cable_length_110;
4338 case em_cable_length_110_140:
4339 *min_length = em_igp_cable_length_110;
4340 *max_length = em_igp_cable_length_140;
4342 case em_cable_length_140:
4343 *min_length = em_igp_cable_length_140;
4344 *max_length = em_igp_cable_length_170;
4347 return -E1000_ERR_PHY;
4350 } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */
4351 uint16_t agc_reg_array[IGP01E1000_PHY_AGC_NUM] = {IGP01E1000_PHY_AGC_A,
4352 IGP01E1000_PHY_AGC_B,
4353 IGP01E1000_PHY_AGC_C,
4354 IGP01E1000_PHY_AGC_D};
4355 /* Read the AGC registers for all channels */
4356 for(i = 0; i < IGP01E1000_PHY_AGC_NUM; i++) {
4357 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
4358 agc_reg_array[i]) != E1000_SUCCESS)
4359 return -E1000_ERR_PHY;
4360 if(em_read_phy_reg(hw, agc_reg_array[i] &
4361 IGP01E1000_PHY_PAGE_SELECT, &phy_data) !=
4363 return -E1000_ERR_PHY;
4365 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4367 /* Array bound check. */
4368 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4370 return -E1000_ERR_PHY;
4372 agc_value += cur_agc;
4374 /* Update minimal AGC value. */
4375 if(min_agc > cur_agc)
4379 /* Return to page 0 */
4380 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) !=
4382 return -E1000_ERR_PHY;
4384 /* Remove the minimal AGC result for length < 50m */
4385 if(agc_value < IGP01E1000_PHY_AGC_NUM * em_igp_cable_length_50) {
4386 agc_value -= min_agc;
4388 /* Get the average length of the remaining 3 channels */
4389 agc_value /= (IGP01E1000_PHY_AGC_NUM - 1);
4391 /* Get the average length of all the 4 channels. */
4392 agc_value /= IGP01E1000_PHY_AGC_NUM;
4395 /* Set the range of the calculated length. */
4396 *min_length = ((em_igp_cable_length_table[agc_value] -
4397 IGP01E1000_AGC_RANGE) > 0) ?
4398 (em_igp_cable_length_table[agc_value] -
4399 IGP01E1000_AGC_RANGE) : 0;
4400 *max_length = em_igp_cable_length_table[agc_value] +
4401 IGP01E1000_AGC_RANGE;
4404 return E1000_SUCCESS;
4407 /******************************************************************************
4408 * Check the cable polarity
4410 * hw - Struct containing variables accessed by shared code
4411 * polarity - output parameter : 0 - Polarity is not reversed
4412 * 1 - Polarity is reversed.
4414 * returns: E1000_SUCCESS / -E1000_ERR_XXX
4416 * For phy's older then IGP, this function simply reads the polarity bit in the
4417 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4418 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4419 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4420 * IGP01E1000_PHY_PCS_INIT_REG.
4421 *****************************************************************************/
4423 em_check_polarity(struct em_hw *hw, uint16_t *polarity)
4427 DEBUGFUNC("em_check_polarity");
4429 if(hw->phy_type == em_phy_m88) {
4430 /* return the Polarity bit in the Status register. */
4431 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
4432 return -E1000_ERR_PHY;
4433 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4434 M88E1000_PSSR_REV_POLARITY_SHIFT;
4435 } else if(hw->phy_type == em_phy_igp) {
4436 /* Read the Status register to check the speed */
4437 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0)
4438 return -E1000_ERR_PHY;
4440 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4441 * find the polarity status */
4442 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4443 IGP01E1000_PSSR_SPEED_1000MBPS) {
4445 /* Read the GIG initialization PCS register (0x00B4) */
4446 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
4447 IGP01E1000_PHY_PCS_INIT_REG) < 0)
4448 return -E1000_ERR_PHY;
4450 if(em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
4451 IGP01E1000_PHY_PAGE_SELECT, &phy_data) < 0)
4452 return -E1000_ERR_PHY;
4454 /* Return to page 0 */
4455 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) !=
4457 return -E1000_ERR_PHY;
4459 /* Check the polarity bits */
4460 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4462 /* For 10 Mbps, read the polarity bit in the status register. (for
4463 * 100 Mbps this bit is always 0) */
4464 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4467 return E1000_SUCCESS;
4470 /******************************************************************************
4471 * Check if Downshift occured
4473 * hw - Struct containing variables accessed by shared code
4474 * downshift - output parameter : 0 - No Downshift ocured.
4475 * 1 - Downshift ocured.
4477 * returns: E1000_SUCCESS / -E1000_ERR_XXX
4479 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4480 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4481 * Link Health register. In IGP this bit is latched high, so the driver must
4482 * read it immediately after link is established.
4483 *****************************************************************************/
4485 em_check_downshift(struct em_hw *hw)
4489 DEBUGFUNC("em_check_downshift");
4491 if(hw->phy_type == em_phy_igp) {
4492 if(em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, &phy_data) < 0) {
4493 DEBUGOUT("PHY Read Error\n");
4494 return -E1000_ERR_PHY;
4496 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4498 else if(hw->phy_type == em_phy_m88) {
4499 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
4500 DEBUGOUT("PHY Read Error\n");
4501 return -E1000_ERR_PHY;
4503 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4504 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4506 return E1000_SUCCESS;