sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35 #include <linux/workqueue.h>
  36
  37 extern struct drm_i915_private *i915_mch_dev;
  38
  39 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  40 {
  41         /*
  42          * The dri breadcrumb update races against the drm master disappearing.
  43          * Instead of trying to fix this (this is by far not the only ums issue)
  44          * just don't do the update in kms mode.
  45          */
  46         if (drm_core_check_feature(dev, DRIVER_MODESET))
  47                 return;
  48
  49         /* XXX: don't do it at all actually */
  50         return;
  51 }
  52
  53 static void i915_write_hws_pga(struct drm_device *dev)
  54 {
  55         drm_i915_private_t *dev_priv = dev->dev_private;
  56         u32 addr;
  57
  58         addr = dev_priv->status_page_dmah->busaddr;
  59         if (INTEL_INFO(dev)->gen >= 4)
  60                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  61         I915_WRITE(HWS_PGA, addr);
  62 }
  63
  64 /**
  65  * Sets up the hardware status page for devices that need a physical address
  66  * in the register.
  67  */
  68 static int i915_init_phys_hws(struct drm_device *dev)
  69 {
  70         drm_i915_private_t *dev_priv = dev->dev_private;
  71         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  72
  73         /*
  74          * Program Hardware Status Page
  75          * XXXKIB Keep 4GB limit for allocation for now.  This method
  76          * of allocation is used on <= 965 hardware, that has several
  77          * erratas regarding the use of physical memory > 4 GB.
  78          */
  79         DRM_UNLOCK(dev);
  80         dev_priv->status_page_dmah =
  81                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  82         DRM_LOCK(dev);
  83         if (!dev_priv->status_page_dmah) {
  84                 DRM_ERROR("Can not allocate hardware status page\n");
  85                 return -ENOMEM;
  86         }
  87         ring->status_page.page_addr = dev_priv->hw_status_page =
  88             dev_priv->status_page_dmah->vaddr;
  89         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  90
  91         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  92
  93         i915_write_hws_pga(dev);
  94         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  95             (uintmax_t)dev_priv->dma_status_page);
  96         return 0;
  97 }
  98
  99 /**
 100  * Frees the hardware status page, whether it's a physical address or a virtual
 101  * address set up by the X Server.
 102  */
 103 static void i915_free_hws(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 107
 108         if (dev_priv->status_page_dmah) {
 109                 drm_pci_free(dev, dev_priv->status_page_dmah);
 110                 dev_priv->status_page_dmah = NULL;
 111         }
 112
 113         if (dev_priv->status_gfx_addr) {
 114                 dev_priv->status_gfx_addr = 0;
 115                 ring->status_page.gfx_addr = 0;
 116                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117         }
 118
 119         /* Need to rewrite hardware status page */
 120         I915_WRITE(HWS_PGA, 0x1ffff000);
 121 }
 122
 123 void i915_kernel_lost_context(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 127
 128         /*
 129          * We should never lose context on the ring with modesetting
 130          * as we don't expose it to userspace
 131          */
 132         if (drm_core_check_feature(dev, DRIVER_MODESET))
 133                 return;
 134
 135         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 136         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 137         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 138         if (ring->space < 0)
 139                 ring->space += ring->size;
 140
 141 #if 1
 142         KIB_NOTYET();
 143 #else
 144         if (!dev->primary->master)
 145                 return;
 146 #endif
 147
 148         if (ring->head == ring->tail && dev_priv->sarea_priv)
 149                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 150 }
 151
 152 static int i915_dma_cleanup(struct drm_device * dev)
 153 {
 154         drm_i915_private_t *dev_priv = dev->dev_private;
 155         int i;
 156
 157
 158         /* Make sure interrupts are disabled here because the uninstall ioctl
 159          * may not have been called from userspace and after dev_private
 160          * is freed, it's too late.
 161          */
 162         if (dev->irq_enabled)
 163                 drm_irq_uninstall(dev);
 164
 165         DRM_LOCK(dev);
 166         for (i = 0; i < I915_NUM_RINGS; i++)
 167                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 168         DRM_UNLOCK(dev);
 169
 170         /* Clear the HWS virtual address at teardown */
 171         if (I915_NEED_GFX_HWS(dev))
 172                 i915_free_hws(dev);
 173
 174         return 0;
 175 }
 176
 177 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 178 {
 179         drm_i915_private_t *dev_priv = dev->dev_private;
 180         int ret;
 181
 182         dev_priv->sarea = drm_getsarea(dev);
 183         if (!dev_priv->sarea) {
 184                 DRM_ERROR("can not find sarea!\n");
 185                 i915_dma_cleanup(dev);
 186                 return -EINVAL;
 187         }
 188
 189         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 190             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 191
 192         if (init->ring_size != 0) {
 193                 if (LP_RING(dev_priv)->obj != NULL) {
 194                         i915_dma_cleanup(dev);
 195                         DRM_ERROR("Client tried to initialize ringbuffer in "
 196                                   "GEM mode\n");
 197                         return -EINVAL;
 198                 }
 199
 200                 ret = intel_render_ring_init_dri(dev,
 201                                                  init->ring_start,
 202                                                  init->ring_size);
 203                 if (ret) {
 204                         i915_dma_cleanup(dev);
 205                         return ret;
 206                 }
 207         }
 208
 209         dev_priv->cpp = init->cpp;
 210         dev_priv->back_offset = init->back_offset;
 211         dev_priv->front_offset = init->front_offset;
 212         dev_priv->current_page = 0;
 213         dev_priv->sarea_priv->pf_current_page = 0;
 214
 215         /* Allow hardware batchbuffers unless told otherwise.
 216          */
 217         dev_priv->dri1.allow_batchbuffer = 1;
 218
 219         return 0;
 220 }
 221
 222 static int i915_dma_resume(struct drm_device * dev)
 223 {
 224         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 225         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 226
 227         DRM_DEBUG("\n");
 228
 229         if (ring->virtual_start == NULL) {
 230                 DRM_ERROR("can not ioremap virtual address for"
 231                           " ring buffer\n");
 232                 return -ENOMEM;
 233         }
 234
 235         /* Program Hardware Status Page */
 236         if (!ring->status_page.page_addr) {
 237                 DRM_ERROR("Can not find hardware status page\n");
 238                 return -EINVAL;
 239         }
 240         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 241         if (ring->status_page.gfx_addr != 0)
 242                 intel_ring_setup_status_page(ring);
 243         else
 244                 i915_write_hws_pga(dev);
 245
 246         DRM_DEBUG("Enabled hardware status page\n");
 247
 248         return 0;
 249 }
 250
 251 static int i915_dma_init(struct drm_device *dev, void *data,
 252                          struct drm_file *file_priv)
 253 {
 254         drm_i915_init_t *init = data;
 255         int retcode = 0;
 256
 257         switch (init->func) {
 258         case I915_INIT_DMA:
 259                 retcode = i915_initialize(dev, init);
 260                 break;
 261         case I915_CLEANUP_DMA:
 262                 retcode = i915_dma_cleanup(dev);
 263                 break;
 264         case I915_RESUME_DMA:
 265                 retcode = i915_dma_resume(dev);
 266                 break;
 267         default:
 268                 retcode = -EINVAL;
 269                 break;
 270         }
 271
 272         return retcode;
 273 }
 274
 275 /* Implement basically the same security restrictions as hardware does
 276  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 277  *
 278  * Most of the calculations below involve calculating the size of a
 279  * particular instruction.  It's important to get the size right as
 280  * that tells us where the next instruction to check is.  Any illegal
 281  * instruction detected will be given a size of zero, which is a
 282  * signal to abort the rest of the buffer.
 283  */
 284 static int do_validate_cmd(int cmd)
 285 {
 286         switch (((cmd >> 29) & 0x7)) {
 287         case 0x0:
 288                 switch ((cmd >> 23) & 0x3f) {
 289                 case 0x0:
 290                         return 1;       /* MI_NOOP */
 291                 case 0x4:
 292                         return 1;       /* MI_FLUSH */
 293                 default:
 294                         return 0;       /* disallow everything else */
 295                 }
 296                 break;
 297         case 0x1:
 298                 return 0;       /* reserved */
 299         case 0x2:
 300                 return (cmd & 0xff) + 2;        /* 2d commands */
 301         case 0x3:
 302                 if (((cmd >> 24) & 0x1f) <= 0x18)
 303                         return 1;
 304
 305                 switch ((cmd >> 24) & 0x1f) {
 306                 case 0x1c:
 307                         return 1;
 308                 case 0x1d:
 309                         switch ((cmd >> 16) & 0xff) {
 310                         case 0x3:
 311                                 return (cmd & 0x1f) + 2;
 312                         case 0x4:
 313                                 return (cmd & 0xf) + 2;
 314                         default:
 315                                 return (cmd & 0xffff) + 2;
 316                         }
 317                 case 0x1e:
 318                         if (cmd & (1 << 23))
 319                                 return (cmd & 0xffff) + 1;
 320                         else
 321                                 return 1;
 322                 case 0x1f:
 323                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 324                                 return (cmd & 0x1ffff) + 2;
 325                         else if (cmd & (1 << 17))       /* indirect random */
 326                                 if ((cmd & 0xffff) == 0)
 327                                         return 0;       /* unknown length, too hard */
 328                                 else
 329                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 330                         else
 331                                 return 2;       /* indirect sequential */
 332                 default:
 333                         return 0;
 334                 }
 335         default:
 336                 return 0;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int validate_cmd(int cmd)
 343 {
 344         int ret = do_validate_cmd(cmd);
 345
 346 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 347
 348         return ret;
 349 }
 350
 351 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 352                           int dwords)
 353 {
 354         drm_i915_private_t *dev_priv = dev->dev_private;
 355         int i, ret;
 356
 357         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 358                 return -EINVAL;
 359
 360         ret = BEGIN_LP_RING((dwords+1)&~1);
 361         if (ret)
 362                 return ret;
 363
 364         for (i = 0; i < dwords;) {
 365                 int cmd, sz;
 366
 367                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 368                         return -EINVAL;
 369
 370                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 371                         return -EINVAL;
 372
 373                 OUT_RING(cmd);
 374
 375                 while (++i, --sz) {
 376                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 377                                                          sizeof(cmd))) {
 378                                 return -EINVAL;
 379                         }
 380                         OUT_RING(cmd);
 381                 }
 382         }
 383
 384         if (dwords & 1)
 385                 OUT_RING(0);
 386
 387         ADVANCE_LP_RING();
 388
 389         return 0;
 390 }
 391
 392 int
 393 i915_emit_box(struct drm_device *dev,
 394               struct drm_clip_rect *box,
 395               int DR1, int DR4)
 396 {
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         int ret;
 399
 400         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 401             box->y2 <= 0 || box->x2 <= 0) {
 402                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 403                           box->x1, box->y1, box->x2, box->y2);
 404                 return -EINVAL;
 405         }
 406
 407         if (INTEL_INFO(dev)->gen >= 4) {
 408                 ret = BEGIN_LP_RING(4);
 409                 if (ret)
 410                         return ret;
 411
 412                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 413                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 414                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 415                 OUT_RING(DR4);
 416         } else {
 417                 ret = BEGIN_LP_RING(6);
 418                 if (ret)
 419                         return ret;
 420
 421                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 422                 OUT_RING(DR1);
 423                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 424                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 425                 OUT_RING(DR4);
 426                 OUT_RING(0);
 427         }
 428         ADVANCE_LP_RING();
 429
 430         return 0;
 431 }
 432
 433 /* XXX: Emitting the counter should really be moved to part of the IRQ
 434  * emit. For now, do it in both places:
 435  */
 436
 437 static void i915_emit_breadcrumb(struct drm_device *dev)
 438 {
 439         drm_i915_private_t *dev_priv = dev->dev_private;
 440
 441         dev_priv->dri1.counter++;
 442         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 443                 dev_priv->dri1.counter = 0;
 444         if (dev_priv->sarea_priv)
 445                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 446
 447         if (BEGIN_LP_RING(4) == 0) {
 448                 OUT_RING(MI_STORE_DWORD_INDEX);
 449                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 450                 OUT_RING(dev_priv->dri1.counter);
 451                 OUT_RING(0);
 452                 ADVANCE_LP_RING();
 453         }
 454 }
 455
 456 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 457                                    drm_i915_cmdbuffer_t *cmd,
 458                                    struct drm_clip_rect *cliprects,
 459                                    void *cmdbuf)
 460 {
 461         int nbox = cmd->num_cliprects;
 462         int i = 0, count, ret;
 463
 464         if (cmd->sz & 0x3) {
 465                 DRM_ERROR("alignment");
 466                 return -EINVAL;
 467         }
 468
 469         i915_kernel_lost_context(dev);
 470
 471         count = nbox ? nbox : 1;
 472
 473         for (i = 0; i < count; i++) {
 474                 if (i < nbox) {
 475                         ret = i915_emit_box(dev, &cliprects[i],
 476                                             cmd->DR1, cmd->DR4);
 477                         if (ret)
 478                                 return ret;
 479                 }
 480
 481                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 482                 if (ret)
 483                         return ret;
 484         }
 485
 486         i915_emit_breadcrumb(dev);
 487         return 0;
 488 }
 489
 490 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 491                                      drm_i915_batchbuffer_t * batch,
 492                                      struct drm_clip_rect *cliprects)
 493 {
 494         struct drm_i915_private *dev_priv = dev->dev_private;
 495         int nbox = batch->num_cliprects;
 496         int i, count, ret;
 497
 498         if ((batch->start | batch->used) & 0x7) {
 499                 DRM_ERROR("alignment");
 500                 return -EINVAL;
 501         }
 502
 503         i915_kernel_lost_context(dev);
 504
 505         count = nbox ? nbox : 1;
 506         for (i = 0; i < count; i++) {
 507                 if (i < nbox) {
 508                         ret = i915_emit_box(dev, &cliprects[i],
 509                                             batch->DR1, batch->DR4);
 510                         if (ret)
 511                                 return ret;
 512                 }
 513
 514                 if (!IS_I830(dev) && !IS_845G(dev)) {
 515                         ret = BEGIN_LP_RING(2);
 516                         if (ret)
 517                                 return ret;
 518
 519                         if (INTEL_INFO(dev)->gen >= 4) {
 520                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 521                                 OUT_RING(batch->start);
 522                         } else {
 523                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 524                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 525                         }
 526                 } else {
 527                         ret = BEGIN_LP_RING(4);
 528                         if (ret)
 529                                 return ret;
 530
 531                         OUT_RING(MI_BATCH_BUFFER);
 532                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 533                         OUT_RING(batch->start + batch->used - 4);
 534                         OUT_RING(0);
 535                 }
 536                 ADVANCE_LP_RING();
 537         }
 538
 539
 540         if (IS_G4X(dev) || IS_GEN5(dev)) {
 541                 if (BEGIN_LP_RING(2) == 0) {
 542                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 543                         OUT_RING(MI_NOOP);
 544                         ADVANCE_LP_RING();
 545                 }
 546         }
 547
 548         i915_emit_breadcrumb(dev);
 549         return 0;
 550 }
 551
 552 static int i915_dispatch_flip(struct drm_device * dev)
 553 {
 554         drm_i915_private_t *dev_priv = dev->dev_private;
 555         int ret;
 556
 557         if (!dev_priv->sarea_priv)
 558                 return -EINVAL;
 559
 560         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 561                           __func__,
 562                          dev_priv->dri1.current_page,
 563                          dev_priv->sarea_priv->pf_current_page);
 564
 565         i915_kernel_lost_context(dev);
 566
 567         ret = BEGIN_LP_RING(10);
 568         if (ret)
 569                 return ret;
 570
 571         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 572         OUT_RING(0);
 573
 574         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 575         OUT_RING(0);
 576         if (dev_priv->dri1.current_page == 0) {
 577                 OUT_RING(dev_priv->dri1.back_offset);
 578                 dev_priv->dri1.current_page = 1;
 579         } else {
 580                 OUT_RING(dev_priv->dri1.front_offset);
 581                 dev_priv->dri1.current_page = 0;
 582         }
 583         OUT_RING(0);
 584
 585         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 586         OUT_RING(0);
 587
 588         ADVANCE_LP_RING();
 589
 590         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 591
 592         if (BEGIN_LP_RING(4) == 0) {
 593                 OUT_RING(MI_STORE_DWORD_INDEX);
 594                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 595                 OUT_RING(dev_priv->dri1.counter);
 596                 OUT_RING(0);
 597                 ADVANCE_LP_RING();
 598         }
 599
 600         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 601         return 0;
 602 }
 603
 604 static int i915_quiescent(struct drm_device *dev)
 605 {
 606         i915_kernel_lost_context(dev);
 607         return intel_ring_idle(LP_RING(dev->dev_private));
 608 }
 609
 610 static int
 611 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 612 {
 613         int ret;
 614
 615         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 616
 617         DRM_LOCK(dev);
 618         ret = i915_quiescent(dev);
 619         DRM_UNLOCK(dev);
 620
 621         return (ret);
 622 }
 623
 624 static int i915_batchbuffer(struct drm_device *dev, void *data,
 625                             struct drm_file *file_priv)
 626 {
 627         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 628         drm_i915_sarea_t *sarea_priv;
 629         drm_i915_batchbuffer_t *batch = data;
 630         struct drm_clip_rect *cliprects;
 631         size_t cliplen;
 632         int ret;
 633
 634         if (!dev_priv->dri1.allow_batchbuffer) {
 635                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 636                 return -EINVAL;
 637         }
 638
 639         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 640                   batch->start, batch->used, batch->num_cliprects);
 641
 642         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 643
 644         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 645         if (batch->num_cliprects < 0)
 646                 return -EFAULT;
 647         if (batch->num_cliprects != 0) {
 648                 cliprects = kmalloc(batch->num_cliprects *
 649                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 650                     M_WAITOK | M_ZERO);
 651
 652                 ret = -copyin(batch->cliprects, cliprects,
 653                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 654                 if (ret != 0) {
 655                         ret = -EFAULT;
 656                         goto fail_free;
 657                 }
 658         } else
 659                 cliprects = NULL;
 660
 661         DRM_LOCK(dev);
 662         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 663         DRM_UNLOCK(dev);
 664
 665         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 666         if (sarea_priv)
 667                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 668
 669 fail_free:
 670         drm_free(cliprects, DRM_MEM_DMA);
 671         return ret;
 672 }
 673
 674 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 675                           struct drm_file *file_priv)
 676 {
 677         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 678         drm_i915_sarea_t *sarea_priv;
 679         drm_i915_cmdbuffer_t *cmdbuf = data;
 680         struct drm_clip_rect *cliprects = NULL;
 681         void *batch_data;
 682         int ret;
 683
 684         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 685                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 686
 687         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 688
 689         if (cmdbuf->num_cliprects < 0)
 690                 return -EINVAL;
 691
 692         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 693
 694         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 695         if (ret != 0) {
 696                 ret = -EFAULT;
 697                 goto fail_batch_free;
 698         }
 699
 700         if (cmdbuf->num_cliprects) {
 701                 cliprects = kmalloc(cmdbuf->num_cliprects *
 702                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 703                     M_WAITOK | M_ZERO);
 704                 ret = -copyin(cmdbuf->cliprects, cliprects,
 705                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 706
 707                 if (ret != 0) {
 708                         ret = -EFAULT;
 709                         goto fail_clip_free;
 710                 }
 711         }
 712
 713         DRM_LOCK(dev);
 714         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 715         DRM_UNLOCK(dev);
 716         if (ret) {
 717                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 718                 goto fail_clip_free;
 719         }
 720
 721         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 722         if (sarea_priv)
 723                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 724
 725 fail_clip_free:
 726         drm_free(cliprects, DRM_MEM_DMA);
 727 fail_batch_free:
 728         drm_free(batch_data, DRM_MEM_DMA);
 729         return ret;
 730 }
 731
 732 static int i915_emit_irq(struct drm_device * dev)
 733 {
 734         drm_i915_private_t *dev_priv = dev->dev_private;
 735 #if 0
 736         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 737 #endif
 738
 739         i915_kernel_lost_context(dev);
 740
 741         DRM_DEBUG_DRIVER("\n");
 742
 743         dev_priv->dri1.counter++;
 744         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 745                 dev_priv->dri1.counter = 1;
 746         if (dev_priv->sarea_priv)
 747                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 748
 749         if (BEGIN_LP_RING(4) == 0) {
 750                 OUT_RING(MI_STORE_DWORD_INDEX);
 751                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 752                 OUT_RING(dev_priv->dri1.counter);
 753                 OUT_RING(MI_USER_INTERRUPT);
 754                 ADVANCE_LP_RING();
 755         }
 756
 757         return dev_priv->dri1.counter;
 758 }
 759
 760 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 761 {
 762         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 763 #if 0
 764         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 765 #endif
 766         int ret = 0;
 767         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 768
 769         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 770                   READ_BREADCRUMB(dev_priv));
 771
 772 #if 0
 773         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 774                 if (master_priv->sarea_priv)
 775                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 776                 return 0;
 777         }
 778
 779         if (master_priv->sarea_priv)
 780                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 781 #else
 782         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 783                 if (dev_priv->sarea_priv) {
 784                         dev_priv->sarea_priv->last_dispatch =
 785                                 READ_BREADCRUMB(dev_priv);
 786                 }
 787                 return 0;
 788         }
 789
 790         if (dev_priv->sarea_priv)
 791                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 792 #endif
 793
 794         if (ring->irq_get(ring)) {
 795                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 796                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 797                 ring->irq_put(ring);
 798         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 799                 ret = -EBUSY;
 800
 801         if (ret == -EBUSY) {
 802                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 803                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 804         }
 805
 806         return ret;
 807 }
 808
 809 /* Needs the lock as it touches the ring.
 810  */
 811 int i915_irq_emit(struct drm_device *dev, void *data,
 812                          struct drm_file *file_priv)
 813 {
 814         drm_i915_private_t *dev_priv = dev->dev_private;
 815         drm_i915_irq_emit_t *emit = data;
 816         int result;
 817
 818         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 819                 DRM_ERROR("called with no initialization\n");
 820                 return -EINVAL;
 821         }
 822
 823         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 824
 825         DRM_LOCK(dev);
 826         result = i915_emit_irq(dev);
 827         DRM_UNLOCK(dev);
 828
 829         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 830                 DRM_ERROR("copy_to_user\n");
 831                 return -EFAULT;
 832         }
 833
 834         return 0;
 835 }
 836
 837 /* Doesn't need the hardware lock.
 838  */
 839 int i915_irq_wait(struct drm_device *dev, void *data,
 840                          struct drm_file *file_priv)
 841 {
 842         drm_i915_private_t *dev_priv = dev->dev_private;
 843         drm_i915_irq_wait_t *irqwait = data;
 844
 845         if (!dev_priv) {
 846                 DRM_ERROR("called with no initialization\n");
 847                 return -EINVAL;
 848         }
 849
 850         return i915_wait_irq(dev, irqwait->irq_seq);
 851 }
 852
 853 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 854                          struct drm_file *file_priv)
 855 {
 856         drm_i915_private_t *dev_priv = dev->dev_private;
 857         drm_i915_vblank_pipe_t *pipe = data;
 858
 859         if (drm_core_check_feature(dev, DRIVER_MODESET))
 860                 return -ENODEV;
 861
 862         if (!dev_priv) {
 863                 DRM_ERROR("called with no initialization\n");
 864                 return -EINVAL;
 865         }
 866
 867         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 868
 869         return 0;
 870 }
 871
 872 /**
 873  * Schedule buffer swap at given vertical blank.
 874  */
 875 static int i915_vblank_swap(struct drm_device *dev, void *data,
 876                      struct drm_file *file_priv)
 877 {
 878         /* The delayed swap mechanism was fundamentally racy, and has been
 879          * removed.  The model was that the client requested a delayed flip/swap
 880          * from the kernel, then waited for vblank before continuing to perform
 881          * rendering.  The problem was that the kernel might wake the client
 882          * up before it dispatched the vblank swap (since the lock has to be
 883          * held while touching the ringbuffer), in which case the client would
 884          * clear and start the next frame before the swap occurred, and
 885          * flicker would occur in addition to likely missing the vblank.
 886          *
 887          * In the absence of this ioctl, userland falls back to a correct path
 888          * of waiting for a vblank, then dispatching the swap on its own.
 889          * Context switching to userland and back is plenty fast enough for
 890          * meeting the requirements of vblank swapping.
 891          */
 892         return -EINVAL;
 893 }
 894
 895 static int i915_flip_bufs(struct drm_device *dev, void *data,
 896                           struct drm_file *file_priv)
 897 {
 898         int ret;
 899
 900         DRM_DEBUG("%s\n", __func__);
 901
 902         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 903
 904         DRM_LOCK(dev);
 905         ret = i915_dispatch_flip(dev);
 906         DRM_UNLOCK(dev);
 907
 908         return ret;
 909 }
 910
 911 static int i915_getparam(struct drm_device *dev, void *data,
 912                          struct drm_file *file_priv)
 913 {
 914         drm_i915_private_t *dev_priv = dev->dev_private;
 915         drm_i915_getparam_t *param = data;
 916         int value;
 917
 918         if (!dev_priv) {
 919                 DRM_ERROR("called with no initialization\n");
 920                 return -EINVAL;
 921         }
 922
 923         switch (param->param) {
 924         case I915_PARAM_IRQ_ACTIVE:
 925                 value = dev->irq_enabled ? 1 : 0;
 926                 break;
 927         case I915_PARAM_ALLOW_BATCHBUFFER:
 928                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 929                 break;
 930         case I915_PARAM_LAST_DISPATCH:
 931                 value = READ_BREADCRUMB(dev_priv);
 932                 break;
 933         case I915_PARAM_CHIPSET_ID:
 934                 value = dev->pci_device;
 935                 break;
 936         case I915_PARAM_HAS_GEM:
 937                 value = 1;
 938                 break;
 939         case I915_PARAM_NUM_FENCES_AVAIL:
 940                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 941                 break;
 942         case I915_PARAM_HAS_OVERLAY:
 943                 value = dev_priv->overlay ? 1 : 0;
 944                 break;
 945         case I915_PARAM_HAS_PAGEFLIPPING:
 946                 value = 1;
 947                 break;
 948         case I915_PARAM_HAS_EXECBUF2:
 949                 /* depends on GEM */
 950                 value = 1;
 951                 break;
 952         case I915_PARAM_HAS_BSD:
 953                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 954                 break;
 955         case I915_PARAM_HAS_BLT:
 956                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 957                 break;
 958         case I915_PARAM_HAS_RELAXED_FENCING:
 959                 value = 1;
 960                 break;
 961         case I915_PARAM_HAS_COHERENT_RINGS:
 962                 value = 1;
 963                 break;
 964         case I915_PARAM_HAS_EXEC_CONSTANTS:
 965                 value = INTEL_INFO(dev)->gen >= 4;
 966                 break;
 967         case I915_PARAM_HAS_RELAXED_DELTA:
 968                 value = 1;
 969                 break;
 970         case I915_PARAM_HAS_GEN7_SOL_RESET:
 971                 value = 1;
 972                 break;
 973         case I915_PARAM_HAS_LLC:
 974                 value = HAS_LLC(dev);
 975                 break;
 976         case I915_PARAM_HAS_ALIASING_PPGTT:
 977                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 978                 break;
 979         case I915_PARAM_HAS_PINNED_BATCHES:
 980                 value = 1;
 981                 break;
 982         default:
 983                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 984                                  param->param);
 985                 return -EINVAL;
 986         }
 987
 988         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 989                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 990                 return -EFAULT;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static int i915_setparam(struct drm_device *dev, void *data,
 997                          struct drm_file *file_priv)
 998 {
 999         drm_i915_private_t *dev_priv = dev->dev_private;
1000         drm_i915_setparam_t *param = data;
1001
1002         if (!dev_priv) {
1003                 DRM_ERROR("called with no initialization\n");
1004                 return -EINVAL;
1005         }
1006
1007         switch (param->param) {
1008         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1009                 break;
1010         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1011                 break;
1012         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1013                 dev_priv->dri1.allow_batchbuffer = param->value;
1014                 break;
1015         case I915_SETPARAM_NUM_USED_FENCES:
1016                 if (param->value > dev_priv->num_fence_regs ||
1017                     param->value < 0)
1018                         return -EINVAL;
1019                 /* Userspace can use first N regs */
1020                 dev_priv->fence_reg_start = param->value;
1021                 break;
1022         default:
1023                 DRM_DEBUG("unknown parameter %d\n", param->param);
1024                 return -EINVAL;
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int i915_set_status_page(struct drm_device *dev, void *data,
1031                                 struct drm_file *file_priv)
1032 {
1033         drm_i915_private_t *dev_priv = dev->dev_private;
1034         drm_i915_hws_addr_t *hws = data;
1035         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1036
1037         if (!I915_NEED_GFX_HWS(dev))
1038                 return -EINVAL;
1039
1040         if (!dev_priv) {
1041                 DRM_ERROR("called with no initialization\n");
1042                 return -EINVAL;
1043         }
1044
1045         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1046         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1047                 DRM_ERROR("tried to set status page when mode setting active\n");
1048                 return 0;
1049         }
1050
1051         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1052             hws->addr & (0x1ffff<<12);
1053
1054         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1055         dev_priv->hws_map.size = 4*1024;
1056         dev_priv->hws_map.type = 0;
1057         dev_priv->hws_map.flags = 0;
1058         dev_priv->hws_map.mtrr = 0;
1059
1060         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1061         if (dev_priv->hws_map.virtual == NULL) {
1062                 i915_dma_cleanup(dev);
1063                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1064                 DRM_ERROR("can not ioremap virtual address for"
1065                                 " G33 hw status page\n");
1066                 return -ENOMEM;
1067         }
1068         ring->status_page.page_addr = dev_priv->hw_status_page =
1069             dev_priv->hws_map.virtual;
1070
1071         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1072         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1073         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1074                         dev_priv->status_gfx_addr);
1075         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1076         return 0;
1077 }
1078
1079 static int i915_load_modeset_init(struct drm_device *dev)
1080 {
1081         struct drm_i915_private *dev_priv = dev->dev_private;
1082         int ret;
1083
1084         ret = intel_parse_bios(dev);
1085         if (ret)
1086                 DRM_INFO("failed to find VBIOS tables\n");
1087
1088 #if 0
1089         /* If we have > 1 VGA cards, then we need to arbitrate access
1090          * to the common VGA resources.
1091          *
1092          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1093          * then we do not take part in VGA arbitration and the
1094          * vga_client_register() fails with -ENODEV.
1095          */
1096         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1097         if (ret && ret != -ENODEV)
1098                 goto out;
1099
1100         intel_register_dsm_handler();
1101
1102         ret = vga_switcheroo_register_client(dev->pdev,
1103                                              i915_switcheroo_set_state,
1104                                              NULL,
1105                                              i915_switcheroo_can_switch);
1106         if (ret)
1107                 goto cleanup_vga_client;
1108
1109         /* Initialise stolen first so that we may reserve preallocated
1110          * objects for the BIOS to KMS transition.
1111          */
1112         ret = i915_gem_init_stolen(dev);
1113         if (ret)
1114                 goto cleanup_vga_switcheroo;
1115 #endif
1116
1117         intel_modeset_init(dev);
1118
1119         ret = i915_gem_init(dev);
1120         if (ret)
1121                 goto cleanup_gem_stolen;
1122
1123         intel_modeset_gem_init(dev);
1124
1125         ret = drm_irq_install(dev);
1126         if (ret)
1127                 goto cleanup_gem;
1128
1129         /* Always safe in the mode setting case. */
1130         /* FIXME: do pre/post-mode set stuff in core KMS code */
1131         dev->vblank_disable_allowed = 1;
1132
1133         ret = intel_fbdev_init(dev);
1134         if (ret)
1135                 goto cleanup_irq;
1136
1137         drm_kms_helper_poll_init(dev);
1138
1139         /* We're off and running w/KMS */
1140         dev_priv->mm.suspended = 0;
1141
1142         return 0;
1143
1144 cleanup_irq:
1145         drm_irq_uninstall(dev);
1146 cleanup_gem:
1147         DRM_LOCK(dev);
1148         i915_gem_cleanup_ringbuffer(dev);
1149         DRM_UNLOCK(dev);
1150         i915_gem_cleanup_aliasing_ppgtt(dev);
1151 cleanup_gem_stolen:
1152 #if 0
1153         i915_gem_cleanup_stolen(dev);
1154 cleanup_vga_switcheroo:
1155         vga_switcheroo_unregister_client(dev->pdev);
1156 cleanup_vga_client:
1157         vga_client_register(dev->pdev, NULL, NULL, NULL);
1158 out:
1159 #endif
1160         return ret;
1161 }
1162
1163 static int i915_get_bridge_dev(struct drm_device *dev)
1164 {
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166
1167         dev_priv->bridge_dev = pci_find_dbsf(0, 0, 0, 0);
1168         if (!dev_priv->bridge_dev) {
1169                 DRM_ERROR("bridge device not found\n");
1170                 return -1;
1171         }
1172         return 0;
1173 }
1174
1175 #define MCHBAR_I915 0x44
1176 #define MCHBAR_I965 0x48
1177 #define MCHBAR_SIZE (4*4096)
1178
1179 #define DEVEN_REG 0x54
1180 #define   DEVEN_MCHBAR_EN (1 << 28)
1181
1182 /* Allocate space for the MCH regs if needed, return nonzero on error */
1183 static int
1184 intel_alloc_mchbar_resource(struct drm_device *dev)
1185 {
1186         drm_i915_private_t *dev_priv;
1187         device_t vga;
1188         int reg;
1189         u32 temp_lo, temp_hi;
1190         u64 mchbar_addr, temp;
1191
1192         dev_priv = dev->dev_private;
1193         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1194
1195         if (INTEL_INFO(dev)->gen >= 4)
1196                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1197         else
1198                 temp_hi = 0;
1199         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1200         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1201
1202         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1203 #ifdef XXX_CONFIG_PNP
1204         if (mchbar_addr &&
1205             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1206                 return 0;
1207 #endif
1208
1209         /* Get some space for it */
1210         vga = device_get_parent(dev->dev);
1211         dev_priv->mch_res_rid = 0x100;
1212         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1213             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1214             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1215         if (dev_priv->mch_res == NULL) {
1216                 DRM_ERROR("failed mchbar resource alloc\n");
1217                 return (-ENOMEM);
1218         }
1219
1220         if (INTEL_INFO(dev)->gen >= 4) {
1221                 temp = rman_get_start(dev_priv->mch_res);
1222                 temp >>= 32;
1223                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1224         }
1225         pci_write_config(dev_priv->bridge_dev, reg,
1226             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1227         return (0);
1228 }
1229
1230 static void
1231 intel_setup_mchbar(struct drm_device *dev)
1232 {
1233         drm_i915_private_t *dev_priv;
1234         int mchbar_reg;
1235         u32 temp;
1236         bool enabled;
1237
1238         dev_priv = dev->dev_private;
1239         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1240
1241         dev_priv->mchbar_need_disable = false;
1242
1243         if (IS_I915G(dev) || IS_I915GM(dev)) {
1244                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1245                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1246         } else {
1247                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1248                 enabled = temp & 1;
1249         }
1250
1251         /* If it's already enabled, don't have to do anything */
1252         if (enabled) {
1253                 DRM_DEBUG("mchbar already enabled\n");
1254                 return;
1255         }
1256
1257         if (intel_alloc_mchbar_resource(dev))
1258                 return;
1259
1260         dev_priv->mchbar_need_disable = true;
1261
1262         /* Space is allocated or reserved, so enable it. */
1263         if (IS_I915G(dev) || IS_I915GM(dev)) {
1264                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1265                     temp | DEVEN_MCHBAR_EN, 4);
1266         } else {
1267                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1268                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1269         }
1270 }
1271
1272 static void
1273 intel_teardown_mchbar(struct drm_device *dev)
1274 {
1275         drm_i915_private_t *dev_priv;
1276         device_t vga;
1277         int mchbar_reg;
1278         u32 temp;
1279
1280         dev_priv = dev->dev_private;
1281         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1282
1283         if (dev_priv->mchbar_need_disable) {
1284                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1285                         temp = pci_read_config(dev_priv->bridge_dev,
1286                             DEVEN_REG, 4);
1287                         temp &= ~DEVEN_MCHBAR_EN;
1288                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1289                             temp, 4);
1290                 } else {
1291                         temp = pci_read_config(dev_priv->bridge_dev,
1292                             mchbar_reg, 4);
1293                         temp &= ~1;
1294                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1295                             temp, 4);
1296                 }
1297         }
1298
1299         if (dev_priv->mch_res != NULL) {
1300                 vga = device_get_parent(dev->dev);
1301                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1302                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1303                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1304                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1305                 dev_priv->mch_res = NULL;
1306         }
1307 }
1308
1309 /**
1310  * i915_driver_load - setup chip and create an initial config
1311  * @dev: DRM device
1312  * @flags: startup flags
1313  *
1314  * The driver load routine has to do several things:
1315  *   - drive output discovery via intel_modeset_init()
1316  *   - initialize the memory manager
1317  *   - allocate initial config memory
1318  *   - setup the DRM framebuffer with the allocated memory
1319  */
1320 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1321 {
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         unsigned long base, size;
1324         int mmio_bar, ret;
1325
1326         ret = 0;
1327
1328         /* i915 has 4 more counters */
1329         dev->counters += 4;
1330         dev->types[6] = _DRM_STAT_IRQ;
1331         dev->types[7] = _DRM_STAT_PRIMARY;
1332         dev->types[8] = _DRM_STAT_SECONDARY;
1333         dev->types[9] = _DRM_STAT_DMA;
1334
1335         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1336             M_ZERO | M_WAITOK);
1337         if (dev_priv == NULL)
1338                 return -ENOMEM;
1339
1340         dev->dev_private = (void *)dev_priv;
1341         dev_priv->dev = dev;
1342         dev_priv->info = i915_get_device_id(dev->pci_device);
1343
1344         if (i915_get_bridge_dev(dev)) {
1345                 drm_free(dev_priv, DRM_MEM_DRIVER);
1346                 return (-EIO);
1347         }
1348         dev_priv->mm.gtt = intel_gtt_get();
1349
1350         /* Add register map (needed for suspend/resume) */
1351         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1352         base = drm_get_resource_start(dev, mmio_bar);
1353         size = drm_get_resource_len(dev, mmio_bar);
1354
1355         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1356             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1357
1358         /* The i915 workqueue is primarily used for batched retirement of
1359          * requests (and thus managing bo) once the task has been completed
1360          * by the GPU. i915_gem_retire_requests() is called directly when we
1361          * need high-priority retirement, such as waiting for an explicit
1362          * bo.
1363          *
1364          * It is also used for periodic low-priority events, such as
1365          * idle-timers and recording error state.
1366          *
1367          * All tasks on the workqueue are expected to acquire the dev mutex
1368          * so there is no point in running more than one instance of the
1369          * workqueue at any time.  Use an ordered one.
1370          */
1371         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1372         if (dev_priv->wq == NULL) {
1373                 DRM_ERROR("Failed to create our workqueue.\n");
1374                 ret = -ENOMEM;
1375                 goto out_mtrrfree;
1376         }
1377
1378         /* This must be called before any calls to HAS_PCH_* */
1379         intel_detect_pch(dev);
1380
1381         intel_irq_init(dev);
1382         intel_gt_init(dev);
1383
1384         /* Try to make sure MCHBAR is enabled before poking at it */
1385         intel_setup_mchbar(dev);
1386         intel_setup_gmbus(dev);
1387         intel_opregion_setup(dev);
1388
1389         intel_setup_bios(dev);
1390
1391         i915_gem_load(dev);
1392
1393         /* On the 945G/GM, the chipset reports the MSI capability on the
1394          * integrated graphics even though the support isn't actually there
1395          * according to the published specs.  It doesn't appear to function
1396          * correctly in testing on 945G.
1397          * This may be a side effect of MSI having been made available for PEG
1398          * and the registers being closely associated.
1399          *
1400          * According to chipset errata, on the 965GM, MSI interrupts may
1401          * be lost or delayed, but we use them anyways to avoid
1402          * stuck interrupts on some machines.
1403          */
1404
1405         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1406         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1407         spin_init(&dev_priv->rps.lock);
1408         spin_init(&dev_priv->dpio_lock);
1409
1410         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1411
1412         /* Init HWS */
1413         if (!I915_NEED_GFX_HWS(dev)) {
1414                 ret = i915_init_phys_hws(dev);
1415                 if (ret != 0) {
1416                         drm_rmmap(dev, dev_priv->mmio_map);
1417                         drm_free(dev_priv, DRM_MEM_DRIVER);
1418                         return ret;
1419                 }
1420         }
1421
1422         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1423                 dev_priv->num_pipe = 3;
1424         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1425                 dev_priv->num_pipe = 2;
1426         else
1427                 dev_priv->num_pipe = 1;
1428
1429         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1430         if (ret)
1431                 goto out_gem_unload;
1432
1433         /* Start out suspended */
1434         dev_priv->mm.suspended = 1;
1435
1436         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1437                 ret = i915_load_modeset_init(dev);
1438                 if (ret < 0) {
1439                         DRM_ERROR("failed to init modeset\n");
1440                         goto out_gem_unload;
1441                 }
1442         }
1443
1444         /* Must be done after probing outputs */
1445         intel_opregion_init(dev);
1446
1447         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1448                     (unsigned long) dev);
1449
1450         if (IS_GEN5(dev)) {
1451                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1452                 i915_mch_dev = dev_priv;
1453                 dev_priv->mchdev_lock = &mchdev_lock;
1454                 lockmgr(&mchdev_lock, LK_RELEASE);
1455         }
1456
1457         return 0;
1458
1459 out_gem_unload:
1460         intel_teardown_gmbus(dev);
1461         intel_teardown_mchbar(dev);
1462         destroy_workqueue(dev_priv->wq);
1463 out_mtrrfree:
1464         return ret;
1465 }
1466
1467 int i915_driver_unload(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470         int ret;
1471
1472         intel_gpu_ips_teardown();
1473
1474         DRM_LOCK(dev);
1475         ret = i915_gpu_idle(dev);
1476         if (ret)
1477                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1478         i915_gem_retire_requests(dev);
1479         DRM_UNLOCK(dev);
1480
1481         /* Cancel the retire work handler, which should be idle now. */
1482         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1483
1484         i915_free_hws(dev);
1485
1486         intel_teardown_mchbar(dev);
1487
1488         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1489                 intel_fbdev_fini(dev);
1490                 intel_modeset_cleanup(dev);
1491         }
1492
1493         /* Free error state after interrupts are fully disabled. */
1494         del_timer_sync(&dev_priv->hangcheck_timer);
1495         cancel_work_sync(&dev_priv->error_work);
1496         i915_destroy_error_state(dev);
1497
1498         intel_opregion_fini(dev);
1499
1500         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1501                 /* Flush any outstanding unpin_work. */
1502                 flush_workqueue(dev_priv->wq);
1503
1504                 DRM_LOCK(dev);
1505                 i915_gem_free_all_phys_object(dev);
1506                 i915_gem_cleanup_ringbuffer(dev);
1507                 DRM_UNLOCK(dev);
1508                 i915_gem_cleanup_aliasing_ppgtt(dev);
1509                 drm_mm_takedown(&dev_priv->mm.stolen);
1510
1511                 intel_cleanup_overlay(dev);
1512
1513                 if (!I915_NEED_GFX_HWS(dev))
1514                         i915_free_hws(dev);
1515         }
1516
1517         i915_gem_unload(dev);
1518
1519         bus_generic_detach(dev->dev);
1520         drm_rmmap(dev, dev_priv->mmio_map);
1521         intel_teardown_gmbus(dev);
1522
1523         destroy_workqueue(dev_priv->wq);
1524
1525         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1526
1527         return 0;
1528 }
1529
1530 int
1531 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1532 {
1533         struct drm_i915_file_private *i915_file_priv;
1534
1535         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1536             M_WAITOK | M_ZERO);
1537
1538         spin_init(&i915_file_priv->mm.lock);
1539         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1540         file_priv->driver_priv = i915_file_priv;
1541
1542         return (0);
1543 }
1544
1545 void
1546 i915_driver_lastclose(struct drm_device * dev)
1547 {
1548         drm_i915_private_t *dev_priv = dev->dev_private;
1549
1550         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1551 #if 1
1552                 KIB_NOTYET();
1553 #else
1554                 drm_fb_helper_restore();
1555                 vga_switcheroo_process_delayed_switch();
1556 #endif
1557                 return;
1558         }
1559         i915_gem_lastclose(dev);
1560         i915_dma_cleanup(dev);
1561 }
1562
1563 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1564 {
1565
1566         i915_gem_release(dev, file_priv);
1567 }
1568
1569 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1570 {
1571         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1572
1573         spin_uninit(&i915_file_priv->mm.lock);
1574         drm_free(i915_file_priv, DRM_MEM_FILES);
1575 }
1576
1577 struct drm_ioctl_desc i915_ioctls[] = {
1578         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1579         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1580         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1581         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1582         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1583         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1584         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1585         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1586         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1587         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1588         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1589         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1590         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1591         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1592         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1593         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1594         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1595         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1596         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1597         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1598         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1599         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1600         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1601         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1602         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1603         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1604         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1605         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1606         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1607         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1608         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1609         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1610         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1611         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1612         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1613         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1614         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1615         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1616         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1617         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1618         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1619         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1620 };
1621
1622 struct drm_driver i915_driver_info = {
1623         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1624             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1625             DRIVER_GEM /*| DRIVER_MODESET*/,
1626
1627         .buf_priv_size  = sizeof(drm_i915_private_t),
1628         .load           = i915_driver_load,
1629         .open           = i915_driver_open,
1630         .unload         = i915_driver_unload,
1631         .preclose       = i915_driver_preclose,
1632         .lastclose      = i915_driver_lastclose,
1633         .postclose      = i915_driver_postclose,
1634         .device_is_agp  = i915_driver_device_is_agp,
1635         .gem_init_object = i915_gem_init_object,
1636         .gem_free_object = i915_gem_free_object,
1637         .gem_pager_ops  = &i915_gem_pager_ops,
1638         .dumb_create    = i915_gem_dumb_create,
1639         .dumb_map_offset = i915_gem_mmap_gtt,
1640         .dumb_destroy   = i915_gem_dumb_destroy,
1641         .sysctl_init    = i915_sysctl_init,
1642         .sysctl_cleanup = i915_sysctl_cleanup,
1643
1644         .ioctls         = i915_ioctls,
1645         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1646
1647         .name           = DRIVER_NAME,
1648         .desc           = DRIVER_DESC,
1649         .date           = DRIVER_DATE,
1650         .major          = DRIVER_MAJOR,
1651         .minor          = DRIVER_MINOR,
1652         .patchlevel     = DRIVER_PATCHLEVEL,
1653 };
1654
1655 /**
1656  * Determine if the device really is AGP or not.
1657  *
1658  * All Intel graphics chipsets are treated as AGP, even if they are really
1659  * built-in.
1660  *
1661  * \param dev   The device to be tested.
1662  *
1663  * \returns
1664  * A value of 1 is always retured to indictate every i9x5 is AGP.
1665  */
1666 int i915_driver_device_is_agp(struct drm_device * dev)
1667 {
1668         return 1;
1669 }