2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/Attic/mpapic.c,v 1.2 2003/06/17 04:28:35 dillon Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <machine/smptests.h> /** TEST_TEST1, GRAB_LOPRIO */
33 #include <machine/smp.h>
34 #include <machine/mpapic.h>
35 #include <machine/segments.h>
37 #include <i386/isa/intr_machdep.h> /* Xspuriousint() */
39 /* EISA Edge/Level trigger control registers */
40 #define ELCR0 0x4d0 /* eisa irq 0-7 */
41 #define ELCR1 0x4d1 /* eisa irq 8-15 */
44 * pointers to pmapped apic hardware.
48 volatile ioapic_t **ioapic;
52 * Enable APIC, configure interrupts.
59 /* setup LVT1 as ExtINT */
60 temp = lapic.lvt_lint0;
61 temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
63 temp |= 0x00000700; /* process ExtInts */
65 temp |= 0x00010700; /* mask ExtInts */
66 lapic.lvt_lint0 = temp;
68 /* setup LVT2 as NMI, masked till later... */
69 temp = lapic.lvt_lint1;
70 temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
71 temp |= 0x00010400; /* masked, edge trigger, active hi */
72 lapic.lvt_lint1 = temp;
74 /* set the Task Priority Register as needed */
76 temp &= ~APIC_TPR_PRIO; /* clear priority field */
78 /* Leave the BSP at TPR 0 during boot to make sure it gets interrupts */
80 temp |= LOPRIO_LEVEL; /* allow INT arbitration */
84 /* enable the local APIC */
86 temp |= APIC_SVR_SWEN; /* software enable APIC */
87 temp &= ~APIC_SVR_FOCUS; /* enable 'focus processor' */
89 /* set the 'spurious INT' vector */
90 if ((XSPURIOUSINT_OFFSET & APIC_SVR_VEC_FIX) != APIC_SVR_VEC_FIX)
91 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
92 temp &= ~APIC_SVR_VEC_PROG; /* clear (programmable) vector field */
93 temp |= (XSPURIOUSINT_OFFSET & APIC_SVR_VEC_PROG);
95 #if defined(TEST_TEST1)
96 if (cpuid == GUARD_CPU) {
97 temp &= ~APIC_SVR_SWEN; /* software DISABLE APIC */
99 #endif /** TEST_TEST1 */
104 apic_dump("apic_initialize()");
109 * dump contents of local APIC registers
114 printf("SMP: CPU%d %s:\n", cpuid, str);
115 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
116 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
126 #define IOAPIC_ISA_INTS 16
127 #define REDIRCNT_IOAPIC(A) \
128 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
130 static int trigger __P((int apic, int pin, u_int32_t * flags));
131 static void polarity __P((int apic, int pin, u_int32_t * flags, int level));
133 #define DEFAULT_FLAGS \
139 #define DEFAULT_ISA_FLAGS \
148 io_apic_set_id(int apic, int id)
152 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
153 if (((ux & APIC_ID_MASK) >> 24) != id) {
154 printf("Changing APIC ID for IO APIC #%d"
155 " from %d to %d on chip\n",
156 apic, ((ux & APIC_ID_MASK) >> 24), id);
157 ux &= ~APIC_ID_MASK; /* clear the ID field */
159 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
160 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
161 if (((ux & APIC_ID_MASK) >> 24) != id)
162 panic("can't control IO APIC #%d ID, reg: 0x%08x",
169 io_apic_get_id(int apic)
171 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
180 extern int apic_pin_trigger; /* 'opaque' */
183 io_apic_setup_intpin(int apic, int pin)
185 int bus, bustype, irq;
186 u_char select; /* the select register is 8 bits */
187 u_int32_t flags; /* the window register is 32 bits */
188 u_int32_t target; /* the window register is 32 bits */
189 u_int32_t vector; /* the window register is 32 bits */
195 select = pin * 2 + IOAPIC_REDTBL0; /* register */
197 * Always disable interrupts, and by default map
198 * pin X to IRQX because the disable doesn't stick
199 * and the uninitialize vector will get translated
202 * This is correct for IRQs 1 and 3-15. In the other cases,
203 * any robust driver will handle the spurious interrupt, and
204 * the effective NOP beats a panic.
206 * A dedicated "bogus interrupt" entry in the IDT would
207 * be a nicer hack, although some one should find out
208 * why some systems are generating interrupts when they
209 * shouldn't and stop the carnage.
211 vector = NRSVIDT + pin; /* IDT vec */
212 eflags = read_eflags();
213 __asm __volatile("cli" : : : "memory");
215 io_apic_write(apic, select,
216 (io_apic_read(apic, select) & ~IOART_INTMASK
217 & ~0xff)|IOART_INTMSET|vector);
218 s_unlock(&imen_lock);
219 write_eflags(eflags);
221 /* we only deal with vectored INTs here */
222 if (apic_int_type(apic, pin) != 0)
225 irq = apic_irq(apic, pin);
229 /* determine the bus type for this pin */
230 bus = apic_src_bus_id(apic, pin);
233 bustype = apic_bus_type(bus);
235 if ((bustype == ISA) &&
236 (pin < IOAPIC_ISA_INTS) &&
238 (apic_polarity(apic, pin) == 0x1) &&
239 (apic_trigger(apic, pin) == 0x3)) {
241 * A broken BIOS might describe some ISA
242 * interrupts as active-high level-triggered.
243 * Use default ISA flags for those interrupts.
245 flags = DEFAULT_ISA_FLAGS;
248 * Program polarity and trigger mode according to
251 flags = DEFAULT_FLAGS;
252 level = trigger(apic, pin, &flags);
254 apic_pin_trigger |= (1 << irq);
255 polarity(apic, pin, &flags, level);
258 /* program the appropriate registers */
259 if (apic != 0 || pin != irq)
260 printf("IOAPIC #%d intpin %d -> irq %d\n",
262 vector = NRSVIDT + irq; /* IDT vec */
263 eflags = read_eflags();
264 __asm __volatile("cli" : : : "memory");
266 io_apic_write(apic, select, flags | vector);
267 io_apic_write(apic, select + 1, target);
268 s_unlock(&imen_lock);
269 write_eflags(eflags);
273 io_apic_setup(int apic)
279 apic_pin_trigger = 0; /* default to edge-triggered */
281 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
282 printf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
284 for (pin = 0; pin < maxpin; ++pin) {
285 io_apic_setup_intpin(apic, pin);
288 /* return GOOD status */
291 #undef DEFAULT_ISA_FLAGS
295 #define DEFAULT_EXTINT_FLAGS \
304 * Setup the source of External INTerrupts.
307 ext_int_setup(int apic, int intr)
309 u_char select; /* the select register is 8 bits */
310 u_int32_t flags; /* the window register is 32 bits */
311 u_int32_t target; /* the window register is 32 bits */
312 u_int32_t vector; /* the window register is 32 bits */
314 if (apic_int_type(apic, intr) != 3)
318 select = IOAPIC_REDTBL0 + (2 * intr);
319 vector = NRSVIDT + intr;
320 flags = DEFAULT_EXTINT_FLAGS;
322 io_apic_write(apic, select, flags | vector);
323 io_apic_write(apic, select + 1, target);
327 #undef DEFAULT_EXTINT_FLAGS
331 * Set the trigger level for an IO APIC pin.
334 trigger(int apic, int pin, u_int32_t * flags)
339 static int intcontrol = -1;
341 switch (apic_trigger(apic, pin)) {
347 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
351 *flags |= IOART_TRGRLVL;
359 if ((id = apic_src_bus_id(apic, pin)) == -1)
362 switch (apic_bus_type(id)) {
364 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
368 eirq = apic_src_bus_irq(apic, pin);
370 if (eirq < 0 || eirq > 15) {
371 printf("EISA IRQ %d?!?!\n", eirq);
375 if (intcontrol == -1) {
376 intcontrol = inb(ELCR1) << 8;
377 intcontrol |= inb(ELCR0);
378 printf("EISA INTCONTROL = %08x\n", intcontrol);
381 /* Use ELCR settings to determine level or edge mode */
382 level = (intcontrol >> eirq) & 1;
385 * Note that on older Neptune chipset based systems, any
386 * pci interrupts often show up here and in the ELCR as well
387 * as level sensitive interrupts attributed to the EISA bus.
391 *flags |= IOART_TRGRLVL;
393 *flags &= ~IOART_TRGRLVL;
398 *flags |= IOART_TRGRLVL;
407 panic("bad APIC IO INT flags");
412 * Set the polarity value for an IO APIC pin.
415 polarity(int apic, int pin, u_int32_t * flags, int level)
419 switch (apic_polarity(apic, pin)) {
425 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
429 *flags |= IOART_INTALO;
437 if ((id = apic_src_bus_id(apic, pin)) == -1)
440 switch (apic_bus_type(id)) {
442 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
446 /* polarity converter always gives active high */
447 *flags &= ~IOART_INTALO;
451 *flags |= IOART_INTALO;
460 panic("bad APIC IO INT flags");
465 * Print contents of apic_imen.
467 extern u_int apic_imen; /* keep apic_imen 'opaque' */
473 printf("SMP: enabled INTs: ");
474 for (x = 0; x < 24; ++x)
475 if ((apic_imen & (1 << x)) == 0)
477 printf("apic_imen: 0x%08x\n", apic_imen);
482 * Inter Processor Interrupt functions.
487 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
489 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
490 * vector is any valid SYSTEM INT vector
491 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
493 #define DETECT_DEADLOCK
495 apic_ipi(int dest_type, int vector, int delivery_mode)
499 #if defined(DETECT_DEADLOCK)
500 #define MAX_SPIN1 10000000
501 #define MAX_SPIN2 1000
504 /* "lazy delivery", ie we only barf if they stack up on us... */
505 for (x = MAX_SPIN1; x; --x) {
506 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
510 panic("apic_ipi was stuck");
511 #endif /* DETECT_DEADLOCK */
514 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
515 | dest_type | delivery_mode | vector;
518 lapic.icr_lo = icr_lo;
520 /* wait for pending status end */
521 #if defined(DETECT_DEADLOCK)
522 for (x = MAX_SPIN2; x; --x) {
523 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
526 #ifdef needsattention
529 * The above loop waits for the message to actually be delivered.
530 * It breaks out after an arbitrary timout on the theory that it eventually
531 * will be delivered and we will catch a real failure on the next entry to
532 * this function, which would panic().
533 * We could skip this wait entirely, EXCEPT it probably protects us from
534 * other "less robust" routines that assume the message was delivered and
535 * acted upon when this function returns. TLB shootdowns are one such
536 * "less robust" function.
539 printf("apic_ipi might be stuck\n");
544 while (lapic.icr_lo & APIC_DELSTAT_MASK)
546 #endif /* DETECT_DEADLOCK */
548 /** XXX FIXME: return result */
553 apic_ipi_singledest(int cpu, int vector, int delivery_mode)
559 #if defined(DETECT_DEADLOCK)
560 #define MAX_SPIN1 10000000
561 #define MAX_SPIN2 1000
564 /* "lazy delivery", ie we only barf if they stack up on us... */
565 for (x = MAX_SPIN1; x; --x) {
566 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
570 panic("apic_ipi was stuck");
571 #endif /* DETECT_DEADLOCK */
573 eflags = read_eflags();
574 __asm __volatile("cli" : : : "memory");
575 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
576 icr_hi |= (CPU_TO_ID(cpu) << 24);
577 lapic.icr_hi = icr_hi;
580 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
581 | APIC_DEST_DESTFLD | delivery_mode | vector;
584 lapic.icr_lo = icr_lo;
585 write_eflags(eflags);
587 /* wait for pending status end */
588 #if defined(DETECT_DEADLOCK)
589 for (x = MAX_SPIN2; x; --x) {
590 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
593 #ifdef needsattention
596 * The above loop waits for the message to actually be delivered.
597 * It breaks out after an arbitrary timout on the theory that it eventually
598 * will be delivered and we will catch a real failure on the next entry to
599 * this function, which would panic().
600 * We could skip this wait entirely, EXCEPT it probably protects us from
601 * other "less robust" routines that assume the message was delivered and
602 * acted upon when this function returns. TLB shootdowns are one such
603 * "less robust" function.
606 printf("apic_ipi might be stuck\n");
611 while (lapic.icr_lo & APIC_DELSTAT_MASK)
613 #endif /* DETECT_DEADLOCK */
615 /** XXX FIXME: return result */
621 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
623 * target contains a bitfield with a bit set for selected APICs.
624 * vector is any valid SYSTEM INT vector
625 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
628 selected_apic_ipi(u_int target, int vector, int delivery_mode)
633 if (target & ~0x7fff)
634 return -1; /* only 15 targets allowed */
636 for (status = 0, x = 0; x <= 14; ++x)
637 if (target & (1 << x)) {
640 if (apic_ipi_singledest(x, vector,
641 delivery_mode) == -1)
650 * Send an IPI INTerrupt containing 'vector' to CPU 'target'
651 * NOTE: target is a LOGICAL APIC ID
654 selected_proc_ipi(int target, int vector)
659 /* write the destination field for the target AP */
660 icr_hi = (lapic.icr_hi & ~APIC_ID_MASK) |
661 (cpu_num_to_apic_id[target] << 24);
662 lapic.icr_hi = icr_hi;
665 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) |
666 APIC_DEST_DESTFLD | APIC_DELMODE_FIXED | vector;
667 lapic.icr_lo = icr_lo;
669 /* wait for pending status end */
670 while (lapic.icr_lo & APIC_DELSTAT_MASK)
673 return 0; /** XXX FIXME: return result */
681 * Timer code, in development...
682 * - suggested by rgrimes@gndrsh.aac.dev.com
685 /** XXX FIXME: temp hack till we can determin bus clock */
687 #define BUS_CLOCK 66000000
688 #define bus_clock() 66000000
692 int acquire_apic_timer __P((void));
693 int release_apic_timer __P((void));
696 * Acquire the APIC timer for exclusive use.
699 acquire_apic_timer(void)
704 /** XXX FIXME: make this really do something */
705 panic("APIC timer in use when attempting to aquire");
711 * Return the APIC timer.
714 release_apic_timer(void)
719 /** XXX FIXME: make this really do something */
720 panic("APIC timer was already released");
727 * Load a 'downcount time' in uSeconds.
730 set_apic_timer(int value)
733 long ticks_per_microsec;
736 * Calculate divisor and count from value:
738 * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128]
739 * value == time in uS
741 lapic.dcr_timer = APIC_TDCR_1;
742 ticks_per_microsec = bus_clock() / 1000000;
744 /* configure timer as one-shot */
745 lvtt = lapic.lvt_timer;
746 lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS | APIC_LVTT_M | APIC_LVTT_TM);
747 lvtt |= APIC_LVTT_M; /* no INT, one-shot */
748 lapic.lvt_timer = lvtt;
751 lapic.icr_timer = value * ticks_per_microsec;
756 * Read remaining time in timer.
759 read_apic_timer(void)
762 /** XXX FIXME: we need to return the actual remaining time,
763 * for now we just return the remaining count.
766 return lapic.ccr_timer;
772 * Spin-style delay, set delay time in uS, spin till it drains.
777 set_apic_timer(count);
778 while (read_apic_timer())