2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
35 * Functions to provide access to special i386 instructions.
36 * This in included in sys/systm.h, and that file should be
37 * used in preference to this.
40 #ifndef _CPU_CPUFUNC_H_
41 #define _CPU_CPUFUNC_H_
43 #include <sys/cdefs.h>
44 #include <sys/thread.h>
45 #include <machine/psl.h>
46 #include <machine/smp.h>
49 struct region_descriptor;
52 #define readb(va) (*(volatile u_int8_t *) (va))
53 #define readw(va) (*(volatile u_int16_t *) (va))
54 #define readl(va) (*(volatile u_int32_t *) (va))
55 #define readq(va) (*(volatile u_int64_t *) (va))
57 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
58 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
59 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
60 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
64 #include <machine/lock.h> /* XXX */
69 __asm __volatile("int $3");
75 __asm __volatile("pause":::"memory");
83 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
87 static __inline u_long
92 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
96 static __inline u_long
101 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
105 static __inline u_int
110 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
114 static __inline u_long
119 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
126 __asm __volatile("clflush %0" : : "m" (*(char *) addr));
130 do_cpuid(u_int ax, u_int *p)
132 __asm __volatile("cpuid"
133 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
138 cpuid_count(u_int ax, u_int cx, u_int *p)
140 __asm __volatile("cpuid"
141 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
142 : "0" (ax), "c" (cx));
145 #ifndef _CPU_DISABLE_INTR_DEFINED
148 cpu_disable_intr(void)
150 __asm __volatile("cli" : : : "memory");
155 #ifndef _CPU_ENABLE_INTR_DEFINED
158 cpu_enable_intr(void)
160 __asm __volatile("sti");
166 * Cpu and compiler memory ordering fence. mfence ensures strong read and
169 * A serializing or fence instruction is required here. A locked bus
170 * cycle on data for which we already own cache mastership is the most
176 __asm __volatile("mfence" : : : "memory");
180 * cpu_lfence() ensures strong read ordering for reads issued prior
181 * to the instruction verses reads issued afterwords.
183 * A serializing or fence instruction is required here. A locked bus
184 * cycle on data for which we already own cache mastership is the most
190 __asm __volatile("lfence" : : : "memory");
194 * cpu_sfence() ensures strong write ordering for writes issued prior
195 * to the instruction verses writes issued afterwords. Writes are
196 * ordered on intel cpus so we do not actually have to do anything.
203 * Don't use 'sfence' here, as it will create a lot of
204 * unnecessary stalls.
206 __asm __volatile("" : : : "memory");
210 * cpu_ccfence() prevents the compiler from reordering instructions, in
211 * particular stores, relative to the current cpu. Use cpu_sfence() if
212 * you need to guarentee ordering by both the compiler and by the cpu.
214 * This also prevents the compiler from caching memory loads into local
215 * variables across the routine.
220 __asm __volatile("" : : : "memory");
224 * This is a horrible, horrible hack that might have to be put at the
225 * end of certain procedures (on a case by case basis), just before it
226 * returns to avoid what we believe to be an unreported AMD cpu bug.
227 * Found to occur on both a Phenom II X4 820 (two of them), as well
228 * as a 48-core built around an Opteron 6168 (Id = 0x100f91 Stepping = 1).
229 * The problem does not appear to occur w/Intel cpus.
231 * The bug is likely related to either a write combining issue or the
232 * Return Address Stack (RAS) hardware cache.
234 * In particular, we had to do this for GCC's fill_sons_in_loop() routine
235 * which due to its deep recursion and stack flow appears to be able to
236 * tickle the amd cpu bug (w/ gcc-4.4.7). Adding a single 'nop' to the
237 * end of the routine just before it returns works around the bug.
239 * The bug appears to be extremely sensitive to %rip and %rsp values, to
240 * the point where even just inserting an instruction in an unrelated
241 * procedure (shifting the entire code base being run) effects the outcome.
242 * DragonFly is probably able to more readily reproduce the bug due to
243 * the stackgap randomization code. We would expect OpenBSD (where we got
244 * the stackgap randomization code from) to also be able to reproduce the
245 * issue. To date we have only reproduced the issue in DragonFly.
247 #define __AMDCPUBUG_DFLY01_AVAILABLE__
250 cpu_amdcpubug_dfly01(void)
252 __asm __volatile("nop" : : : "memory");
257 #define HAVE_INLINE_FFS
264 * Note that gcc-2's builtin ffs would be used if we didn't declare
265 * this inline or turn off the builtin. The builtin is faster but
266 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
269 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
271 /* Actually, the above is way out of date. The builtins use cmov etc */
272 return (__builtin_ffs(mask));
276 #define HAVE_INLINE_FFSL
281 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
284 #define HAVE_INLINE_FLS
289 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
292 #define HAVE_INLINE_FLSL
297 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
300 #define HAVE_INLINE_FLSLL
303 flsll(long long mask)
305 return (flsl((long)mask));
313 __asm __volatile("hlt");
317 * The following complications are to get around gcc not having a
318 * constraint letter for the range 0..255. We still put "d" in the
319 * constraint because "i" isn't a valid constraint when the port
320 * isn't constant. This only matters for -O0 because otherwise
321 * the non-working version gets optimized away.
323 * Use an expression-statement instead of a conditional expression
324 * because gcc-2.6.0 would promote the operands of the conditional
325 * and produce poor code for "if ((inb(var) & const1) == const2)".
327 * The unnecessary test `(port) < 0x10000' is to generate a warning if
328 * the `port' has type u_short or smaller. Such types are pessimal.
329 * This actually only works for signed types. The range check is
330 * careful to avoid generating warnings.
332 #define inb(port) __extension__ ({ \
334 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
335 && (port) < 0x10000) \
336 _data = inbc(port); \
338 _data = inbv(port); \
341 #define outb(port, data) ( \
342 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
343 && (port) < 0x10000 \
344 ? outbc(port, data) : outbv(port, data))
346 static __inline u_char
351 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
356 outbc(u_int port, u_char data)
358 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
361 static __inline u_char
366 * We use %%dx and not %1 here because i/o is done at %dx and not at
367 * %edx, while gcc generates inferior code (movw instead of movl)
368 * if we tell it to load (u_short) port.
370 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
374 static __inline u_int
379 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
384 insb(u_int port, void *addr, size_t cnt)
386 __asm __volatile("cld; rep; insb"
387 : "+D" (addr), "+c" (cnt)
393 insw(u_int port, void *addr, size_t cnt)
395 __asm __volatile("cld; rep; insw"
396 : "+D" (addr), "+c" (cnt)
402 insl(u_int port, void *addr, size_t cnt)
404 __asm __volatile("cld; rep; insl"
405 : "+D" (addr), "+c" (cnt)
413 __asm __volatile("invd");
418 void smp_invltlb(void);
419 void smp_invltlb_intr(void);
421 #ifndef _CPU_INVLPG_DEFINED
424 * Invalidate a particular VA on this cpu only
426 * TLB flush for an individual page (even if it has PG_G).
427 * Only works on 486+ CPUs (i386 does not have PG_G).
430 cpu_invlpg(void *addr)
432 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
438 struct smp_invlpg_range_cpusync_arg {
444 smp_invlpg_range_cpusync(void *arg);
447 smp_invlpg_range(cpumask_t mask, vm_offset_t sva, vm_offset_t eva)
449 struct smp_invlpg_range_cpusync_arg arg;
453 lwkt_cpusync_simple(mask, smp_invlpg_range_cpusync, &arg);
460 __asm __volatile("rep; nop");
465 static __inline u_short
470 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
474 static __inline u_int
475 loadandclear(volatile u_int *addr)
479 __asm __volatile("xorl %0,%0; xchgl %1,%0"
480 : "=&r" (result) : "m" (*addr));
485 outbv(u_int port, u_char data)
489 * Use an unnecessary assignment to help gcc's register allocator.
490 * This make a large difference for gcc-1.40 and a tiny difference
491 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
492 * best results. gcc-2.6.0 can't handle this.
495 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
499 outl(u_int port, u_int data)
502 * outl() and outw() aren't used much so we haven't looked at
503 * possible micro-optimizations such as the unnecessary
504 * assignment for them.
506 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
510 outsb(u_int port, const void *addr, size_t cnt)
512 __asm __volatile("cld; rep; outsb"
513 : "+S" (addr), "+c" (cnt)
518 outsw(u_int port, const void *addr, size_t cnt)
520 __asm __volatile("cld; rep; outsw"
521 : "+S" (addr), "+c" (cnt)
526 outsl(u_int port, const void *addr, size_t cnt)
528 __asm __volatile("cld; rep; outsl"
529 : "+S" (addr), "+c" (cnt)
534 outw(u_int port, u_short data)
536 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
542 __asm __volatile("pause");
545 static __inline u_long
550 __asm __volatile("pushfq; popq %0" : "=r" (rf));
554 static __inline u_int64_t
559 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
560 return (low | ((u_int64_t)high << 32));
563 static __inline u_int64_t
568 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
569 return (low | ((u_int64_t)high << 32));
572 #define _RDTSC_SUPPORTED_
574 static __inline u_int64_t
579 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
580 return (low | ((u_int64_t)high << 32));
584 #include <machine/cputypes.h>
585 #include <machine/md_var.h>
587 static __inline u_int64_t
590 if (cpu_vendor_id == CPU_VENDOR_INTEL)
601 __asm __volatile("wbinvd");
605 void cpu_wbinvd_on_all_cpus_callback(void *arg);
608 cpu_wbinvd_on_all_cpus(void)
610 lwkt_cpusync_simple(smp_active_mask, cpu_wbinvd_on_all_cpus_callback, NULL);
615 write_rflags(u_long rf)
617 __asm __volatile("pushq %0; popfq" : : "r" (rf));
621 wrmsr(u_int msr, u_int64_t newval)
627 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
631 xsetbv(u_int ecx, u_int eax, u_int edx)
633 __asm __volatile(".byte 0x0f,0x01,0xd1"
635 : "a" (eax), "c" (ecx), "d" (edx));
639 load_cr0(u_long data)
642 __asm __volatile("movq %0,%%cr0" : : "r" (data));
645 static __inline u_long
650 __asm __volatile("movq %%cr0,%0" : "=r" (data));
654 static __inline u_long
659 __asm __volatile("movq %%cr2,%0" : "=r" (data));
664 load_cr3(u_long data)
667 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
670 static __inline u_long
675 __asm __volatile("movq %%cr3,%0" : "=r" (data));
680 load_cr4(u_long data)
682 __asm __volatile("movq %0,%%cr4" : : "r" (data));
685 static __inline u_long
690 __asm __volatile("movq %%cr4,%0" : "=r" (data));
694 #ifndef _CPU_INVLTLB_DEFINED
697 * Invalidate the TLB on this cpu only
703 #if defined(SWTCH_OPTIM_STATS)
710 static __inline u_short
714 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
718 static __inline u_short
722 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
729 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
735 __asm __volatile("movw %0,%%es" : : "rm" (sel));
739 /* This is defined in <machine/specialreg.h> but is too painful to get to */
741 #define MSR_FSBASE 0xc0000100
746 /* Preserve the fsbase value across the selector load */
747 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
748 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
752 #define MSR_GSBASE 0xc0000101
758 * Preserve the gsbase value across the selector load.
759 * Note that we have to disable interrupts because the gsbase
760 * being trashed happens to be the kernel gsbase at the time.
762 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
763 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
766 /* Usable by userland */
770 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
776 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
780 /* void lidt(struct region_descriptor *addr); */
782 lidt(struct region_descriptor *addr)
784 __asm __volatile("lidt (%0)" : : "r" (addr));
787 /* void lldt(u_short sel); */
791 __asm __volatile("lldt %0" : : "r" (sel));
794 /* void ltr(u_short sel); */
798 __asm __volatile("ltr %0" : : "r" (sel));
801 static __inline u_int64_t
805 __asm __volatile("movq %%dr0,%0" : "=r" (data));
810 load_dr0(u_int64_t dr0)
812 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
815 static __inline u_int64_t
819 __asm __volatile("movq %%dr1,%0" : "=r" (data));
824 load_dr1(u_int64_t dr1)
826 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
829 static __inline u_int64_t
833 __asm __volatile("movq %%dr2,%0" : "=r" (data));
838 load_dr2(u_int64_t dr2)
840 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
843 static __inline u_int64_t
847 __asm __volatile("movq %%dr3,%0" : "=r" (data));
852 load_dr3(u_int64_t dr3)
854 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
857 static __inline u_int64_t
861 __asm __volatile("movq %%dr4,%0" : "=r" (data));
866 load_dr4(u_int64_t dr4)
868 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
871 static __inline u_int64_t
875 __asm __volatile("movq %%dr5,%0" : "=r" (data));
880 load_dr5(u_int64_t dr5)
882 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
885 static __inline u_int64_t
889 __asm __volatile("movq %%dr6,%0" : "=r" (data));
894 load_dr6(u_int64_t dr6)
896 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
899 static __inline u_int64_t
903 __asm __volatile("movq %%dr7,%0" : "=r" (data));
908 load_dr7(u_int64_t dr7)
910 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
913 static __inline register_t
918 rflags = read_rflags();
924 intr_restore(register_t rflags)
926 write_rflags(rflags);
929 #else /* !__GNUC__ */
931 int breakpoint(void);
932 void cpu_pause(void);
933 u_int bsfl(u_int mask);
934 u_int bsrl(u_int mask);
935 void cpu_disable_intr(void);
936 void cpu_enable_intr(void);
937 void cpu_invlpg(u_long addr);
938 void cpu_invlpg_range(u_long start, u_long end);
939 void do_cpuid(u_int ax, u_int *p);
941 u_char inb(u_int port);
942 u_int inl(u_int port);
943 void insb(u_int port, void *addr, size_t cnt);
944 void insl(u_int port, void *addr, size_t cnt);
945 void insw(u_int port, void *addr, size_t cnt);
947 void invlpg_range(u_int start, u_int end);
948 void cpu_invltlb(void);
949 u_short inw(u_int port);
950 void load_cr0(u_int cr0);
951 void load_cr3(u_int cr3);
952 void load_cr4(u_int cr4);
953 void load_fs(u_int sel);
954 void load_gs(u_int sel);
955 struct region_descriptor;
956 void lidt(struct region_descriptor *addr);
957 void lldt(u_short sel);
958 void ltr(u_short sel);
959 void outb(u_int port, u_char data);
960 void outl(u_int port, u_int data);
961 void outsb(u_int port, void *addr, size_t cnt);
962 void outsl(u_int port, void *addr, size_t cnt);
963 void outsw(u_int port, void *addr, size_t cnt);
964 void outw(u_int port, u_short data);
965 void ia32_pause(void);
972 u_int64_t rdmsr(u_int msr);
973 u_int64_t rdpmc(u_int pmc);
974 u_int64_t rdtsc(void);
975 u_int read_rflags(void);
977 void write_rflags(u_int rf);
978 void wrmsr(u_int msr, u_int64_t newval);
979 u_int64_t rdr0(void);
980 void load_dr0(u_int64_t dr0);
981 u_int64_t rdr1(void);
982 void load_dr1(u_int64_t dr1);
983 u_int64_t rdr2(void);
984 void load_dr2(u_int64_t dr2);
985 u_int64_t rdr3(void);
986 void load_dr3(u_int64_t dr3);
987 u_int64_t rdr4(void);
988 void load_dr4(u_int64_t dr4);
989 u_int64_t rdr5(void);
990 void load_dr5(u_int64_t dr5);
991 u_int64_t rdr6(void);
992 void load_dr6(u_int64_t dr6);
993 u_int64_t rdr7(void);
994 void load_dr7(u_int64_t dr7);
995 register_t intr_disable(void);
996 void intr_restore(register_t rf);
998 #endif /* __GNUC__ */
1000 int rdmsr_safe(u_int msr, uint64_t *val);
1001 int wrmsr_safe(u_int msr, uint64_t newval);
1002 void reset_dbregs(void);
1006 #endif /* !_CPU_CPUFUNC_H_ */