sys/dev/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 #include <linux/highmem.h>
  33
  34 /**
  35  * DOC: Global GTT views
  36  *
  37  * Background and previous state
  38  *
  39  * Historically objects could exists (be bound) in global GTT space only as
  40  * singular instances with a view representing all of the object's backing pages
  41  * in a linear fashion. This view will be called a normal view.
  42  *
  43  * To support multiple views of the same object, where the number of mapped
  44  * pages is not equal to the backing store, or where the layout of the pages
  45  * is not linear, concept of a GGTT view was added.
  46  *
  47  * One example of an alternative view is a stereo display driven by a single
  48  * image. In this case we would have a framebuffer looking like this
  49  * (2x2 pages):
  50  *
  51  *    12
  52  *    34
  53  *
  54  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  55  * rendering. In contrast, fed to the display engine would be an alternative
  56  * view which could look something like this:
  57  *
  58  *   1212
  59  *   3434
  60  *
  61  * In this example both the size and layout of pages in the alternative view is
  62  * different from the normal view.
  63  *
  64  * Implementation and usage
  65  *
  66  * GGTT views are implemented using VMAs and are distinguished via enum
  67  * i915_ggtt_view_type and struct i915_ggtt_view.
  68  *
  69  * A new flavour of core GEM functions which work with GGTT bound objects were
  70  * added with the _view suffix. They take the struct i915_ggtt_view parameter
  71  * encapsulating all metadata required to implement a view.
  72  *
  73  * As a helper for callers which are only interested in the normal view,
  74  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  75  * GEM API functions, the ones not taking the view parameter, are operating on,
  76  * or with the normal GGTT view.
  77  *
  78  * Code wanting to add or use a new GGTT view needs to:
  79  *
  80  * 1. Add a new enum with a suitable name.
  81  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  82  * 3. Add support to i915_get_vma_pages().
  83  *
  84  * New views are required to build a scatter-gather table from within the
  85  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  86  * exists for the lifetime of an VMA.
  87  *
  88  * Core API is designed to have copy semantics which means that passed in
  89  * struct i915_ggtt_view does not need to be persistent (left around after
  90  * calling the core API functions).
  91  *
  92  */
  93
  94 const struct i915_ggtt_view i915_ggtt_view_normal;
  95
  96 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
  97 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
  98
  99 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 100 {
 101         bool has_aliasing_ppgtt;
 102         bool has_full_ppgtt;
 103
 104         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 105         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 106
 107         /*
 108          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 109          * execlists, the sole mechanism available to submit work.
 110          */
 111         if (INTEL_INFO(dev)->gen < 9 &&
 112             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 113                 return 0;
 114
 115         if (enable_ppgtt == 1)
 116                 return 1;
 117
 118         if (enable_ppgtt == 2 && has_full_ppgtt)
 119                 return 2;
 120
 121 #ifdef CONFIG_INTEL_IOMMU
 122         /* Disable ppgtt on SNB if VT-d is on. */
 123         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 124                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 125                 return 0;
 126         }
 127 #endif
 128
 129         /* Early VLV doesn't have this */
 130         int revision = pci_read_config(dev->dev, PCIR_REVID, 1);
 131         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 132             revision < 0xb) {
 133                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 134                 return 0;
 135         }
 136
 137         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 138                 return 2;
 139         else
 140                 return has_aliasing_ppgtt ? 1 : 0;
 141 }
 142
 143 static void ppgtt_bind_vma(struct i915_vma *vma,
 144                            enum i915_cache_level cache_level,
 145                            u32 flags);
 146 static void ppgtt_unbind_vma(struct i915_vma *vma);
 147
 148 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
 149                                              enum i915_cache_level level,
 150                                              bool valid)
 151 {
 152         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 153         pte |= addr;
 154
 155         switch (level) {
 156         case I915_CACHE_NONE:
 157                 pte |= PPAT_UNCACHED_INDEX;
 158                 break;
 159         case I915_CACHE_WT:
 160                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 161                 break;
 162         default:
 163                 pte |= PPAT_CACHED_INDEX;
 164                 break;
 165         }
 166
 167         return pte;
 168 }
 169
 170 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
 171                                              dma_addr_t addr,
 172                                              enum i915_cache_level level)
 173 {
 174         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 175         pde |= addr;
 176         if (level != I915_CACHE_NONE)
 177                 pde |= PPAT_CACHED_PDE_INDEX;
 178         else
 179                 pde |= PPAT_UNCACHED_INDEX;
 180         return pde;
 181 }
 182
 183 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 184                                      enum i915_cache_level level,
 185                                      bool valid, u32 unused)
 186 {
 187         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 188         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 189
 190         switch (level) {
 191         case I915_CACHE_L3_LLC:
 192         case I915_CACHE_LLC:
 193                 pte |= GEN6_PTE_CACHE_LLC;
 194                 break;
 195         case I915_CACHE_NONE:
 196                 pte |= GEN6_PTE_UNCACHED;
 197                 break;
 198         default:
 199                 MISSING_CASE(level);
 200         }
 201
 202         return pte;
 203 }
 204
 205 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 206                                      enum i915_cache_level level,
 207                                      bool valid, u32 unused)
 208 {
 209         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 210         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 211
 212         switch (level) {
 213         case I915_CACHE_L3_LLC:
 214                 pte |= GEN7_PTE_CACHE_L3_LLC;
 215                 break;
 216         case I915_CACHE_LLC:
 217                 pte |= GEN6_PTE_CACHE_LLC;
 218                 break;
 219         case I915_CACHE_NONE:
 220                 pte |= GEN6_PTE_UNCACHED;
 221                 break;
 222         default:
 223                 MISSING_CASE(level);
 224         }
 225
 226         return pte;
 227 }
 228
 229 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 230                                      enum i915_cache_level level,
 231                                      bool valid, u32 flags)
 232 {
 233         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 234         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 235
 236         if (!(flags & PTE_READ_ONLY))
 237                 pte |= BYT_PTE_WRITEABLE;
 238
 239         if (level != I915_CACHE_NONE)
 240                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 241
 242         return pte;
 243 }
 244
 245 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 246                                      enum i915_cache_level level,
 247                                      bool valid, u32 unused)
 248 {
 249         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 250         pte |= HSW_PTE_ADDR_ENCODE(addr);
 251
 252         if (level != I915_CACHE_NONE)
 253                 pte |= HSW_WB_LLC_AGE3;
 254
 255         return pte;
 256 }
 257
 258 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 259                                       enum i915_cache_level level,
 260                                       bool valid, u32 unused)
 261 {
 262         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 263         pte |= HSW_PTE_ADDR_ENCODE(addr);
 264
 265         switch (level) {
 266         case I915_CACHE_NONE:
 267                 break;
 268         case I915_CACHE_WT:
 269                 pte |= HSW_WT_ELLC_LLC_AGE3;
 270                 break;
 271         default:
 272                 pte |= HSW_WB_ELLC_LLC_AGE3;
 273                 break;
 274         }
 275
 276         return pte;
 277 }
 278
 279 /* Broadwell Page Directory Pointer Descriptors */
 280 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
 281                            uint64_t val)
 282 {
 283         int ret;
 284
 285         BUG_ON(entry >= 4);
 286
 287         ret = intel_ring_begin(ring, 6);
 288         if (ret)
 289                 return ret;
 290
 291         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 292         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 293         intel_ring_emit(ring, (u32)(val >> 32));
 294         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 295         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 296         intel_ring_emit(ring, (u32)(val));
 297         intel_ring_advance(ring);
 298
 299         return 0;
 300 }
 301
 302 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 303                           struct intel_engine_cs *ring)
 304 {
 305         int i, ret;
 306
 307         /* bit of a hack to find the actual last used pd */
 308         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 309
 310         for (i = used_pd - 1; i >= 0; i--) {
 311                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 312                 ret = gen8_write_pdp(ring, i, addr);
 313                 if (ret)
 314                         return ret;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 321                                    uint64_t start,
 322                                    uint64_t length,
 323                                    bool use_scratch)
 324 {
 325         struct i915_hw_ppgtt *ppgtt =
 326                 container_of(vm, struct i915_hw_ppgtt, base);
 327         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 328         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 329         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 330         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 331         unsigned num_entries = length >> PAGE_SHIFT;
 332         unsigned last_pte, i;
 333
 334         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 335                                       I915_CACHE_LLC, use_scratch);
 336
 337         while (num_entries) {
 338                 struct vm_page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
 339
 340                 last_pte = pte + num_entries;
 341                 if (last_pte > GEN8_PTES_PER_PAGE)
 342                         last_pte = GEN8_PTES_PER_PAGE;
 343
 344                 pt_vaddr = kmap_atomic(page_table);
 345
 346                 for (i = pte; i < last_pte; i++) {
 347                         pt_vaddr[i] = scratch_pte;
 348                         num_entries--;
 349                 }
 350
 351                 if (!HAS_LLC(ppgtt->base.dev))
 352                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 353                 kunmap_atomic(pt_vaddr);
 354
 355                 pte = 0;
 356                 if (++pde == GEN8_PDES_PER_PAGE) {
 357                         pdpe++;
 358                         pde = 0;
 359                 }
 360         }
 361 }
 362
 363 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 364                                       vm_page_t *pages,
 365                                       uint64_t start,
 366                                       unsigned int num_entries,
 367                                       enum i915_cache_level cache_level, u32 unused)
 368 {
 369         struct i915_hw_ppgtt *ppgtt =
 370                 container_of(vm, struct i915_hw_ppgtt, base);
 371         gen8_gtt_pte_t *pt_vaddr;
 372         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 373         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 374         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 375         int i;
 376
 377         pt_vaddr = NULL;
 378
 379         for (i=0;i<num_entries;i++) {
 380                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
 381                         break;
 382
 383                 if (pt_vaddr == NULL)
 384                         pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
 385
 386                 pt_vaddr[pte] =
 387                         gen8_pte_encode(VM_PAGE_TO_PHYS(pages[i]),
 388                                         cache_level, true);
 389                 if (++pte == GEN8_PTES_PER_PAGE) {
 390                         if (!HAS_LLC(ppgtt->base.dev))
 391                                 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 392                         kunmap_atomic(pt_vaddr);
 393                         pt_vaddr = NULL;
 394                         if (++pde == GEN8_PDES_PER_PAGE) {
 395                                 pdpe++;
 396                                 pde = 0;
 397                         }
 398                         pte = 0;
 399                 }
 400         }
 401         if (pt_vaddr) {
 402                 if (!HAS_LLC(ppgtt->base.dev))
 403                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 404                 kunmap_atomic(pt_vaddr);
 405         }
 406 }
 407
 408 static void gen8_free_page_tables(struct vm_page **pt_pages)
 409 {
 410         int i;
 411
 412         if (pt_pages == NULL)
 413                 return;
 414
 415         for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
 416                 if (pt_pages[i])
 417                         __free_pages(pt_pages[i], 0);
 418 }
 419
 420 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
 421 {
 422         int i;
 423
 424         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 425                 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
 426                 kfree(ppgtt->gen8_pt_pages[i]);
 427                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 428         }
 429
 430         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 431 }
 432
 433 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 434 {
 435         struct pci_dev *hwdev = ppgtt->base.dev->pdev;
 436         int i, j;
 437
 438         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 439                 /* TODO: In the future we'll support sparse mappings, so this
 440                  * will have to change. */
 441                 if (!ppgtt->pd_dma_addr[i])
 442                         continue;
 443
 444                 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
 445                                PCI_DMA_BIDIRECTIONAL);
 446
 447                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 448                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 449                         if (addr)
 450                                 pci_unmap_page(hwdev, addr, PAGE_SIZE,
 451                                                PCI_DMA_BIDIRECTIONAL);
 452                 }
 453         }
 454 }
 455
 456 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 457 {
 458         struct i915_hw_ppgtt *ppgtt =
 459                 container_of(vm, struct i915_hw_ppgtt, base);
 460
 461         gen8_ppgtt_unmap_pages(ppgtt);
 462         gen8_ppgtt_free(ppgtt);
 463 }
 464
 465 static struct vm_page **__gen8_alloc_page_tables(void)
 466 {
 467         struct vm_page **pt_pages;
 468         int i;
 469
 470         pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct vm_page *), GFP_KERNEL);
 471         if (!pt_pages)
 472                 return ERR_PTR(-ENOMEM);
 473
 474         for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
 475                 pt_pages[i] = alloc_page(GFP_KERNEL);
 476                 if (!pt_pages[i])
 477                         goto bail;
 478         }
 479
 480         return pt_pages;
 481
 482 bail:
 483         gen8_free_page_tables(pt_pages);
 484         kfree(pt_pages);
 485         return ERR_PTR(-ENOMEM);
 486 }
 487
 488 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
 489                                            const int max_pdp)
 490 {
 491         struct vm_page **pt_pages[GEN8_LEGACY_PDPS];
 492         int i, ret;
 493
 494         for (i = 0; i < max_pdp; i++) {
 495                 pt_pages[i] = __gen8_alloc_page_tables();
 496                 if (IS_ERR(pt_pages[i])) {
 497                         ret = PTR_ERR(pt_pages[i]);
 498                         goto unwind_out;
 499                 }
 500         }
 501
 502         /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
 503          * "atomic" - for cleanup purposes.
 504          */
 505         for (i = 0; i < max_pdp; i++)
 506                 ppgtt->gen8_pt_pages[i] = pt_pages[i];
 507
 508         return 0;
 509
 510 unwind_out:
 511         while (i--) {
 512                 gen8_free_page_tables(pt_pages[i]);
 513                 kfree(pt_pages[i]);
 514         }
 515
 516         return ret;
 517 }
 518
 519 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
 520 {
 521         int i;
 522
 523         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 524                 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
 525                                                      sizeof(dma_addr_t),
 526                                                      GFP_KERNEL);
 527                 if (!ppgtt->gen8_pt_dma_addr[i])
 528                         return -ENOMEM;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
 535                                                 const int max_pdp)
 536 {
 537         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 538         if (!ppgtt->pd_pages)
 539                 return -ENOMEM;
 540
 541         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 542         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 543
 544         return 0;
 545 }
 546
 547 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
 548                             const int max_pdp)
 549 {
 550         int ret;
 551
 552         ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
 553         if (ret)
 554                 return ret;
 555
 556         ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
 557         if (ret) {
 558                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 559                 return ret;
 560         }
 561
 562         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 563
 564         ret = gen8_ppgtt_allocate_dma(ppgtt);
 565         if (ret)
 566                 gen8_ppgtt_free(ppgtt);
 567
 568         return ret;
 569 }
 570
 571 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
 572                                              const int pd)
 573 {
 574         dma_addr_t pd_addr;
 575         int ret;
 576
 577         pd_addr = pci_map_page(ppgtt->base.dev->pdev,
 578                                &ppgtt->pd_pages[pd], 0,
 579                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 580
 581         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
 582         if (ret)
 583                 return ret;
 584
 585         ppgtt->pd_dma_addr[pd] = pd_addr;
 586
 587         return 0;
 588 }
 589
 590 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
 591                                         const int pd,
 592                                         const int pt)
 593 {
 594         dma_addr_t pt_addr;
 595         struct vm_page *p;
 596         int ret;
 597
 598         p = ppgtt->gen8_pt_pages[pd][pt];
 599         pt_addr = pci_map_page(ppgtt->base.dev->pdev,
 600                                p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 601         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
 602         if (ret)
 603                 return ret;
 604
 605         ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
 606
 607         return 0;
 608 }
 609
 610 /**
 611  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 612  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 613  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 614  * space.
 615  *
 616  * FIXME: split allocation into smaller pieces. For now we only ever do this
 617  * once, but with full PPGTT, the multiple contiguous allocations will be bad.
 618  * TODO: Do something with the size parameter
 619  */
 620 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 621 {
 622         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 623         const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 624         int i, j, ret;
 625
 626         if (size % (1<<30))
 627                 DRM_INFO("Pages will be wasted unless GTT size (%lu) is divisible by 1GB\n", size);
 628
 629         /* 1. Do all our allocations for page directories and page tables. */
 630         ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
 631         if (ret)
 632                 return ret;
 633
 634         /*
 635          * 2. Create DMA mappings for the page directories and page tables.
 636          */
 637         for (i = 0; i < max_pdp; i++) {
 638                 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
 639                 if (ret)
 640                         goto bail;
 641
 642                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 643                         ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
 644                         if (ret)
 645                                 goto bail;
 646                 }
 647         }
 648
 649         /*
 650          * 3. Map all the page directory entires to point to the page tables
 651          * we've allocated.
 652          *
 653          * For now, the PPGTT helper functions all require that the PDEs are
 654          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 655          * will never need to touch the PDEs again.
 656          */
 657         for (i = 0; i < max_pdp; i++) {
 658                 gen8_ppgtt_pde_t *pd_vaddr;
 659                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 660                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 661                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 662                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 663                                                       I915_CACHE_LLC);
 664                 }
 665                 if (!HAS_LLC(ppgtt->base.dev))
 666                         drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
 667                 kunmap_atomic(pd_vaddr);
 668         }
 669
 670         ppgtt->switch_mm = gen8_mm_switch;
 671         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 672         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 673         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 674         ppgtt->base.start = 0;
 675         ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 676
 677         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
 678
 679         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 680                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 681         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%ld wasted)\n",
 682                          ppgtt->num_pd_entries,
 683                          (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
 684         return 0;
 685
 686 bail:
 687         gen8_ppgtt_unmap_pages(ppgtt);
 688         gen8_ppgtt_free(ppgtt);
 689         return ret;
 690 }
 691
 692 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 693 {
 694         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 695         struct i915_address_space *vm = &ppgtt->base;
 696         gen6_gtt_pte_t __iomem *pd_addr;
 697         gen6_gtt_pte_t scratch_pte;
 698         uint32_t pd_entry;
 699         int pte, pde;
 700
 701         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 702
 703         pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
 704                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 705
 706         seq_printf(m, "  VM %p (pd_offset %x-%x):\n", vm,
 707                    ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
 708         for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
 709                 u32 expected;
 710                 gen6_gtt_pte_t *pt_vaddr;
 711                 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
 712                 pd_entry = readl(pd_addr + pde);
 713                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 714
 715                 if (pd_entry != expected)
 716                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 717                                    pde,
 718                                    pd_entry,
 719                                    expected);
 720                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 721
 722                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
 723                 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
 724                         unsigned long va =
 725                                 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
 726                                 (pte * PAGE_SIZE);
 727                         int i;
 728                         bool found = false;
 729                         for (i = 0; i < 4; i++)
 730                                 if (pt_vaddr[pte + i] != scratch_pte)
 731                                         found = true;
 732                         if (!found)
 733                                 continue;
 734
 735                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
 736                         for (i = 0; i < 4; i++) {
 737                                 if (pt_vaddr[pte + i] != scratch_pte)
 738                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
 739                                 else
 740                                         seq_printf(m, "  SCRATCH ");
 741                         }
 742                         seq_printf(m, "\n");
 743                 }
 744                 kunmap_atomic(pt_vaddr);
 745         }
 746 }
 747
 748 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 749 {
 750         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 751         gen6_gtt_pte_t __iomem *pd_addr;
 752         uint32_t pd_entry;
 753         int i;
 754
 755         WARN_ON(ppgtt->pd_offset & 0x3f);
 756         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 757                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 758         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 759                 dma_addr_t pt_addr;
 760
 761                 pt_addr = ppgtt->pt_dma_addr[i];
 762                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 763                 pd_entry |= GEN6_PDE_VALID;
 764
 765                 writel(pd_entry, pd_addr + i);
 766         }
 767         readl(pd_addr);
 768 }
 769
 770 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
 771 {
 772         BUG_ON(ppgtt->pd_offset & 0x3f);
 773
 774         return (ppgtt->pd_offset / 64) << 16;
 775 }
 776
 777 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 778                          struct intel_engine_cs *ring)
 779 {
 780         int ret;
 781
 782         /* NB: TLBs must be flushed and invalidated before a switch */
 783         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 784         if (ret)
 785                 return ret;
 786
 787         ret = intel_ring_begin(ring, 6);
 788         if (ret)
 789                 return ret;
 790
 791         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 792         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 793         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 794         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 795         intel_ring_emit(ring, get_pd_offset(ppgtt));
 796         intel_ring_emit(ring, MI_NOOP);
 797         intel_ring_advance(ring);
 798
 799         return 0;
 800 }
 801
 802 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 803                           struct intel_engine_cs *ring)
 804 {
 805         int ret;
 806
 807         /* NB: TLBs must be flushed and invalidated before a switch */
 808         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 809         if (ret)
 810                 return ret;
 811
 812         ret = intel_ring_begin(ring, 6);
 813         if (ret)
 814                 return ret;
 815
 816         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 817         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 818         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 819         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 820         intel_ring_emit(ring, get_pd_offset(ppgtt));
 821         intel_ring_emit(ring, MI_NOOP);
 822         intel_ring_advance(ring);
 823
 824         /* XXX: RCS is the only one to auto invalidate the TLBs? */
 825         if (ring->id != RCS) {
 826                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 827                 if (ret)
 828                         return ret;
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
 835                           struct intel_engine_cs *ring)
 836 {
 837         struct drm_device *dev = ppgtt->base.dev;
 838         struct drm_i915_private *dev_priv = dev->dev_private;
 839
 840
 841         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 842         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 843
 844         POSTING_READ(RING_PP_DIR_DCLV(ring));
 845
 846         return 0;
 847 }
 848
 849 static void gen8_ppgtt_enable(struct drm_device *dev)
 850 {
 851         struct drm_i915_private *dev_priv = dev->dev_private;
 852         struct intel_engine_cs *ring;
 853         int j;
 854
 855         for_each_ring(ring, dev_priv, j) {
 856                 I915_WRITE(RING_MODE_GEN7(ring),
 857                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 858         }
 859 }
 860
 861 static void gen7_ppgtt_enable(struct drm_device *dev)
 862 {
 863         struct drm_i915_private *dev_priv = dev->dev_private;
 864         struct intel_engine_cs *ring;
 865         uint32_t ecochk, ecobits;
 866         int i;
 867
 868         ecobits = I915_READ(GAC_ECO_BITS);
 869         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 870
 871         ecochk = I915_READ(GAM_ECOCHK);
 872         if (IS_HASWELL(dev)) {
 873                 ecochk |= ECOCHK_PPGTT_WB_HSW;
 874         } else {
 875                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
 876                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 877         }
 878         I915_WRITE(GAM_ECOCHK, ecochk);
 879
 880         for_each_ring(ring, dev_priv, i) {
 881                 /* GFX_MODE is per-ring on gen7+ */
 882                 I915_WRITE(RING_MODE_GEN7(ring),
 883                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 884         }
 885 }
 886
 887 static void gen6_ppgtt_enable(struct drm_device *dev)
 888 {
 889         struct drm_i915_private *dev_priv = dev->dev_private;
 890         uint32_t ecochk, gab_ctl, ecobits;
 891
 892         ecobits = I915_READ(GAC_ECO_BITS);
 893         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 894                    ECOBITS_PPGTT_CACHE64B);
 895
 896         gab_ctl = I915_READ(GAB_CTL);
 897         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 898
 899         ecochk = I915_READ(GAM_ECOCHK);
 900         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 901
 902         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 903 }
 904
 905 /* PPGTT support for Sandybdrige/Gen6 and later */
 906 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 907                                    uint64_t start,
 908                                    uint64_t length,
 909                                    bool use_scratch)
 910 {
 911         struct i915_hw_ppgtt *ppgtt =
 912                 container_of(vm, struct i915_hw_ppgtt, base);
 913         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 914         unsigned first_entry = start >> PAGE_SHIFT;
 915         unsigned num_entries = length >> PAGE_SHIFT;
 916         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 917         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 918         unsigned last_pte, i;
 919
 920         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 921
 922         while (num_entries) {
 923                 last_pte = first_pte + num_entries;
 924                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 925                         last_pte = I915_PPGTT_PT_ENTRIES;
 926
 927                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 928
 929                 for (i = first_pte; i < last_pte; i++)
 930                         pt_vaddr[i] = scratch_pte;
 931
 932                 kunmap_atomic(pt_vaddr);
 933
 934                 num_entries -= last_pte - first_pte;
 935                 first_pte = 0;
 936                 act_pt++;
 937         }
 938 }
 939
 940 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 941                                       vm_page_t *pages,
 942                                       uint64_t start,
 943                                       unsigned num_entries,
 944                                       enum i915_cache_level cache_level, u32 flags)
 945 {
 946         struct i915_hw_ppgtt *ppgtt =
 947                 container_of(vm, struct i915_hw_ppgtt, base);
 948         gen6_gtt_pte_t *pt_vaddr;
 949         unsigned first_entry = start >> PAGE_SHIFT;
 950         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 951         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 952
 953         pt_vaddr = NULL;
 954         for (int i=0;i<num_entries;i++) {
 955                 if (pt_vaddr == NULL)
 956                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 957
 958                 pt_vaddr[act_pte] =
 959                         vm->pte_encode(VM_PAGE_TO_PHYS(pages[i]),
 960                                        cache_level, true, flags);
 961                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 962                         kunmap_atomic(pt_vaddr);
 963                         pt_vaddr = NULL;
 964                         act_pt++;
 965                         act_pte = 0;
 966                 }
 967         }
 968         if (pt_vaddr)
 969                 kunmap_atomic(pt_vaddr);
 970 }
 971
 972 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 973 {
 974         int i;
 975
 976         if (ppgtt->pt_dma_addr) {
 977                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 978                         pci_unmap_page(ppgtt->base.dev->pdev,
 979                                        ppgtt->pt_dma_addr[i],
 980                                        4096, PCI_DMA_BIDIRECTIONAL);
 981         }
 982 }
 983
 984 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
 985 {
 986         int i;
 987
 988         kfree(ppgtt->pt_dma_addr);
 989         for (i = 0; i < ppgtt->num_pd_entries; i++)
 990                 __free_page(ppgtt->pt_pages[i]);
 991         kfree(ppgtt->pt_pages);
 992 }
 993
 994 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 995 {
 996         struct i915_hw_ppgtt *ppgtt =
 997                 container_of(vm, struct i915_hw_ppgtt, base);
 998
 999         drm_mm_remove_node(&ppgtt->node);
1000
1001         gen6_ppgtt_unmap_pages(ppgtt);
1002         gen6_ppgtt_free(ppgtt);
1003 }
1004
1005 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1006 {
1007         struct drm_device *dev = ppgtt->base.dev;
1008         struct drm_i915_private *dev_priv = dev->dev_private;
1009         bool retried = false;
1010         int ret;
1011
1012         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1013          * allocator works in address space sizes, so it's multiplied by page
1014          * size. We allocate at the top of the GTT to avoid fragmentation.
1015          */
1016         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1017 alloc:
1018         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1019                                                   &ppgtt->node, GEN6_PD_SIZE,
1020                                                   GEN6_PD_ALIGN, 0,
1021                                                   0, dev_priv->gtt.base.total,
1022                                                   DRM_MM_TOPDOWN);
1023         if (ret == -ENOSPC && !retried) {
1024                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1025                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1026                                                I915_CACHE_NONE,
1027                                                0, dev_priv->gtt.base.total,
1028                                                0);
1029                 if (ret)
1030                         return ret;
1031
1032                 retried = true;
1033                 goto alloc;
1034         }
1035
1036         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1037                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1038
1039         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1040         return ret;
1041 }
1042
1043 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1044 {
1045         int i;
1046
1047         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct vm_page *),
1048                                   GFP_KERNEL);
1049
1050         if (!ppgtt->pt_pages)
1051                 return -ENOMEM;
1052
1053         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1054                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1055                 if (!ppgtt->pt_pages[i]) {
1056                         gen6_ppgtt_free(ppgtt);
1057                         return -ENOMEM;
1058                 }
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1065 {
1066         int ret;
1067
1068         ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1069         if (ret)
1070                 return ret;
1071
1072         ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1073         if (ret) {
1074                 drm_mm_remove_node(&ppgtt->node);
1075                 return ret;
1076         }
1077
1078         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1079                                      GFP_KERNEL);
1080         if (!ppgtt->pt_dma_addr) {
1081                 drm_mm_remove_node(&ppgtt->node);
1082                 gen6_ppgtt_free(ppgtt);
1083                 return -ENOMEM;
1084         }
1085
1086         return 0;
1087 }
1088
1089 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1090 {
1091         struct drm_device *dev = ppgtt->base.dev;
1092         int i;
1093
1094         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1095                 dma_addr_t pt_addr;
1096
1097                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1098                                        PCI_DMA_BIDIRECTIONAL);
1099
1100                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1101                         gen6_ppgtt_unmap_pages(ppgtt);
1102                         return -EIO;
1103                 }
1104
1105                 ppgtt->pt_dma_addr[i] = pt_addr;
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1112 {
1113         struct drm_device *dev = ppgtt->base.dev;
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         int ret;
1116
1117         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1118         if (IS_GEN6(dev)) {
1119                 ppgtt->switch_mm = gen6_mm_switch;
1120         } else if (IS_HASWELL(dev)) {
1121                 ppgtt->switch_mm = hsw_mm_switch;
1122         } else if (IS_GEN7(dev)) {
1123                 ppgtt->switch_mm = gen7_mm_switch;
1124         } else
1125                 BUG();
1126
1127         ret = gen6_ppgtt_alloc(ppgtt);
1128         if (ret)
1129                 return ret;
1130
1131         ret = gen6_ppgtt_setup_page_tables(ppgtt);
1132         if (ret) {
1133                 gen6_ppgtt_free(ppgtt);
1134                 return ret;
1135         }
1136
1137         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1138         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1139         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1140         ppgtt->base.start = 0;
1141         ppgtt->base.total =  ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1142         ppgtt->debug_dump = gen6_dump_ppgtt;
1143
1144         ppgtt->pd_offset =
1145                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1146
1147         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1148
1149         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1150                          ppgtt->node.size >> 20,
1151                          ppgtt->node.start / PAGE_SIZE);
1152
1153         gen6_write_pdes(ppgtt);
1154         DRM_DEBUG("Adding PPGTT at offset %x\n",
1155                   ppgtt->pd_offset << 10);
1156
1157         return 0;
1158 }
1159
1160 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1161 {
1162         struct drm_i915_private *dev_priv = dev->dev_private;
1163
1164         ppgtt->base.dev = dev;
1165         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1166
1167         if (INTEL_INFO(dev)->gen < 8)
1168                 return gen6_ppgtt_init(ppgtt);
1169         else
1170                 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1171 }
1172 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1173 {
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         int ret = 0;
1176
1177         ret = __hw_ppgtt_init(dev, ppgtt);
1178         if (ret == 0) {
1179                 kref_init(&ppgtt->ref);
1180                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1181                             ppgtt->base.total);
1182                 i915_init_vm(dev_priv, &ppgtt->base);
1183         }
1184
1185         return ret;
1186 }
1187
1188 int i915_ppgtt_init_hw(struct drm_device *dev)
1189 {
1190         struct drm_i915_private *dev_priv = dev->dev_private;
1191         struct intel_engine_cs *ring;
1192         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1193         int i, ret = 0;
1194
1195         /* In the case of execlists, PPGTT is enabled by the context descriptor
1196          * and the PDPs are contained within the context itself.  We don't
1197          * need to do anything here. */
1198         if (i915.enable_execlists)
1199                 return 0;
1200
1201         if (!USES_PPGTT(dev))
1202                 return 0;
1203
1204         if (IS_GEN6(dev))
1205                 gen6_ppgtt_enable(dev);
1206         else if (IS_GEN7(dev))
1207                 gen7_ppgtt_enable(dev);
1208         else if (INTEL_INFO(dev)->gen >= 8)
1209                 gen8_ppgtt_enable(dev);
1210         else
1211                 MISSING_CASE(INTEL_INFO(dev)->gen);
1212
1213         if (ppgtt) {
1214                 for_each_ring(ring, dev_priv, i) {
1215                         ret = ppgtt->switch_mm(ppgtt, ring);
1216                         if (ret != 0)
1217                                 return ret;
1218                 }
1219         }
1220
1221         return ret;
1222 }
1223 struct i915_hw_ppgtt *
1224 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1225 {
1226         struct i915_hw_ppgtt *ppgtt;
1227         int ret;
1228
1229         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1230         if (!ppgtt)
1231                 return ERR_PTR(-ENOMEM);
1232
1233         ret = i915_ppgtt_init(dev, ppgtt);
1234         if (ret) {
1235                 kfree(ppgtt);
1236                 return ERR_PTR(ret);
1237         }
1238
1239         ppgtt->file_priv = fpriv;
1240
1241         trace_i915_ppgtt_create(&ppgtt->base);
1242
1243         return ppgtt;
1244 }
1245
1246 void  i915_ppgtt_release(struct kref *kref)
1247 {
1248         struct i915_hw_ppgtt *ppgtt =
1249                 container_of(kref, struct i915_hw_ppgtt, ref);
1250
1251         trace_i915_ppgtt_release(&ppgtt->base);
1252
1253         /* vmas should already be unbound */
1254         WARN_ON(!list_empty(&ppgtt->base.active_list));
1255         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1256
1257         list_del(&ppgtt->base.global_link);
1258         drm_mm_takedown(&ppgtt->base.mm);
1259
1260         ppgtt->base.cleanup(&ppgtt->base);
1261         kfree(ppgtt);
1262 }
1263
1264 static void
1265 ppgtt_bind_vma(struct i915_vma *vma,
1266                enum i915_cache_level cache_level,
1267                u32 flags)
1268 {
1269         const unsigned int num_entries = vma->obj->base.size >> PAGE_SHIFT;
1270
1271         /* Currently applicable only to VLV */
1272         if (vma->obj->gt_ro)
1273                 flags |= PTE_READ_ONLY;
1274
1275         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1276                                 num_entries,
1277                                 cache_level, flags);
1278 }
1279
1280 static void ppgtt_unbind_vma(struct i915_vma *vma)
1281 {
1282         vma->vm->clear_range(vma->vm,
1283                              vma->node.start,
1284                              vma->obj->base.size,
1285                              true);
1286 }
1287
1288 extern int intel_iommu_gfx_mapped;
1289 /* Certain Gen5 chipsets require require idling the GPU before
1290  * unmapping anything from the GTT when VT-d is enabled.
1291  */
1292 static inline bool needs_idle_maps(struct drm_device *dev)
1293 {
1294 #ifdef CONFIG_INTEL_IOMMU
1295         /* Query intel_iommu to see if we need the workaround. Presumably that
1296          * was loaded first.
1297          */
1298         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1299                 return true;
1300 #endif
1301         return false;
1302 }
1303
1304 static bool do_idling(struct drm_i915_private *dev_priv)
1305 {
1306         bool ret = dev_priv->mm.interruptible;
1307
1308         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1309                 dev_priv->mm.interruptible = false;
1310                 if (i915_gpu_idle(dev_priv->dev)) {
1311                         DRM_ERROR("Couldn't idle GPU\n");
1312                         /* Wait a bit, in hopes it avoids the hang */
1313                         udelay(10);
1314                 }
1315         }
1316
1317         return ret;
1318 }
1319
1320 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1321 {
1322         if (unlikely(dev_priv->gtt.do_idle_maps))
1323                 dev_priv->mm.interruptible = interruptible;
1324 }
1325
1326 void i915_check_and_clear_faults(struct drm_device *dev)
1327 {
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         struct intel_engine_cs *ring;
1330         int i;
1331
1332         if (INTEL_INFO(dev)->gen < 6)
1333                 return;
1334
1335         for_each_ring(ring, dev_priv, i) {
1336                 u32 fault_reg;
1337                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1338                 if (fault_reg & RING_FAULT_VALID) {
1339 #if 0
1340                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1341                                          "\tAddr: 0x%08lx\n"
1342                                          "\tAddress space: %s\n"
1343                                          "\tSource ID: %d\n"
1344                                          "\tType: %d\n",
1345                                          fault_reg & PAGE_MASK,
1346                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1347                                          RING_FAULT_SRCID(fault_reg),
1348                                          RING_FAULT_FAULT_TYPE(fault_reg));
1349 #endif
1350                         I915_WRITE(RING_FAULT_REG(ring),
1351                                    fault_reg & ~RING_FAULT_VALID);
1352                 }
1353         }
1354         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1355 }
1356
1357 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1358 {
1359         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1360                 intel_gtt_chipset_flush();
1361         } else {
1362                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1363                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1364         }
1365 }
1366
1367 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1368 {
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370
1371         /* Don't bother messing with faults pre GEN6 as we have little
1372          * documentation supporting that it's a good idea.
1373          */
1374         if (INTEL_INFO(dev)->gen < 6)
1375                 return;
1376
1377         i915_check_and_clear_faults(dev);
1378
1379         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1380                                        dev_priv->gtt.base.start,
1381                                        dev_priv->gtt.base.total,
1382                                        true);
1383
1384         i915_ggtt_flush(dev_priv);
1385 }
1386
1387 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1388 {
1389         struct drm_i915_private *dev_priv = dev->dev_private;
1390         struct drm_i915_gem_object *obj;
1391         struct i915_address_space *vm;
1392
1393         i915_check_and_clear_faults(dev);
1394
1395         /* First fill our portion of the GTT with scratch pages */
1396         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1397                                        dev_priv->gtt.base.start,
1398                                        dev_priv->gtt.base.total,
1399                                        true);
1400
1401         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1402                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1403                                                            &dev_priv->gtt.base);
1404                 if (!vma)
1405                         continue;
1406
1407                 i915_gem_clflush_object(obj, obj->pin_display);
1408                 /* The bind_vma code tries to be smart about tracking mappings.
1409                  * Unfortunately above, we've just wiped out the mappings
1410                  * without telling our object about it. So we need to fake it.
1411                  *
1412                  * Bind is not expected to fail since this is only called on
1413                  * resume and assumption is all requirements exist already.
1414                  */
1415                 vma->bound &= ~GLOBAL_BIND;
1416                 WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND));
1417         }
1418
1419
1420         if (INTEL_INFO(dev)->gen >= 8) {
1421                 if (IS_CHERRYVIEW(dev))
1422                         chv_setup_private_ppat(dev_priv);
1423                 else
1424                         bdw_setup_private_ppat(dev_priv);
1425
1426                 return;
1427         }
1428
1429         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1430                 /* TODO: Perhaps it shouldn't be gen6 specific */
1431                 if (i915_is_ggtt(vm)) {
1432                         if (dev_priv->mm.aliasing_ppgtt)
1433                                 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1434                         continue;
1435                 }
1436
1437                 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1438         }
1439
1440         i915_ggtt_flush(dev_priv);
1441 }
1442
1443 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1444 {
1445         if (obj->has_dma_mapping)
1446                 return 0;
1447
1448 #if 0
1449         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1450                         obj->pages->sgl, obj->pages->nents,
1451                         PCI_DMA_BIDIRECTIONAL))
1452                 return -ENOSPC;
1453 #endif
1454
1455         return 0;
1456 }
1457
1458 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1459 {
1460 #if 0
1461         writeq(pte, addr);
1462 #else
1463         iowrite32((u32)pte, addr);
1464         iowrite32(pte >> 32, addr + 4);
1465 #endif
1466 }
1467
1468 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1469                                      vm_page_t *pages,
1470                                      uint64_t start,
1471                                      unsigned int num_entries,
1472                                      enum i915_cache_level level, u32 unused)
1473 {
1474         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1475         unsigned first_entry = start >> PAGE_SHIFT;
1476         gen8_gtt_pte_t __iomem *gtt_entries =
1477                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1478         int i = 0;
1479         dma_addr_t addr = 0;
1480
1481         for (i=0;i<num_entries;i++) {
1482                 addr = VM_PAGE_TO_PHYS(pages[i]);
1483                 gen8_set_pte(&gtt_entries[i],
1484                              gen8_pte_encode(addr, level, true));
1485         }
1486
1487         /*
1488          * XXX: This serves as a posting read to make sure that the PTE has
1489          * actually been updated. There is some concern that even though
1490          * registers and PTEs are within the same BAR that they are potentially
1491          * of NUMA access patterns. Therefore, even with the way we assume
1492          * hardware should work, we must keep this posting read for paranoia.
1493          */
1494         if (i != 0)
1495                 WARN_ON(readq(&gtt_entries[i-1])
1496                         != gen8_pte_encode(addr, level, true));
1497
1498         /* This next bit makes the above posting read even more important. We
1499          * want to flush the TLBs only after we're certain all the PTE updates
1500          * have finished.
1501          */
1502         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1503         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1504 }
1505
1506 /*
1507  * Binds an object into the global gtt with the specified cache level. The object
1508  * will be accessible to the GPU via commands whose operands reference offsets
1509  * within the global GTT as well as accessible by the GPU through the GMADR
1510  * mapped BAR (dev_priv->mm.gtt->gtt).
1511  */
1512 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1513                                      vm_page_t *pages,
1514                                      uint64_t start,
1515                                      unsigned int num_entries,
1516                                      enum i915_cache_level level, u32 flags)
1517 {
1518         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1519         unsigned first_entry = start >> PAGE_SHIFT;
1520         gen6_gtt_pte_t __iomem *gtt_entries =
1521                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1522         int i = 0;
1523         dma_addr_t addr = 0; /* shut up gcc */
1524
1525         for (i = 0; i < num_entries; i++) {
1526                 addr = VM_PAGE_TO_PHYS(pages[i]);
1527                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1528         }
1529
1530         /* XXX: This serves as a posting read to make sure that the PTE has
1531          * actually been updated. There is some concern that even though
1532          * registers and PTEs are within the same BAR that they are potentially
1533          * of NUMA access patterns. Therefore, even with the way we assume
1534          * hardware should work, we must keep this posting read for paranoia.
1535          */
1536         if (i != 0) {
1537                 unsigned long gtt = readl(&gtt_entries[i-1]);
1538                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1539         }
1540
1541         /* This next bit makes the above posting read even more important. We
1542          * want to flush the TLBs only after we're certain all the PTE updates
1543          * have finished.
1544          */
1545         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1546         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1547 }
1548
1549 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1550                                   uint64_t start,
1551                                   uint64_t length,
1552                                   bool use_scratch)
1553 {
1554         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1555         unsigned first_entry = start >> PAGE_SHIFT;
1556         unsigned num_entries = length >> PAGE_SHIFT;
1557         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1558                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1559         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1560         int i;
1561
1562         if (WARN(num_entries > max_entries,
1563                  "First entry = %d; Num entries = %d (max=%d)\n",
1564                  first_entry, num_entries, max_entries))
1565                 num_entries = max_entries;
1566
1567         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1568                                       I915_CACHE_LLC,
1569                                       use_scratch);
1570         for (i = 0; i < num_entries; i++)
1571                 gen8_set_pte(&gtt_base[i], scratch_pte);
1572         readl(gtt_base);
1573 }
1574
1575 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1576                                   uint64_t start,
1577                                   uint64_t length,
1578                                   bool use_scratch)
1579 {
1580         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1581         unsigned first_entry = start >> PAGE_SHIFT;
1582         unsigned num_entries = length >> PAGE_SHIFT;
1583         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1584                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1585         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1586         int i;
1587
1588         if (WARN(num_entries > max_entries,
1589                  "First entry = %d; Num entries = %d (max=%d)\n",
1590                  first_entry, num_entries, max_entries))
1591                 num_entries = max_entries;
1592
1593         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1594
1595         for (i = 0; i < num_entries; i++)
1596                 iowrite32(scratch_pte, &gtt_base[i]);
1597         readl(gtt_base);
1598 }
1599
1600 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1601                                enum i915_cache_level cache_level,
1602                                u32 unused)
1603 {
1604         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1605         const unsigned int num_entries = vma->obj->base.size >> PAGE_SHIFT;
1606         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1607                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1608
1609         BUG_ON(!i915_is_ggtt(vma->vm));
1610         intel_gtt_insert_pages(entry, num_entries, vma->ggtt_view.pages, flags);
1611         vma->bound = GLOBAL_BIND;
1612 }
1613
1614 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1615                                   uint64_t start,
1616                                   uint64_t length,
1617                                   bool unused)
1618 {
1619         unsigned first_entry = start >> PAGE_SHIFT;
1620         unsigned num_entries = length >> PAGE_SHIFT;
1621         intel_gtt_clear_range(first_entry, num_entries);
1622 }
1623
1624 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1625 {
1626         const unsigned int first = vma->node.start >> PAGE_SHIFT;
1627         const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1628
1629         BUG_ON(!i915_is_ggtt(vma->vm));
1630         vma->bound = 0;
1631         intel_gtt_clear_range(first, size);
1632 }
1633
1634 static void ggtt_bind_vma(struct i915_vma *vma,
1635                           enum i915_cache_level cache_level,
1636                           u32 flags)
1637 {
1638         struct drm_device *dev = vma->vm->dev;
1639         struct drm_i915_private *dev_priv = dev->dev_private;
1640         struct drm_i915_gem_object *obj = vma->obj;
1641
1642         /* Currently applicable only to VLV */
1643         if (obj->gt_ro)
1644                 flags |= PTE_READ_ONLY;
1645
1646         /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1647          * or we have a global mapping already but the cacheability flags have
1648          * changed, set the global PTEs.
1649          *
1650          * If there is an aliasing PPGTT it is anecdotally faster, so use that
1651          * instead if none of the above hold true.
1652          *
1653          * NB: A global mapping should only be needed for special regions like
1654          * "gtt mappable", SNB errata, or if specified via special execbuf
1655          * flags. At all other times, the GPU will use the aliasing PPGTT.
1656          */
1657         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1658                 if (!(vma->bound & GLOBAL_BIND) ||
1659                     (cache_level != obj->cache_level)) {
1660                         vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
1661                                                 vma->node.start,
1662                                                 obj->base.size >> PAGE_SHIFT,
1663                                                 cache_level, flags);
1664                         vma->bound |= GLOBAL_BIND;
1665                 }
1666         }
1667
1668         if (dev_priv->mm.aliasing_ppgtt &&
1669             (!(vma->bound & LOCAL_BIND) ||
1670              (cache_level != obj->cache_level))) {
1671                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1672                 appgtt->base.insert_entries(&appgtt->base,
1673                                             vma->ggtt_view.pages,
1674                                             vma->node.start,
1675                                             obj->base.size >> PAGE_SHIFT,
1676                                             cache_level, flags);
1677                 vma->bound |= LOCAL_BIND;
1678         }
1679 }
1680
1681 static void ggtt_unbind_vma(struct i915_vma *vma)
1682 {
1683         struct drm_device *dev = vma->vm->dev;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         struct drm_i915_gem_object *obj = vma->obj;
1686
1687         if (vma->bound & GLOBAL_BIND) {
1688                 vma->vm->clear_range(vma->vm,
1689                                      vma->node.start,
1690                                      obj->base.size,
1691                                      true);
1692                 vma->bound &= ~GLOBAL_BIND;
1693         }
1694
1695         if (vma->bound & LOCAL_BIND) {
1696                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1697                 appgtt->base.clear_range(&appgtt->base,
1698                                          vma->node.start,
1699                                          obj->base.size,
1700                                          true);
1701                 vma->bound &= ~LOCAL_BIND;
1702         }
1703 }
1704
1705 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1706 {
1707         struct drm_device *dev = obj->base.dev;
1708         struct drm_i915_private *dev_priv = dev->dev_private;
1709         bool interruptible;
1710
1711         interruptible = do_idling(dev_priv);
1712
1713 #if 0
1714         if (!obj->has_dma_mapping)
1715                 dma_unmap_sg(&dev->pdev->dev,
1716                              obj->pages->sgl, obj->pages->nents,
1717                              PCI_DMA_BIDIRECTIONAL);
1718 #endif
1719
1720         undo_idling(dev_priv, interruptible);
1721 }
1722
1723 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1724                                   unsigned long color,
1725                                   u64 *start,
1726                                   u64 *end)
1727 {
1728         if (node->color != color)
1729                 *start += 4096;
1730
1731         if (!list_empty(&node->node_list)) {
1732                 node = list_entry(node->node_list.next,
1733                                   struct drm_mm_node,
1734                                   node_list);
1735                 if (node->allocated && node->color != color)
1736                         *end -= 4096;
1737         }
1738 }
1739
1740 static int i915_gem_setup_global_gtt(struct drm_device *dev,
1741                                      unsigned long start,
1742                                      unsigned long mappable_end,
1743                                      unsigned long end)
1744 {
1745         /* Let GEM Manage all of the aperture.
1746          *
1747          * However, leave one page at the end still bound to the scratch page.
1748          * There are a number of places where the hardware apparently prefetches
1749          * past the end of the object, and we've seen multiple hangs with the
1750          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1751          * aperture.  One page should be enough to keep any prefetching inside
1752          * of the aperture.
1753          */
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1756         unsigned long mappable;
1757         int error;
1758         struct drm_mm_node *entry;
1759         struct drm_i915_gem_object *obj;
1760         unsigned long hole_start, hole_end;
1761         int ret;
1762
1763         kprintf("MAPPABLE_END VS END %016jx %016jx\n", mappable_end, end);
1764         tsleep(&mappable_end, 0, "DELAY", hz); /* for kprintf */
1765         /*BUG_ON(mappable_end > end);*/
1766
1767         mappable = min(end, mappable_end) - start;
1768
1769         /* Subtract the guard page ... */
1770         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1771         if (!HAS_LLC(dev))
1772                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1773
1774         /* Mark any preallocated objects as occupied */
1775         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1776                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1777
1778                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1779                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1780
1781                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1782                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1783                 if (ret) {
1784                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1785                         return ret;
1786                 }
1787                 vma->bound |= GLOBAL_BIND;
1788         }
1789
1790         dev_priv->gtt.base.start = start;
1791         dev_priv->gtt.base.total = end - start;
1792
1793         /* Clear any non-preallocated blocks */
1794         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1795                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1796                               hole_start, hole_end);
1797                 ggtt_vm->clear_range(ggtt_vm, hole_start,
1798                                      hole_end - hole_start, true);
1799         }
1800
1801 #ifdef __DragonFly__
1802         device_printf(dev->dev,
1803             "taking over the fictitious range 0x%lx-0x%lx\n",
1804             dev_priv->gtt.mappable_base + start, dev_priv->gtt.mappable_base + start + mappable);
1805         error = -vm_phys_fictitious_reg_range(dev_priv->gtt.mappable_base + start,
1806             dev_priv->gtt.mappable_base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
1807 #endif
1808
1809         /* And finally clear the reserved guard page */
1810         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1811
1812         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1813                 struct i915_hw_ppgtt *ppgtt;
1814
1815                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1816                 if (!ppgtt)
1817                         return -ENOMEM;
1818
1819                 ret = __hw_ppgtt_init(dev, ppgtt);
1820                 if (ret != 0)
1821                         return ret;
1822
1823                 dev_priv->mm.aliasing_ppgtt = ppgtt;
1824         }
1825
1826         return 0;
1827 }
1828
1829 void i915_gem_init_global_gtt(struct drm_device *dev)
1830 {
1831         struct drm_i915_private *dev_priv = dev->dev_private;
1832         unsigned long gtt_size, mappable_size;
1833
1834         gtt_size = dev_priv->gtt.base.total;
1835         mappable_size = dev_priv->gtt.mappable_end;
1836
1837         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1838 }
1839
1840 void i915_global_gtt_cleanup(struct drm_device *dev)
1841 {
1842         struct drm_i915_private *dev_priv = dev->dev_private;
1843         struct i915_address_space *vm = &dev_priv->gtt.base;
1844
1845         if (dev_priv->mm.aliasing_ppgtt) {
1846                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1847
1848                 ppgtt->base.cleanup(&ppgtt->base);
1849         }
1850
1851         if (drm_mm_initialized(&vm->mm)) {
1852                 drm_mm_takedown(&vm->mm);
1853                 list_del(&vm->global_link);
1854         }
1855
1856         vm->cleanup(vm);
1857 }
1858
1859 static int setup_scratch_page(struct drm_device *dev)
1860 {
1861         struct drm_i915_private *dev_priv = dev->dev_private;
1862         struct vm_page *page;
1863         dma_addr_t dma_addr;
1864
1865         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1866         if (page == NULL)
1867                 return -ENOMEM;
1868         set_pages_uc(page, 1);
1869
1870 #ifdef CONFIG_INTEL_IOMMU
1871         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1872                                 PCI_DMA_BIDIRECTIONAL);
1873         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1874                 return -EINVAL;
1875 #else
1876         dma_addr = page_to_phys(page);
1877 #endif
1878         dev_priv->gtt.base.scratch.page = page;
1879         dev_priv->gtt.base.scratch.addr = dma_addr;
1880
1881         return 0;
1882 }
1883
1884 #if 0
1885 static void teardown_scratch_page(struct drm_device *dev)
1886 {
1887         struct drm_i915_private *dev_priv = dev->dev_private;
1888         struct vm_page *page = dev_priv->gtt.base.scratch.page;
1889
1890         set_pages_wb(page, 1);
1891         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1892                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1893         __free_page(page);
1894 }
1895 #endif
1896
1897 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1898 {
1899         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1900         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1901         return snb_gmch_ctl << 20;
1902 }
1903
1904 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1905 {
1906         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1907         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1908         if (bdw_gmch_ctl)
1909                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1910
1911 #ifdef CONFIG_X86_32
1912         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1913         if (bdw_gmch_ctl > 4)
1914                 bdw_gmch_ctl = 4;
1915 #endif
1916
1917         return bdw_gmch_ctl << 20;
1918 }
1919
1920 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1921 {
1922         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1923         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1924
1925         if (gmch_ctrl)
1926                 return 1 << (20 + gmch_ctrl);
1927
1928         return 0;
1929 }
1930
1931 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1932 {
1933         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1934         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1935         return snb_gmch_ctl << 25; /* 32 MB units */
1936 }
1937
1938 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1939 {
1940         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1941         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1942         return bdw_gmch_ctl << 25; /* 32 MB units */
1943 }
1944
1945 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1946 {
1947         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1948         gmch_ctrl &= SNB_GMCH_GMS_MASK;
1949
1950         /*
1951          * 0x0  to 0x10: 32MB increments starting at 0MB
1952          * 0x11 to 0x16: 4MB increments starting at 8MB
1953          * 0x17 to 0x1d: 4MB increments start at 36MB
1954          */
1955         if (gmch_ctrl < 0x11)
1956                 return gmch_ctrl << 25;
1957         else if (gmch_ctrl < 0x17)
1958                 return (gmch_ctrl - 0x11 + 2) << 22;
1959         else
1960                 return (gmch_ctrl - 0x17 + 9) << 22;
1961 }
1962
1963 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
1964 {
1965         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1966         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
1967
1968         if (gen9_gmch_ctl < 0xf0)
1969                 return gen9_gmch_ctl << 25; /* 32 MB units */
1970         else
1971                 /* 4MB increments starting at 0xf0 for 4MB */
1972                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
1973 }
1974
1975 static int ggtt_probe_common(struct drm_device *dev,
1976                              size_t gtt_size)
1977 {
1978         struct drm_i915_private *dev_priv = dev->dev_private;
1979         phys_addr_t gtt_phys_addr;
1980         int ret;
1981
1982         /* For Modern GENs the PTEs and register space are split in the BAR */
1983         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1984                 (pci_resource_len(dev->pdev, 0) / 2);
1985
1986         kprintf("gtt_probe_common: gtt_phys_addr=0x%lx\n", gtt_phys_addr);
1987         dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1988         if (!dev_priv->gtt.gsm) {
1989                 DRM_ERROR("Failed to map the gtt page table\n");
1990                 return -ENOMEM;
1991         }
1992
1993         ret = setup_scratch_page(dev);
1994         if (ret) {
1995                 DRM_ERROR("Scratch setup failed\n");
1996                 /* iounmap will also get called at remove, but meh */
1997 #if 0
1998                 iounmap(dev_priv->gtt.gsm);
1999 #endif
2000         }
2001
2002         return ret;
2003 }
2004
2005 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2006  * bits. When using advanced contexts each context stores its own PAT, but
2007  * writing this data shouldn't be harmful even in those cases. */
2008 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2009 {
2010         uint64_t pat;
2011
2012         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2013               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2014               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2015               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2016               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2017               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2018               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2019               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2020
2021         if (!USES_PPGTT(dev_priv->dev))
2022                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2023                  * so RTL will always use the value corresponding to
2024                  * pat_sel = 000".
2025                  * So let's disable cache for GGTT to avoid screen corruptions.
2026                  * MOCS still can be used though.
2027                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2028                  * before this patch, i.e. the same uncached + snooping access
2029                  * like on gen6/7 seems to be in effect.
2030                  * - So this just fixes blitter/render access. Again it looks
2031                  * like it's not just uncached access, but uncached + snooping.
2032                  * So we can still hold onto all our assumptions wrt cpu
2033                  * clflushing on LLC machines.
2034                  */
2035                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2036
2037         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2038          * write would work. */
2039         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2040         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2041 }
2042
2043 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2044 {
2045         uint64_t pat;
2046
2047         /*
2048          * Map WB on BDW to snooped on CHV.
2049          *
2050          * Only the snoop bit has meaning for CHV, the rest is
2051          * ignored.
2052          *
2053          * The hardware will never snoop for certain types of accesses:
2054          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2055          * - PPGTT page tables
2056          * - some other special cycles
2057          *
2058          * As with BDW, we also need to consider the following for GT accesses:
2059          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2060          * so RTL will always use the value corresponding to
2061          * pat_sel = 000".
2062          * Which means we must set the snoop bit in PAT entry 0
2063          * in order to keep the global status page working.
2064          */
2065         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2066               GEN8_PPAT(1, 0) |
2067               GEN8_PPAT(2, 0) |
2068               GEN8_PPAT(3, 0) |
2069               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2070               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2071               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2072               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2073
2074         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2075         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2076 }
2077
2078 static int gen8_gmch_probe(struct drm_device *dev,
2079                            size_t *gtt_total,
2080                            size_t *stolen,
2081                            phys_addr_t *mappable_base,
2082                            unsigned long *mappable_end)
2083 {
2084         struct drm_i915_private *dev_priv = dev->dev_private;
2085         unsigned int gtt_size;
2086         u16 snb_gmch_ctl;
2087         int ret;
2088
2089         /* TODO: We're not aware of mappable constraints on gen8 yet */
2090         *mappable_base = pci_resource_start(dev->pdev, 2);
2091         *mappable_end = pci_resource_len(dev->pdev, 2);
2092
2093 #if 0
2094         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2095                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2096 #endif
2097
2098         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2099
2100         if (INTEL_INFO(dev)->gen >= 9) {
2101                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2102                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2103         } else if (IS_CHERRYVIEW(dev)) {
2104                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2105                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2106         } else {
2107                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2108                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2109         }
2110
2111         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
2112
2113         if (IS_CHERRYVIEW(dev))
2114                 chv_setup_private_ppat(dev_priv);
2115         else
2116                 bdw_setup_private_ppat(dev_priv);
2117
2118         ret = ggtt_probe_common(dev, gtt_size);
2119
2120         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2121         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2122
2123         return ret;
2124 }
2125
2126 static int gen6_gmch_probe(struct drm_device *dev,
2127                            size_t *gtt_total,
2128                            size_t *stolen,
2129                            phys_addr_t *mappable_base,
2130                            unsigned long *mappable_end)
2131 {
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         unsigned int gtt_size;
2134         u16 snb_gmch_ctl;
2135         int ret;
2136
2137         *mappable_base = pci_resource_start(dev->pdev, 2);
2138         *mappable_end = pci_resource_len(dev->pdev, 2);
2139
2140         /* 64/512MB is the current min/max we actually know of, but this is just
2141          * a coarse sanity check.
2142          */
2143         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2144                 DRM_ERROR("Unknown GMADR size (%lx)\n",
2145                           dev_priv->gtt.mappable_end);
2146                 return -ENXIO;
2147         }
2148
2149 #if 0
2150         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2151                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2152 #endif
2153         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2154
2155         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2156
2157         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2158         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2159
2160         ret = ggtt_probe_common(dev, gtt_size);
2161
2162         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2163         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2164
2165         return ret;
2166 }
2167
2168 static void gen6_gmch_remove(struct i915_address_space *vm)
2169 {
2170 #if 0
2171         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2172
2173         iounmap(gtt->gsm);
2174         teardown_scratch_page(vm->dev);
2175 #endif
2176 }
2177
2178 static int i915_gmch_probe(struct drm_device *dev,
2179                            size_t *gtt_total,
2180                            size_t *stolen,
2181                            phys_addr_t *mappable_base,
2182                            unsigned long *mappable_end)
2183 {
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185 #if 0
2186         int ret;
2187
2188         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2189         if (!ret) {
2190                 DRM_ERROR("failed to set up gmch\n");
2191                 return -EIO;
2192         }
2193 #endif
2194
2195         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2196
2197         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2198         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2199
2200         if (unlikely(dev_priv->gtt.do_idle_maps))
2201                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2202
2203         return 0;
2204 }
2205
2206 static void i915_gmch_remove(struct i915_address_space *vm)
2207 {
2208         intel_gmch_remove();
2209 }
2210
2211 int i915_gem_gtt_init(struct drm_device *dev)
2212 {
2213         struct drm_i915_private *dev_priv = dev->dev_private;
2214         struct i915_gtt *gtt = &dev_priv->gtt;
2215         int ret;
2216
2217         if (INTEL_INFO(dev)->gen <= 5) {
2218                 gtt->gtt_probe = i915_gmch_probe;
2219                 gtt->base.cleanup = i915_gmch_remove;
2220         } else if (INTEL_INFO(dev)->gen < 8) {
2221                 gtt->gtt_probe = gen6_gmch_probe;
2222                 gtt->base.cleanup = gen6_gmch_remove;
2223                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2224                         gtt->base.pte_encode = iris_pte_encode;
2225                 else if (IS_HASWELL(dev))
2226                         gtt->base.pte_encode = hsw_pte_encode;
2227                 else if (IS_VALLEYVIEW(dev))
2228                         gtt->base.pte_encode = byt_pte_encode;
2229                 else if (INTEL_INFO(dev)->gen >= 7)
2230                         gtt->base.pte_encode = ivb_pte_encode;
2231                 else
2232                         gtt->base.pte_encode = snb_pte_encode;
2233         } else {
2234                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2235                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2236         }
2237
2238         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2239                              &gtt->mappable_base, &gtt->mappable_end);
2240         if (ret)
2241                 return ret;
2242
2243         gtt->base.dev = dev;
2244
2245         /* GMADR is the PCI mmio aperture into the global GTT. */
2246         DRM_INFO("Memory usable by graphics device = %zdM\n",
2247                  gtt->base.total >> 20);
2248         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2249         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2250 #ifdef CONFIG_INTEL_IOMMU
2251         if (intel_iommu_gfx_mapped)
2252                 DRM_INFO("VT-d active for gfx access\n");
2253 #endif
2254         /*
2255          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2256          * user's requested state against the hardware/driver capabilities.  We
2257          * do this now so that we can print out any log messages once rather
2258          * than every time we check intel_enable_ppgtt().
2259          */
2260         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2261         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2262
2263         return 0;
2264 }
2265
2266 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2267                                               struct i915_address_space *vm,
2268                                               const struct i915_ggtt_view *view)
2269 {
2270         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2271         if (vma == NULL)
2272                 return ERR_PTR(-ENOMEM);
2273
2274         INIT_LIST_HEAD(&vma->vma_link);
2275         INIT_LIST_HEAD(&vma->mm_list);
2276         INIT_LIST_HEAD(&vma->exec_list);
2277         vma->vm = vm;
2278         vma->obj = obj;
2279         vma->ggtt_view = *view;
2280
2281         if (INTEL_INFO(vm->dev)->gen >= 6) {
2282                 if (i915_is_ggtt(vm)) {
2283                         vma->unbind_vma = ggtt_unbind_vma;
2284                         vma->bind_vma = ggtt_bind_vma;
2285                 } else {
2286                         vma->unbind_vma = ppgtt_unbind_vma;
2287                         vma->bind_vma = ppgtt_bind_vma;
2288                 }
2289         } else {
2290                 BUG_ON(!i915_is_ggtt(vm));
2291                 vma->unbind_vma = i915_ggtt_unbind_vma;
2292                 vma->bind_vma = i915_ggtt_bind_vma;
2293         }
2294
2295         list_add_tail(&vma->vma_link, &obj->vma_list);
2296         if (!i915_is_ggtt(vm))
2297                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2298
2299         return vma;
2300 }
2301
2302 struct i915_vma *
2303 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
2304                                        struct i915_address_space *vm,
2305                                        const struct i915_ggtt_view *view)
2306 {
2307         struct i915_vma *vma;
2308
2309         vma = i915_gem_obj_to_vma_view(obj, vm, view);
2310         if (!vma)
2311                 vma = __i915_gem_vma_create(obj, vm, view);
2312
2313         return vma;
2314 }
2315
2316 static inline
2317 int i915_get_vma_pages(struct i915_vma *vma)
2318 {
2319         if (vma->ggtt_view.pages)
2320                 return 0;
2321
2322         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2323                 vma->ggtt_view.pages = vma->obj->pages;
2324         else
2325                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2326                           vma->ggtt_view.type);
2327
2328         if (!vma->ggtt_view.pages) {
2329                 DRM_ERROR("Failed to get pages for VMA view type %u!\n",
2330                           vma->ggtt_view.type);
2331                 return -EINVAL;
2332         }
2333
2334         return 0;
2335 }
2336
2337 /**
2338  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2339  * @vma: VMA to map
2340  * @cache_level: mapping cache level
2341  * @flags: flags like global or local mapping
2342  *
2343  * DMA addresses are taken from the scatter-gather table of this object (or of
2344  * this VMA in case of non-default GGTT views) and PTE entries set up.
2345  * Note that DMA addresses are also the only part of the SG table we care about.
2346  */
2347 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2348                   u32 flags)
2349 {
2350         int ret = i915_get_vma_pages(vma);
2351
2352         if (ret)
2353                 return ret;
2354
2355         vma->bind_vma(vma, cache_level, flags);
2356
2357         return 0;
2358 }