2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/export.h>
31 #include <linux/slab.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
47 static const struct dp_link_dpll gen4_dpll[] = {
49 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54 static const struct dp_link_dpll pch_dpll[] = {
56 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61 static const struct dp_link_dpll vlv_dpll[] = {
63 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
69 * CHV supports eDP 1.4 that have more link rates.
70 * Below only provides the fixed rate but exclude variable rate.
72 static const struct dp_link_dpll chv_dpll[] = {
74 * CHV requires to program fractional division for m2.
75 * m2 is stored in fixed point format using formula below
76 * (m2_int << 22) | m2_fraction
78 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
79 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
80 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
81 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
82 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
83 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
87 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
88 * @intel_dp: DP struct
90 * If a CPU or PCH DP output is attached to an eDP panel, this function
91 * will return true, and false otherwise.
93 static bool is_edp(struct intel_dp *intel_dp)
95 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
100 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
102 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104 return intel_dig_port->base.base.dev;
107 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
112 static void intel_dp_link_down(struct intel_dp *intel_dp);
113 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
114 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
115 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
116 static void vlv_steal_power_sequencer(struct drm_device *dev,
117 enum i915_pipe pipe);
120 intel_dp_max_link_bw(struct intel_dp *intel_dp)
122 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
123 struct drm_device *dev = intel_dp->attached_connector->base.dev;
125 switch (max_link_bw) {
126 case DP_LINK_BW_1_62:
129 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
130 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
131 INTEL_INFO(dev)->gen >= 8) &&
132 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
133 max_link_bw = DP_LINK_BW_5_4;
135 max_link_bw = DP_LINK_BW_2_7;
138 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw = DP_LINK_BW_1_62;
146 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
149 struct drm_device *dev = intel_dig_port->base.base.dev;
150 u8 source_max, sink_max;
153 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
154 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
157 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159 return min(source_max, sink_max);
163 * The units on the numbers in the next two are... bizarre. Examples will
164 * make it clearer; this one parallels an example in the eDP spec.
166 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 * 270000 * 1 * 8 / 10 == 216000
170 * The actual data capacity of that configuration is 2.16Gbit/s, so the
171 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
172 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
173 * 119000. At 18bpp that's 2142000 kilobits per second.
175 * Thus the strange-looking division by 10 in intel_dp_link_required, to
176 * get the result in decakilobits instead of kilobits.
180 intel_dp_link_required(int pixel_clock, int bpp)
182 return (pixel_clock * bpp + 9) / 10;
186 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188 return (max_link_clock * max_lanes * 8) / 10;
191 static enum drm_mode_status
192 intel_dp_mode_valid(struct drm_connector *connector,
193 struct drm_display_mode *mode)
195 struct intel_dp *intel_dp = intel_attached_dp(connector);
196 struct intel_connector *intel_connector = to_intel_connector(connector);
197 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
198 int target_clock = mode->clock;
199 int max_rate, mode_rate, max_lanes, max_link_clock;
201 if (is_edp(intel_dp) && fixed_mode) {
202 if (mode->hdisplay > fixed_mode->hdisplay)
205 if (mode->vdisplay > fixed_mode->vdisplay)
208 target_clock = fixed_mode->clock;
211 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
212 max_lanes = intel_dp_max_lane_count(intel_dp);
214 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
215 mode_rate = intel_dp_link_required(target_clock, 18);
217 if (mode_rate > max_rate)
218 return MODE_CLOCK_HIGH;
220 if (mode->clock < 10000)
221 return MODE_CLOCK_LOW;
223 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
224 return MODE_H_ILLEGAL;
229 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
236 for (i = 0; i < src_bytes; i++)
237 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device *dev)
254 struct drm_i915_private *dev_priv = dev->dev_private;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
271 case CLKCFG_FSB_1067:
273 case CLKCFG_FSB_1333:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp);
288 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
289 struct intel_dp *intel_dp);
291 static void pps_lock(struct intel_dp *intel_dp)
293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
294 struct intel_encoder *encoder = &intel_dig_port->base;
295 struct drm_device *dev = encoder->base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297 enum intel_display_power_domain power_domain;
300 * See vlv_power_sequencer_reset() why we need
301 * a power domain reference here.
303 power_domain = intel_display_port_power_domain(encoder);
304 intel_display_power_get(dev_priv, power_domain);
306 mutex_lock(&dev_priv->pps_mutex);
309 static void pps_unlock(struct intel_dp *intel_dp)
311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
312 struct intel_encoder *encoder = &intel_dig_port->base;
313 struct drm_device *dev = encoder->base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 enum intel_display_power_domain power_domain;
317 mutex_unlock(&dev_priv->pps_mutex);
319 power_domain = intel_display_port_power_domain(encoder);
320 intel_display_power_put(dev_priv, power_domain);
324 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
327 struct drm_device *dev = intel_dig_port->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
329 enum i915_pipe pipe = intel_dp->pps_pipe;
333 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
334 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
335 pipe_name(pipe), port_name(intel_dig_port->port)))
338 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
339 pipe_name(pipe), port_name(intel_dig_port->port));
341 /* Preserve the BIOS-computed detected bit. This is
342 * supposed to be read-only.
344 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
345 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
346 DP |= DP_PORT_WIDTH(1);
347 DP |= DP_LINK_TRAIN_PAT_1;
349 if (IS_CHERRYVIEW(dev))
350 DP |= DP_PIPE_SELECT_CHV(pipe);
351 else if (pipe == PIPE_B)
352 DP |= DP_PIPEB_SELECT;
354 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
357 * The DPLL for the pipe must be enabled for this to work.
358 * So enable temporarily it if it's not already enabled.
361 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
362 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
365 * Similar magic as in intel_dp_enable_port().
366 * We _must_ do this port enable + disable trick
367 * to make this power seqeuencer lock onto the port.
368 * Otherwise even VDD force bit won't work.
370 I915_WRITE(intel_dp->output_reg, DP);
371 POSTING_READ(intel_dp->output_reg);
373 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
374 POSTING_READ(intel_dp->output_reg);
376 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
377 POSTING_READ(intel_dp->output_reg);
380 vlv_force_pll_off(dev, pipe);
383 static enum i915_pipe
384 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
387 struct drm_device *dev = intel_dig_port->base.base.dev;
388 struct drm_i915_private *dev_priv = dev->dev_private;
389 struct intel_encoder *encoder;
390 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
393 lockdep_assert_held(&dev_priv->pps_mutex);
395 /* We should never land here with regular DP ports */
396 WARN_ON(!is_edp(intel_dp));
398 if (intel_dp->pps_pipe != INVALID_PIPE)
399 return intel_dp->pps_pipe;
402 * We don't have power sequencer currently.
403 * Pick one that's not used by other ports.
405 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 struct intel_dp *tmp;
409 if (encoder->type != INTEL_OUTPUT_EDP)
412 tmp = enc_to_intel_dp(&encoder->base);
414 if (tmp->pps_pipe != INVALID_PIPE)
415 pipes &= ~(1 << tmp->pps_pipe);
419 * Didn't find one. This should not happen since there
420 * are two power sequencers and up to two eDP ports.
422 if (WARN_ON(pipes == 0))
425 pipe = ffs(pipes) - 1;
427 vlv_steal_power_sequencer(dev, pipe);
428 intel_dp->pps_pipe = pipe;
430 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
431 pipe_name(intel_dp->pps_pipe),
432 port_name(intel_dig_port->port));
434 /* init power sequencer on this pipe and port */
435 intel_dp_init_panel_power_sequencer(dev, intel_dp);
436 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
439 * Even vdd force doesn't work until we've made
440 * the power sequencer lock in on the port.
442 vlv_power_sequencer_kick(intel_dp);
444 return intel_dp->pps_pipe;
447 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
448 enum i915_pipe pipe);
450 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
453 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
456 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
459 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
462 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
468 static enum i915_pipe
469 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 vlv_pipe_check pipe_check)
475 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
476 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
477 PANEL_PORT_SELECT_MASK;
479 if (port_sel != PANEL_PORT_SELECT_VLV(port))
482 if (!pipe_check(dev_priv, pipe))
492 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 struct drm_i915_private *dev_priv = dev->dev_private;
497 enum port port = intel_dig_port->port;
499 lockdep_assert_held(&dev_priv->pps_mutex);
501 /* try to find a pipe with this port selected */
502 /* first pick one where the panel is on */
503 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 /* didn't find one? pick one where vdd is on */
506 if (intel_dp->pps_pipe == INVALID_PIPE)
507 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
508 vlv_pipe_has_vdd_on);
509 /* didn't find one? pick one with just the correct port */
510 if (intel_dp->pps_pipe == INVALID_PIPE)
511 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
514 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
515 if (intel_dp->pps_pipe == INVALID_PIPE) {
516 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
521 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
522 port_name(port), pipe_name(intel_dp->pps_pipe));
524 intel_dp_init_panel_power_sequencer(dev, intel_dp);
525 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
528 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530 struct drm_device *dev = dev_priv->dev;
531 struct intel_encoder *encoder;
533 if (WARN_ON(!IS_VALLEYVIEW(dev)))
537 * We can't grab pps_mutex here due to deadlock with power_domain
538 * mutex when power_domain functions are called while holding pps_mutex.
539 * That also means that in order to use pps_pipe the code needs to
540 * hold both a power domain reference and pps_mutex, and the power domain
541 * reference get/put must be done while _not_ holding pps_mutex.
542 * pps_{lock,unlock}() do these steps in the correct order, so one
543 * should use them always.
546 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
547 struct intel_dp *intel_dp;
549 if (encoder->type != INTEL_OUTPUT_EDP)
552 intel_dp = enc_to_intel_dp(&encoder->base);
553 intel_dp->pps_pipe = INVALID_PIPE;
557 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561 if (HAS_PCH_SPLIT(dev))
562 return PCH_PP_CONTROL;
564 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
567 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571 if (HAS_PCH_SPLIT(dev))
572 return PCH_PP_STATUS;
574 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
577 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
578 This function only applicable when panel PM state is not to be tracked */
580 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
588 u32 pp_ctrl_reg, pp_div_reg;
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
595 if (IS_VALLEYVIEW(dev)) {
596 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
609 pps_unlock(intel_dp);
615 static bool edp_have_panel_power(struct intel_dp *intel_dp)
617 struct drm_device *dev = intel_dp_to_dev(intel_dp);
618 struct drm_i915_private *dev_priv = dev->dev_private;
620 lockdep_assert_held(&dev_priv->pps_mutex);
622 if (IS_VALLEYVIEW(dev) &&
623 intel_dp->pps_pipe == INVALID_PIPE)
626 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
629 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
631 struct drm_device *dev = intel_dp_to_dev(intel_dp);
632 struct drm_i915_private *dev_priv = dev->dev_private;
634 lockdep_assert_held(&dev_priv->pps_mutex);
636 if (IS_VALLEYVIEW(dev) &&
637 intel_dp->pps_pipe == INVALID_PIPE)
640 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
644 intel_dp_check_edp(struct intel_dp *intel_dp)
646 struct drm_device *dev = intel_dp_to_dev(intel_dp);
647 struct drm_i915_private *dev_priv = dev->dev_private;
649 if (!is_edp(intel_dp))
652 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
653 WARN(1, "eDP powered off while attempting aux channel communication.\n");
654 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
655 I915_READ(_pp_stat_reg(intel_dp)),
656 I915_READ(_pp_ctrl_reg(intel_dp)));
661 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
663 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
664 struct drm_device *dev = intel_dig_port->base.base.dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
670 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
672 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
673 msecs_to_jiffies_timeout(10));
675 done = wait_for_atomic(C, 10) == 0;
677 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
684 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 struct drm_device *dev = intel_dig_port->base.base.dev;
690 * The clock divider is based off the hrawclk, and would like to run at
691 * 2MHz. So, take the hrawclk value and divide by 2 and use that
693 return index ? 0 : intel_hrawclk(dev) / 2;
696 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
698 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
699 struct drm_device *dev = intel_dig_port->base.base.dev;
704 if (intel_dig_port->port == PORT_A) {
705 if (IS_GEN6(dev) || IS_GEN7(dev))
706 return 200; /* SNB & IVB eDP input clock at 400Mhz */
708 return 225; /* eDP input clock at 450Mhz */
710 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
714 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
716 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
717 struct drm_device *dev = intel_dig_port->base.base.dev;
718 struct drm_i915_private *dev_priv = dev->dev_private;
720 if (intel_dig_port->port == PORT_A) {
723 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
724 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
725 /* Workaround for non-ULT HSW */
732 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
736 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
738 return index ? 0 : 100;
741 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
744 * SKL doesn't need us to program the AUX clock divider (Hardware will
745 * derive the clock from CDCLK automatically). We still implement the
746 * get_aux_clock_divider vfunc to plug-in into the existing code.
748 return index ? 0 : 1;
751 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
754 uint32_t aux_clock_divider)
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
757 struct drm_device *dev = intel_dig_port->base.base.dev;
758 uint32_t precharge, timeout;
765 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
766 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
768 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
770 return DP_AUX_CH_CTL_SEND_BUSY |
772 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
773 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR |
776 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
777 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
778 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
781 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
786 return DP_AUX_CH_CTL_SEND_BUSY |
788 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
789 DP_AUX_CH_CTL_TIME_OUT_ERROR |
790 DP_AUX_CH_CTL_TIME_OUT_1600us |
791 DP_AUX_CH_CTL_RECEIVE_ERROR |
792 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
793 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
797 intel_dp_aux_ch(struct intel_dp *intel_dp,
798 const uint8_t *send, int send_bytes,
799 uint8_t *recv, int recv_size)
801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
802 struct drm_device *dev = intel_dig_port->base.base.dev;
803 struct drm_i915_private *dev_priv = dev->dev_private;
804 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
805 uint32_t ch_data = ch_ctl + 4;
806 uint32_t aux_clock_divider;
807 int i, ret, recv_bytes;
810 bool has_aux_irq = HAS_AUX_IRQ(dev);
816 * We will be called with VDD already enabled for dpcd/edid/oui reads.
817 * In such cases we want to leave VDD enabled and it's up to upper layers
818 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
821 vdd = edp_panel_vdd_on(intel_dp);
823 /* dp aux is extremely sensitive to irq latency, hence request the
824 * lowest possible wakeup latency and so prevent the cpu from going into
827 pm_qos_update_request(&dev_priv->pm_qos, 0);
829 intel_dp_check_edp(intel_dp);
831 intel_aux_display_runtime_get(dev_priv);
833 /* Try to wait for any previous AUX channel activity */
834 for (try = 0; try < 3; try++) {
835 status = I915_READ_NOTRACE(ch_ctl);
836 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
842 WARN(1, "dp_aux_ch not started status 0x%08x\n",
848 /* Only 5 data registers! */
849 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
854 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
855 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
860 /* Must try at least 3 times according to DP spec */
861 for (try = 0; try < 5; try++) {
862 /* Load the send data into the aux channel data registers */
863 for (i = 0; i < send_bytes; i += 4)
864 I915_WRITE(ch_data + i,
865 intel_dp_pack_aux(send + i,
868 /* Send the command and wait for it to complete */
869 I915_WRITE(ch_ctl, send_ctl);
871 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
873 /* Clear done status and any errors */
877 DP_AUX_CH_CTL_TIME_OUT_ERROR |
878 DP_AUX_CH_CTL_RECEIVE_ERROR);
880 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
881 DP_AUX_CH_CTL_RECEIVE_ERROR))
883 if (status & DP_AUX_CH_CTL_DONE)
886 if (status & DP_AUX_CH_CTL_DONE)
890 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
891 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
899 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
907 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
913 /* Unload any bytes sent back from the other side */
914 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
916 if (recv_bytes > recv_size)
917 recv_bytes = recv_size;
919 for (i = 0; i < recv_bytes; i += 4)
920 intel_dp_unpack_aux(I915_READ(ch_data + i),
921 recv + i, recv_bytes - i);
925 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
926 intel_aux_display_runtime_put(dev_priv);
929 edp_panel_vdd_off(intel_dp, false);
931 pps_unlock(intel_dp);
936 #define BARE_ADDRESS_SIZE 3
937 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
939 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
941 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
942 uint8_t txbuf[20], rxbuf[20];
943 size_t txsize, rxsize;
946 txbuf[0] = msg->request << 4;
947 txbuf[1] = msg->address >> 8;
948 txbuf[2] = msg->address & 0xff;
949 txbuf[3] = msg->size - 1;
951 switch (msg->request & ~DP_AUX_I2C_MOT) {
952 case DP_AUX_NATIVE_WRITE:
953 case DP_AUX_I2C_WRITE:
954 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
957 if (WARN_ON(txsize > 20))
960 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
962 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
964 msg->reply = rxbuf[0] >> 4;
966 /* Return payload size. */
971 case DP_AUX_NATIVE_READ:
972 case DP_AUX_I2C_READ:
973 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
974 rxsize = msg->size + 1;
976 if (WARN_ON(rxsize > 20))
979 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
981 msg->reply = rxbuf[0] >> 4;
983 * Assume happy day, and copy the data. The caller is
984 * expected to check msg->reply before touching it.
986 * Return payload size.
989 memcpy(msg->buffer, rxbuf + 1, ret);
1002 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
1003 uint8_t write_byte, uint8_t *read_byte)
1005 struct i2c_algo_dp_aux_data *data = device_get_softc(adapter);
1006 struct intel_dp *intel_dp = data->priv;
1007 uint16_t address = data->address;
1015 intel_edp_panel_vdd_on(intel_dp);
1016 intel_dp_check_edp(intel_dp);
1017 /* Set up the command byte */
1018 if (mode & MODE_I2C_READ)
1019 msg[0] = DP_AUX_I2C_READ << 4;
1021 msg[0] = DP_AUX_I2C_WRITE << 4;
1023 if (!(mode & MODE_I2C_STOP))
1024 msg[0] |= DP_AUX_I2C_MOT << 4;
1026 msg[1] = address >> 8;
1030 case MODE_I2C_WRITE:
1032 msg[4] = write_byte;
1048 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
1049 * required to retry at least seven times upon receiving AUX_DEFER
1050 * before giving up the AUX transaction.
1052 for (retry = 0; retry < 7; retry++) {
1053 ret = intel_dp_aux_ch(intel_dp,
1055 reply, reply_bytes);
1057 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
1061 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
1062 case DP_AUX_NATIVE_REPLY_ACK:
1063 /* I2C-over-AUX Reply field is only valid
1064 * when paired with AUX ACK.
1067 case DP_AUX_NATIVE_REPLY_NACK:
1068 DRM_DEBUG_KMS("aux_ch native nack\n");
1071 case DP_AUX_NATIVE_REPLY_DEFER:
1073 * For now, just give more slack to branch devices. We
1074 * could check the DPCD for I2C bit rate capabilities,
1075 * and if available, adjust the interval. We could also
1076 * be more careful with DP-to-Legacy adapters where a
1077 * long legacy cable may force very low I2C bit rates.
1079 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1080 DP_DWN_STRM_PORT_PRESENT)
1081 usleep_range(500, 600);
1083 usleep_range(300, 400);
1086 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
1092 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
1093 case DP_AUX_I2C_REPLY_ACK:
1094 if (mode == MODE_I2C_READ) {
1095 *read_byte = reply[1];
1097 ret = 0; /* reply_bytes - 1 */
1099 case DP_AUX_I2C_REPLY_NACK:
1100 DRM_DEBUG_KMS("aux_i2c nack\n");
1103 case DP_AUX_I2C_REPLY_DEFER:
1104 DRM_DEBUG_KMS("aux_i2c defer\n");
1108 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
1114 DRM_ERROR("too many retries, giving up\n");
1122 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1124 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1125 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1126 enum port port = intel_dig_port->port;
1127 const char *name = NULL;
1132 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1136 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1140 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1144 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1152 * The AUX_CTL register is usually DP_CTL + 0x10.
1154 * On Haswell and Broadwell though:
1155 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1156 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1158 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1160 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1161 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1163 intel_dp->aux.name = name;
1164 intel_dp->aux.dev = dev->dev;
1165 intel_dp->aux.transfer = intel_dp_aux_transfer;
1167 DRM_DEBUG_KMS("i2c_init %s\n", name);
1168 ret = iic_dp_aux_add_bus(connector->base.dev->dev, name,
1169 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
1170 &intel_dp->aux.ddc);
1171 WARN(ret, "intel_dp_i2c_init failed with error %d for port %c\n",
1172 ret, port_name(port));
1177 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1179 intel_connector_unregister(intel_connector);
1184 intel_dp_i2c_init(struct intel_dp *intel_dp,
1185 struct intel_connector *intel_connector, const char *name)
1189 DRM_DEBUG_KMS("i2c_init %s\n", name);
1191 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
1192 intel_dp->adapter.owner = THIS_MODULE;
1193 intel_dp->adapter.class = I2C_CLASS_DDC;
1194 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
1195 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
1196 intel_dp->adapter.algo_data = &intel_dp->algo;
1197 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
1199 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
1203 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
1204 &intel_dp->adapter.dev.kobj,
1205 intel_dp->adapter.dev.kobj.name);
1207 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
1208 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
1209 &intel_dp->adapter);
1216 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
1220 pipe_config->ddi_pll_sel = SKL_DPLL0;
1221 pipe_config->dpll_hw_state.cfgcr1 = 0;
1222 pipe_config->dpll_hw_state.cfgcr2 = 0;
1224 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1226 case DP_LINK_BW_1_62:
1227 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1230 case DP_LINK_BW_2_7:
1231 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1234 case DP_LINK_BW_5_4:
1235 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1239 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1243 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1246 case DP_LINK_BW_1_62:
1247 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1249 case DP_LINK_BW_2_7:
1250 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1252 case DP_LINK_BW_5_4:
1253 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1259 intel_dp_set_clock(struct intel_encoder *encoder,
1260 struct intel_crtc_state *pipe_config, int link_bw)
1262 struct drm_device *dev = encoder->base.dev;
1263 const struct dp_link_dpll *divisor = NULL;
1267 divisor = gen4_dpll;
1268 count = ARRAY_SIZE(gen4_dpll);
1269 } else if (HAS_PCH_SPLIT(dev)) {
1271 count = ARRAY_SIZE(pch_dpll);
1272 } else if (IS_CHERRYVIEW(dev)) {
1274 count = ARRAY_SIZE(chv_dpll);
1275 } else if (IS_VALLEYVIEW(dev)) {
1277 count = ARRAY_SIZE(vlv_dpll);
1280 if (divisor && count) {
1281 for (i = 0; i < count; i++) {
1282 if (link_bw == divisor[i].link_bw) {
1283 pipe_config->dpll = divisor[i].dpll;
1284 pipe_config->clock_set = true;
1292 intel_dp_compute_config(struct intel_encoder *encoder,
1293 struct intel_crtc_state *pipe_config)
1295 struct drm_device *dev = encoder->base.dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1298 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1299 enum port port = dp_to_dig_port(intel_dp)->port;
1300 struct intel_crtc *intel_crtc = encoder->new_crtc;
1301 struct intel_connector *intel_connector = intel_dp->attached_connector;
1302 int lane_count, clock;
1303 int min_lane_count = 1;
1304 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1305 /* Conveniently, the link BW constants become indices with a shift...*/
1307 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1309 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1310 int link_avail, link_clock;
1312 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1313 pipe_config->has_pch_encoder = true;
1315 pipe_config->has_dp_encoder = true;
1316 pipe_config->has_drrs = false;
1317 pipe_config->has_audio = intel_dp->has_audio;
1319 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1320 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1322 if (!HAS_PCH_SPLIT(dev))
1323 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1324 intel_connector->panel.fitting_mode);
1326 intel_pch_panel_fitting(intel_crtc, pipe_config,
1327 intel_connector->panel.fitting_mode);
1330 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1333 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1334 "max bw %02x pixel clock %iKHz\n",
1335 max_lane_count, bws[max_clock],
1336 adjusted_mode->crtc_clock);
1338 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1339 * bpc in between. */
1340 bpp = pipe_config->pipe_bpp;
1341 if (is_edp(intel_dp)) {
1342 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1343 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1344 dev_priv->vbt.edp_bpp);
1345 bpp = dev_priv->vbt.edp_bpp;
1349 * Use the maximum clock and number of lanes the eDP panel
1350 * advertizes being capable of. The panels are generally
1351 * designed to support only a single clock and lane
1352 * configuration, and typically these values correspond to the
1353 * native resolution of the panel.
1355 min_lane_count = max_lane_count;
1356 min_clock = max_clock;
1359 for (; bpp >= 6*3; bpp -= 2*3) {
1360 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1363 for (clock = min_clock; clock <= max_clock; clock++) {
1364 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1365 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1366 link_avail = intel_dp_max_data_rate(link_clock,
1369 if (mode_rate <= link_avail) {
1379 if (intel_dp->color_range_auto) {
1382 * CEA-861-E - 5.1 Default Encoding Parameters
1383 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1385 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1386 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1388 intel_dp->color_range = 0;
1391 if (intel_dp->color_range)
1392 pipe_config->limited_color_range = true;
1394 intel_dp->link_bw = bws[clock];
1395 intel_dp->lane_count = lane_count;
1396 pipe_config->pipe_bpp = bpp;
1397 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1399 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1400 intel_dp->link_bw, intel_dp->lane_count,
1401 pipe_config->port_clock, bpp);
1402 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1403 mode_rate, link_avail);
1405 intel_link_compute_m_n(bpp, lane_count,
1406 adjusted_mode->crtc_clock,
1407 pipe_config->port_clock,
1408 &pipe_config->dp_m_n);
1410 if (intel_connector->panel.downclock_mode != NULL &&
1411 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1412 pipe_config->has_drrs = true;
1413 intel_link_compute_m_n(bpp, lane_count,
1414 intel_connector->panel.downclock_mode->clock,
1415 pipe_config->port_clock,
1416 &pipe_config->dp_m2_n2);
1419 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1420 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1421 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1422 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1424 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1429 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1431 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1432 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1433 struct drm_device *dev = crtc->base.dev;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1437 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1438 crtc->config->port_clock);
1439 dpa_ctl = I915_READ(DP_A);
1440 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1442 if (crtc->config->port_clock == 162000) {
1443 /* For a long time we've carried around a ILK-DevA w/a for the
1444 * 160MHz clock. If we're really unlucky, it's still required.
1446 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1447 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1448 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1450 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1451 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1454 I915_WRITE(DP_A, dpa_ctl);
1460 static void intel_dp_prepare(struct intel_encoder *encoder)
1462 struct drm_device *dev = encoder->base.dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1465 enum port port = dp_to_dig_port(intel_dp)->port;
1466 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1467 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1470 * There are four kinds of DP registers:
1477 * IBX PCH and CPU are the same for almost everything,
1478 * except that the CPU DP PLL is configured in this
1481 * CPT PCH is quite different, having many bits moved
1482 * to the TRANS_DP_CTL register instead. That
1483 * configuration happens (oddly) in ironlake_pch_enable
1486 /* Preserve the BIOS-computed detected bit. This is
1487 * supposed to be read-only.
1489 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1491 /* Handle DP bits in common between all three register formats */
1492 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1493 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1495 if (crtc->config->has_audio)
1496 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1498 /* Split out the IBX/CPU vs CPT settings */
1500 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1501 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1502 intel_dp->DP |= DP_SYNC_HS_HIGH;
1503 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1504 intel_dp->DP |= DP_SYNC_VS_HIGH;
1505 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1507 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1508 intel_dp->DP |= DP_ENHANCED_FRAMING;
1510 intel_dp->DP |= crtc->pipe << 29;
1511 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1512 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1513 intel_dp->DP |= intel_dp->color_range;
1515 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1516 intel_dp->DP |= DP_SYNC_HS_HIGH;
1517 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1518 intel_dp->DP |= DP_SYNC_VS_HIGH;
1519 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1521 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1522 intel_dp->DP |= DP_ENHANCED_FRAMING;
1524 if (!IS_CHERRYVIEW(dev)) {
1525 if (crtc->pipe == 1)
1526 intel_dp->DP |= DP_PIPEB_SELECT;
1528 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1531 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1535 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1536 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1538 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1539 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1541 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1542 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1544 static void wait_panel_status(struct intel_dp *intel_dp,
1548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 u32 pp_stat_reg, pp_ctrl_reg;
1552 lockdep_assert_held(&dev_priv->pps_mutex);
1554 pp_stat_reg = _pp_stat_reg(intel_dp);
1555 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1557 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1559 I915_READ(pp_stat_reg),
1560 I915_READ(pp_ctrl_reg));
1562 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1563 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1564 I915_READ(pp_stat_reg),
1565 I915_READ(pp_ctrl_reg));
1568 DRM_DEBUG_KMS("Wait complete\n");
1571 static void wait_panel_on(struct intel_dp *intel_dp)
1573 DRM_DEBUG_KMS("Wait for panel power on\n");
1574 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1577 static void wait_panel_off(struct intel_dp *intel_dp)
1579 DRM_DEBUG_KMS("Wait for panel power off time\n");
1580 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1583 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1585 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1587 /* When we disable the VDD override bit last we have to do the manual
1589 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1590 intel_dp->panel_power_cycle_delay);
1592 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1595 static void wait_backlight_on(struct intel_dp *intel_dp)
1597 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1598 intel_dp->backlight_on_delay);
1601 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1603 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1604 intel_dp->backlight_off_delay);
1607 /* Read the current pp_control value, unlocking the register if it
1611 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1613 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1617 lockdep_assert_held(&dev_priv->pps_mutex);
1619 control = I915_READ(_pp_ctrl_reg(intel_dp));
1620 control &= ~PANEL_UNLOCK_MASK;
1621 control |= PANEL_UNLOCK_REGS;
1626 * Must be paired with edp_panel_vdd_off().
1627 * Must hold pps_mutex around the whole on/off sequence.
1628 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1630 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1632 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1634 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636 enum intel_display_power_domain power_domain;
1638 u32 pp_stat_reg, pp_ctrl_reg;
1639 bool need_to_disable = !intel_dp->want_panel_vdd;
1641 lockdep_assert_held(&dev_priv->pps_mutex);
1643 if (!is_edp(intel_dp))
1646 cancel_delayed_work(&intel_dp->panel_vdd_work);
1647 intel_dp->want_panel_vdd = true;
1649 if (edp_have_panel_vdd(intel_dp))
1650 return need_to_disable;
1652 power_domain = intel_display_port_power_domain(intel_encoder);
1653 intel_display_power_get(dev_priv, power_domain);
1655 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1656 port_name(intel_dig_port->port));
1658 if (!edp_have_panel_power(intel_dp))
1659 wait_panel_power_cycle(intel_dp);
1661 pp = ironlake_get_pp_control(intel_dp);
1662 pp |= EDP_FORCE_VDD;
1664 pp_stat_reg = _pp_stat_reg(intel_dp);
1665 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1667 I915_WRITE(pp_ctrl_reg, pp);
1668 POSTING_READ(pp_ctrl_reg);
1669 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1670 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1672 * If the panel wasn't on, delay before accessing aux channel
1674 if (!edp_have_panel_power(intel_dp)) {
1675 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1676 port_name(intel_dig_port->port));
1677 msleep(intel_dp->panel_power_up_delay);
1680 return need_to_disable;
1684 * Must be paired with intel_edp_panel_vdd_off() or
1685 * intel_edp_panel_off().
1686 * Nested calls to these functions are not allowed since
1687 * we drop the lock. Caller must use some higher level
1688 * locking to prevent nested calls from other threads.
1690 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1694 if (!is_edp(intel_dp))
1698 vdd = edp_panel_vdd_on(intel_dp);
1699 pps_unlock(intel_dp);
1701 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1702 port_name(dp_to_dig_port(intel_dp)->port));
1705 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1707 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 struct intel_digital_port *intel_dig_port =
1710 dp_to_dig_port(intel_dp);
1711 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1712 enum intel_display_power_domain power_domain;
1714 u32 pp_stat_reg, pp_ctrl_reg;
1716 lockdep_assert_held(&dev_priv->pps_mutex);
1718 WARN_ON(intel_dp->want_panel_vdd);
1720 if (!edp_have_panel_vdd(intel_dp))
1723 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1724 port_name(intel_dig_port->port));
1726 pp = ironlake_get_pp_control(intel_dp);
1727 pp &= ~EDP_FORCE_VDD;
1729 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1730 pp_stat_reg = _pp_stat_reg(intel_dp);
1732 I915_WRITE(pp_ctrl_reg, pp);
1733 POSTING_READ(pp_ctrl_reg);
1735 /* Make sure sequencer is idle before allowing subsequent activity */
1736 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1737 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1739 if ((pp & POWER_TARGET_ON) == 0)
1740 intel_dp->last_power_cycle = jiffies;
1742 power_domain = intel_display_port_power_domain(intel_encoder);
1743 intel_display_power_put(dev_priv, power_domain);
1746 static void edp_panel_vdd_work(struct work_struct *__work)
1748 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1749 struct intel_dp, panel_vdd_work);
1752 if (!intel_dp->want_panel_vdd)
1753 edp_panel_vdd_off_sync(intel_dp);
1754 pps_unlock(intel_dp);
1757 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1759 unsigned long delay;
1762 * Queue the timer to fire a long time from now (relative to the power
1763 * down delay) to keep the panel power up across a sequence of
1766 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1767 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1771 * Must be paired with edp_panel_vdd_on().
1772 * Must hold pps_mutex around the whole on/off sequence.
1773 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1775 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1777 struct drm_i915_private *dev_priv =
1778 intel_dp_to_dev(intel_dp)->dev_private;
1780 lockdep_assert_held(&dev_priv->pps_mutex);
1782 if (!is_edp(intel_dp))
1785 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1786 port_name(dp_to_dig_port(intel_dp)->port));
1788 intel_dp->want_panel_vdd = false;
1791 edp_panel_vdd_off_sync(intel_dp);
1793 edp_panel_vdd_schedule_off(intel_dp);
1796 static void edp_panel_on(struct intel_dp *intel_dp)
1798 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1803 lockdep_assert_held(&dev_priv->pps_mutex);
1805 if (!is_edp(intel_dp))
1808 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1809 port_name(dp_to_dig_port(intel_dp)->port));
1811 if (WARN(edp_have_panel_power(intel_dp),
1812 "eDP port %c panel power already on\n",
1813 port_name(dp_to_dig_port(intel_dp)->port)))
1816 wait_panel_power_cycle(intel_dp);
1818 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1819 pp = ironlake_get_pp_control(intel_dp);
1821 /* ILK workaround: disable reset around power sequence */
1822 pp &= ~PANEL_POWER_RESET;
1823 I915_WRITE(pp_ctrl_reg, pp);
1824 POSTING_READ(pp_ctrl_reg);
1827 pp |= POWER_TARGET_ON;
1829 pp |= PANEL_POWER_RESET;
1831 I915_WRITE(pp_ctrl_reg, pp);
1832 POSTING_READ(pp_ctrl_reg);
1834 wait_panel_on(intel_dp);
1835 intel_dp->last_power_on = jiffies;
1838 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1839 I915_WRITE(pp_ctrl_reg, pp);
1840 POSTING_READ(pp_ctrl_reg);
1844 void intel_edp_panel_on(struct intel_dp *intel_dp)
1846 if (!is_edp(intel_dp))
1850 edp_panel_on(intel_dp);
1851 pps_unlock(intel_dp);
1855 static void edp_panel_off(struct intel_dp *intel_dp)
1857 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1858 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1859 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1860 struct drm_i915_private *dev_priv = dev->dev_private;
1861 enum intel_display_power_domain power_domain;
1865 lockdep_assert_held(&dev_priv->pps_mutex);
1867 if (!is_edp(intel_dp))
1870 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1871 port_name(dp_to_dig_port(intel_dp)->port));
1873 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1874 port_name(dp_to_dig_port(intel_dp)->port));
1876 pp = ironlake_get_pp_control(intel_dp);
1877 /* We need to switch off panel power _and_ force vdd, for otherwise some
1878 * panels get very unhappy and cease to work. */
1879 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1882 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1884 intel_dp->want_panel_vdd = false;
1886 I915_WRITE(pp_ctrl_reg, pp);
1887 POSTING_READ(pp_ctrl_reg);
1889 intel_dp->last_power_cycle = jiffies;
1890 wait_panel_off(intel_dp);
1892 /* We got a reference when we enabled the VDD. */
1893 power_domain = intel_display_port_power_domain(intel_encoder);
1894 intel_display_power_put(dev_priv, power_domain);
1897 void intel_edp_panel_off(struct intel_dp *intel_dp)
1899 if (!is_edp(intel_dp))
1903 edp_panel_off(intel_dp);
1904 pps_unlock(intel_dp);
1907 /* Enable backlight in the panel power control. */
1908 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1910 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1911 struct drm_device *dev = intel_dig_port->base.base.dev;
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1917 * If we enable the backlight right away following a panel power
1918 * on, we may see slight flicker as the panel syncs with the eDP
1919 * link. So delay a bit to make sure the image is solid before
1920 * allowing it to appear.
1922 wait_backlight_on(intel_dp);
1926 pp = ironlake_get_pp_control(intel_dp);
1927 pp |= EDP_BLC_ENABLE;
1929 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1931 I915_WRITE(pp_ctrl_reg, pp);
1932 POSTING_READ(pp_ctrl_reg);
1934 pps_unlock(intel_dp);
1937 /* Enable backlight PWM and backlight PP control. */
1938 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1940 if (!is_edp(intel_dp))
1943 DRM_DEBUG_KMS("\n");
1945 intel_panel_enable_backlight(intel_dp->attached_connector);
1946 _intel_edp_backlight_on(intel_dp);
1949 /* Disable backlight in the panel power control. */
1950 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1952 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1957 if (!is_edp(intel_dp))
1962 pp = ironlake_get_pp_control(intel_dp);
1963 pp &= ~EDP_BLC_ENABLE;
1965 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1967 I915_WRITE(pp_ctrl_reg, pp);
1968 POSTING_READ(pp_ctrl_reg);
1970 pps_unlock(intel_dp);
1972 intel_dp->last_backlight_off = jiffies;
1973 edp_wait_backlight_off(intel_dp);
1976 /* Disable backlight PP control and backlight PWM. */
1977 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1979 if (!is_edp(intel_dp))
1982 DRM_DEBUG_KMS("\n");
1984 _intel_edp_backlight_off(intel_dp);
1985 intel_panel_disable_backlight(intel_dp->attached_connector);
1989 * Hook for controlling the panel power control backlight through the bl_power
1990 * sysfs attribute. Take care to handle multiple calls.
1992 static void intel_edp_backlight_power(struct intel_connector *connector,
1995 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1999 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2000 pps_unlock(intel_dp);
2002 if (is_enabled == enable)
2005 DRM_DEBUG_KMS("panel power control backlight %s\n",
2006 enable ? "enable" : "disable");
2009 _intel_edp_backlight_on(intel_dp);
2011 _intel_edp_backlight_off(intel_dp);
2014 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2016 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2017 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2018 struct drm_device *dev = crtc->dev;
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2022 assert_pipe_disabled(dev_priv,
2023 to_intel_crtc(crtc)->pipe);
2025 DRM_DEBUG_KMS("\n");
2026 dpa_ctl = I915_READ(DP_A);
2027 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2028 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2030 /* We don't adjust intel_dp->DP while tearing down the link, to
2031 * facilitate link retraining (e.g. after hotplug). Hence clear all
2032 * enable bits here to ensure that we don't enable too much. */
2033 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2034 intel_dp->DP |= DP_PLL_ENABLE;
2035 I915_WRITE(DP_A, intel_dp->DP);
2040 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2042 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2043 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2044 struct drm_device *dev = crtc->dev;
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2048 assert_pipe_disabled(dev_priv,
2049 to_intel_crtc(crtc)->pipe);
2051 dpa_ctl = I915_READ(DP_A);
2052 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2053 "dp pll off, should be on\n");
2054 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2056 /* We can't rely on the value tracked for the DP register in
2057 * intel_dp->DP because link_down must not change that (otherwise link
2058 * re-training will fail. */
2059 dpa_ctl &= ~DP_PLL_ENABLE;
2060 I915_WRITE(DP_A, dpa_ctl);
2065 /* If the sink supports it, try to set the power state appropriately */
2066 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2070 /* Should have a valid DPCD by this point */
2071 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2074 if (mode != DRM_MODE_DPMS_ON) {
2075 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2079 * When turning on, we need to retry for 1ms to give the sink
2082 for (i = 0; i < 3; i++) {
2083 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2092 DRM_DEBUG_KMS("failed to %s sink power state\n",
2093 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2096 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2097 enum i915_pipe *pipe)
2099 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2100 enum port port = dp_to_dig_port(intel_dp)->port;
2101 struct drm_device *dev = encoder->base.dev;
2102 struct drm_i915_private *dev_priv = dev->dev_private;
2103 enum intel_display_power_domain power_domain;
2106 power_domain = intel_display_port_power_domain(encoder);
2107 if (!intel_display_power_is_enabled(dev_priv, power_domain))
2110 tmp = I915_READ(intel_dp->output_reg);
2112 if (!(tmp & DP_PORT_EN))
2115 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
2116 *pipe = PORT_TO_PIPE_CPT(tmp);
2117 } else if (IS_CHERRYVIEW(dev)) {
2118 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2119 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
2120 *pipe = PORT_TO_PIPE(tmp);
2126 switch (intel_dp->output_reg) {
2128 trans_sel = TRANS_DP_PORT_SEL_B;
2131 trans_sel = TRANS_DP_PORT_SEL_C;
2134 trans_sel = TRANS_DP_PORT_SEL_D;
2140 for_each_pipe(dev_priv, i) {
2141 trans_dp = I915_READ(TRANS_DP_CTL(i));
2142 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2148 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2149 intel_dp->output_reg);
2155 static void intel_dp_get_config(struct intel_encoder *encoder,
2156 struct intel_crtc_state *pipe_config)
2158 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2160 struct drm_device *dev = encoder->base.dev;
2161 struct drm_i915_private *dev_priv = dev->dev_private;
2162 enum port port = dp_to_dig_port(intel_dp)->port;
2163 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2166 tmp = I915_READ(intel_dp->output_reg);
2167 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2168 pipe_config->has_audio = true;
2170 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
2171 if (tmp & DP_SYNC_HS_HIGH)
2172 flags |= DRM_MODE_FLAG_PHSYNC;
2174 flags |= DRM_MODE_FLAG_NHSYNC;
2176 if (tmp & DP_SYNC_VS_HIGH)
2177 flags |= DRM_MODE_FLAG_PVSYNC;
2179 flags |= DRM_MODE_FLAG_NVSYNC;
2181 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2182 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2183 flags |= DRM_MODE_FLAG_PHSYNC;
2185 flags |= DRM_MODE_FLAG_NHSYNC;
2187 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2188 flags |= DRM_MODE_FLAG_PVSYNC;
2190 flags |= DRM_MODE_FLAG_NVSYNC;
2193 pipe_config->base.adjusted_mode.flags |= flags;
2195 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2196 tmp & DP_COLOR_RANGE_16_235)
2197 pipe_config->limited_color_range = true;
2199 pipe_config->has_dp_encoder = true;
2201 intel_dp_get_m_n(crtc, pipe_config);
2203 if (port == PORT_A) {
2204 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2205 pipe_config->port_clock = 162000;
2207 pipe_config->port_clock = 270000;
2210 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2211 &pipe_config->dp_m_n);
2213 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2214 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2216 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2218 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2219 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2221 * This is a big fat ugly hack.
2223 * Some machines in UEFI boot mode provide us a VBT that has 18
2224 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2225 * unknown we fail to light up. Yet the same BIOS boots up with
2226 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2227 * max, not what it tells us to use.
2229 * Note: This will still be broken if the eDP panel is not lit
2230 * up by the BIOS, and thus we can't get the mode at module
2233 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2234 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2235 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2239 static void intel_disable_dp(struct intel_encoder *encoder)
2241 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2242 struct drm_device *dev = encoder->base.dev;
2243 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2245 if (crtc->config->has_audio)
2246 intel_audio_codec_disable(encoder);
2248 if (HAS_PSR(dev) && !HAS_DDI(dev))
2249 intel_psr_disable(intel_dp);
2251 /* Make sure the panel is off before trying to change the mode. But also
2252 * ensure that we have vdd while we switch off the panel. */
2253 intel_edp_panel_vdd_on(intel_dp);
2254 intel_edp_backlight_off(intel_dp);
2255 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2256 intel_edp_panel_off(intel_dp);
2258 /* disable the port before the pipe on g4x */
2259 if (INTEL_INFO(dev)->gen < 5)
2260 intel_dp_link_down(intel_dp);
2263 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2265 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2266 enum port port = dp_to_dig_port(intel_dp)->port;
2268 intel_dp_link_down(intel_dp);
2270 ironlake_edp_pll_off(intel_dp);
2273 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2275 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2277 intel_dp_link_down(intel_dp);
2280 static void chv_post_disable_dp(struct intel_encoder *encoder)
2282 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2283 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2284 struct drm_device *dev = encoder->base.dev;
2285 struct drm_i915_private *dev_priv = dev->dev_private;
2286 struct intel_crtc *intel_crtc =
2287 to_intel_crtc(encoder->base.crtc);
2288 enum dpio_channel ch = vlv_dport_to_channel(dport);
2289 enum i915_pipe pipe = intel_crtc->pipe;
2292 intel_dp_link_down(intel_dp);
2294 mutex_lock(&dev_priv->dpio_lock);
2296 /* Propagate soft reset to data lane reset */
2297 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2298 val |= CHV_PCS_REQ_SOFTRESET_EN;
2299 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2301 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2302 val |= CHV_PCS_REQ_SOFTRESET_EN;
2303 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2305 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2306 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2307 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2309 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2310 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2311 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2313 mutex_unlock(&dev_priv->dpio_lock);
2317 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2319 uint8_t dp_train_pat)
2321 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2322 struct drm_device *dev = intel_dig_port->base.base.dev;
2323 struct drm_i915_private *dev_priv = dev->dev_private;
2324 enum port port = intel_dig_port->port;
2327 uint32_t temp = I915_READ(DP_TP_CTL(port));
2329 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2330 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2332 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2334 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2335 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2336 case DP_TRAINING_PATTERN_DISABLE:
2337 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2340 case DP_TRAINING_PATTERN_1:
2341 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2343 case DP_TRAINING_PATTERN_2:
2344 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2346 case DP_TRAINING_PATTERN_3:
2347 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2350 I915_WRITE(DP_TP_CTL(port), temp);
2352 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2353 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2355 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2356 case DP_TRAINING_PATTERN_DISABLE:
2357 *DP |= DP_LINK_TRAIN_OFF_CPT;
2359 case DP_TRAINING_PATTERN_1:
2360 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2362 case DP_TRAINING_PATTERN_2:
2363 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2365 case DP_TRAINING_PATTERN_3:
2366 DRM_ERROR("DP training pattern 3 not supported\n");
2367 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2372 if (IS_CHERRYVIEW(dev))
2373 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2375 *DP &= ~DP_LINK_TRAIN_MASK;
2377 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2378 case DP_TRAINING_PATTERN_DISABLE:
2379 *DP |= DP_LINK_TRAIN_OFF;
2381 case DP_TRAINING_PATTERN_1:
2382 *DP |= DP_LINK_TRAIN_PAT_1;
2384 case DP_TRAINING_PATTERN_2:
2385 *DP |= DP_LINK_TRAIN_PAT_2;
2387 case DP_TRAINING_PATTERN_3:
2388 if (IS_CHERRYVIEW(dev)) {
2389 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2391 DRM_ERROR("DP training pattern 3 not supported\n");
2392 *DP |= DP_LINK_TRAIN_PAT_2;
2399 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2401 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2404 /* enable with pattern 1 (as per spec) */
2405 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2406 DP_TRAINING_PATTERN_1);
2408 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2409 POSTING_READ(intel_dp->output_reg);
2412 * Magic for VLV/CHV. We _must_ first set up the register
2413 * without actually enabling the port, and then do another
2414 * write to enable the port. Otherwise link training will
2415 * fail when the power sequencer is freshly used for this port.
2417 intel_dp->DP |= DP_PORT_EN;
2419 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2420 POSTING_READ(intel_dp->output_reg);
2423 static void intel_enable_dp(struct intel_encoder *encoder)
2425 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2426 struct drm_device *dev = encoder->base.dev;
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2428 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2429 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2431 if (WARN_ON(dp_reg & DP_PORT_EN))
2436 if (IS_VALLEYVIEW(dev))
2437 vlv_init_panel_power_sequencer(intel_dp);
2439 intel_dp_enable_port(intel_dp);
2441 edp_panel_vdd_on(intel_dp);
2442 edp_panel_on(intel_dp);
2443 edp_panel_vdd_off(intel_dp, true);
2445 pps_unlock(intel_dp);
2447 if (IS_VALLEYVIEW(dev))
2448 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2450 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2451 intel_dp_start_link_train(intel_dp);
2452 intel_dp_complete_link_train(intel_dp);
2453 intel_dp_stop_link_train(intel_dp);
2455 if (crtc->config->has_audio) {
2456 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2457 pipe_name(crtc->pipe));
2458 intel_audio_codec_enable(encoder);
2462 static void g4x_enable_dp(struct intel_encoder *encoder)
2464 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2466 intel_enable_dp(encoder);
2467 intel_edp_backlight_on(intel_dp);
2470 static void vlv_enable_dp(struct intel_encoder *encoder)
2472 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2474 intel_edp_backlight_on(intel_dp);
2475 intel_psr_enable(intel_dp);
2478 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2480 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2481 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2483 intel_dp_prepare(encoder);
2485 /* Only ilk+ has port A */
2486 if (dport->port == PORT_A) {
2487 ironlake_set_pll_cpu_edp(intel_dp);
2488 ironlake_edp_pll_on(intel_dp);
2492 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2495 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2496 enum i915_pipe pipe = intel_dp->pps_pipe;
2497 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2499 edp_panel_vdd_off_sync(intel_dp);
2502 * VLV seems to get confused when multiple power seqeuencers
2503 * have the same port selected (even if only one has power/vdd
2504 * enabled). The failure manifests as vlv_wait_port_ready() failing
2505 * CHV on the other hand doesn't seem to mind having the same port
2506 * selected in multiple power seqeuencers, but let's clear the
2507 * port select always when logically disconnecting a power sequencer
2510 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2511 pipe_name(pipe), port_name(intel_dig_port->port));
2512 I915_WRITE(pp_on_reg, 0);
2513 POSTING_READ(pp_on_reg);
2515 intel_dp->pps_pipe = INVALID_PIPE;
2518 static void vlv_steal_power_sequencer(struct drm_device *dev,
2519 enum i915_pipe pipe)
2521 struct drm_i915_private *dev_priv = dev->dev_private;
2522 struct intel_encoder *encoder;
2524 lockdep_assert_held(&dev_priv->pps_mutex);
2526 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2529 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2531 struct intel_dp *intel_dp;
2534 if (encoder->type != INTEL_OUTPUT_EDP)
2537 intel_dp = enc_to_intel_dp(&encoder->base);
2538 port = dp_to_dig_port(intel_dp)->port;
2540 if (intel_dp->pps_pipe != pipe)
2543 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2544 pipe_name(pipe), port_name(port));
2546 WARN(encoder->connectors_active,
2547 "stealing pipe %c power sequencer from active eDP port %c\n",
2548 pipe_name(pipe), port_name(port));
2550 /* make sure vdd is off before we steal it */
2551 vlv_detach_power_sequencer(intel_dp);
2555 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2558 struct intel_encoder *encoder = &intel_dig_port->base;
2559 struct drm_device *dev = encoder->base.dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2563 lockdep_assert_held(&dev_priv->pps_mutex);
2565 if (!is_edp(intel_dp))
2568 if (intel_dp->pps_pipe == crtc->pipe)
2572 * If another power sequencer was being used on this
2573 * port previously make sure to turn off vdd there while
2574 * we still have control of it.
2576 if (intel_dp->pps_pipe != INVALID_PIPE)
2577 vlv_detach_power_sequencer(intel_dp);
2580 * We may be stealing the power
2581 * sequencer from another port.
2583 vlv_steal_power_sequencer(dev, crtc->pipe);
2585 /* now it's all ours */
2586 intel_dp->pps_pipe = crtc->pipe;
2588 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2589 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2591 /* init power sequencer on this pipe and port */
2592 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2593 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2596 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2598 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2599 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2600 struct drm_device *dev = encoder->base.dev;
2601 struct drm_i915_private *dev_priv = dev->dev_private;
2602 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2603 enum dpio_channel port = vlv_dport_to_channel(dport);
2604 int pipe = intel_crtc->pipe;
2607 mutex_lock(&dev_priv->dpio_lock);
2609 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2616 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2617 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2618 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2620 mutex_unlock(&dev_priv->dpio_lock);
2622 intel_enable_dp(encoder);
2625 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2627 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2628 struct drm_device *dev = encoder->base.dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct intel_crtc *intel_crtc =
2631 to_intel_crtc(encoder->base.crtc);
2632 enum dpio_channel port = vlv_dport_to_channel(dport);
2633 int pipe = intel_crtc->pipe;
2635 intel_dp_prepare(encoder);
2637 /* Program Tx lane resets to default */
2638 mutex_lock(&dev_priv->dpio_lock);
2639 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2640 DPIO_PCS_TX_LANE2_RESET |
2641 DPIO_PCS_TX_LANE1_RESET);
2642 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2643 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2644 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2645 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2646 DPIO_PCS_CLK_SOFT_RESET);
2648 /* Fix up inter-pair skew failure */
2649 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2650 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2651 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2652 mutex_unlock(&dev_priv->dpio_lock);
2655 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2657 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2658 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2659 struct drm_device *dev = encoder->base.dev;
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_crtc *intel_crtc =
2662 to_intel_crtc(encoder->base.crtc);
2663 enum dpio_channel ch = vlv_dport_to_channel(dport);
2664 int pipe = intel_crtc->pipe;
2668 mutex_lock(&dev_priv->dpio_lock);
2670 /* allow hardware to manage TX FIFO reset source */
2671 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2672 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2676 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2677 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2679 /* Deassert soft data lane reset*/
2680 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2681 val |= CHV_PCS_REQ_SOFTRESET_EN;
2682 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2684 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2685 val |= CHV_PCS_REQ_SOFTRESET_EN;
2686 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2688 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2689 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2690 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2692 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2693 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2696 /* Program Tx lane latency optimal setting*/
2697 for (i = 0; i < 4; i++) {
2698 /* Set the latency optimal bit */
2699 data = (i == 1) ? 0x0 : 0x6;
2700 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2701 data << DPIO_FRC_LATENCY_SHFIT);
2703 /* Set the upar bit */
2704 data = (i == 1) ? 0x0 : 0x1;
2705 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2706 data << DPIO_UPAR_SHIFT);
2709 /* Data lane stagger programming */
2710 /* FIXME: Fix up value only after power analysis */
2712 mutex_unlock(&dev_priv->dpio_lock);
2714 intel_enable_dp(encoder);
2717 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2719 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2720 struct drm_device *dev = encoder->base.dev;
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 struct intel_crtc *intel_crtc =
2723 to_intel_crtc(encoder->base.crtc);
2724 enum dpio_channel ch = vlv_dport_to_channel(dport);
2725 enum i915_pipe pipe = intel_crtc->pipe;
2728 mutex_lock(&dev_priv->dpio_lock);
2730 /* program left/right clock distribution */
2731 if (pipe != PIPE_B) {
2732 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2733 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2735 val |= CHV_BUFLEFTENA1_FORCE;
2737 val |= CHV_BUFRIGHTENA1_FORCE;
2738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2743 val |= CHV_BUFLEFTENA2_FORCE;
2745 val |= CHV_BUFRIGHTENA2_FORCE;
2746 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2749 /* program clock channel usage */
2750 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2751 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2753 val &= ~CHV_PCS_USEDCLKCHANNEL;
2755 val |= CHV_PCS_USEDCLKCHANNEL;
2756 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2758 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2759 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2761 val &= ~CHV_PCS_USEDCLKCHANNEL;
2763 val |= CHV_PCS_USEDCLKCHANNEL;
2764 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2767 * This a a bit weird since generally CL
2768 * matches the pipe, but here we need to
2769 * pick the CL based on the port.
2771 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2773 val &= ~CHV_CMN_USEDCLKCHANNEL;
2775 val |= CHV_CMN_USEDCLKCHANNEL;
2776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2778 mutex_unlock(&dev_priv->dpio_lock);
2782 * Native read with retry for link status and receiver capability reads for
2783 * cases where the sink may still be asleep.
2785 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2786 * supposed to retry 3 times per the spec.
2789 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2790 void *buffer, size_t size)
2796 * Sometime we just get the same incorrect byte repeated
2797 * over the entire buffer. Doing just one throw away read
2798 * initially seems to "solve" it.
2800 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2802 for (i = 0; i < 3; i++) {
2803 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2813 * Fetch AUX CH registers 0x202 - 0x207 which contain
2814 * link status information
2817 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2819 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2822 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2825 /* These are source-specific values. */
2827 intel_dp_voltage_max(struct intel_dp *intel_dp)
2829 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2830 enum port port = dp_to_dig_port(intel_dp)->port;
2832 if (INTEL_INFO(dev)->gen >= 9)
2833 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2834 else if (IS_VALLEYVIEW(dev))
2835 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2836 else if (IS_GEN7(dev) && port == PORT_A)
2837 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2838 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2839 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2841 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2845 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2847 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2848 enum port port = dp_to_dig_port(intel_dp)->port;
2850 if (INTEL_INFO(dev)->gen >= 9) {
2851 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2853 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2854 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2855 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2856 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2857 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2859 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2861 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2862 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2864 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2866 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2868 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2869 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2871 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2873 } else if (IS_VALLEYVIEW(dev)) {
2874 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2875 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2876 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2878 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2880 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2881 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2883 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2885 } else if (IS_GEN7(dev) && port == PORT_A) {
2886 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2888 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2889 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2891 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2893 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2896 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2898 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2900 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2902 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2903 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2905 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2910 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2912 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2915 struct intel_crtc *intel_crtc =
2916 to_intel_crtc(dport->base.base.crtc);
2917 unsigned long demph_reg_value, preemph_reg_value,
2918 uniqtranscale_reg_value;
2919 uint8_t train_set = intel_dp->train_set[0];
2920 enum dpio_channel port = vlv_dport_to_channel(dport);
2921 int pipe = intel_crtc->pipe;
2923 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2924 case DP_TRAIN_PRE_EMPH_LEVEL_0:
2925 preemph_reg_value = 0x0004000;
2926 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2928 demph_reg_value = 0x2B405555;
2929 uniqtranscale_reg_value = 0x552AB83A;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2932 demph_reg_value = 0x2B404040;
2933 uniqtranscale_reg_value = 0x5548B83A;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2936 demph_reg_value = 0x2B245555;
2937 uniqtranscale_reg_value = 0x5560B83A;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2940 demph_reg_value = 0x2B405555;
2941 uniqtranscale_reg_value = 0x5598DA3A;
2947 case DP_TRAIN_PRE_EMPH_LEVEL_1:
2948 preemph_reg_value = 0x0002000;
2949 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2951 demph_reg_value = 0x2B404040;
2952 uniqtranscale_reg_value = 0x5552B83A;
2954 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2955 demph_reg_value = 0x2B404848;
2956 uniqtranscale_reg_value = 0x5580B83A;
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2959 demph_reg_value = 0x2B404040;
2960 uniqtranscale_reg_value = 0x55ADDA3A;
2966 case DP_TRAIN_PRE_EMPH_LEVEL_2:
2967 preemph_reg_value = 0x0000000;
2968 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2970 demph_reg_value = 0x2B305555;
2971 uniqtranscale_reg_value = 0x5570B83A;
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2974 demph_reg_value = 0x2B2B4040;
2975 uniqtranscale_reg_value = 0x55ADDA3A;
2981 case DP_TRAIN_PRE_EMPH_LEVEL_3:
2982 preemph_reg_value = 0x0006000;
2983 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2985 demph_reg_value = 0x1B405555;
2986 uniqtranscale_reg_value = 0x55ADDA3A;
2996 mutex_lock(&dev_priv->dpio_lock);
2997 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3000 uniqtranscale_reg_value);
3001 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3002 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3003 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3004 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3005 mutex_unlock(&dev_priv->dpio_lock);
3010 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3012 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3015 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3016 u32 deemph_reg_value, margin_reg_value, val;
3017 uint8_t train_set = intel_dp->train_set[0];
3018 enum dpio_channel ch = vlv_dport_to_channel(dport);
3019 enum i915_pipe pipe = intel_crtc->pipe;
3022 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3023 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3024 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3026 deemph_reg_value = 128;
3027 margin_reg_value = 52;
3029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3030 deemph_reg_value = 128;
3031 margin_reg_value = 77;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3034 deemph_reg_value = 128;
3035 margin_reg_value = 102;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3038 deemph_reg_value = 128;
3039 margin_reg_value = 154;
3040 /* FIXME extra to set for 1200 */
3046 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3047 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3049 deemph_reg_value = 85;
3050 margin_reg_value = 78;
3052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3053 deemph_reg_value = 85;
3054 margin_reg_value = 116;
3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3057 deemph_reg_value = 85;
3058 margin_reg_value = 154;
3064 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3065 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3067 deemph_reg_value = 64;
3068 margin_reg_value = 104;
3070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3071 deemph_reg_value = 64;
3072 margin_reg_value = 154;
3078 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3079 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3081 deemph_reg_value = 43;
3082 margin_reg_value = 154;
3092 mutex_lock(&dev_priv->dpio_lock);
3094 /* Clear calc init */
3095 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3096 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3097 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3098 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3099 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3101 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3102 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3103 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3104 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3105 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3107 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3108 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3109 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3110 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3112 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3113 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3114 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3115 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3117 /* Program swing deemph */
3118 for (i = 0; i < 4; i++) {
3119 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3120 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3121 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3122 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3125 /* Program swing margin */
3126 for (i = 0; i < 4; i++) {
3127 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3128 val &= ~DPIO_SWING_MARGIN000_MASK;
3129 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3130 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3133 /* Disable unique transition scale */
3134 for (i = 0; i < 4; i++) {
3135 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3136 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3137 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3140 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3141 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3142 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3143 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3146 * The document said it needs to set bit 27 for ch0 and bit 26
3147 * for ch1. Might be a typo in the doc.
3148 * For now, for this unique transition scale selection, set bit
3149 * 27 for ch0 and ch1.
3151 for (i = 0; i < 4; i++) {
3152 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3153 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3154 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3157 for (i = 0; i < 4; i++) {
3158 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3159 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3160 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3161 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3165 /* Start swing calculation */
3166 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3167 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3168 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3170 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3171 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3172 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3175 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3176 val |= DPIO_LRC_BYPASS;
3177 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3179 mutex_unlock(&dev_priv->dpio_lock);
3185 intel_get_adjust_train(struct intel_dp *intel_dp,
3186 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3191 uint8_t voltage_max;
3192 uint8_t preemph_max;
3194 for (lane = 0; lane < intel_dp->lane_count; lane++) {
3195 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3196 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3204 voltage_max = intel_dp_voltage_max(intel_dp);
3205 if (v >= voltage_max)
3206 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3208 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3209 if (p >= preemph_max)
3210 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3212 for (lane = 0; lane < 4; lane++)
3213 intel_dp->train_set[lane] = v | p;
3217 intel_gen4_signal_levels(uint8_t train_set)
3219 uint32_t signal_levels = 0;
3221 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3224 signal_levels |= DP_VOLTAGE_0_4;
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3227 signal_levels |= DP_VOLTAGE_0_6;
3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3230 signal_levels |= DP_VOLTAGE_0_8;
3232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3233 signal_levels |= DP_VOLTAGE_1_2;
3236 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3237 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3239 signal_levels |= DP_PRE_EMPHASIS_0;
3241 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3242 signal_levels |= DP_PRE_EMPHASIS_3_5;
3244 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3245 signal_levels |= DP_PRE_EMPHASIS_6;
3247 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3248 signal_levels |= DP_PRE_EMPHASIS_9_5;
3251 return signal_levels;
3254 /* Gen6's DP voltage swing and pre-emphasis control */
3256 intel_gen6_edp_signal_levels(uint8_t train_set)
3258 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3259 DP_TRAIN_PRE_EMPHASIS_MASK);
3260 switch (signal_levels) {
3261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3263 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3265 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3267 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3268 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3271 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3274 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3276 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3277 "0x%x\n", signal_levels);
3278 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3282 /* Gen7's DP voltage swing and pre-emphasis control */
3284 intel_gen7_edp_signal_levels(uint8_t train_set)
3286 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3287 DP_TRAIN_PRE_EMPHASIS_MASK);
3288 switch (signal_levels) {
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3290 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3292 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3294 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3297 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3298 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3299 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3302 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3304 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3307 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3308 "0x%x\n", signal_levels);
3309 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3313 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3315 intel_hsw_signal_levels(uint8_t train_set)
3317 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3318 DP_TRAIN_PRE_EMPHASIS_MASK);
3319 switch (signal_levels) {
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3321 return DDI_BUF_TRANS_SELECT(0);
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3323 return DDI_BUF_TRANS_SELECT(1);
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3325 return DDI_BUF_TRANS_SELECT(2);
3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3327 return DDI_BUF_TRANS_SELECT(3);
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3330 return DDI_BUF_TRANS_SELECT(4);
3331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3332 return DDI_BUF_TRANS_SELECT(5);
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3334 return DDI_BUF_TRANS_SELECT(6);
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3337 return DDI_BUF_TRANS_SELECT(7);
3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3339 return DDI_BUF_TRANS_SELECT(8);
3341 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3342 "0x%x\n", signal_levels);
3343 return DDI_BUF_TRANS_SELECT(0);
3347 /* Properly updates "DP" with the correct signal levels. */
3349 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3352 enum port port = intel_dig_port->port;
3353 struct drm_device *dev = intel_dig_port->base.base.dev;
3354 uint32_t signal_levels, mask;
3355 uint8_t train_set = intel_dp->train_set[0];
3357 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3358 signal_levels = intel_hsw_signal_levels(train_set);
3359 mask = DDI_BUF_EMP_MASK;
3360 } else if (IS_CHERRYVIEW(dev)) {
3361 signal_levels = intel_chv_signal_levels(intel_dp);
3363 } else if (IS_VALLEYVIEW(dev)) {
3364 signal_levels = intel_vlv_signal_levels(intel_dp);
3366 } else if (IS_GEN7(dev) && port == PORT_A) {
3367 signal_levels = intel_gen7_edp_signal_levels(train_set);
3368 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3369 } else if (IS_GEN6(dev) && port == PORT_A) {
3370 signal_levels = intel_gen6_edp_signal_levels(train_set);
3371 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3373 signal_levels = intel_gen4_signal_levels(train_set);
3374 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3377 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3379 *DP = (*DP & ~mask) | signal_levels;
3383 intel_dp_set_link_train(struct intel_dp *intel_dp,
3385 uint8_t dp_train_pat)
3387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3388 struct drm_device *dev = intel_dig_port->base.base.dev;
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3393 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3395 I915_WRITE(intel_dp->output_reg, *DP);
3396 POSTING_READ(intel_dp->output_reg);
3398 buf[0] = dp_train_pat;
3399 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3400 DP_TRAINING_PATTERN_DISABLE) {
3401 /* don't write DP_TRAINING_LANEx_SET on disable */
3404 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3405 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3406 len = intel_dp->lane_count + 1;
3409 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3416 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3417 uint8_t dp_train_pat)
3419 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3420 intel_dp_set_signal_levels(intel_dp, DP);
3421 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3425 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3426 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3428 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3429 struct drm_device *dev = intel_dig_port->base.base.dev;
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3433 intel_get_adjust_train(intel_dp, link_status);
3434 intel_dp_set_signal_levels(intel_dp, DP);
3436 I915_WRITE(intel_dp->output_reg, *DP);
3437 POSTING_READ(intel_dp->output_reg);
3439 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3440 intel_dp->train_set, intel_dp->lane_count);
3442 return ret == intel_dp->lane_count;
3445 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3447 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3448 struct drm_device *dev = intel_dig_port->base.base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 enum port port = intel_dig_port->port;
3456 val = I915_READ(DP_TP_CTL(port));
3457 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3458 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3459 I915_WRITE(DP_TP_CTL(port), val);
3462 * On PORT_A we can have only eDP in SST mode. There the only reason
3463 * we need to set idle transmission mode is to work around a HW issue
3464 * where we enable the pipe while not in idle link-training mode.
3465 * In this case there is requirement to wait for a minimum number of
3466 * idle patterns to be sent.
3471 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3473 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3476 /* Enable corresponding port and start training pattern 1 */
3478 intel_dp_start_link_train(struct intel_dp *intel_dp)
3480 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3481 struct drm_device *dev = encoder->dev;
3484 int voltage_tries, loop_tries;
3485 uint32_t DP = intel_dp->DP;
3486 uint8_t link_config[2];
3489 intel_ddi_prepare_link_retrain(encoder);
3491 /* Write the link configuration data */
3492 link_config[0] = intel_dp->link_bw;
3493 link_config[1] = intel_dp->lane_count;
3494 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3495 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3496 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3499 link_config[1] = DP_SET_ANSI_8B10B;
3500 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3504 /* clock recovery */
3505 if (!intel_dp_reset_link_train(intel_dp, &DP,
3506 DP_TRAINING_PATTERN_1 |
3507 DP_LINK_SCRAMBLING_DISABLE)) {
3508 DRM_ERROR("failed to enable link training\n");
3516 uint8_t link_status[DP_LINK_STATUS_SIZE];
3518 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3519 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3520 DRM_ERROR("failed to get link status\n");
3524 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3525 DRM_DEBUG_KMS("clock recovery OK\n");
3529 /* Check to see if we've tried the max voltage */
3530 for (i = 0; i < intel_dp->lane_count; i++)
3531 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3533 if (i == intel_dp->lane_count) {
3535 if (loop_tries == 5) {
3536 DRM_ERROR("too many full retries, give up\n");
3539 intel_dp_reset_link_train(intel_dp, &DP,
3540 DP_TRAINING_PATTERN_1 |
3541 DP_LINK_SCRAMBLING_DISABLE);
3546 /* Check to see if we've tried the same voltage 5 times */
3547 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3549 if (voltage_tries == 5) {
3550 DRM_ERROR("too many voltage retries, give up\n");
3555 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3557 /* Update training set as requested by target */
3558 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3559 DRM_ERROR("failed to update link training\n");
3568 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3570 bool channel_eq = false;
3571 int tries, cr_tries;
3572 uint32_t DP = intel_dp->DP;
3573 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3575 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3576 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3577 training_pattern = DP_TRAINING_PATTERN_3;
3579 /* channel equalization */
3580 if (!intel_dp_set_link_train(intel_dp, &DP,
3582 DP_LINK_SCRAMBLING_DISABLE)) {
3583 DRM_ERROR("failed to start channel equalization\n");
3591 uint8_t link_status[DP_LINK_STATUS_SIZE];
3594 DRM_ERROR("failed to train DP, aborting\n");
3598 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3599 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3600 DRM_ERROR("failed to get link status\n");
3604 /* Make sure clock is still ok */
3605 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3606 intel_dp_start_link_train(intel_dp);
3607 intel_dp_set_link_train(intel_dp, &DP,
3609 DP_LINK_SCRAMBLING_DISABLE);
3614 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3619 /* Try 5 times, then try clock recovery if that fails */
3621 intel_dp_start_link_train(intel_dp);
3622 intel_dp_set_link_train(intel_dp, &DP,
3624 DP_LINK_SCRAMBLING_DISABLE);
3630 /* Update training set as requested by target */
3631 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3632 DRM_ERROR("failed to update link training\n");
3638 intel_dp_set_idle_link_train(intel_dp);
3643 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3647 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3649 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3650 DP_TRAINING_PATTERN_DISABLE);
3654 intel_dp_link_down(struct intel_dp *intel_dp)
3656 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3657 enum port port = intel_dig_port->port;
3658 struct drm_device *dev = intel_dig_port->base.base.dev;
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660 uint32_t DP = intel_dp->DP;
3662 if (WARN_ON(HAS_DDI(dev)))
3665 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3668 DRM_DEBUG_KMS("\n");
3670 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3671 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3672 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3674 if (IS_CHERRYVIEW(dev))
3675 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3677 DP &= ~DP_LINK_TRAIN_MASK;
3678 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3680 POSTING_READ(intel_dp->output_reg);
3682 if (HAS_PCH_IBX(dev) &&
3683 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3684 /* Hardware workaround: leaving our transcoder select
3685 * set to transcoder B while it's off will prevent the
3686 * corresponding HDMI output on transcoder A.
3688 * Combine this with another hardware workaround:
3689 * transcoder select bit can only be cleared while the
3692 DP &= ~DP_PIPEB_SELECT;
3693 I915_WRITE(intel_dp->output_reg, DP);
3694 POSTING_READ(intel_dp->output_reg);
3697 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3698 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3699 POSTING_READ(intel_dp->output_reg);
3700 msleep(intel_dp->panel_power_down_delay);
3704 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3706 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3707 struct drm_device *dev = dig_port->base.base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3710 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3711 sizeof(intel_dp->dpcd)) < 0)
3712 return false; /* aux transfer failed */
3714 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3716 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3717 return false; /* DPCD not present */
3719 /* Check if the panel supports PSR */
3720 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3721 if (is_edp(intel_dp)) {
3722 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3724 sizeof(intel_dp->psr_dpcd));
3725 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3726 dev_priv->psr.sink_support = true;
3727 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3731 /* Training Pattern 3 support, both source and sink */
3732 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3733 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3734 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3735 intel_dp->use_tps3 = true;
3736 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3738 intel_dp->use_tps3 = false;
3740 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3741 DP_DWN_STRM_PORT_PRESENT))
3742 return true; /* native DP sink */
3744 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3745 return true; /* no per-port downstream info */
3747 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3748 intel_dp->downstream_ports,
3749 DP_MAX_DOWNSTREAM_PORTS) < 0)
3750 return false; /* downstream port status fetch failed */
3756 intel_dp_probe_oui(struct intel_dp *intel_dp)
3760 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3763 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3764 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3765 buf[0], buf[1], buf[2]);
3767 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3768 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3769 buf[0], buf[1], buf[2]);
3774 intel_dp_probe_mst(struct intel_dp *intel_dp)
3778 if (!intel_dp->can_mst)
3781 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3784 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3785 if (buf[0] & DP_MST_CAP) {
3786 DRM_DEBUG_KMS("Sink is MST capable\n");
3787 intel_dp->is_mst = true;
3789 DRM_DEBUG_KMS("Sink is not MST capable\n");
3790 intel_dp->is_mst = false;
3794 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3795 return intel_dp->is_mst;
3799 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3802 struct drm_device *dev = intel_dig_port->base.base.dev;
3803 struct intel_crtc *intel_crtc =
3804 to_intel_crtc(intel_dig_port->base.base.crtc);
3809 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3812 if (!(buf & DP_TEST_CRC_SUPPORTED))
3815 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3818 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3819 buf | DP_TEST_SINK_START) < 0)
3822 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3824 test_crc_count = buf & DP_TEST_COUNT_MASK;
3827 if (drm_dp_dpcd_readb(&intel_dp->aux,
3828 DP_TEST_SINK_MISC, &buf) < 0)
3830 intel_wait_for_vblank(dev, intel_crtc->pipe);
3831 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3833 if (attempts == 0) {
3834 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3838 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3841 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3843 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3844 buf & ~DP_TEST_SINK_START) < 0)
3851 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3853 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3854 DP_DEVICE_SERVICE_IRQ_VECTOR,
3855 sink_irq_vector, 1) == 1;
3859 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3861 /* NAK by default */
3862 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3867 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3871 if (intel_dp->is_mst) {
3876 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3880 /* check link status - esi[10] = 0x200c */
3881 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3882 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3883 intel_dp_start_link_train(intel_dp);
3884 intel_dp_complete_link_train(intel_dp);
3885 intel_dp_stop_link_train(intel_dp);
3888 DRM_DEBUG_KMS("got esi %3ph\n", esi);
3889 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3892 for (retry = 0; retry < 3; retry++) {
3894 wret = drm_dp_dpcd_write(&intel_dp->aux,
3895 DP_SINK_COUNT_ESI+1,
3902 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3904 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3912 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3913 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3914 intel_dp->is_mst = false;
3915 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3916 /* send a hotplug event */
3917 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3925 * According to DP spec
3928 * 2. Configure link according to Receiver Capabilities
3929 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3930 * 4. Check link status on receipt of hot-plug interrupt
3933 intel_dp_check_link_status(struct intel_dp *intel_dp)
3935 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3936 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3938 u8 link_status[DP_LINK_STATUS_SIZE];
3940 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3942 if (!intel_encoder->connectors_active)
3945 if (WARN_ON(!intel_encoder->base.crtc))
3948 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3951 /* Try to read receiver status if the link appears to be up */
3952 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3956 /* Now read the DPCD to see if it's actually running */
3957 if (!intel_dp_get_dpcd(intel_dp)) {
3961 /* Try to read the source of the interrupt */
3962 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3963 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3964 /* Clear interrupt source */
3965 drm_dp_dpcd_writeb(&intel_dp->aux,
3966 DP_DEVICE_SERVICE_IRQ_VECTOR,
3969 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3970 intel_dp_handle_test_request(intel_dp);
3971 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3972 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3975 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3976 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3977 intel_encoder->base.name);
3978 intel_dp_start_link_train(intel_dp);
3979 intel_dp_complete_link_train(intel_dp);
3980 intel_dp_stop_link_train(intel_dp);
3984 /* XXX this is probably wrong for multiple downstream ports */
3985 static enum drm_connector_status
3986 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3988 uint8_t *dpcd = intel_dp->dpcd;
3991 if (!intel_dp_get_dpcd(intel_dp))
3992 return connector_status_disconnected;
3994 /* if there's no downstream port, we're done */
3995 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3996 return connector_status_connected;
3998 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3999 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4000 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4003 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4005 return connector_status_unknown;
4007 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4008 : connector_status_disconnected;
4011 /* If no HPD, poke DDC gently */
4012 if (drm_probe_ddc(intel_dp->aux.ddc))
4013 return connector_status_connected;
4015 /* Well we tried, say unknown for unreliable port types */
4016 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4017 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4018 if (type == DP_DS_PORT_TYPE_VGA ||
4019 type == DP_DS_PORT_TYPE_NON_EDID)
4020 return connector_status_unknown;
4022 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4023 DP_DWN_STRM_PORT_TYPE_MASK;
4024 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4025 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4026 return connector_status_unknown;
4029 /* Anything else is out of spec, warn and ignore */
4030 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4031 return connector_status_disconnected;
4034 static enum drm_connector_status
4035 edp_detect(struct intel_dp *intel_dp)
4037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4038 enum drm_connector_status status;
4040 status = intel_panel_detect(dev);
4041 if (status == connector_status_unknown)
4042 status = connector_status_connected;
4047 static enum drm_connector_status
4048 ironlake_dp_detect(struct intel_dp *intel_dp)
4050 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4051 struct drm_i915_private *dev_priv = dev->dev_private;
4052 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4054 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4055 return connector_status_disconnected;
4057 return intel_dp_detect_dpcd(intel_dp);
4060 static int g4x_digital_port_connected(struct drm_device *dev,
4061 struct intel_digital_port *intel_dig_port)
4063 struct drm_i915_private *dev_priv = dev->dev_private;
4066 if (IS_VALLEYVIEW(dev)) {
4067 switch (intel_dig_port->port) {
4069 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4072 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4075 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4081 switch (intel_dig_port->port) {
4083 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4086 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4089 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4096 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4101 static enum drm_connector_status
4102 g4x_dp_detect(struct intel_dp *intel_dp)
4104 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4109 if (IS_VALLEYVIEW(dev)) {
4110 switch (intel_dig_port->port) {
4112 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4115 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4118 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4121 return connector_status_unknown;
4124 switch (intel_dig_port->port) {
4126 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4129 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4132 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4135 return connector_status_unknown;
4139 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4140 return connector_status_disconnected;
4142 return intel_dp_detect_dpcd(intel_dp);
4145 static struct edid *
4146 intel_dp_get_edid(struct intel_dp *intel_dp)
4148 struct intel_connector *intel_connector = intel_dp->attached_connector;
4150 /* use cached edid if we have one */
4151 if (intel_connector->edid) {
4153 if (IS_ERR(intel_connector->edid))
4156 return drm_edid_duplicate(intel_connector->edid);
4158 return drm_get_edid(&intel_connector->base,
4163 intel_dp_set_edid(struct intel_dp *intel_dp)
4165 struct intel_connector *intel_connector = intel_dp->attached_connector;
4168 edid = intel_dp_get_edid(intel_dp);
4169 intel_connector->detect_edid = edid;
4171 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4172 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4174 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4178 intel_dp_unset_edid(struct intel_dp *intel_dp)
4180 struct intel_connector *intel_connector = intel_dp->attached_connector;
4182 kfree(intel_connector->detect_edid);
4183 intel_connector->detect_edid = NULL;
4185 intel_dp->has_audio = false;
4188 static enum intel_display_power_domain
4189 intel_dp_power_get(struct intel_dp *dp)
4191 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4192 enum intel_display_power_domain power_domain;
4194 power_domain = intel_display_port_power_domain(encoder);
4195 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4197 return power_domain;
4201 intel_dp_power_put(struct intel_dp *dp,
4202 enum intel_display_power_domain power_domain)
4204 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4205 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4208 static enum drm_connector_status
4209 intel_dp_detect(struct drm_connector *connector, bool force)
4211 struct intel_dp *intel_dp = intel_attached_dp(connector);
4212 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4213 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4214 struct drm_device *dev = connector->dev;
4215 enum drm_connector_status status;
4216 enum intel_display_power_domain power_domain;
4218 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4219 connector->base.id, connector->name);
4220 intel_dp_unset_edid(intel_dp);
4222 if (intel_dp->is_mst) {
4223 /* MST devices are disconnected from a monitor POV */
4224 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4225 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4226 return connector_status_disconnected;
4229 power_domain = intel_dp_power_get(intel_dp);
4231 /* Can't disconnect eDP, but you can close the lid... */
4232 if (is_edp(intel_dp))
4233 status = edp_detect(intel_dp);
4234 else if (HAS_PCH_SPLIT(dev))
4235 status = ironlake_dp_detect(intel_dp);
4237 status = g4x_dp_detect(intel_dp);
4238 if (status != connector_status_connected)
4241 intel_dp_probe_oui(intel_dp);
4244 ret = intel_dp_probe_mst(intel_dp);
4246 /* if we are in MST mode then this connector
4247 won't appear connected or have anything with EDID on it */
4248 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4249 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4250 status = connector_status_disconnected;
4255 intel_dp_set_edid(intel_dp);
4257 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4258 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4259 status = connector_status_connected;
4262 intel_dp_power_put(intel_dp, power_domain);
4267 intel_dp_force(struct drm_connector *connector)
4269 struct intel_dp *intel_dp = intel_attached_dp(connector);
4270 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4271 enum intel_display_power_domain power_domain;
4273 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4274 connector->base.id, connector->name);
4275 intel_dp_unset_edid(intel_dp);
4277 if (connector->status != connector_status_connected)
4280 power_domain = intel_dp_power_get(intel_dp);
4282 intel_dp_set_edid(intel_dp);
4284 intel_dp_power_put(intel_dp, power_domain);
4286 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4287 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4290 static int intel_dp_get_modes(struct drm_connector *connector)
4292 struct intel_connector *intel_connector = to_intel_connector(connector);
4295 edid = intel_connector->detect_edid;
4297 int ret = intel_connector_update_modes(connector, edid);
4302 /* if eDP has no EDID, fall back to fixed mode */
4303 if (is_edp(intel_attached_dp(connector)) &&
4304 intel_connector->panel.fixed_mode) {
4305 struct drm_display_mode *mode;
4307 mode = drm_mode_duplicate(connector->dev,
4308 intel_connector->panel.fixed_mode);
4310 drm_mode_probed_add(connector, mode);
4319 intel_dp_detect_audio(struct drm_connector *connector)
4321 bool has_audio = false;
4324 edid = to_intel_connector(connector)->detect_edid;
4326 has_audio = drm_detect_monitor_audio(edid);
4332 intel_dp_set_property(struct drm_connector *connector,
4333 struct drm_property *property,
4336 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4337 struct intel_connector *intel_connector = to_intel_connector(connector);
4338 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4339 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4342 ret = drm_object_property_set_value(&connector->base, property, val);
4346 if (property == dev_priv->force_audio_property) {
4350 if (i == intel_dp->force_audio)
4353 intel_dp->force_audio = i;
4355 if (i == HDMI_AUDIO_AUTO)
4356 has_audio = intel_dp_detect_audio(connector);
4358 has_audio = (i == HDMI_AUDIO_ON);
4360 if (has_audio == intel_dp->has_audio)
4363 intel_dp->has_audio = has_audio;
4367 if (property == dev_priv->broadcast_rgb_property) {
4368 bool old_auto = intel_dp->color_range_auto;
4369 uint32_t old_range = intel_dp->color_range;
4372 case INTEL_BROADCAST_RGB_AUTO:
4373 intel_dp->color_range_auto = true;
4375 case INTEL_BROADCAST_RGB_FULL:
4376 intel_dp->color_range_auto = false;
4377 intel_dp->color_range = 0;
4379 case INTEL_BROADCAST_RGB_LIMITED:
4380 intel_dp->color_range_auto = false;
4381 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4387 if (old_auto == intel_dp->color_range_auto &&
4388 old_range == intel_dp->color_range)
4394 if (is_edp(intel_dp) &&
4395 property == connector->dev->mode_config.scaling_mode_property) {
4396 if (val == DRM_MODE_SCALE_NONE) {
4397 DRM_DEBUG_KMS("no scaling not supported\n");
4401 if (intel_connector->panel.fitting_mode == val) {
4402 /* the eDP scaling property is not changed */
4405 intel_connector->panel.fitting_mode = val;
4413 if (intel_encoder->base.crtc)
4414 intel_crtc_restore_mode(intel_encoder->base.crtc);
4420 intel_dp_connector_destroy(struct drm_connector *connector)
4422 struct intel_connector *intel_connector = to_intel_connector(connector);
4424 kfree(intel_connector->detect_edid);
4426 if (!IS_ERR_OR_NULL(intel_connector->edid))
4427 kfree(intel_connector->edid);
4429 /* Can't call is_edp() since the encoder may have been destroyed
4431 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4432 intel_panel_fini(&intel_connector->panel);
4434 drm_connector_cleanup(connector);
4438 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4440 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4441 struct intel_dp *intel_dp = &intel_dig_port->dp;
4443 drm_dp_aux_unregister(&intel_dp->aux);
4444 intel_dp_mst_encoder_cleanup(intel_dig_port);
4445 if (is_edp(intel_dp)) {
4446 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4448 * vdd might still be enabled do to the delayed vdd off.
4449 * Make sure vdd is actually turned off here.
4452 edp_panel_vdd_off_sync(intel_dp);
4453 pps_unlock(intel_dp);
4456 if (intel_dp->edp_notifier.notifier_call) {
4457 unregister_reboot_notifier(&intel_dp->edp_notifier);
4458 intel_dp->edp_notifier.notifier_call = NULL;
4462 drm_encoder_cleanup(encoder);
4463 kfree(intel_dig_port);
4466 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4468 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4470 if (!is_edp(intel_dp))
4474 * vdd might still be enabled do to the delayed vdd off.
4475 * Make sure vdd is actually turned off here.
4477 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4479 edp_panel_vdd_off_sync(intel_dp);
4480 pps_unlock(intel_dp);
4483 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4485 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4486 struct drm_device *dev = intel_dig_port->base.base.dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488 enum intel_display_power_domain power_domain;
4490 lockdep_assert_held(&dev_priv->pps_mutex);
4492 if (!edp_have_panel_vdd(intel_dp))
4496 * The VDD bit needs a power domain reference, so if the bit is
4497 * already enabled when we boot or resume, grab this reference and
4498 * schedule a vdd off, so we don't hold on to the reference
4501 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4502 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4503 intel_display_power_get(dev_priv, power_domain);
4505 edp_panel_vdd_schedule_off(intel_dp);
4508 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4510 struct intel_dp *intel_dp;
4512 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4515 intel_dp = enc_to_intel_dp(encoder);
4520 * Read out the current power sequencer assignment,
4521 * in case the BIOS did something with it.
4523 if (IS_VALLEYVIEW(encoder->dev))
4524 vlv_initial_power_sequencer_setup(intel_dp);
4526 intel_edp_panel_vdd_sanitize(intel_dp);
4528 pps_unlock(intel_dp);
4531 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4532 .dpms = intel_connector_dpms,
4533 .detect = intel_dp_detect,
4534 .force = intel_dp_force,
4535 .fill_modes = drm_helper_probe_single_connector_modes,
4536 .set_property = intel_dp_set_property,
4537 .atomic_get_property = intel_connector_atomic_get_property,
4538 .destroy = intel_dp_connector_destroy,
4539 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4542 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4543 .get_modes = intel_dp_get_modes,
4544 .mode_valid = intel_dp_mode_valid,
4545 .best_encoder = intel_best_encoder,
4548 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4549 .reset = intel_dp_encoder_reset,
4550 .destroy = intel_dp_encoder_destroy,
4554 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4556 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4558 intel_dp_check_link_status(intel_dp);
4562 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4564 struct intel_dp *intel_dp = &intel_dig_port->dp;
4565 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4566 struct drm_device *dev = intel_dig_port->base.base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 enum intel_display_power_domain power_domain;
4571 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4572 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4574 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4576 * vdd off can generate a long pulse on eDP which
4577 * would require vdd on to handle it, and thus we
4578 * would end up in an endless cycle of
4579 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4581 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4582 port_name(intel_dig_port->port));
4586 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4587 port_name(intel_dig_port->port),
4588 long_hpd ? "long" : "short");
4590 power_domain = intel_display_port_power_domain(intel_encoder);
4591 intel_display_power_get(dev_priv, power_domain);
4597 if (HAS_PCH_SPLIT(dev)) {
4598 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4601 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4605 if (!intel_dp_get_dpcd(intel_dp)) {
4611 * we'll check the link status via the normal hot plug path later -
4612 * but for short hpds we should check it now
4614 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4615 intel_dp_check_link_status(intel_dp);
4616 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4621 /* if we were in MST mode, and device is not there get out of MST mode */
4622 if (intel_dp->is_mst) {
4623 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4624 intel_dp->is_mst = false;
4625 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4628 intel_display_power_put(dev_priv, power_domain);
4633 /* Return which DP Port should be selected for Transcoder DP control */
4635 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4637 struct drm_device *dev = crtc->dev;
4638 struct intel_encoder *intel_encoder;
4639 struct intel_dp *intel_dp;
4641 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4642 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4644 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4645 intel_encoder->type == INTEL_OUTPUT_EDP)
4646 return intel_dp->output_reg;
4652 /* check the VBT to see whether the eDP is on DP-D port */
4653 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656 union child_device_config *p_child;
4658 static const short port_mapping[] = {
4659 [PORT_B] = PORT_IDPB,
4660 [PORT_C] = PORT_IDPC,
4661 [PORT_D] = PORT_IDPD,
4667 if (!dev_priv->vbt.child_dev_num)
4670 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4671 p_child = dev_priv->vbt.child_dev + i;
4673 if (p_child->common.dvo_port == port_mapping[port] &&
4674 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4675 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4682 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4684 struct intel_connector *intel_connector = to_intel_connector(connector);
4686 intel_attach_force_audio_property(connector);
4687 intel_attach_broadcast_rgb_property(connector);
4688 intel_dp->color_range_auto = true;
4690 if (is_edp(intel_dp)) {
4691 drm_mode_create_scaling_mode_property(connector->dev);
4692 drm_object_attach_property(
4694 connector->dev->mode_config.scaling_mode_property,
4695 DRM_MODE_SCALE_ASPECT);
4696 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4700 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4702 intel_dp->last_power_cycle = jiffies;
4703 intel_dp->last_power_on = jiffies;
4704 intel_dp->last_backlight_off = jiffies;
4708 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4709 struct intel_dp *intel_dp)
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 struct edp_power_seq cur, vbt, spec,
4713 *final = &intel_dp->pps_delays;
4714 u32 pp_on, pp_off, pp_div, pp;
4715 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4717 lockdep_assert_held(&dev_priv->pps_mutex);
4719 /* already initialized? */
4720 if (final->t11_t12 != 0)
4723 if (HAS_PCH_SPLIT(dev)) {
4724 pp_ctrl_reg = PCH_PP_CONTROL;
4725 pp_on_reg = PCH_PP_ON_DELAYS;
4726 pp_off_reg = PCH_PP_OFF_DELAYS;
4727 pp_div_reg = PCH_PP_DIVISOR;
4729 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4731 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4732 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4733 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4734 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4737 /* Workaround: Need to write PP_CONTROL with the unlock key as
4738 * the very first thing. */
4739 pp = ironlake_get_pp_control(intel_dp);
4740 I915_WRITE(pp_ctrl_reg, pp);
4742 pp_on = I915_READ(pp_on_reg);
4743 pp_off = I915_READ(pp_off_reg);
4744 pp_div = I915_READ(pp_div_reg);
4746 /* Pull timing values out of registers */
4747 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4748 PANEL_POWER_UP_DELAY_SHIFT;
4750 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4751 PANEL_LIGHT_ON_DELAY_SHIFT;
4753 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4754 PANEL_LIGHT_OFF_DELAY_SHIFT;
4756 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4757 PANEL_POWER_DOWN_DELAY_SHIFT;
4759 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4760 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4762 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4763 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4765 vbt = dev_priv->vbt.edp_pps;
4767 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4768 * our hw here, which are all in 100usec. */
4769 spec.t1_t3 = 210 * 10;
4770 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4771 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4772 spec.t10 = 500 * 10;
4773 /* This one is special and actually in units of 100ms, but zero
4774 * based in the hw (so we need to add 100 ms). But the sw vbt
4775 * table multiplies it with 1000 to make it in units of 100usec,
4777 spec.t11_t12 = (510 + 100) * 10;
4779 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4780 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4782 /* Use the max of the register settings and vbt. If both are
4783 * unset, fall back to the spec limits. */
4784 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4786 max(cur.field, vbt.field))
4787 assign_final(t1_t3);
4791 assign_final(t11_t12);
4794 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4795 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4796 intel_dp->backlight_on_delay = get_delay(t8);
4797 intel_dp->backlight_off_delay = get_delay(t9);
4798 intel_dp->panel_power_down_delay = get_delay(t10);
4799 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4802 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4803 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4804 intel_dp->panel_power_cycle_delay);
4806 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4807 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4811 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4812 struct intel_dp *intel_dp)
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 u32 pp_on, pp_off, pp_div, port_sel = 0;
4816 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4817 int pp_on_reg, pp_off_reg, pp_div_reg;
4818 enum port port = dp_to_dig_port(intel_dp)->port;
4819 const struct edp_power_seq *seq = &intel_dp->pps_delays;
4821 lockdep_assert_held(&dev_priv->pps_mutex);
4823 if (HAS_PCH_SPLIT(dev)) {
4824 pp_on_reg = PCH_PP_ON_DELAYS;
4825 pp_off_reg = PCH_PP_OFF_DELAYS;
4826 pp_div_reg = PCH_PP_DIVISOR;
4828 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4830 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4831 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4832 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4836 * And finally store the new values in the power sequencer. The
4837 * backlight delays are set to 1 because we do manual waits on them. For
4838 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4839 * we'll end up waiting for the backlight off delay twice: once when we
4840 * do the manual sleep, and once when we disable the panel and wait for
4841 * the PP_STATUS bit to become zero.
4843 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4844 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4845 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4846 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4847 /* Compute the divisor for the pp clock, simply match the Bspec
4849 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4850 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4851 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4853 /* Haswell doesn't have any port selection bits for the panel
4854 * power sequencer any more. */
4855 if (IS_VALLEYVIEW(dev)) {
4856 port_sel = PANEL_PORT_SELECT_VLV(port);
4857 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4859 port_sel = PANEL_PORT_SELECT_DPA;
4861 port_sel = PANEL_PORT_SELECT_DPD;
4866 I915_WRITE(pp_on_reg, pp_on);
4867 I915_WRITE(pp_off_reg, pp_off);
4868 I915_WRITE(pp_div_reg, pp_div);
4870 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4871 I915_READ(pp_on_reg),
4872 I915_READ(pp_off_reg),
4873 I915_READ(pp_div_reg));
4876 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879 struct intel_encoder *encoder;
4880 struct intel_digital_port *dig_port = NULL;
4881 struct intel_dp *intel_dp = dev_priv->drrs.dp;
4882 struct intel_crtc_state *config = NULL;
4883 struct intel_crtc *intel_crtc = NULL;
4885 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4887 if (refresh_rate <= 0) {
4888 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4892 if (intel_dp == NULL) {
4893 DRM_DEBUG_KMS("DRRS not supported.\n");
4898 * FIXME: This needs proper synchronization with psr state for some
4899 * platforms that cannot have PSR and DRRS enabled at the same time.
4902 dig_port = dp_to_dig_port(intel_dp);
4903 encoder = &dig_port->base;
4904 intel_crtc = encoder->new_crtc;
4907 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4911 config = intel_crtc->config;
4913 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4914 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4918 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4920 index = DRRS_LOW_RR;
4922 if (index == dev_priv->drrs.refresh_rate_type) {
4924 "DRRS requested for previously set RR...ignoring\n");
4928 if (!intel_crtc->active) {
4929 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4933 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4934 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
4935 val = I915_READ(reg);
4936 if (index > DRRS_HIGH_RR) {
4937 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4938 intel_dp_set_m_n(intel_crtc);
4940 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4942 I915_WRITE(reg, val);
4945 dev_priv->drrs.refresh_rate_type = index;
4947 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4950 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
4952 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4953 struct drm_i915_private *dev_priv = dev->dev_private;
4954 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4955 struct drm_crtc *crtc = dig_port->base.base.crtc;
4956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4958 if (!intel_crtc->config->has_drrs) {
4959 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4963 mutex_lock(&dev_priv->drrs.mutex);
4964 if (WARN_ON(dev_priv->drrs.dp)) {
4965 DRM_ERROR("DRRS already enabled\n");
4969 dev_priv->drrs.busy_frontbuffer_bits = 0;
4971 dev_priv->drrs.dp = intel_dp;
4974 mutex_unlock(&dev_priv->drrs.mutex);
4977 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
4979 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4980 struct drm_i915_private *dev_priv = dev->dev_private;
4981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4982 struct drm_crtc *crtc = dig_port->base.base.crtc;
4983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4985 if (!intel_crtc->config->has_drrs)
4988 mutex_lock(&dev_priv->drrs.mutex);
4989 if (!dev_priv->drrs.dp) {
4990 mutex_unlock(&dev_priv->drrs.mutex);
4994 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4995 intel_dp_set_drrs_state(dev_priv->dev,
4996 intel_dp->attached_connector->panel.
4997 fixed_mode->vrefresh);
4999 dev_priv->drrs.dp = NULL;
5000 mutex_unlock(&dev_priv->drrs.mutex);
5002 cancel_delayed_work_sync(&dev_priv->drrs.work);
5005 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5007 struct drm_i915_private *dev_priv =
5008 container_of(work, typeof(*dev_priv), drrs.work.work);
5009 struct intel_dp *intel_dp;
5011 mutex_lock(&dev_priv->drrs.mutex);
5013 intel_dp = dev_priv->drrs.dp;
5019 * The delayed work can race with an invalidate hence we need to
5023 if (dev_priv->drrs.busy_frontbuffer_bits)
5026 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5027 intel_dp_set_drrs_state(dev_priv->dev,
5028 intel_dp->attached_connector->panel.
5029 downclock_mode->vrefresh);
5033 mutex_unlock(&dev_priv->drrs.mutex);
5036 void intel_edp_drrs_invalidate(struct drm_device *dev,
5037 unsigned frontbuffer_bits)
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 struct drm_crtc *crtc;
5041 enum i915_pipe pipe;
5043 if (!dev_priv->drrs.dp)
5046 mutex_lock(&dev_priv->drrs.mutex);
5047 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5048 pipe = to_intel_crtc(crtc)->pipe;
5050 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
5051 cancel_delayed_work_sync(&dev_priv->drrs.work);
5052 intel_dp_set_drrs_state(dev_priv->dev,
5053 dev_priv->drrs.dp->attached_connector->panel.
5054 fixed_mode->vrefresh);
5057 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5059 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5060 mutex_unlock(&dev_priv->drrs.mutex);
5063 void intel_edp_drrs_flush(struct drm_device *dev,
5064 unsigned frontbuffer_bits)
5066 struct drm_i915_private *dev_priv = dev->dev_private;
5067 struct drm_crtc *crtc;
5068 enum i915_pipe pipe;
5070 if (!dev_priv->drrs.dp)
5073 mutex_lock(&dev_priv->drrs.mutex);
5074 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5075 pipe = to_intel_crtc(crtc)->pipe;
5076 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5078 cancel_delayed_work_sync(&dev_priv->drrs.work);
5080 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5081 !dev_priv->drrs.busy_frontbuffer_bits)
5082 schedule_delayed_work(&dev_priv->drrs.work,
5083 msecs_to_jiffies(1000));
5084 mutex_unlock(&dev_priv->drrs.mutex);
5087 static struct drm_display_mode *
5088 intel_dp_drrs_init(struct intel_connector *intel_connector,
5089 struct drm_display_mode *fixed_mode)
5091 struct drm_connector *connector = &intel_connector->base;
5092 struct drm_device *dev = connector->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct drm_display_mode *downclock_mode = NULL;
5096 if (INTEL_INFO(dev)->gen <= 6) {
5097 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5101 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5102 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5106 downclock_mode = intel_find_panel_downclock
5107 (dev, fixed_mode, connector);
5109 if (!downclock_mode) {
5110 DRM_DEBUG_KMS("DRRS not supported\n");
5114 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5116 lockinit(&dev_priv->drrs.mutex, "i915dm", 0, LK_CANRECURSE);
5118 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5120 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5121 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5122 return downclock_mode;
5125 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5126 struct intel_connector *intel_connector)
5128 struct drm_connector *connector = &intel_connector->base;
5129 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5130 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5131 struct drm_device *dev = intel_encoder->base.dev;
5132 struct drm_i915_private *dev_priv = dev->dev_private;
5133 struct drm_display_mode *fixed_mode = NULL;
5134 struct drm_display_mode *downclock_mode = NULL;
5136 struct drm_display_mode *scan;
5138 enum i915_pipe pipe = INVALID_PIPE;
5140 dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
5142 if (!is_edp(intel_dp))
5146 intel_edp_panel_vdd_sanitize(intel_dp);
5147 pps_unlock(intel_dp);
5149 /* Cache DPCD and EDID for edp. */
5150 has_dpcd = intel_dp_get_dpcd(intel_dp);
5153 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5154 dev_priv->no_aux_handshake =
5155 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5156 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5158 /* if this fails, presume the device is a ghost */
5159 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5163 /* We now know it's not a ghost, init power sequence regs. */
5165 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5166 pps_unlock(intel_dp);
5168 mutex_lock(&dev->mode_config.mutex);
5169 edid = drm_get_edid(connector, intel_dp->aux.ddc);
5171 if (drm_add_edid_modes(connector, edid)) {
5172 drm_mode_connector_update_edid_property(connector,
5174 drm_edid_to_eld(connector, edid);
5177 edid = ERR_PTR(-EINVAL);
5180 edid = ERR_PTR(-ENOENT);
5182 intel_connector->edid = edid;
5184 /* prefer fixed mode from EDID if available */
5185 list_for_each_entry(scan, &connector->probed_modes, head) {
5186 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5187 fixed_mode = drm_mode_duplicate(dev, scan);
5188 downclock_mode = intel_dp_drrs_init(
5189 intel_connector, fixed_mode);
5194 /* fallback to VBT if available for eDP */
5195 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5196 fixed_mode = drm_mode_duplicate(dev,
5197 dev_priv->vbt.lfp_lvds_vbt_mode);
5199 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5201 mutex_unlock(&dev->mode_config.mutex);
5203 if (IS_VALLEYVIEW(dev)) {
5205 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5206 register_reboot_notifier(&intel_dp->edp_notifier);
5210 * Figure out the current pipe for the initial backlight setup.
5211 * If the current pipe isn't valid, try the PPS pipe, and if that
5212 * fails just assume pipe A.
5214 if (IS_CHERRYVIEW(dev))
5215 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5217 pipe = PORT_TO_PIPE(intel_dp->DP);
5219 if (pipe != PIPE_A && pipe != PIPE_B)
5220 pipe = intel_dp->pps_pipe;
5222 if (pipe != PIPE_A && pipe != PIPE_B)
5225 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5229 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5230 intel_connector->panel.backlight_power = intel_edp_backlight_power;
5231 intel_panel_setup_backlight(connector, pipe);
5237 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5238 struct intel_connector *intel_connector)
5240 struct drm_connector *connector = &intel_connector->base;
5241 struct intel_dp *intel_dp = &intel_dig_port->dp;
5242 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5243 struct drm_device *dev = intel_encoder->base.dev;
5244 struct drm_i915_private *dev_priv = dev->dev_private;
5245 enum port port = intel_dig_port->port;
5248 intel_dp->pps_pipe = INVALID_PIPE;
5250 /* intel_dp vfuncs */
5251 if (INTEL_INFO(dev)->gen >= 9)
5252 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5253 else if (IS_VALLEYVIEW(dev))
5254 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5255 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5256 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5257 else if (HAS_PCH_SPLIT(dev))
5258 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5260 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5262 if (INTEL_INFO(dev)->gen >= 9)
5263 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5265 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5267 /* Preserve the current hw state. */
5268 intel_dp->DP = I915_READ(intel_dp->output_reg);
5269 intel_dp->attached_connector = intel_connector;
5271 if (intel_dp_is_edp(dev, port))
5272 type = DRM_MODE_CONNECTOR_eDP;
5274 type = DRM_MODE_CONNECTOR_DisplayPort;
5277 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5278 * for DP the encoder type can be set by the caller to
5279 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5281 if (type == DRM_MODE_CONNECTOR_eDP)
5282 intel_encoder->type = INTEL_OUTPUT_EDP;
5284 /* eDP only on port B and/or C on vlv/chv */
5285 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5286 port != PORT_B && port != PORT_C))
5289 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5290 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5293 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5294 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5296 connector->interlace_allowed = true;
5297 connector->doublescan_allowed = 0;
5299 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5300 edp_panel_vdd_work);
5302 intel_connector_attach_encoder(intel_connector, intel_encoder);
5303 drm_connector_register(connector);
5306 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5308 intel_connector->get_hw_state = intel_connector_get_hw_state;
5309 intel_connector->unregister = intel_dp_connector_unregister;
5311 /* Set up the hotplug pin. */
5314 intel_encoder->hpd_pin = HPD_PORT_A;
5317 intel_encoder->hpd_pin = HPD_PORT_B;
5320 intel_encoder->hpd_pin = HPD_PORT_C;
5323 intel_encoder->hpd_pin = HPD_PORT_D;
5329 if (is_edp(intel_dp)) {
5331 intel_dp_init_panel_power_timestamps(intel_dp);
5332 if (IS_VALLEYVIEW(dev))
5333 vlv_initial_power_sequencer_setup(intel_dp);
5335 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5336 pps_unlock(intel_dp);
5339 intel_dp_aux_init(intel_dp, intel_connector);
5341 /* init MST on ports that can support it */
5342 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
5343 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5344 intel_dp_mst_encoder_init(intel_dig_port,
5345 intel_connector->base.base.id);
5349 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5350 drm_dp_aux_unregister(&intel_dp->aux);
5351 if (is_edp(intel_dp)) {
5352 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5354 * vdd might still be enabled do to the delayed vdd off.
5355 * Make sure vdd is actually turned off here.
5358 edp_panel_vdd_off_sync(intel_dp);
5359 pps_unlock(intel_dp);
5361 drm_connector_unregister(connector);
5362 drm_connector_cleanup(connector);
5366 intel_dp_add_properties(intel_dp, connector);
5368 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5369 * 0xd. Failure to do so will result in spurious interrupts being
5370 * generated on the port when a cable is not attached.
5372 if (IS_G4X(dev) && !IS_GM45(dev)) {
5373 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5374 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5381 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5383 struct drm_i915_private *dev_priv = dev->dev_private;
5384 struct intel_digital_port *intel_dig_port;
5385 struct intel_encoder *intel_encoder;
5386 struct drm_encoder *encoder;
5387 struct intel_connector *intel_connector;
5389 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5390 if (!intel_dig_port)
5393 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5394 if (!intel_connector) {
5395 kfree(intel_dig_port);
5399 intel_encoder = &intel_dig_port->base;
5400 encoder = &intel_encoder->base;
5402 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5403 DRM_MODE_ENCODER_TMDS);
5405 intel_encoder->compute_config = intel_dp_compute_config;
5406 intel_encoder->disable = intel_disable_dp;
5407 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5408 intel_encoder->get_config = intel_dp_get_config;
5409 intel_encoder->suspend = intel_dp_encoder_suspend;
5410 if (IS_CHERRYVIEW(dev)) {
5411 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5412 intel_encoder->pre_enable = chv_pre_enable_dp;
5413 intel_encoder->enable = vlv_enable_dp;
5414 intel_encoder->post_disable = chv_post_disable_dp;
5415 } else if (IS_VALLEYVIEW(dev)) {
5416 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5417 intel_encoder->pre_enable = vlv_pre_enable_dp;
5418 intel_encoder->enable = vlv_enable_dp;
5419 intel_encoder->post_disable = vlv_post_disable_dp;
5421 intel_encoder->pre_enable = g4x_pre_enable_dp;
5422 intel_encoder->enable = g4x_enable_dp;
5423 if (INTEL_INFO(dev)->gen >= 5)
5424 intel_encoder->post_disable = ilk_post_disable_dp;
5427 intel_dig_port->port = port;
5428 intel_dig_port->dp.output_reg = output_reg;
5430 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5431 if (IS_CHERRYVIEW(dev)) {
5433 intel_encoder->crtc_mask = 1 << 2;
5435 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5437 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5439 intel_encoder->cloneable = 0;
5440 intel_encoder->hot_plug = intel_dp_hot_plug;
5442 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5443 dev_priv->hpd_irq_port[port] = intel_dig_port;
5445 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5446 drm_encoder_cleanup(encoder);
5447 kfree(intel_dig_port);
5448 kfree(intel_connector);
5452 void intel_dp_mst_resume(struct drm_device *dev)
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5457 for (i = 0; i < I915_MAX_PORTS; i++) {
5458 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5459 if (!intel_dig_port)
5461 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5465 if (!intel_dig_port->dp.can_mst)
5468 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5470 intel_dp_check_mst_status(&intel_dig_port->dp);