2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
31 #include <machine/globaldata.h>
32 #include <machine/smp.h>
33 #include <machine/cputypes.h>
34 #include <machine/md_var.h>
35 #include <machine/pmap.h>
36 #include <machine_base/apic/mpapic.h>
37 #include <machine/segments.h>
38 #include <sys/thread2.h>
40 #include <machine/intr_machdep.h>
43 extern pt_entry_t *SMPpt;
45 /* EISA Edge/Level trigger control registers */
46 #define ELCR0 0x4d0 /* eisa irq 0-7 */
47 #define ELCR1 0x4d1 /* eisa irq 8-15 */
49 static void lapic_timer_calibrate(void);
50 static void lapic_timer_set_divisor(int);
51 static void lapic_timer_fixup_handler(void *);
52 static void lapic_timer_restart_handler(void *);
54 void lapic_timer_process(void);
55 void lapic_timer_process_frame(struct intrframe *);
57 static int lapic_timer_enable = 1;
58 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
60 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
61 static void lapic_timer_intr_enable(struct cputimer_intr *);
62 static void lapic_timer_intr_restart(struct cputimer_intr *);
63 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
65 static struct cputimer_intr lapic_cputimer_intr = {
67 .reload = lapic_timer_intr_reload,
68 .enable = lapic_timer_intr_enable,
69 .config = cputimer_intr_default_config,
70 .restart = lapic_timer_intr_restart,
71 .pmfixup = lapic_timer_intr_pmfixup,
72 .initclock = cputimer_intr_default_initclock,
73 .next = SLIST_ENTRY_INITIALIZER,
75 .type = CPUTIMER_INTR_LAPIC,
76 .prio = CPUTIMER_INTR_PRIO_LAPIC,
77 .caps = CPUTIMER_INTR_CAP_NONE
81 * pointers to pmapped apic hardware.
84 volatile ioapic_t **ioapic;
86 static int lapic_timer_divisor_idx = -1;
87 static const uint32_t lapic_timer_divisors[] = {
88 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
89 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
91 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
96 * Enable LAPIC, configure interrupts.
99 apic_initialize(boolean_t bsp)
105 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
106 * aggregate interrupt input from the 8259. The INTA cycle
107 * will be routed to the external controller (the 8259) which
108 * is expected to supply the vector.
110 * Must be setup edge triggered, active high.
112 * Disable LINT0 on the APs. It doesn't matter what delivery
113 * mode we use because we leave it masked.
115 temp = lapic.lvt_lint0;
116 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
117 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
118 if (mycpu->gd_cpuid == 0)
119 temp |= APIC_LVT_DM_EXTINT;
121 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
122 lapic.lvt_lint0 = temp;
125 * Setup LINT1 as NMI, masked till later.
126 * Edge trigger, active high.
128 temp = lapic.lvt_lint1;
129 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
130 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
131 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
132 lapic.lvt_lint1 = temp;
135 * Mask the LAPIC error interrupt, LAPIC performance counter
138 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
139 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
142 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
144 timer = lapic.lvt_timer;
145 timer &= ~APIC_LVTT_VECTOR;
146 timer |= XTIMER_OFFSET;
147 timer |= APIC_LVTT_MASKED;
148 lapic.lvt_timer = timer;
151 * Set the Task Priority Register as needed. At the moment allow
152 * interrupts on all cpus (the APs will remain CLId until they are
153 * ready to deal). We could disable all but IPIs by setting
154 * temp |= TPR_IPI for cpu != 0.
157 temp &= ~APIC_TPR_PRIO; /* clear priority field */
158 #ifdef SMP /* APIC-IO */
159 if (!apic_io_enable) {
162 * If we are NOT running the IO APICs, the LAPIC will only be used
163 * for IPIs. Set the TPR to prevent any unintentional interrupts.
166 #ifdef SMP /* APIC-IO */
176 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
177 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
180 * Set the spurious interrupt vector. The low 4 bits of the vector
183 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
184 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
185 temp &= ~APIC_SVR_VECTOR;
186 temp |= XSPURIOUSINT_OFFSET;
191 * Pump out a few EOIs to clean out interrupts that got through
192 * before we were able to set the TPR.
199 lapic_timer_calibrate();
200 if (lapic_timer_enable) {
201 cputimer_intr_register(&lapic_cputimer_intr);
202 cputimer_intr_select(&lapic_cputimer_intr, 0);
205 lapic_timer_set_divisor(lapic_timer_divisor_idx);
209 apic_dump("apic_initialize()");
213 lapic_timer_set_divisor(int divisor_idx)
215 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
216 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
220 lapic_timer_oneshot(u_int count)
224 value = lapic.lvt_timer;
225 value &= ~APIC_LVTT_PERIODIC;
226 lapic.lvt_timer = value;
227 lapic.icr_timer = count;
231 lapic_timer_oneshot_quick(u_int count)
233 lapic.icr_timer = count;
237 lapic_timer_calibrate(void)
241 /* Try to calibrate the local APIC timer. */
242 for (lapic_timer_divisor_idx = 0;
243 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
244 lapic_timer_divisor_idx++) {
245 lapic_timer_set_divisor(lapic_timer_divisor_idx);
246 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
248 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
249 if (value != APIC_TIMER_MAX_COUNT)
252 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
253 panic("lapic: no proper timer divisor?!\n");
254 lapic_cputimer_intr.freq = value / 2;
256 kprintf("lapic: divisor index %d, frequency %u Hz\n",
257 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
261 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
265 gd->gd_timer_running = 0;
267 count = sys_cputimer->count();
268 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
269 systimer_intr(&count, 0, frame);
273 lapic_timer_process(void)
275 lapic_timer_process_oncpu(mycpu, NULL);
279 lapic_timer_process_frame(struct intrframe *frame)
281 lapic_timer_process_oncpu(mycpu, frame);
285 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
287 struct globaldata *gd = mycpu;
289 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
293 if (gd->gd_timer_running) {
294 if (reload < lapic.ccr_timer)
295 lapic_timer_oneshot_quick(reload);
297 gd->gd_timer_running = 1;
298 lapic_timer_oneshot_quick(reload);
303 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
307 timer = lapic.lvt_timer;
308 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
309 lapic.lvt_timer = timer;
311 lapic_timer_fixup_handler(NULL);
315 lapic_timer_fixup_handler(void *arg)
322 if (cpu_vendor_id == CPU_VENDOR_AMD) {
324 * Detect the presence of C1E capability mostly on latest
325 * dual-cores (or future) k8 family. This feature renders
326 * the local APIC timer dead, so we disable it by reading
327 * the Interrupt Pending Message register and clearing both
328 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
331 * "BIOS and Kernel Developer's Guide for AMD NPT
332 * Family 0Fh Processors"
333 * #32559 revision 3.00
335 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
336 (cpu_id & 0x0fff0000) >= 0x00040000) {
339 msr = rdmsr(0xc0010055);
340 if (msr & 0x18000000) {
341 struct globaldata *gd = mycpu;
343 kprintf("cpu%d: AMD C1E detected\n",
345 wrmsr(0xc0010055, msr & ~0x18000000ULL);
348 * We are kinda stalled;
351 gd->gd_timer_running = 1;
352 lapic_timer_oneshot_quick(2);
362 lapic_timer_restart_handler(void *dummy __unused)
366 lapic_timer_fixup_handler(&started);
368 struct globaldata *gd = mycpu;
370 gd->gd_timer_running = 1;
371 lapic_timer_oneshot_quick(2);
376 * This function is called only by ACPI-CA code currently:
377 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
378 * module controls PM. So once ACPI-CA is attached, we try
379 * to apply the fixup to prevent LAPIC timer from hanging.
382 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
384 lwkt_send_ipiq_mask(smp_active_mask,
385 lapic_timer_fixup_handler, NULL);
389 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
391 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
396 * dump contents of local APIC registers
401 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
402 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
403 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
407 #ifdef SMP /* APIC-IO */
413 #define IOAPIC_ISA_INTS 16
414 #define REDIRCNT_IOAPIC(A) \
415 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
417 static int trigger (int apic, int pin, u_int32_t * flags);
418 static void polarity (int apic, int pin, u_int32_t * flags, int level);
420 #define DEFAULT_FLAGS \
426 #define DEFAULT_ISA_FLAGS \
435 io_apic_set_id(int apic, int id)
439 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* get current contents */
440 if (((ux & APIC_ID_MASK) >> 24) != id) {
441 kprintf("Changing APIC ID for IO APIC #%d"
442 " from %d to %d on chip\n",
443 apic, ((ux & APIC_ID_MASK) >> 24), id);
444 ux &= ~APIC_ID_MASK; /* clear the ID field */
446 ioapic_write(ioapic[apic], IOAPIC_ID, ux); /* write new value */
447 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* re-read && test */
448 if (((ux & APIC_ID_MASK) >> 24) != id)
449 panic("can't control IO APIC #%d ID, reg: 0x%08x",
456 io_apic_get_id(int apic)
458 return (ioapic_read(ioapic[apic], IOAPIC_ID) & APIC_ID_MASK) >> 24;
467 io_apic_setup_intpin(int apic, int pin)
469 int bus, bustype, irq;
470 u_char select; /* the select register is 8 bits */
471 u_int32_t flags; /* the window register is 32 bits */
472 u_int32_t target; /* the window register is 32 bits */
473 u_int32_t vector; /* the window register is 32 bits */
478 select = pin * 2 + IOAPIC_REDTBL0; /* register */
481 * Always clear an IO APIC pin before [re]programming it. This is
482 * particularly important if the pin is set up for a level interrupt
483 * as the IOART_REM_IRR bit might be set. When we reprogram the
484 * vector any EOI from pending ints on this pin could be lost and
485 * IRR might never get reset.
487 * To fix this problem, clear the vector and make sure it is
488 * programmed as an edge interrupt. This should theoretically
489 * clear IRR so we can later, safely program it as a level
494 flags = ioapic_read(ioapic[apic], select) & IOART_RESV;
495 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
496 flags |= IOART_DESTPHY | IOART_DELFIXED;
498 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
499 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
503 ioapic_write(ioapic[apic], select, flags | vector);
504 ioapic_write(ioapic[apic], select + 1, target);
509 * We only deal with vectored interrupts here. ? documentation is
510 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
513 * This test also catches unconfigured pins.
515 if (apic_int_type(apic, pin) != 0)
519 * Leave the pin unprogrammed if it does not correspond to
522 irq = apic_irq(apic, pin);
526 /* determine the bus type for this pin */
527 bus = apic_src_bus_id(apic, pin);
530 bustype = apic_bus_type(bus);
532 if ((bustype == ISA) &&
533 (pin < IOAPIC_ISA_INTS) &&
535 (apic_polarity(apic, pin) == 0x1) &&
536 (apic_trigger(apic, pin) == 0x3)) {
538 * A broken BIOS might describe some ISA
539 * interrupts as active-high level-triggered.
540 * Use default ISA flags for those interrupts.
542 flags = DEFAULT_ISA_FLAGS;
545 * Program polarity and trigger mode according to
548 flags = DEFAULT_FLAGS;
549 level = trigger(apic, pin, &flags);
551 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
552 polarity(apic, pin, &flags, level);
556 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
557 kgetenv_int(envpath, &cpuid);
559 /* ncpus may not be available yet */
564 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
565 apic, pin, irq, cpuid);
569 * Program the appropriate registers. This routing may be
570 * overridden when an interrupt handler for a device is
571 * actually added (see register_int(), which calls through
572 * the MACHINTR ABI to set up an interrupt handler/vector).
574 * The order in which we must program the two registers for
575 * safety is unclear! XXX
579 vector = IDT_OFFSET + irq; /* IDT vec */
580 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
581 /* Deliver all interrupts to CPU0 (BSP) */
582 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
584 flags |= ioapic_read(ioapic[apic], select) & IOART_RESV;
585 ioapic_write(ioapic[apic], select, flags | vector);
586 ioapic_write(ioapic[apic], select + 1, target);
592 io_apic_setup(int apic)
597 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
598 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
600 for (pin = 0; pin < maxpin; ++pin) {
601 io_apic_setup_intpin(apic, pin);
604 if (apic_int_type(apic, pin) >= 0) {
605 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
606 " cannot program!\n", apic, pin);
611 /* return GOOD status */
614 #undef DEFAULT_ISA_FLAGS
618 #define DEFAULT_EXTINT_FLAGS \
627 * XXX this function is only used by 8254 setup
628 * Setup the source of External INTerrupts.
631 ext_int_setup(int apic, int intr)
633 u_char select; /* the select register is 8 bits */
634 u_int32_t flags; /* the window register is 32 bits */
635 u_int32_t target; /* the window register is 32 bits */
636 u_int32_t vector; /* the window register is 32 bits */
640 if (apic_int_type(apic, intr) != 3)
644 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
645 kgetenv_int(envpath, &cpuid);
647 /* ncpus may not be available yet */
651 /* Deliver interrupts to CPU0 (BSP) */
652 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
654 select = IOAPIC_REDTBL0 + (2 * intr);
655 vector = IDT_OFFSET + intr;
656 flags = DEFAULT_EXTINT_FLAGS;
658 ioapic_write(ioapic[apic], select, flags | vector);
659 ioapic_write(ioapic[apic], select + 1, target);
663 #undef DEFAULT_EXTINT_FLAGS
667 * Set the trigger level for an IO APIC pin.
670 trigger(int apic, int pin, u_int32_t * flags)
675 static int intcontrol = -1;
677 switch (apic_trigger(apic, pin)) {
683 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
687 *flags |= IOART_TRGRLVL;
695 if ((id = apic_src_bus_id(apic, pin)) == -1)
698 switch (apic_bus_type(id)) {
700 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
704 eirq = apic_src_bus_irq(apic, pin);
706 if (eirq < 0 || eirq > 15) {
707 kprintf("EISA IRQ %d?!?!\n", eirq);
711 if (intcontrol == -1) {
712 intcontrol = inb(ELCR1) << 8;
713 intcontrol |= inb(ELCR0);
714 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
717 /* Use ELCR settings to determine level or edge mode */
718 level = (intcontrol >> eirq) & 1;
721 * Note that on older Neptune chipset based systems, any
722 * pci interrupts often show up here and in the ELCR as well
723 * as level sensitive interrupts attributed to the EISA bus.
727 *flags |= IOART_TRGRLVL;
729 *flags &= ~IOART_TRGRLVL;
734 *flags |= IOART_TRGRLVL;
743 panic("bad APIC IO INT flags");
748 * Set the polarity value for an IO APIC pin.
751 polarity(int apic, int pin, u_int32_t * flags, int level)
755 switch (apic_polarity(apic, pin)) {
761 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
765 *flags |= IOART_INTALO;
773 if ((id = apic_src_bus_id(apic, pin)) == -1)
776 switch (apic_bus_type(id)) {
778 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
782 /* polarity converter always gives active high */
783 *flags &= ~IOART_INTALO;
787 *flags |= IOART_INTALO;
796 panic("bad APIC IO INT flags");
801 * Print contents of unmasked IRQs.
808 kprintf("SMP: enabled INTs: ");
809 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
810 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
818 * Inter Processor Interrupt functions.
821 #endif /* SMP APIC-IO */
824 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
826 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
827 * vector is any valid SYSTEM INT vector
828 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
830 * A backlog of requests can create a deadlock between cpus. To avoid this
831 * we have to be able to accept IPIs at the same time we are trying to send
832 * them. The critical section prevents us from attempting to send additional
833 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
834 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
835 * to occur but fortunately it does not happen too often.
838 apic_ipi(int dest_type, int vector, int delivery_mode)
843 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
844 unsigned int eflags = read_eflags();
846 DEBUG_PUSH_INFO("apic_ipi");
847 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
851 write_eflags(eflags);
854 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
855 delivery_mode | vector;
856 lapic.icr_lo = icr_lo;
862 single_apic_ipi(int cpu, int vector, int delivery_mode)
868 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
869 unsigned int eflags = read_eflags();
871 DEBUG_PUSH_INFO("single_apic_ipi");
872 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
876 write_eflags(eflags);
878 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
879 icr_hi |= (CPU_TO_ID(cpu) << 24);
880 lapic.icr_hi = icr_hi;
883 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
884 | APIC_DEST_DESTFLD | delivery_mode | vector;
887 lapic.icr_lo = icr_lo;
894 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
896 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
897 * to the target, and the scheduler does not 'poll' for IPI messages.
900 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
906 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
910 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
911 icr_hi |= (CPU_TO_ID(cpu) << 24);
912 lapic.icr_hi = icr_hi;
915 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
916 | APIC_DEST_DESTFLD | delivery_mode | vector;
919 lapic.icr_lo = icr_lo;
927 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
929 * target is a bitmask of destination cpus. Vector is any
930 * valid system INT vector. Delivery mode may be either
931 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
934 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
938 int n = BSFCPUMASK(target);
939 target &= ~CPUMASK(n);
940 single_apic_ipi(n, vector, delivery_mode);
946 * Timer code, in development...
947 * - suggested by rgrimes@gndrsh.aac.dev.com
950 get_apic_timer_frequency(void)
952 return(lapic_cputimer_intr.freq);
956 * Load a 'downcount time' in uSeconds.
959 set_apic_timer(int us)
964 * When we reach here, lapic timer's frequency
965 * must have been calculated as well as the
966 * divisor (lapic.dcr_timer is setup during the
967 * divisor calculation).
969 KKASSERT(lapic_cputimer_intr.freq != 0 &&
970 lapic_timer_divisor_idx >= 0);
972 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
973 lapic_timer_oneshot(count);
978 * Read remaining time in timer.
981 read_apic_timer(void)
984 /** XXX FIXME: we need to return the actual remaining time,
985 * for now we just return the remaining count.
988 return lapic.ccr_timer;
994 * Spin-style delay, set delay time in uS, spin till it drains.
999 set_apic_timer(count);
1000 while (read_apic_timer())
1005 lapic_map(vm_offset_t lapic_addr)
1007 /* Local apic is mapped on last page */
1008 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1009 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1011 kprintf("lapic: at %p\n", (void *)lapic_addr);
1014 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1015 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1020 struct lapic_enumerator *e;
1023 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1024 error = e->lapic_probe(e);
1029 panic("can't config lapic\n");
1031 e->lapic_enumerate(e);
1035 lapic_enumerator_register(struct lapic_enumerator *ne)
1037 struct lapic_enumerator *e;
1039 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1040 if (e->lapic_prio < ne->lapic_prio) {
1041 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1045 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1048 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
1049 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
1054 struct ioapic_enumerator *e;
1057 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1058 error = e->ioapic_probe(e);
1064 panic("can't config I/O APIC\n");
1066 kprintf("no I/O APIC\n");
1071 e->ioapic_enumerate(e);
1075 ioapic_enumerator_register(struct ioapic_enumerator *ne)
1077 struct ioapic_enumerator *e;
1079 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1080 if (e->ioapic_prio < ne->ioapic_prio) {
1081 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
1085 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);