2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $");
30 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
47 #include <machine/smp.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_enable_msix(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix(device_t dev, u_int index);
114 static void pci_unmask_msix(device_t dev, u_int index);
115 static int pci_msi_blacklisted(void);
116 static void pci_resume_msi(device_t dev);
117 static void pci_resume_msix(device_t dev);
118 static int pcie_slotimpl(const pcicfgregs *);
119 static void pci_print_verbose_expr(const pcicfgregs *);
121 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
122 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_subvendor(device_t, int, int,
128 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
129 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
131 static device_method_t pci_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, pci_probe),
134 DEVMETHOD(device_attach, pci_attach),
135 DEVMETHOD(device_detach, bus_generic_detach),
136 DEVMETHOD(device_shutdown, bus_generic_shutdown),
137 DEVMETHOD(device_suspend, pci_suspend),
138 DEVMETHOD(device_resume, pci_resume),
141 DEVMETHOD(bus_print_child, pci_print_child),
142 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
143 DEVMETHOD(bus_read_ivar, pci_read_ivar),
144 DEVMETHOD(bus_write_ivar, pci_write_ivar),
145 DEVMETHOD(bus_driver_added, pci_driver_added),
146 DEVMETHOD(bus_child_detached, pci_child_detached),
147 DEVMETHOD(bus_setup_intr, pci_setup_intr),
148 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
150 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
151 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
152 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
153 DEVMETHOD(bus_delete_resource, pci_delete_resource),
154 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
155 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
158 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
159 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
162 DEVMETHOD(pci_read_config, pci_read_config_method),
163 DEVMETHOD(pci_write_config, pci_write_config_method),
164 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
165 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
166 DEVMETHOD(pci_enable_io, pci_enable_io_method),
167 DEVMETHOD(pci_disable_io, pci_disable_io_method),
168 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
169 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
170 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
171 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
172 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
173 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
174 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
175 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
176 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_msi_count, pci_msi_count_method),
179 DEVMETHOD(pci_msix_count, pci_msix_count_method),
184 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
186 static devclass_t pci_devclass;
187 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
188 MODULE_VERSION(pci, 1);
190 static char *pci_vendordata;
191 static size_t pci_vendordata_size;
194 static const struct pci_read_cap {
196 pci_read_cap_t read_cap;
197 } pci_read_caps[] = {
198 { PCIY_PMG, pci_read_cap_pmgt },
199 { PCIY_HT, pci_read_cap_ht },
200 { PCIY_MSI, pci_read_cap_msi },
201 { PCIY_MSIX, pci_read_cap_msix },
202 { PCIY_VPD, pci_read_cap_vpd },
203 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
204 { PCIY_PCIX, pci_read_cap_pcix },
205 { PCIY_EXPRESS, pci_read_cap_express },
206 { 0, NULL } /* required last entry */
210 uint32_t devid; /* Vendor/device of the card */
212 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
213 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
218 struct pci_quirk pci_quirks[] = {
219 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
220 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
221 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 /* As does the Serverworks OSB4 (the SMBus mapping register) */
223 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
226 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
227 * or the CMIC-SL (AKA ServerWorks GC_LE).
229 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 * MSI doesn't work on earlier Intel chipsets including
234 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
236 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
245 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
248 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
253 /* map register information */
254 #define PCI_MAPMEM 0x01 /* memory map */
255 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
256 #define PCI_MAPPORT 0x04 /* port map */
258 struct devlist pci_devq;
259 uint32_t pci_generation;
260 uint32_t pci_numdevs = 0;
261 static int pcie_chipset, pcix_chipset;
264 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
266 static int pci_enable_io_modes = 1;
267 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
268 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
269 &pci_enable_io_modes, 1,
270 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
271 enable these bits correctly. We'd like to do this all the time, but there\n\
272 are some peripherals that this causes problems with.");
274 static int pci_do_power_nodriver = 0;
275 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
276 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
277 &pci_do_power_nodriver, 0,
278 "Place a function into D3 state when no driver attaches to it. 0 means\n\
279 disable. 1 means conservatively place devices into D3 state. 2 means\n\
280 aggressively place devices into D3 state. 3 means put absolutely everything\n\
283 static int pci_do_power_resume = 1;
284 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
285 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
286 &pci_do_power_resume, 1,
287 "Transition from D3 -> D0 on resume.");
289 static int pci_do_msi = 1;
290 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
291 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
292 "Enable support for MSI interrupts");
294 static int pci_do_msix = 1;
295 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
296 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
297 "Enable support for MSI-X interrupts");
299 static int pci_honor_msi_blacklist = 1;
300 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
301 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
302 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
304 /* Find a device_t by bus/slot/function in domain 0 */
307 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
310 return (pci_find_dbsf(0, bus, slot, func));
313 /* Find a device_t by domain/bus/slot/function */
316 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
318 struct pci_devinfo *dinfo;
320 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
321 if ((dinfo->cfg.domain == domain) &&
322 (dinfo->cfg.bus == bus) &&
323 (dinfo->cfg.slot == slot) &&
324 (dinfo->cfg.func == func)) {
325 return (dinfo->cfg.dev);
332 /* Find a device_t by vendor/device ID */
335 pci_find_device(uint16_t vendor, uint16_t device)
337 struct pci_devinfo *dinfo;
339 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
340 if ((dinfo->cfg.vendor == vendor) &&
341 (dinfo->cfg.device == device)) {
342 return (dinfo->cfg.dev);
349 /* return base address of memory or port map */
352 pci_mapbase(uint32_t mapreg)
355 if (PCI_BAR_MEM(mapreg))
356 return (mapreg & PCIM_BAR_MEM_BASE);
358 return (mapreg & PCIM_BAR_IO_BASE);
361 /* return map type of memory or port map */
364 pci_maptype(unsigned mapreg)
367 if (PCI_BAR_IO(mapreg))
369 if (mapreg & PCIM_BAR_MEM_PREFETCH)
370 return ("Prefetchable Memory");
374 /* return log2 of map size decoded for memory or port map */
377 pci_mapsize(uint32_t testval)
381 testval = pci_mapbase(testval);
384 while ((testval & 1) == 0)
393 /* return log2 of address range supported by map register */
396 pci_maprange(unsigned mapreg)
400 if (PCI_BAR_IO(mapreg))
403 switch (mapreg & PCIM_BAR_MEM_TYPE) {
404 case PCIM_BAR_MEM_32:
407 case PCIM_BAR_MEM_1MB:
410 case PCIM_BAR_MEM_64:
417 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
420 pci_fixancient(pcicfgregs *cfg)
422 if (cfg->hdrtype != 0)
425 /* PCI to PCI bridges use header type 1 */
426 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
430 /* extract header type specific config data */
433 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
435 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
436 switch (cfg->hdrtype) {
438 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
439 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
440 cfg->nummaps = PCI_MAXMAPS_0;
443 cfg->nummaps = PCI_MAXMAPS_1;
446 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
447 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
448 cfg->nummaps = PCI_MAXMAPS_2;
454 /* read configuration header into pcicfgregs structure */
456 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
458 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
459 pcicfgregs *cfg = NULL;
460 struct pci_devinfo *devlist_entry;
461 struct devlist *devlist_head;
463 devlist_head = &pci_devq;
465 devlist_entry = NULL;
467 if (REG(PCIR_DEVVENDOR, 4) != -1) {
468 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
470 cfg = &devlist_entry->cfg;
476 cfg->vendor = REG(PCIR_VENDOR, 2);
477 cfg->device = REG(PCIR_DEVICE, 2);
478 cfg->cmdreg = REG(PCIR_COMMAND, 2);
479 cfg->statreg = REG(PCIR_STATUS, 2);
480 cfg->baseclass = REG(PCIR_CLASS, 1);
481 cfg->subclass = REG(PCIR_SUBCLASS, 1);
482 cfg->progif = REG(PCIR_PROGIF, 1);
483 cfg->revid = REG(PCIR_REVID, 1);
484 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
485 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
486 cfg->lattimer = REG(PCIR_LATTIMER, 1);
487 cfg->intpin = REG(PCIR_INTPIN, 1);
488 cfg->intline = REG(PCIR_INTLINE, 1);
492 * If using the APIC the intpin is probably wrong, since it
493 * is often setup by the BIOS with the PIC in mind.
495 if (cfg->intpin != 0) {
498 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
500 /* PCI specific entry found in MP table */
501 if (airq != cfg->intline) {
502 undirect_pci_irq(cfg->intline);
507 * PCI interrupts might be redirected to the
508 * ISA bus according to some MP tables. Use the
509 * same methods as used by the ISA devices
510 * devices to find the proper IOAPIC int pin.
512 airq = isa_apic_irq(cfg->intline);
513 if ((airq >= 0) && (airq != cfg->intline)) {
514 /* XXX: undirect_pci_irq() ? */
515 undirect_isa_irq(cfg->intline);
522 cfg->mingnt = REG(PCIR_MINGNT, 1);
523 cfg->maxlat = REG(PCIR_MAXLAT, 1);
525 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
526 cfg->hdrtype &= ~PCIM_MFDEV;
529 pci_hdrtypedata(pcib, b, s, f, cfg);
531 pci_read_capabilities(pcib, cfg);
533 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
535 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
536 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
537 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
538 devlist_entry->conf.pc_sel.pc_func = cfg->func;
539 devlist_entry->conf.pc_hdr = cfg->hdrtype;
541 devlist_entry->conf.pc_subvendor = cfg->subvendor;
542 devlist_entry->conf.pc_subdevice = cfg->subdevice;
543 devlist_entry->conf.pc_vendor = cfg->vendor;
544 devlist_entry->conf.pc_device = cfg->device;
546 devlist_entry->conf.pc_class = cfg->baseclass;
547 devlist_entry->conf.pc_subclass = cfg->subclass;
548 devlist_entry->conf.pc_progif = cfg->progif;
549 devlist_entry->conf.pc_revid = cfg->revid;
554 return (devlist_entry);
559 pci_fixup_nextptr(int *nextptr0)
561 int nextptr = *nextptr0;
563 /* "Next pointer" is only one byte */
564 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
568 * PCI local bus spec 3.0:
570 * "... The bottom two bits of all pointers are reserved
571 * and must be implemented as 00b although software must
572 * mask them to allow for future uses of these bits ..."
575 kprintf("Illegal PCI extended capability "
576 "offset, fixup 0x%02x -> 0x%02x\n",
577 nextptr, nextptr & ~0x3);
583 if (nextptr < 0x40) {
585 kprintf("Illegal PCI extended capability "
586 "offset 0x%02x", nextptr);
594 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
597 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
599 struct pcicfg_pp *pp = &cfg->pp;
604 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
605 pp->pp_status = ptr + PCIR_POWER_STATUS;
606 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
608 if ((nextptr - ptr) > PCIR_POWER_DATA) {
611 * We should write to data_select and read back from
612 * data_scale to determine whether data register is
616 pp->pp_data = ptr + PCIR_POWER_DATA;
626 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
629 #if defined(__i386__) || defined(__amd64__)
632 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
634 struct pcicfg_ht *ht = &cfg->ht;
638 /* Determine HT-specific capability type. */
639 val = REG(ptr + PCIR_HT_COMMAND, 2);
641 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
644 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
645 /* Sanity check the mapping window. */
646 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
648 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
649 if (addr != MSI_INTEL_ADDR_BASE) {
650 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
651 "has non-default MSI window 0x%llx\n",
652 cfg->domain, cfg->bus, cfg->slot, cfg->func,
656 addr = MSI_INTEL_ADDR_BASE;
660 ht->ht_msictrl = val;
661 ht->ht_msiaddr = addr;
665 #endif /* __i386__ || __amd64__ */
670 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
673 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
675 struct pcicfg_msi *msi = &cfg->msi;
677 msi->msi_location = ptr;
678 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
679 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
685 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
688 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
690 struct pcicfg_msix *msix = &cfg->msix;
693 msix->msix_location = ptr;
694 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
695 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
697 val = REG(ptr + PCIR_MSIX_TABLE, 4);
698 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
699 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
701 val = REG(ptr + PCIR_MSIX_PBA, 4);
702 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
703 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
709 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
711 cfg->vpd.vpd_reg = ptr;
715 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
718 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
720 /* Should always be true. */
721 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
724 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
725 cfg->subvendor = val & 0xffff;
726 cfg->subdevice = val >> 16;
733 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
736 * Assume we have a PCI-X chipset if we have
737 * at least one PCI-PCI bridge with a PCI-X
738 * capability. Note that some systems with
739 * PCI-express or HT chipsets might match on
740 * this check as well.
742 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
745 cfg->pcix.pcix_ptr = ptr;
749 pcie_slotimpl(const pcicfgregs *cfg)
751 const struct pcicfg_expr *expr = &cfg->expr;
755 * Only version 1 can be parsed currently
757 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
761 * - Slot implemented bit is meaningful iff current port is
762 * root port or down stream port.
763 * - Testing for root port or down stream port is meanningful
764 * iff PCI configure has type 1 header.
767 if (cfg->hdrtype != 1)
770 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
771 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
774 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
781 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
784 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
786 struct pcicfg_expr *expr = &cfg->expr;
789 * Assume we have a PCI-express chipset if we have
790 * at least one PCI-express device.
794 expr->expr_ptr = ptr;
795 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
798 * Only version 1 can be parsed currently
800 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
804 * Read slot capabilities. Slot capabilities exists iff
805 * current port's slot is implemented
807 if (pcie_slotimpl(cfg))
808 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
814 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
816 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
817 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
822 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
823 /* No capabilities */
827 switch (cfg->hdrtype & PCIM_HDRTYPE) {
830 ptrptr = PCIR_CAP_PTR;
833 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
836 return; /* no capabilities support */
838 nextptr = REG(ptrptr, 1); /* sanity check? */
841 * Read capability entries.
843 while (pci_fixup_nextptr(&nextptr)) {
844 const struct pci_read_cap *rc;
847 /* Find the next entry */
848 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
850 /* Process this entry */
851 val = REG(ptr + PCICAP_ID, 1);
852 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
853 if (rc->cap == val) {
854 rc->read_cap(pcib, ptr, nextptr, cfg);
859 /* REG and WREG use carry through to next functions */
863 * PCI Vital Product Data
866 #define PCI_VPD_TIMEOUT 1000000
869 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
871 int count = PCI_VPD_TIMEOUT;
873 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
875 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
877 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
880 DELAY(1); /* limit looping */
882 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
889 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
891 int count = PCI_VPD_TIMEOUT;
893 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
895 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
896 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
897 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
900 DELAY(1); /* limit looping */
907 #undef PCI_VPD_TIMEOUT
909 struct vpd_readstate {
919 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
924 if (vrs->bytesinval == 0) {
925 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
927 vrs->val = le32toh(reg);
929 byte = vrs->val & 0xff;
932 vrs->val = vrs->val >> 8;
933 byte = vrs->val & 0xff;
943 pcie_slot_implemented(device_t dev)
945 struct pci_devinfo *dinfo = device_get_ivars(dev);
947 return pcie_slotimpl(&dinfo->cfg);
951 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
956 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
957 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
958 panic("%s: invalid max read request size 0x%02x\n",
959 device_get_nameunit(dev), rqsize);
962 expr_ptr = pci_get_pciecap_ptr(dev);
964 panic("%s: not PCIe device\n", device_get_nameunit(dev));
966 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
967 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
969 device_printf(dev, "adjust device control 0x%04x", val);
971 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
973 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
976 kprintf(" -> 0x%04x\n", val);
981 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
983 struct vpd_readstate vrs;
988 int alloc, off; /* alloc/off for RO/W arrays */
994 /* init vpd reader */
1002 name = remain = i = 0; /* shut up stupid gcc */
1003 alloc = off = 0; /* shut up stupid gcc */
1004 dflen = 0; /* shut up stupid gcc */
1006 while (state >= 0) {
1007 if (vpd_nextbyte(&vrs, &byte)) {
1012 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1013 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1014 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1017 case 0: /* item name */
1019 if (vpd_nextbyte(&vrs, &byte2)) {
1024 if (vpd_nextbyte(&vrs, &byte2)) {
1028 remain |= byte2 << 8;
1029 if (remain > (0x7f*4 - vrs.off)) {
1032 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1033 cfg->domain, cfg->bus, cfg->slot,
1038 remain = byte & 0x7;
1039 name = (byte >> 3) & 0xf;
1042 case 0x2: /* String */
1043 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1044 M_DEVBUF, M_WAITOK);
1051 case 0x10: /* VPD-R */
1054 cfg->vpd.vpd_ros = kmalloc(alloc *
1055 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1059 case 0x11: /* VPD-W */
1062 cfg->vpd.vpd_w = kmalloc(alloc *
1063 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1067 default: /* Invalid data, abort */
1073 case 1: /* Identifier String */
1074 cfg->vpd.vpd_ident[i++] = byte;
1077 cfg->vpd.vpd_ident[i] = '\0';
1082 case 2: /* VPD-R Keyword Header */
1084 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1085 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1086 M_DEVBUF, M_WAITOK | M_ZERO);
1088 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1089 if (vpd_nextbyte(&vrs, &byte2)) {
1093 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1094 if (vpd_nextbyte(&vrs, &byte2)) {
1100 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1103 * if this happens, we can't trust the rest
1107 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1108 cfg->domain, cfg->bus, cfg->slot,
1113 } else if (dflen == 0) {
1114 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1115 sizeof(*cfg->vpd.vpd_ros[off].value),
1116 M_DEVBUF, M_WAITOK);
1117 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1119 cfg->vpd.vpd_ros[off].value = kmalloc(
1121 sizeof(*cfg->vpd.vpd_ros[off].value),
1122 M_DEVBUF, M_WAITOK);
1125 /* keep in sync w/ state 3's transistions */
1126 if (dflen == 0 && remain == 0)
1128 else if (dflen == 0)
1134 case 3: /* VPD-R Keyword Value */
1135 cfg->vpd.vpd_ros[off].value[i++] = byte;
1136 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1137 "RV", 2) == 0 && cksumvalid == -1) {
1143 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1144 cfg->domain, cfg->bus,
1145 cfg->slot, cfg->func,
1154 /* keep in sync w/ state 2's transistions */
1156 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1157 if (dflen == 0 && remain == 0) {
1158 cfg->vpd.vpd_rocnt = off;
1159 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1160 off * sizeof(*cfg->vpd.vpd_ros),
1161 M_DEVBUF, M_WAITOK | M_ZERO);
1163 } else if (dflen == 0)
1173 case 5: /* VPD-W Keyword Header */
1175 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1176 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1177 M_DEVBUF, M_WAITOK | M_ZERO);
1179 cfg->vpd.vpd_w[off].keyword[0] = byte;
1180 if (vpd_nextbyte(&vrs, &byte2)) {
1184 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1185 if (vpd_nextbyte(&vrs, &byte2)) {
1189 cfg->vpd.vpd_w[off].len = dflen = byte2;
1190 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1191 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1192 sizeof(*cfg->vpd.vpd_w[off].value),
1193 M_DEVBUF, M_WAITOK);
1196 /* keep in sync w/ state 6's transistions */
1197 if (dflen == 0 && remain == 0)
1199 else if (dflen == 0)
1205 case 6: /* VPD-W Keyword Value */
1206 cfg->vpd.vpd_w[off].value[i++] = byte;
1209 /* keep in sync w/ state 5's transistions */
1211 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1212 if (dflen == 0 && remain == 0) {
1213 cfg->vpd.vpd_wcnt = off;
1214 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1215 off * sizeof(*cfg->vpd.vpd_w),
1216 M_DEVBUF, M_WAITOK | M_ZERO);
1218 } else if (dflen == 0)
1223 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1224 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1231 if (cksumvalid == 0 || state < -1) {
1232 /* read-only data bad, clean up */
1233 if (cfg->vpd.vpd_ros != NULL) {
1234 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1235 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1236 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1237 cfg->vpd.vpd_ros = NULL;
1241 /* I/O error, clean up */
1242 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1243 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1244 if (cfg->vpd.vpd_ident != NULL) {
1245 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1246 cfg->vpd.vpd_ident = NULL;
1248 if (cfg->vpd.vpd_w != NULL) {
1249 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1250 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1251 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1252 cfg->vpd.vpd_w = NULL;
1255 cfg->vpd.vpd_cached = 1;
1261 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1263 struct pci_devinfo *dinfo = device_get_ivars(child);
1264 pcicfgregs *cfg = &dinfo->cfg;
1266 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1267 pci_read_vpd(device_get_parent(dev), cfg);
1269 *identptr = cfg->vpd.vpd_ident;
1271 if (*identptr == NULL)
1278 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1281 struct pci_devinfo *dinfo = device_get_ivars(child);
1282 pcicfgregs *cfg = &dinfo->cfg;
1285 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1286 pci_read_vpd(device_get_parent(dev), cfg);
1288 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1289 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1290 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1291 *vptr = cfg->vpd.vpd_ros[i].value;
1294 if (i != cfg->vpd.vpd_rocnt)
1302 * Return the offset in configuration space of the requested extended
1303 * capability entry or 0 if the specified capability was not found.
1306 pci_find_extcap_method(device_t dev, device_t child, int capability,
1309 struct pci_devinfo *dinfo = device_get_ivars(child);
1310 pcicfgregs *cfg = &dinfo->cfg;
1315 * Check the CAP_LIST bit of the PCI status register first.
1317 status = pci_read_config(child, PCIR_STATUS, 2);
1318 if (!(status & PCIM_STATUS_CAPPRESENT))
1322 * Determine the start pointer of the capabilities list.
1324 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1330 ptr = PCIR_CAP_PTR_2;
1334 return (ENXIO); /* no extended capabilities support */
1336 ptr = pci_read_config(child, ptr, 1);
1339 * Traverse the capabilities list.
1342 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1347 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1354 * Support for MSI-X message interrupts.
1357 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1359 struct pci_devinfo *dinfo = device_get_ivars(dev);
1360 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1363 KASSERT(msix->msix_table_len > index, ("bogus index"));
1364 offset = msix->msix_table_offset + index * 16;
1365 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1366 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1367 bus_write_4(msix->msix_table_res, offset + 8, data);
1369 /* Enable MSI -> HT mapping. */
1370 pci_ht_map_msi(dev, address);
1374 pci_mask_msix(device_t dev, u_int index)
1376 struct pci_devinfo *dinfo = device_get_ivars(dev);
1377 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1378 uint32_t offset, val;
1380 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1381 offset = msix->msix_table_offset + index * 16 + 12;
1382 val = bus_read_4(msix->msix_table_res, offset);
1383 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1384 val |= PCIM_MSIX_VCTRL_MASK;
1385 bus_write_4(msix->msix_table_res, offset, val);
1390 pci_unmask_msix(device_t dev, u_int index)
1392 struct pci_devinfo *dinfo = device_get_ivars(dev);
1393 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1394 uint32_t offset, val;
1396 KASSERT(msix->msix_table_len > index, ("bogus index"));
1397 offset = msix->msix_table_offset + index * 16 + 12;
1398 val = bus_read_4(msix->msix_table_res, offset);
1399 if (val & PCIM_MSIX_VCTRL_MASK) {
1400 val &= ~PCIM_MSIX_VCTRL_MASK;
1401 bus_write_4(msix->msix_table_res, offset, val);
1406 pci_pending_msix(device_t dev, u_int index)
1408 struct pci_devinfo *dinfo = device_get_ivars(dev);
1409 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1410 uint32_t offset, bit;
1412 KASSERT(msix->msix_table_len > index, ("bogus index"));
1413 offset = msix->msix_pba_offset + (index / 32) * 4;
1414 bit = 1 << index % 32;
1415 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1419 * Restore MSI-X registers and table during resume. If MSI-X is
1420 * enabled then walk the virtual table to restore the actual MSI-X
1424 pci_resume_msix(device_t dev)
1426 struct pci_devinfo *dinfo = device_get_ivars(dev);
1427 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1428 struct msix_table_entry *mte;
1429 struct msix_vector *mv;
1432 if (msix->msix_alloc > 0) {
1433 /* First, mask all vectors. */
1434 for (i = 0; i < msix->msix_msgnum; i++)
1435 pci_mask_msix(dev, i);
1437 /* Second, program any messages with at least one handler. */
1438 for (i = 0; i < msix->msix_table_len; i++) {
1439 mte = &msix->msix_table[i];
1440 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1442 mv = &msix->msix_vectors[mte->mte_vector - 1];
1443 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1444 pci_unmask_msix(dev, i);
1447 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1448 msix->msix_ctrl, 2);
1452 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1453 * returned in *count. After this function returns, each message will be
1454 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1457 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1459 struct pci_devinfo *dinfo = device_get_ivars(child);
1460 pcicfgregs *cfg = &dinfo->cfg;
1461 struct resource_list_entry *rle;
1462 int actual, error, i, irq, max;
1464 /* Don't let count == 0 get us into trouble. */
1468 /* If rid 0 is allocated, then fail. */
1469 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1470 if (rle != NULL && rle->res != NULL)
1473 /* Already have allocated messages? */
1474 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1477 /* If MSI is blacklisted for this system, fail. */
1478 if (pci_msi_blacklisted())
1481 /* MSI-X capability present? */
1482 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1485 /* Make sure the appropriate BARs are mapped. */
1486 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1487 cfg->msix.msix_table_bar);
1488 if (rle == NULL || rle->res == NULL ||
1489 !(rman_get_flags(rle->res) & RF_ACTIVE))
1491 cfg->msix.msix_table_res = rle->res;
1492 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1493 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1494 cfg->msix.msix_pba_bar);
1495 if (rle == NULL || rle->res == NULL ||
1496 !(rman_get_flags(rle->res) & RF_ACTIVE))
1499 cfg->msix.msix_pba_res = rle->res;
1502 device_printf(child,
1503 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1504 *count, cfg->msix.msix_msgnum);
1505 max = min(*count, cfg->msix.msix_msgnum);
1506 for (i = 0; i < max; i++) {
1507 /* Allocate a message. */
1508 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1511 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1517 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1519 device_printf(child, "using IRQ %lu for MSI-X\n",
1525 * Be fancy and try to print contiguous runs of
1526 * IRQ values as ranges. 'irq' is the previous IRQ.
1527 * 'run' is true if we are in a range.
1529 device_printf(child, "using IRQs %lu", rle->start);
1532 for (i = 1; i < actual; i++) {
1533 rle = resource_list_find(&dinfo->resources,
1534 SYS_RES_IRQ, i + 1);
1536 /* Still in a run? */
1537 if (rle->start == irq + 1) {
1543 /* Finish previous range. */
1545 kprintf("-%d", irq);
1549 /* Start new range. */
1550 kprintf(",%lu", rle->start);
1554 /* Unfinished range? */
1556 kprintf("-%d", irq);
1557 kprintf(" for MSI-X\n");
1561 /* Mask all vectors. */
1562 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1563 pci_mask_msix(child, i);
1565 /* Allocate and initialize vector data and virtual table. */
1566 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1567 M_DEVBUF, M_WAITOK | M_ZERO);
1568 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1569 M_DEVBUF, M_WAITOK | M_ZERO);
1570 for (i = 0; i < actual; i++) {
1571 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1572 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1573 cfg->msix.msix_table[i].mte_vector = i + 1;
1576 /* Update control register to enable MSI-X. */
1577 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1578 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1579 cfg->msix.msix_ctrl, 2);
1581 /* Update counts of alloc'd messages. */
1582 cfg->msix.msix_alloc = actual;
1583 cfg->msix.msix_table_len = actual;
1589 * By default, pci_alloc_msix() will assign the allocated IRQ
1590 * resources consecutively to the first N messages in the MSI-X table.
1591 * However, device drivers may want to use different layouts if they
1592 * either receive fewer messages than they asked for, or they wish to
1593 * populate the MSI-X table sparsely. This method allows the driver
1594 * to specify what layout it wants. It must be called after a
1595 * successful pci_alloc_msix() but before any of the associated
1596 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1598 * The 'vectors' array contains 'count' message vectors. The array
1599 * maps directly to the MSI-X table in that index 0 in the array
1600 * specifies the vector for the first message in the MSI-X table, etc.
1601 * The vector value in each array index can either be 0 to indicate
1602 * that no vector should be assigned to a message slot, or it can be a
1603 * number from 1 to N (where N is the count returned from a
1604 * succcessful call to pci_alloc_msix()) to indicate which message
1605 * vector (IRQ) to be used for the corresponding message.
1607 * On successful return, each message with a non-zero vector will have
1608 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1609 * 1. Additionally, if any of the IRQs allocated via the previous
1610 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1611 * will be kfreed back to the system automatically.
1613 * For example, suppose a driver has a MSI-X table with 6 messages and
1614 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1615 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1616 * C. After the call to pci_alloc_msix(), the device will be setup to
1617 * have an MSI-X table of ABC--- (where - means no vector assigned).
1618 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1619 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1620 * be kfreed back to the system. This device will also have valid
1621 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1623 * In any case, the SYS_RES_IRQ rid X will always map to the message
1624 * at MSI-X table index X - 1 and will only be valid if a vector is
1625 * assigned to that table entry.
1628 pci_remap_msix_method(device_t dev, device_t child, int count,
1629 const u_int *vectors)
1631 struct pci_devinfo *dinfo = device_get_ivars(child);
1632 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1633 struct resource_list_entry *rle;
1634 int i, irq, j, *used;
1637 * Have to have at least one message in the table but the
1638 * table can't be bigger than the actual MSI-X table in the
1641 if (count == 0 || count > msix->msix_msgnum)
1644 /* Sanity check the vectors. */
1645 for (i = 0; i < count; i++)
1646 if (vectors[i] > msix->msix_alloc)
1650 * Make sure there aren't any holes in the vectors to be used.
1651 * It's a big pain to support it, and it doesn't really make
1652 * sense anyway. Also, at least one vector must be used.
1654 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1656 for (i = 0; i < count; i++)
1657 if (vectors[i] != 0)
1658 used[vectors[i] - 1] = 1;
1659 for (i = 0; i < msix->msix_alloc - 1; i++)
1660 if (used[i] == 0 && used[i + 1] == 1) {
1661 kfree(used, M_DEVBUF);
1665 kfree(used, M_DEVBUF);
1669 /* Make sure none of the resources are allocated. */
1670 for (i = 0; i < msix->msix_table_len; i++) {
1671 if (msix->msix_table[i].mte_vector == 0)
1673 if (msix->msix_table[i].mte_handlers > 0)
1675 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1676 KASSERT(rle != NULL, ("missing resource"));
1677 if (rle->res != NULL)
1681 /* Free the existing resource list entries. */
1682 for (i = 0; i < msix->msix_table_len; i++) {
1683 if (msix->msix_table[i].mte_vector == 0)
1685 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1689 * Build the new virtual table keeping track of which vectors are
1692 kfree(msix->msix_table, M_DEVBUF);
1693 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1694 M_DEVBUF, M_WAITOK | M_ZERO);
1695 for (i = 0; i < count; i++)
1696 msix->msix_table[i].mte_vector = vectors[i];
1697 msix->msix_table_len = count;
1699 /* Free any unused IRQs and resize the vectors array if necessary. */
1700 j = msix->msix_alloc - 1;
1702 struct msix_vector *vec;
1704 while (used[j] == 0) {
1705 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1706 msix->msix_vectors[j].mv_irq);
1709 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1711 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1713 kfree(msix->msix_vectors, M_DEVBUF);
1714 msix->msix_vectors = vec;
1715 msix->msix_alloc = j + 1;
1717 kfree(used, M_DEVBUF);
1719 /* Map the IRQs onto the rids. */
1720 for (i = 0; i < count; i++) {
1721 if (vectors[i] == 0)
1723 irq = msix->msix_vectors[vectors[i]].mv_irq;
1724 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1729 device_printf(child, "Remapped MSI-X IRQs as: ");
1730 for (i = 0; i < count; i++) {
1733 if (vectors[i] == 0)
1737 msix->msix_vectors[vectors[i]].mv_irq);
1746 pci_release_msix(device_t dev, device_t child)
1748 struct pci_devinfo *dinfo = device_get_ivars(child);
1749 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1750 struct resource_list_entry *rle;
1753 /* Do we have any messages to release? */
1754 if (msix->msix_alloc == 0)
1757 /* Make sure none of the resources are allocated. */
1758 for (i = 0; i < msix->msix_table_len; i++) {
1759 if (msix->msix_table[i].mte_vector == 0)
1761 if (msix->msix_table[i].mte_handlers > 0)
1763 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1764 KASSERT(rle != NULL, ("missing resource"));
1765 if (rle->res != NULL)
1769 /* Update control register to disable MSI-X. */
1770 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1771 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1772 msix->msix_ctrl, 2);
1774 /* Free the resource list entries. */
1775 for (i = 0; i < msix->msix_table_len; i++) {
1776 if (msix->msix_table[i].mte_vector == 0)
1778 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1780 kfree(msix->msix_table, M_DEVBUF);
1781 msix->msix_table_len = 0;
1783 /* Release the IRQs. */
1784 for (i = 0; i < msix->msix_alloc; i++)
1785 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1786 msix->msix_vectors[i].mv_irq);
1787 kfree(msix->msix_vectors, M_DEVBUF);
1788 msix->msix_alloc = 0;
1793 * Return the max supported MSI-X messages this device supports.
1794 * Basically, assuming the MD code can alloc messages, this function
1795 * should return the maximum value that pci_alloc_msix() can return.
1796 * Thus, it is subject to the tunables, etc.
1799 pci_msix_count_method(device_t dev, device_t child)
1801 struct pci_devinfo *dinfo = device_get_ivars(child);
1802 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1804 if (pci_do_msix && msix->msix_location != 0)
1805 return (msix->msix_msgnum);
1810 * HyperTransport MSI mapping control
1813 pci_ht_map_msi(device_t dev, uint64_t addr)
1815 struct pci_devinfo *dinfo = device_get_ivars(dev);
1816 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1821 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1822 ht->ht_msiaddr >> 20 == addr >> 20) {
1823 /* Enable MSI -> HT mapping. */
1824 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1825 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1829 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1830 /* Disable MSI -> HT mapping. */
1831 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1832 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1838 * Support for MSI message signalled interrupts.
1841 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1843 struct pci_devinfo *dinfo = device_get_ivars(dev);
1844 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1846 /* Write data and address values. */
1847 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1848 address & 0xffffffff, 4);
1849 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1850 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1852 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1855 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1858 /* Enable MSI in the control register. */
1859 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1860 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1863 /* Enable MSI -> HT mapping. */
1864 pci_ht_map_msi(dev, address);
1868 pci_disable_msi(device_t dev)
1870 struct pci_devinfo *dinfo = device_get_ivars(dev);
1871 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1873 /* Disable MSI -> HT mapping. */
1874 pci_ht_map_msi(dev, 0);
1876 /* Disable MSI in the control register. */
1877 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1878 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1883 * Restore MSI registers during resume. If MSI is enabled then
1884 * restore the data and address registers in addition to the control
1888 pci_resume_msi(device_t dev)
1890 struct pci_devinfo *dinfo = device_get_ivars(dev);
1891 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1895 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1896 address = msi->msi_addr;
1897 data = msi->msi_data;
1898 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1899 address & 0xffffffff, 4);
1900 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1901 pci_write_config(dev, msi->msi_location +
1902 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1903 pci_write_config(dev, msi->msi_location +
1904 PCIR_MSI_DATA_64BIT, data, 2);
1906 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1909 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1914 pci_remap_msi_irq(device_t dev, u_int irq)
1916 struct pci_devinfo *dinfo = device_get_ivars(dev);
1917 pcicfgregs *cfg = &dinfo->cfg;
1918 struct resource_list_entry *rle;
1919 struct msix_table_entry *mte;
1920 struct msix_vector *mv;
1926 bus = device_get_parent(dev);
1929 * Handle MSI first. We try to find this IRQ among our list
1930 * of MSI IRQs. If we find it, we request updated address and
1931 * data registers and apply the results.
1933 if (cfg->msi.msi_alloc > 0) {
1935 /* If we don't have any active handlers, nothing to do. */
1936 if (cfg->msi.msi_handlers == 0)
1938 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1939 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1941 if (rle->start == irq) {
1942 error = PCIB_MAP_MSI(device_get_parent(bus),
1943 dev, irq, &addr, &data);
1946 pci_disable_msi(dev);
1947 dinfo->cfg.msi.msi_addr = addr;
1948 dinfo->cfg.msi.msi_data = data;
1949 pci_enable_msi(dev, addr, data);
1957 * For MSI-X, we check to see if we have this IRQ. If we do,
1958 * we request the updated mapping info. If that works, we go
1959 * through all the slots that use this IRQ and update them.
1961 if (cfg->msix.msix_alloc > 0) {
1962 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1963 mv = &cfg->msix.msix_vectors[i];
1964 if (mv->mv_irq == irq) {
1965 error = PCIB_MAP_MSI(device_get_parent(bus),
1966 dev, irq, &addr, &data);
1969 mv->mv_address = addr;
1971 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1972 mte = &cfg->msix.msix_table[j];
1973 if (mte->mte_vector != i + 1)
1975 if (mte->mte_handlers == 0)
1977 pci_mask_msix(dev, j);
1978 pci_enable_msix(dev, j, addr, data);
1979 pci_unmask_msix(dev, j);
1990 * Returns true if the specified device is blacklisted because MSI
1994 pci_msi_device_blacklisted(device_t dev)
1996 struct pci_quirk *q;
1998 if (!pci_honor_msi_blacklist)
2001 for (q = &pci_quirks[0]; q->devid; q++) {
2002 if (q->devid == pci_get_devid(dev) &&
2003 q->type == PCI_QUIRK_DISABLE_MSI)
2010 * Determine if MSI is blacklisted globally on this sytem. Currently,
2011 * we just check for blacklisted chipsets as represented by the
2012 * host-PCI bridge at device 0:0:0. In the future, it may become
2013 * necessary to check other system attributes, such as the kenv values
2014 * that give the motherboard manufacturer and model number.
2017 pci_msi_blacklisted(void)
2021 if (!pci_honor_msi_blacklist)
2024 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2025 if (!(pcie_chipset || pcix_chipset))
2028 dev = pci_find_bsf(0, 0, 0);
2030 return (pci_msi_device_blacklisted(dev));
2035 * Attempt to allocate *count MSI messages. The actual number allocated is
2036 * returned in *count. After this function returns, each message will be
2037 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2040 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2042 struct pci_devinfo *dinfo = device_get_ivars(child);
2043 pcicfgregs *cfg = &dinfo->cfg;
2044 struct resource_list_entry *rle;
2045 int actual, error, i, irqs[32];
2048 /* Don't let count == 0 get us into trouble. */
2052 /* If rid 0 is allocated, then fail. */
2053 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2054 if (rle != NULL && rle->res != NULL)
2057 /* Already have allocated messages? */
2058 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2061 /* If MSI is blacklisted for this system, fail. */
2062 if (pci_msi_blacklisted())
2065 /* MSI capability present? */
2066 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2070 device_printf(child,
2071 "attempting to allocate %d MSI vectors (%d supported)\n",
2072 *count, cfg->msi.msi_msgnum);
2074 /* Don't ask for more than the device supports. */
2075 actual = min(*count, cfg->msi.msi_msgnum);
2077 /* Don't ask for more than 32 messages. */
2078 actual = min(actual, 32);
2080 /* MSI requires power of 2 number of messages. */
2081 if (!powerof2(actual))
2085 /* Try to allocate N messages. */
2086 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2087 cfg->msi.msi_msgnum, irqs);
2098 * We now have N actual messages mapped onto SYS_RES_IRQ
2099 * resources in the irqs[] array, so add new resources
2100 * starting at rid 1.
2102 for (i = 0; i < actual; i++)
2103 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2104 irqs[i], irqs[i], 1);
2108 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2113 * Be fancy and try to print contiguous runs
2114 * of IRQ values as ranges. 'run' is true if
2115 * we are in a range.
2117 device_printf(child, "using IRQs %d", irqs[0]);
2119 for (i = 1; i < actual; i++) {
2121 /* Still in a run? */
2122 if (irqs[i] == irqs[i - 1] + 1) {
2127 /* Finish previous range. */
2129 kprintf("-%d", irqs[i - 1]);
2133 /* Start new range. */
2134 kprintf(",%d", irqs[i]);
2137 /* Unfinished range? */
2139 kprintf("-%d", irqs[actual - 1]);
2140 kprintf(" for MSI\n");
2144 /* Update control register with actual count. */
2145 ctrl = cfg->msi.msi_ctrl;
2146 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2147 ctrl |= (ffs(actual) - 1) << 4;
2148 cfg->msi.msi_ctrl = ctrl;
2149 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2151 /* Update counts of alloc'd messages. */
2152 cfg->msi.msi_alloc = actual;
2153 cfg->msi.msi_handlers = 0;
2158 /* Release the MSI messages associated with this device. */
2160 pci_release_msi_method(device_t dev, device_t child)
2162 struct pci_devinfo *dinfo = device_get_ivars(child);
2163 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2164 struct resource_list_entry *rle;
2165 int error, i, irqs[32];
2167 /* Try MSI-X first. */
2168 error = pci_release_msix(dev, child);
2169 if (error != ENODEV)
2172 /* Do we have any messages to release? */
2173 if (msi->msi_alloc == 0)
2175 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2177 /* Make sure none of the resources are allocated. */
2178 if (msi->msi_handlers > 0)
2180 for (i = 0; i < msi->msi_alloc; i++) {
2181 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2182 KASSERT(rle != NULL, ("missing MSI resource"));
2183 if (rle->res != NULL)
2185 irqs[i] = rle->start;
2188 /* Update control register with 0 count. */
2189 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2190 ("%s: MSI still enabled", __func__));
2191 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2192 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2195 /* Release the messages. */
2196 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2197 for (i = 0; i < msi->msi_alloc; i++)
2198 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2200 /* Update alloc count. */
2208 * Return the max supported MSI messages this device supports.
2209 * Basically, assuming the MD code can alloc messages, this function
2210 * should return the maximum value that pci_alloc_msi() can return.
2211 * Thus, it is subject to the tunables, etc.
2214 pci_msi_count_method(device_t dev, device_t child)
2216 struct pci_devinfo *dinfo = device_get_ivars(child);
2217 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2219 if (pci_do_msi && msi->msi_location != 0)
2220 return (msi->msi_msgnum);
2224 /* kfree pcicfgregs structure and all depending data structures */
2227 pci_freecfg(struct pci_devinfo *dinfo)
2229 struct devlist *devlist_head;
2232 devlist_head = &pci_devq;
2234 if (dinfo->cfg.vpd.vpd_reg) {
2235 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2236 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2237 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2238 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2239 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2240 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2241 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2243 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2244 kfree(dinfo, M_DEVBUF);
2246 /* increment the generation count */
2249 /* we're losing one device */
2255 * PCI power manangement
2258 pci_set_powerstate_method(device_t dev, device_t child, int state)
2260 struct pci_devinfo *dinfo = device_get_ivars(child);
2261 pcicfgregs *cfg = &dinfo->cfg;
2263 int result, oldstate, highest, delay;
2265 if (cfg->pp.pp_cap == 0)
2266 return (EOPNOTSUPP);
2269 * Optimize a no state change request away. While it would be OK to
2270 * write to the hardware in theory, some devices have shown odd
2271 * behavior when going from D3 -> D3.
2273 oldstate = pci_get_powerstate(child);
2274 if (oldstate == state)
2278 * The PCI power management specification states that after a state
2279 * transition between PCI power states, system software must
2280 * guarantee a minimal delay before the function accesses the device.
2281 * Compute the worst case delay that we need to guarantee before we
2282 * access the device. Many devices will be responsive much more
2283 * quickly than this delay, but there are some that don't respond
2284 * instantly to state changes. Transitions to/from D3 state require
2285 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2286 * is done below with DELAY rather than a sleeper function because
2287 * this function can be called from contexts where we cannot sleep.
2289 highest = (oldstate > state) ? oldstate : state;
2290 if (highest == PCI_POWERSTATE_D3)
2292 else if (highest == PCI_POWERSTATE_D2)
2296 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2297 & ~PCIM_PSTAT_DMASK;
2300 case PCI_POWERSTATE_D0:
2301 status |= PCIM_PSTAT_D0;
2303 case PCI_POWERSTATE_D1:
2304 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2305 return (EOPNOTSUPP);
2306 status |= PCIM_PSTAT_D1;
2308 case PCI_POWERSTATE_D2:
2309 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2310 return (EOPNOTSUPP);
2311 status |= PCIM_PSTAT_D2;
2313 case PCI_POWERSTATE_D3:
2314 status |= PCIM_PSTAT_D3;
2322 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2323 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2324 dinfo->cfg.func, oldstate, state);
2326 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2333 pci_get_powerstate_method(device_t dev, device_t child)
2335 struct pci_devinfo *dinfo = device_get_ivars(child);
2336 pcicfgregs *cfg = &dinfo->cfg;
2340 if (cfg->pp.pp_cap != 0) {
2341 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2342 switch (status & PCIM_PSTAT_DMASK) {
2344 result = PCI_POWERSTATE_D0;
2347 result = PCI_POWERSTATE_D1;
2350 result = PCI_POWERSTATE_D2;
2353 result = PCI_POWERSTATE_D3;
2356 result = PCI_POWERSTATE_UNKNOWN;
2360 /* No support, device is always at D0 */
2361 result = PCI_POWERSTATE_D0;
2367 * Some convenience functions for PCI device drivers.
2370 static __inline void
2371 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2375 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2377 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2380 static __inline void
2381 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2385 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2387 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2391 pci_enable_busmaster_method(device_t dev, device_t child)
2393 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2398 pci_disable_busmaster_method(device_t dev, device_t child)
2400 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2405 pci_enable_io_method(device_t dev, device_t child, int space)
2415 case SYS_RES_IOPORT:
2416 bit = PCIM_CMD_PORTEN;
2419 case SYS_RES_MEMORY:
2420 bit = PCIM_CMD_MEMEN;
2426 pci_set_command_bit(dev, child, bit);
2427 /* Some devices seem to need a brief stall here, what do to? */
2428 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2431 device_printf(child, "failed to enable %s mapping!\n", error);
2436 pci_disable_io_method(device_t dev, device_t child, int space)
2446 case SYS_RES_IOPORT:
2447 bit = PCIM_CMD_PORTEN;
2450 case SYS_RES_MEMORY:
2451 bit = PCIM_CMD_MEMEN;
2457 pci_clear_command_bit(dev, child, bit);
2458 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2459 if (command & bit) {
2460 device_printf(child, "failed to disable %s mapping!\n", error);
2467 * New style pci driver. Parent device is either a pci-host-bridge or a
2468 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2472 pci_print_verbose(struct pci_devinfo *dinfo)
2476 pcicfgregs *cfg = &dinfo->cfg;
2478 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2479 cfg->vendor, cfg->device, cfg->revid);
2480 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2481 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2482 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2483 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2485 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2486 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2487 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2488 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2489 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2490 if (cfg->intpin > 0)
2491 kprintf("\tintpin=%c, irq=%d\n",
2492 cfg->intpin +'a' -1, cfg->intline);
2493 if (cfg->pp.pp_cap) {
2496 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2497 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2498 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2499 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2500 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2501 status & PCIM_PSTAT_DMASK);
2503 if (cfg->msi.msi_location) {
2506 ctrl = cfg->msi.msi_ctrl;
2507 kprintf("\tMSI supports %d message%s%s%s\n",
2508 cfg->msi.msi_msgnum,
2509 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2510 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2511 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2513 if (cfg->msix.msix_location) {
2514 kprintf("\tMSI-X supports %d message%s ",
2515 cfg->msix.msix_msgnum,
2516 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2517 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2518 kprintf("in map 0x%x\n",
2519 cfg->msix.msix_table_bar);
2521 kprintf("in maps 0x%x and 0x%x\n",
2522 cfg->msix.msix_table_bar,
2523 cfg->msix.msix_pba_bar);
2525 pci_print_verbose_expr(cfg);
2530 pci_print_verbose_expr(const pcicfgregs *cfg)
2532 const struct pcicfg_expr *expr = &cfg->expr;
2533 const char *port_name;
2539 if (expr->expr_ptr == 0) /* No PCI Express capability */
2542 kprintf("\tPCI Express ver.%d cap=0x%04x",
2543 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2544 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2547 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2549 switch (port_type) {
2550 case PCIE_END_POINT:
2551 port_name = "DEVICE";
2553 case PCIE_LEG_END_POINT:
2554 port_name = "LEGDEV";
2556 case PCIE_ROOT_PORT:
2559 case PCIE_UP_STREAM_PORT:
2560 port_name = "UPSTREAM";
2562 case PCIE_DOWN_STREAM_PORT:
2563 port_name = "DOWNSTRM";
2565 case PCIE_PCIE2PCI_BRIDGE:
2566 port_name = "PCIE2PCI";
2568 case PCIE_PCI2PCIE_BRIDGE:
2569 port_name = "PCI2PCIE";
2575 if ((port_type == PCIE_ROOT_PORT ||
2576 port_type == PCIE_DOWN_STREAM_PORT) &&
2577 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2579 if (port_name != NULL)
2580 kprintf("[%s]", port_name);
2582 if (pcie_slotimpl(cfg)) {
2583 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2584 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2585 kprintf("[HOTPLUG]");
2592 pci_porten(device_t pcib, int b, int s, int f)
2594 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2595 & PCIM_CMD_PORTEN) != 0;
2599 pci_memen(device_t pcib, int b, int s, int f)
2601 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2602 & PCIM_CMD_MEMEN) != 0;
2606 * Add a resource based on a pci map register. Return 1 if the map
2607 * register is a 32bit map register or 2 if it is a 64bit register.
2610 pci_add_map(device_t pcib, device_t bus, device_t dev,
2611 int b, int s, int f, int reg, struct resource_list *rl, int force,
2616 pci_addr_t start, end, count;
2623 struct resource *res;
2625 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2626 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2627 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2628 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2630 if (PCI_BAR_MEM(map)) {
2631 type = SYS_RES_MEMORY;
2632 if (map & PCIM_BAR_MEM_PREFETCH)
2635 type = SYS_RES_IOPORT;
2636 ln2size = pci_mapsize(testval);
2637 ln2range = pci_maprange(testval);
2638 base = pci_mapbase(map);
2639 barlen = ln2range == 64 ? 2 : 1;
2642 * For I/O registers, if bottom bit is set, and the next bit up
2643 * isn't clear, we know we have a BAR that doesn't conform to the
2644 * spec, so ignore it. Also, sanity check the size of the data
2645 * areas to the type of memory involved. Memory must be at least
2646 * 16 bytes in size, while I/O ranges must be at least 4.
2648 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2650 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2651 (type == SYS_RES_IOPORT && ln2size < 2))
2655 /* Read the other half of a 64bit map register */
2656 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2658 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2659 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2660 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2661 kprintf(", port disabled\n");
2662 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2663 kprintf(", memory disabled\n");
2665 kprintf(", enabled\n");
2669 * If base is 0, then we have problems. It is best to ignore
2670 * such entries for the moment. These will be allocated later if
2671 * the driver specifically requests them. However, some
2672 * removable busses look better when all resources are allocated,
2673 * so allow '0' to be overriden.
2675 * Similarly treat maps whose values is the same as the test value
2676 * read back. These maps have had all f's written to them by the
2677 * BIOS in an attempt to disable the resources.
2679 if (!force && (base == 0 || map == testval))
2681 if ((u_long)base != base) {
2683 "pci%d:%d:%d:%d bar %#x too many address bits",
2684 pci_get_domain(dev), b, s, f, reg);
2689 * This code theoretically does the right thing, but has
2690 * undesirable side effects in some cases where peripherals
2691 * respond oddly to having these bits enabled. Let the user
2692 * be able to turn them off (since pci_enable_io_modes is 1 by
2695 if (pci_enable_io_modes) {
2696 /* Turn on resources that have been left off by a lazy BIOS */
2697 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2698 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2699 cmd |= PCIM_CMD_PORTEN;
2700 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2702 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2703 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2704 cmd |= PCIM_CMD_MEMEN;
2705 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2708 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2710 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2714 count = 1 << ln2size;
2715 if (base == 0 || base == pci_mapbase(testval)) {
2716 start = 0; /* Let the parent decide. */
2720 end = base + (1 << ln2size) - 1;
2722 resource_list_add(rl, type, reg, start, end, count);
2725 * Try to allocate the resource for this BAR from our parent
2726 * so that this resource range is already reserved. The
2727 * driver for this device will later inherit this resource in
2728 * pci_alloc_resource().
2730 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2731 prefetch ? RF_PREFETCHABLE : 0);
2734 * If the allocation fails, clear the BAR and delete
2735 * the resource list entry to force
2736 * pci_alloc_resource() to allocate resources from the
2739 resource_list_delete(rl, type, reg);
2742 start = rman_get_start(res);
2743 pci_write_config(dev, reg, start, 4);
2745 pci_write_config(dev, reg + 4, start >> 32, 4);
2750 * For ATA devices we need to decide early what addressing mode to use.
2751 * Legacy demands that the primary and secondary ATA ports sits on the
2752 * same addresses that old ISA hardware did. This dictates that we use
2753 * those addresses and ignore the BAR's if we cannot set PCI native
2757 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2758 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2760 int rid, type, progif;
2762 /* if this device supports PCI native addressing use it */
2763 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2764 if ((progif & 0x8a) == 0x8a) {
2765 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2766 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2767 kprintf("Trying ATA native PCI addressing mode\n");
2768 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2772 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2773 type = SYS_RES_IOPORT;
2774 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2775 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2776 prefetchmask & (1 << 0));
2777 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2778 prefetchmask & (1 << 1));
2781 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2782 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2785 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2786 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2789 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2790 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2791 prefetchmask & (1 << 2));
2792 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2793 prefetchmask & (1 << 3));
2796 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2797 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2800 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2801 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2804 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2805 prefetchmask & (1 << 4));
2806 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2807 prefetchmask & (1 << 5));
2811 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2813 struct pci_devinfo *dinfo = device_get_ivars(dev);
2814 pcicfgregs *cfg = &dinfo->cfg;
2815 char tunable_name[64];
2818 /* Has to have an intpin to have an interrupt. */
2819 if (cfg->intpin == 0)
2822 /* Let the user override the IRQ with a tunable. */
2823 irq = PCI_INVALID_IRQ;
2824 ksnprintf(tunable_name, sizeof(tunable_name),
2825 "hw.pci%d.%d.%d.INT%c.irq",
2826 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2827 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2828 irq = PCI_INVALID_IRQ;
2831 * If we didn't get an IRQ via the tunable, then we either use the
2832 * IRQ value in the intline register or we ask the bus to route an
2833 * interrupt for us. If force_route is true, then we only use the
2834 * value in the intline register if the bus was unable to assign an
2837 if (!PCI_INTERRUPT_VALID(irq)) {
2838 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2839 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2840 if (!PCI_INTERRUPT_VALID(irq))
2844 /* If after all that we don't have an IRQ, just bail. */
2845 if (!PCI_INTERRUPT_VALID(irq))
2848 /* Update the config register if it changed. */
2849 if (irq != cfg->intline) {
2851 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2854 /* Add this IRQ as rid 0 interrupt resource. */
2855 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2859 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2861 struct pci_devinfo *dinfo = device_get_ivars(dev);
2862 pcicfgregs *cfg = &dinfo->cfg;
2863 struct resource_list *rl = &dinfo->resources;
2864 struct pci_quirk *q;
2871 /* ATA devices needs special map treatment */
2872 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2873 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2874 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2875 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2876 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2877 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2879 for (i = 0; i < cfg->nummaps;)
2880 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2881 rl, force, prefetchmask & (1 << i));
2884 * Add additional, quirked resources.
2886 for (q = &pci_quirks[0]; q->devid; q++) {
2887 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2888 && q->type == PCI_QUIRK_MAP_REG)
2889 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2893 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2894 #ifdef __PCI_REROUTE_INTERRUPT
2896 * Try to re-route interrupts. Sometimes the BIOS or
2897 * firmware may leave bogus values in these registers.
2898 * If the re-route fails, then just stick with what we
2901 pci_assign_interrupt(bus, dev, 1);
2903 pci_assign_interrupt(bus, dev, 0);
2909 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2911 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2912 device_t pcib = device_get_parent(dev);
2913 struct pci_devinfo *dinfo;
2915 int s, f, pcifunchigh;
2918 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2919 ("dinfo_size too small"));
2920 maxslots = PCIB_MAXSLOTS(pcib);
2921 for (s = 0; s <= maxslots; s++) {
2925 hdrtype = REG(PCIR_HDRTYPE, 1);
2926 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2928 if (hdrtype & PCIM_MFDEV)
2929 pcifunchigh = PCI_FUNCMAX;
2930 for (f = 0; f <= pcifunchigh; f++) {
2931 dinfo = pci_read_device(pcib, domain, busno, s, f,
2933 if (dinfo != NULL) {
2934 pci_add_child(dev, dinfo);
2942 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2946 pcib = device_get_parent(bus);
2947 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2948 device_set_ivars(dinfo->cfg.dev, dinfo);
2949 resource_list_init(&dinfo->resources);
2950 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2951 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2952 pci_print_verbose(dinfo);
2953 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2957 pci_probe(device_t dev)
2959 device_set_desc(dev, "PCI bus");
2961 /* Allow other subclasses to override this driver. */
2966 pci_attach(device_t dev)
2971 * Since there can be multiple independantly numbered PCI
2972 * busses on systems with multiple PCI domains, we can't use
2973 * the unit number to decide which bus we are probing. We ask
2974 * the parent pcib what our domain and bus numbers are.
2976 domain = pcib_get_domain(dev);
2977 busno = pcib_get_bus(dev);
2979 device_printf(dev, "domain=%d, physical bus=%d\n",
2982 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2984 return (bus_generic_attach(dev));
2988 pci_suspend(device_t dev)
2990 int dstate, error, i, numdevs;
2991 device_t acpi_dev, child, *devlist;
2992 struct pci_devinfo *dinfo;
2995 * Save the PCI configuration space for each child and set the
2996 * device in the appropriate power state for this sleep state.
2999 if (pci_do_power_resume)
3000 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3001 device_get_children(dev, &devlist, &numdevs);
3002 for (i = 0; i < numdevs; i++) {
3004 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3005 pci_cfg_save(child, dinfo, 0);
3008 /* Suspend devices before potentially powering them down. */
3009 error = bus_generic_suspend(dev);
3011 kfree(devlist, M_TEMP);
3016 * Always set the device to D3. If ACPI suggests a different
3017 * power state, use it instead. If ACPI is not present, the
3018 * firmware is responsible for managing device power. Skip
3019 * children who aren't attached since they are powered down
3020 * separately. Only manage type 0 devices for now.
3022 for (i = 0; acpi_dev && i < numdevs; i++) {
3024 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3025 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3026 dstate = PCI_POWERSTATE_D3;
3027 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3028 pci_set_powerstate(child, dstate);
3031 kfree(devlist, M_TEMP);
3036 pci_resume(device_t dev)
3039 device_t acpi_dev, child, *devlist;
3040 struct pci_devinfo *dinfo;
3043 * Set each child to D0 and restore its PCI configuration space.
3046 if (pci_do_power_resume)
3047 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3048 device_get_children(dev, &devlist, &numdevs);
3049 for (i = 0; i < numdevs; i++) {
3051 * Notify ACPI we're going to D0 but ignore the result. If
3052 * ACPI is not present, the firmware is responsible for
3053 * managing device power. Only manage type 0 devices for now.
3056 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3057 if (acpi_dev && device_is_attached(child) &&
3058 dinfo->cfg.hdrtype == 0) {
3059 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3060 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3063 /* Now the device is powered up, restore its config space. */
3064 pci_cfg_restore(child, dinfo);
3066 kfree(devlist, M_TEMP);
3067 return (bus_generic_resume(dev));
3071 pci_load_vendor_data(void)
3073 caddr_t vendordata, info;
3075 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3076 info = preload_search_info(vendordata, MODINFO_ADDR);
3077 pci_vendordata = *(char **)info;
3078 info = preload_search_info(vendordata, MODINFO_SIZE);
3079 pci_vendordata_size = *(size_t *)info;
3080 /* terminate the database */
3081 pci_vendordata[pci_vendordata_size] = '\n';
3086 pci_driver_added(device_t dev, driver_t *driver)
3091 struct pci_devinfo *dinfo;
3095 device_printf(dev, "driver added\n");
3096 DEVICE_IDENTIFY(driver, dev);
3097 device_get_children(dev, &devlist, &numdevs);
3098 for (i = 0; i < numdevs; i++) {
3100 if (device_get_state(child) != DS_NOTPRESENT)
3102 dinfo = device_get_ivars(child);
3103 pci_print_verbose(dinfo);
3105 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3106 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3108 pci_cfg_restore(child, dinfo);
3109 if (device_probe_and_attach(child) != 0)
3110 pci_cfg_save(child, dinfo, 1);
3112 kfree(devlist, M_TEMP);
3116 pci_child_detached(device_t parent __unused, device_t child)
3118 /* Turn child's power off */
3119 pci_cfg_save(child, device_get_ivars(child), 1);
3123 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3124 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3127 struct pci_devinfo *dinfo;
3128 struct msix_table_entry *mte;
3129 struct msix_vector *mv;
3136 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3137 arg, &cookie, serializer);
3141 /* If this is not a direct child, just bail out. */
3142 if (device_get_parent(child) != dev) {
3147 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3149 rid = rman_get_rid(irq);
3151 /* Make sure that INTx is enabled */
3152 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3155 * Check to see if the interrupt is MSI or MSI-X.
3156 * Ask our parent to map the MSI and give
3157 * us the address and data register values.
3158 * If we fail for some reason, teardown the
3159 * interrupt handler.
3161 dinfo = device_get_ivars(child);
3162 if (dinfo->cfg.msi.msi_alloc > 0) {
3163 if (dinfo->cfg.msi.msi_addr == 0) {
3164 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3165 ("MSI has handlers, but vectors not mapped"));
3166 error = PCIB_MAP_MSI(device_get_parent(dev),
3167 child, rman_get_start(irq), &addr, &data);
3170 dinfo->cfg.msi.msi_addr = addr;
3171 dinfo->cfg.msi.msi_data = data;
3172 pci_enable_msi(child, addr, data);
3174 dinfo->cfg.msi.msi_handlers++;
3176 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3177 ("No MSI or MSI-X interrupts allocated"));
3178 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3179 ("MSI-X index too high"));
3180 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3181 KASSERT(mte->mte_vector != 0, ("no message vector"));
3182 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3183 KASSERT(mv->mv_irq == rman_get_start(irq),
3185 if (mv->mv_address == 0) {
3186 KASSERT(mte->mte_handlers == 0,
3187 ("MSI-X table entry has handlers, but vector not mapped"));
3188 error = PCIB_MAP_MSI(device_get_parent(dev),
3189 child, rman_get_start(irq), &addr, &data);
3192 mv->mv_address = addr;
3195 if (mte->mte_handlers == 0) {
3196 pci_enable_msix(child, rid - 1, mv->mv_address,
3198 pci_unmask_msix(child, rid - 1);
3200 mte->mte_handlers++;
3203 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3204 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3207 (void)bus_generic_teardown_intr(dev, child, irq,
3218 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3222 struct msix_table_entry *mte;
3223 struct resource_list_entry *rle;
3224 struct pci_devinfo *dinfo;
3229 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3232 /* If this isn't a direct child, just bail out */
3233 if (device_get_parent(child) != dev)
3234 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3236 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3238 rid = rman_get_rid(irq);
3241 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3244 * Check to see if the interrupt is MSI or MSI-X. If so,
3245 * decrement the appropriate handlers count and mask the
3246 * MSI-X message, or disable MSI messages if the count
3249 dinfo = device_get_ivars(child);
3250 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3251 if (rle->res != irq)
3253 if (dinfo->cfg.msi.msi_alloc > 0) {
3254 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3255 ("MSI-X index too high"));
3256 if (dinfo->cfg.msi.msi_handlers == 0)
3258 dinfo->cfg.msi.msi_handlers--;
3259 if (dinfo->cfg.msi.msi_handlers == 0)
3260 pci_disable_msi(child);
3262 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3263 ("No MSI or MSI-X interrupts allocated"));
3264 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3265 ("MSI-X index too high"));
3266 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3267 if (mte->mte_handlers == 0)
3269 mte->mte_handlers--;
3270 if (mte->mte_handlers == 0)
3271 pci_mask_msix(child, rid - 1);
3274 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3277 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3279 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3284 pci_print_child(device_t dev, device_t child)
3286 struct pci_devinfo *dinfo;
3287 struct resource_list *rl;
3290 dinfo = device_get_ivars(child);
3291 rl = &dinfo->resources;
3293 retval += bus_print_child_header(dev, child);
3295 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3296 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3297 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3298 if (device_get_flags(dev))
3299 retval += kprintf(" flags %#x", device_get_flags(dev));
3301 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3302 pci_get_function(child));
3304 retval += bus_print_child_footer(dev, child);
3314 } pci_nomatch_tab[] = {
3315 {PCIC_OLD, -1, "old"},
3316 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3317 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3318 {PCIC_STORAGE, -1, "mass storage"},
3319 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3320 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3321 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3322 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3323 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3324 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3325 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3326 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3327 {PCIC_NETWORK, -1, "network"},
3328 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3329 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3330 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3331 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3332 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3333 {PCIC_DISPLAY, -1, "display"},
3334 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3335 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3336 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3337 {PCIC_MULTIMEDIA, -1, "multimedia"},
3338 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3339 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3340 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3341 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3342 {PCIC_MEMORY, -1, "memory"},
3343 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3344 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3345 {PCIC_BRIDGE, -1, "bridge"},
3346 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3347 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3348 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3349 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3350 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3351 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3352 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3353 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3354 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3355 {PCIC_SIMPLECOMM, -1, "simple comms"},
3356 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3357 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3358 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3359 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3360 {PCIC_BASEPERIPH, -1, "base peripheral"},
3361 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3362 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3363 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3364 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3365 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3366 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3367 {PCIC_INPUTDEV, -1, "input device"},
3368 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3369 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3370 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3371 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3372 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3373 {PCIC_DOCKING, -1, "docking station"},
3374 {PCIC_PROCESSOR, -1, "processor"},
3375 {PCIC_SERIALBUS, -1, "serial bus"},
3376 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3377 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3378 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3379 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3380 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3381 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3382 {PCIC_WIRELESS, -1, "wireless controller"},
3383 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3384 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3385 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3386 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3387 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3388 {PCIC_SATCOM, -1, "satellite communication"},
3389 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3390 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3391 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3392 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3393 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3394 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3395 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3396 {PCIC_DASP, -1, "dasp"},
3397 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3402 pci_probe_nomatch(device_t dev, device_t child)
3405 char *cp, *scp, *device;
3408 * Look for a listing for this device in a loaded device database.
3410 if ((device = pci_describe_device(child)) != NULL) {
3411 device_printf(dev, "<%s>", device);
3412 kfree(device, M_DEVBUF);
3415 * Scan the class/subclass descriptions for a general
3420 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3421 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3422 if (pci_nomatch_tab[i].subclass == -1) {
3423 cp = pci_nomatch_tab[i].desc;
3424 } else if (pci_nomatch_tab[i].subclass ==
3425 pci_get_subclass(child)) {
3426 scp = pci_nomatch_tab[i].desc;
3430 device_printf(dev, "<%s%s%s>",
3432 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3435 kprintf(" at device %d.%d (no driver attached)\n",
3436 pci_get_slot(child), pci_get_function(child));
3437 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3442 * Parse the PCI device database, if loaded, and return a pointer to a
3443 * description of the device.
3445 * The database is flat text formatted as follows:
3447 * Any line not in a valid format is ignored.
3448 * Lines are terminated with newline '\n' characters.
3450 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3453 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3454 * - devices cannot be listed without a corresponding VENDOR line.
3455 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3456 * another TAB, then the device name.
3460 * Assuming (ptr) points to the beginning of a line in the database,
3461 * return the vendor or device and description of the next entry.
3462 * The value of (vendor) or (device) inappropriate for the entry type
3463 * is set to -1. Returns nonzero at the end of the database.
3465 * Note that this is slightly unrobust in the face of corrupt data;
3466 * we attempt to safeguard against this by spamming the end of the
3467 * database with a newline when we initialise.
3470 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3479 left = pci_vendordata_size - (cp - pci_vendordata);
3487 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3491 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3494 /* skip to next line */
3495 while (*cp != '\n' && left > 0) {
3504 /* skip to next line */
3505 while (*cp != '\n' && left > 0) {
3509 if (*cp == '\n' && left > 0)
3516 pci_describe_device(device_t dev)
3519 char *desc, *vp, *dp, *line;
3521 desc = vp = dp = NULL;
3524 * If we have no vendor data, we can't do anything.
3526 if (pci_vendordata == NULL)
3530 * Scan the vendor data looking for this device
3532 line = pci_vendordata;
3533 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3536 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3538 if (vendor == pci_get_vendor(dev))
3541 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3544 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3552 if (device == pci_get_device(dev))
3556 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3557 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3559 ksprintf(desc, "%s, %s", vp, dp);
3562 kfree(vp, M_DEVBUF);
3564 kfree(dp, M_DEVBUF);
3569 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3571 struct pci_devinfo *dinfo;
3574 dinfo = device_get_ivars(child);
3578 case PCI_IVAR_ETHADDR:
3580 * The generic accessor doesn't deal with failure, so
3581 * we set the return value, then return an error.
3583 *((uint8_t **) result) = NULL;
3585 case PCI_IVAR_SUBVENDOR:
3586 *result = cfg->subvendor;
3588 case PCI_IVAR_SUBDEVICE:
3589 *result = cfg->subdevice;
3591 case PCI_IVAR_VENDOR:
3592 *result = cfg->vendor;
3594 case PCI_IVAR_DEVICE:
3595 *result = cfg->device;
3597 case PCI_IVAR_DEVID:
3598 *result = (cfg->device << 16) | cfg->vendor;
3600 case PCI_IVAR_CLASS:
3601 *result = cfg->baseclass;
3603 case PCI_IVAR_SUBCLASS:
3604 *result = cfg->subclass;
3606 case PCI_IVAR_PROGIF:
3607 *result = cfg->progif;
3609 case PCI_IVAR_REVID:
3610 *result = cfg->revid;
3612 case PCI_IVAR_INTPIN:
3613 *result = cfg->intpin;
3616 *result = cfg->intline;
3618 case PCI_IVAR_DOMAIN:
3619 *result = cfg->domain;
3625 *result = cfg->slot;
3627 case PCI_IVAR_FUNCTION:
3628 *result = cfg->func;
3630 case PCI_IVAR_CMDREG:
3631 *result = cfg->cmdreg;
3633 case PCI_IVAR_CACHELNSZ:
3634 *result = cfg->cachelnsz;
3636 case PCI_IVAR_MINGNT:
3637 *result = cfg->mingnt;
3639 case PCI_IVAR_MAXLAT:
3640 *result = cfg->maxlat;
3642 case PCI_IVAR_LATTIMER:
3643 *result = cfg->lattimer;
3645 case PCI_IVAR_PCIXCAP_PTR:
3646 *result = cfg->pcix.pcix_ptr;
3648 case PCI_IVAR_PCIECAP_PTR:
3649 *result = cfg->expr.expr_ptr;
3651 case PCI_IVAR_VPDCAP_PTR:
3652 *result = cfg->vpd.vpd_reg;
3661 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3663 struct pci_devinfo *dinfo;
3665 dinfo = device_get_ivars(child);
3668 case PCI_IVAR_INTPIN:
3669 dinfo->cfg.intpin = value;
3671 case PCI_IVAR_ETHADDR:
3672 case PCI_IVAR_SUBVENDOR:
3673 case PCI_IVAR_SUBDEVICE:
3674 case PCI_IVAR_VENDOR:
3675 case PCI_IVAR_DEVICE:
3676 case PCI_IVAR_DEVID:
3677 case PCI_IVAR_CLASS:
3678 case PCI_IVAR_SUBCLASS:
3679 case PCI_IVAR_PROGIF:
3680 case PCI_IVAR_REVID:
3682 case PCI_IVAR_DOMAIN:
3685 case PCI_IVAR_FUNCTION:
3686 return (EINVAL); /* disallow for now */
3693 #include "opt_ddb.h"
3695 #include <ddb/ddb.h>
3696 #include <sys/cons.h>
3699 * List resources based on pci map registers, used for within ddb
3702 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3704 struct pci_devinfo *dinfo;
3705 struct devlist *devlist_head;
3708 int i, error, none_count;
3711 /* get the head of the device queue */
3712 devlist_head = &pci_devq;
3715 * Go through the list of devices and print out devices
3717 for (error = 0, i = 0,
3718 dinfo = STAILQ_FIRST(devlist_head);
3719 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3720 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3722 /* Populate pd_name and pd_unit */
3725 name = device_get_name(dinfo->cfg.dev);
3728 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3729 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3730 (name && *name) ? name : "none",
3731 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3733 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3734 p->pc_sel.pc_func, (p->pc_class << 16) |
3735 (p->pc_subclass << 8) | p->pc_progif,
3736 (p->pc_subdevice << 16) | p->pc_subvendor,
3737 (p->pc_device << 16) | p->pc_vendor,
3738 p->pc_revid, p->pc_hdr);
3744 static struct resource *
3745 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3746 u_long start, u_long end, u_long count, u_int flags)
3748 struct pci_devinfo *dinfo = device_get_ivars(child);
3749 struct resource_list *rl = &dinfo->resources;
3750 struct resource_list_entry *rle;
3751 struct resource *res;
3752 pci_addr_t map, testval;
3756 * Weed out the bogons, and figure out how large the BAR/map
3757 * is. Bars that read back 0 here are bogus and unimplemented.
3758 * Note: atapci in legacy mode are special and handled elsewhere
3759 * in the code. If you have a atapci device in legacy mode and
3760 * it fails here, that other code is broken.
3763 map = pci_read_config(child, *rid, 4);
3764 pci_write_config(child, *rid, 0xffffffff, 4);
3765 testval = pci_read_config(child, *rid, 4);
3766 if (pci_maprange(testval) == 64)
3767 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3768 if (pci_mapbase(testval) == 0)
3772 * Restore the original value of the BAR. We may have reprogrammed
3773 * the BAR of the low-level console device and when booting verbose,
3774 * we need the console device addressable.
3776 pci_write_config(child, *rid, map, 4);
3778 if (PCI_BAR_MEM(testval)) {
3779 if (type != SYS_RES_MEMORY) {
3782 "child %s requested type %d for rid %#x,"
3783 " but the BAR says it is an memio\n",
3784 device_get_nameunit(child), type, *rid);
3788 if (type != SYS_RES_IOPORT) {
3791 "child %s requested type %d for rid %#x,"
3792 " but the BAR says it is an ioport\n",
3793 device_get_nameunit(child), type, *rid);
3798 * For real BARs, we need to override the size that
3799 * the driver requests, because that's what the BAR
3800 * actually uses and we would otherwise have a
3801 * situation where we might allocate the excess to
3802 * another driver, which won't work.
3804 mapsize = pci_mapsize(testval);
3805 count = 1UL << mapsize;
3806 if (RF_ALIGNMENT(flags) < mapsize)
3807 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3808 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3809 flags |= RF_PREFETCHABLE;
3812 * Allocate enough resource, and then write back the
3813 * appropriate bar for that resource.
3815 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3816 start, end, count, flags);
3818 device_printf(child,
3819 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3820 count, *rid, type, start, end);
3823 resource_list_add(rl, type, *rid, start, end, count);
3824 rle = resource_list_find(rl, type, *rid);
3826 panic("pci_alloc_map: unexpectedly can't find resource.");
3828 rle->start = rman_get_start(res);
3829 rle->end = rman_get_end(res);
3832 device_printf(child,
3833 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3834 count, *rid, type, rman_get_start(res));
3835 map = rman_get_start(res);
3837 pci_write_config(child, *rid, map, 4);
3838 if (pci_maprange(testval) == 64)
3839 pci_write_config(child, *rid + 4, map >> 32, 4);
3845 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3846 u_long start, u_long end, u_long count, u_int flags)
3848 struct pci_devinfo *dinfo = device_get_ivars(child);
3849 struct resource_list *rl = &dinfo->resources;
3850 struct resource_list_entry *rle;
3851 pcicfgregs *cfg = &dinfo->cfg;
3854 * Perform lazy resource allocation
3856 if (device_get_parent(child) == dev) {
3860 * Can't alloc legacy interrupt once MSI messages
3861 * have been allocated.
3864 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3865 cfg->msix.msix_alloc > 0))
3869 * If the child device doesn't have an
3870 * interrupt routed and is deserving of an
3871 * interrupt, try to assign it one.
3873 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3875 pci_assign_interrupt(dev, child, 0);
3877 case SYS_RES_IOPORT:
3878 case SYS_RES_MEMORY:
3879 if (*rid < PCIR_BAR(cfg->nummaps)) {
3881 * Enable the I/O mode. We should
3882 * also be assigning resources too
3883 * when none are present. The
3884 * resource_list_alloc kind of sorta does
3887 if (PCI_ENABLE_IO(dev, child, type))
3890 rle = resource_list_find(rl, type, *rid);
3892 return (pci_alloc_map(dev, child, type, rid,
3893 start, end, count, flags));
3897 * If we've already allocated the resource, then
3898 * return it now. But first we may need to activate
3899 * it, since we don't allocate the resource as active
3900 * above. Normally this would be done down in the
3901 * nexus, but since we short-circuit that path we have
3902 * to do its job here. Not sure if we should kfree the
3903 * resource if it fails to activate.
3905 rle = resource_list_find(rl, type, *rid);
3906 if (rle != NULL && rle->res != NULL) {
3908 device_printf(child,
3909 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3910 rman_get_size(rle->res), *rid, type,
3911 rman_get_start(rle->res));
3912 if ((flags & RF_ACTIVE) &&
3913 bus_generic_activate_resource(dev, child, type,
3914 *rid, rle->res) != 0)
3919 return (resource_list_alloc(rl, dev, child, type, rid,
3920 start, end, count, flags));
3924 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3926 struct pci_devinfo *dinfo;
3927 struct resource_list *rl;
3928 struct resource_list_entry *rle;
3930 if (device_get_parent(child) != dev)
3933 dinfo = device_get_ivars(child);
3934 rl = &dinfo->resources;
3935 rle = resource_list_find(rl, type, rid);
3938 if (rman_get_device(rle->res) != dev ||
3939 rman_get_flags(rle->res) & RF_ACTIVE) {
3940 device_printf(dev, "delete_resource: "
3941 "Resource still owned by child, oops. "
3942 "(type=%d, rid=%d, addr=%lx)\n",
3943 rle->type, rle->rid,
3944 rman_get_start(rle->res));
3947 bus_release_resource(dev, type, rid, rle->res);
3949 resource_list_delete(rl, type, rid);
3952 * Why do we turn off the PCI configuration BAR when we delete a
3955 pci_write_config(child, rid, 0, 4);
3956 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3959 struct resource_list *
3960 pci_get_resource_list (device_t dev, device_t child)
3962 struct pci_devinfo *dinfo = device_get_ivars(child);
3967 return (&dinfo->resources);
3971 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3973 struct pci_devinfo *dinfo = device_get_ivars(child);
3974 pcicfgregs *cfg = &dinfo->cfg;
3976 return (PCIB_READ_CONFIG(device_get_parent(dev),
3977 cfg->bus, cfg->slot, cfg->func, reg, width));
3981 pci_write_config_method(device_t dev, device_t child, int reg,
3982 uint32_t val, int width)
3984 struct pci_devinfo *dinfo = device_get_ivars(child);
3985 pcicfgregs *cfg = &dinfo->cfg;
3987 PCIB_WRITE_CONFIG(device_get_parent(dev),
3988 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3992 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3996 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3997 pci_get_function(child));
4002 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4005 struct pci_devinfo *dinfo;
4008 dinfo = device_get_ivars(child);
4010 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4011 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4012 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4018 pci_assign_interrupt_method(device_t dev, device_t child)
4020 struct pci_devinfo *dinfo = device_get_ivars(child);
4021 pcicfgregs *cfg = &dinfo->cfg;
4023 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4028 pci_modevent(module_t mod, int what, void *arg)
4030 static struct cdev *pci_cdev;
4034 STAILQ_INIT(&pci_devq);
4036 dev_ops_add(&pcic_ops, -1, 0);
4037 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
4039 pci_load_vendor_data();
4043 destroy_dev(pci_cdev);
4051 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4056 * Only do header type 0 devices. Type 1 devices are bridges,
4057 * which we know need special treatment. Type 2 devices are
4058 * cardbus bridges which also require special treatment.
4059 * Other types are unknown, and we err on the side of safety
4062 if (dinfo->cfg.hdrtype != 0)
4066 * Restore the device to full power mode. We must do this
4067 * before we restore the registers because moving from D3 to
4068 * D0 will cause the chip's BARs and some other registers to
4069 * be reset to some unknown power on reset values. Cut down
4070 * the noise on boot by doing nothing if we are already in
4073 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4074 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4076 for (i = 0; i < dinfo->cfg.nummaps; i++)
4077 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4078 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4079 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4080 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4081 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4082 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4083 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4084 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4085 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4086 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4087 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4089 /* Restore MSI and MSI-X configurations if they are present. */
4090 if (dinfo->cfg.msi.msi_location != 0)
4091 pci_resume_msi(dev);
4092 if (dinfo->cfg.msix.msix_location != 0)
4093 pci_resume_msix(dev);
4097 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4104 * Only do header type 0 devices. Type 1 devices are bridges, which
4105 * we know need special treatment. Type 2 devices are cardbus bridges
4106 * which also require special treatment. Other types are unknown, and
4107 * we err on the side of safety by ignoring them. Powering down
4108 * bridges should not be undertaken lightly.
4110 if (dinfo->cfg.hdrtype != 0)
4112 for (i = 0; i < dinfo->cfg.nummaps; i++)
4113 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4114 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4117 * Some drivers apparently write to these registers w/o updating our
4118 * cached copy. No harm happens if we update the copy, so do so here
4119 * so we can restore them. The COMMAND register is modified by the
4120 * bus w/o updating the cache. This should represent the normally
4121 * writable portion of the 'defined' part of type 0 headers. In
4122 * theory we also need to save/restore the PCI capability structures
4123 * we know about, but apart from power we don't know any that are
4126 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4127 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4128 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4129 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4130 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4131 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4132 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4133 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4134 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4135 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4136 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4137 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4138 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4139 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4140 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4143 * don't set the state for display devices, base peripherals and
4144 * memory devices since bad things happen when they are powered down.
4145 * We should (a) have drivers that can easily detach and (b) use
4146 * generic drivers for these devices so that some device actually
4147 * attaches. We need to make sure that when we implement (a) we don't
4148 * power the device down on a reattach.
4150 cls = pci_get_class(dev);
4153 switch (pci_do_power_nodriver)
4155 case 0: /* NO powerdown at all */
4157 case 1: /* Conservative about what to power down */
4158 if (cls == PCIC_STORAGE)
4161 case 2: /* Agressive about what to power down */
4162 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4163 cls == PCIC_BASEPERIPH)
4166 case 3: /* Power down everything */
4170 * PCI spec says we can only go into D3 state from D0 state.
4171 * Transition from D[12] into D0 before going to D3 state.
4173 ps = pci_get_powerstate(dev);
4174 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4175 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4176 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4177 pci_set_powerstate(dev, PCI_POWERSTATE_D3);