2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
40 #define RQ_BUG_ON(expr)
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
52 return HAS_LLC(dev) || level != I915_CACHE_NONE;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
57 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
60 return obj->pin_display;
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
67 spin_lock(&dev_priv->mm.object_stat_lock);
68 dev_priv->mm.object_count++;
69 dev_priv->mm.object_memory += size;
70 spin_unlock(&dev_priv->mm.object_stat_lock);
73 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
76 spin_lock(&dev_priv->mm.object_stat_lock);
77 dev_priv->mm.object_count--;
78 dev_priv->mm.object_memory -= size;
79 spin_unlock(&dev_priv->mm.object_stat_lock);
83 i915_gem_wait_for_error(struct i915_gpu_error *error)
87 #define EXIT_COND (!i915_reset_in_progress(error) || \
88 i915_terminally_wedged(error))
93 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
94 * userspace. If it takes that long something really bad is going on and
95 * we should simply try to bail out and fail as gracefully as possible.
97 ret = wait_event_interruptible_timeout(error->reset_queue,
101 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
103 } else if (ret < 0) {
111 int i915_mutex_lock_interruptible(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
116 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
120 ret = mutex_lock_interruptible(&dev->struct_mutex);
124 WARN_ON(i915_verify_lists(dev));
129 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
130 struct drm_file *file)
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct drm_i915_gem_get_aperture *args = data;
134 struct i915_gtt *ggtt = &dev_priv->gtt;
135 struct i915_vma *vma;
139 mutex_lock(&dev->struct_mutex);
140 list_for_each_entry(vma, &ggtt->base.active_list, mm_list)
142 pinned += vma->node.size;
143 list_for_each_entry(vma, &ggtt->base.inactive_list, mm_list)
145 pinned += vma->node.size;
146 mutex_unlock(&dev->struct_mutex);
148 args->aper_size = dev_priv->gtt.base.total;
149 args->aper_available_size = args->aper_size - pinned;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
158 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
159 char *vaddr = obj->phys_handle->vaddr;
161 struct scatterlist *sg;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
167 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
171 page = shmem_read_mapping_page(mapping, i);
173 return PTR_ERR(page);
175 src = kmap_atomic(page);
176 memcpy(vaddr, src, PAGE_SIZE);
177 drm_clflush_virt_range(vaddr, PAGE_SIZE);
180 page_cache_release(page);
184 i915_gem_chipset_flush(obj->base.dev);
186 st = kmalloc(sizeof(*st), GFP_KERNEL);
190 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
197 sg->length = obj->base.size;
199 sg_dma_address(sg) = obj->phys_handle->busaddr;
200 sg_dma_len(sg) = obj->base.size;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
211 BUG_ON(obj->madv == __I915_MADV_PURGED);
213 ret = i915_gem_object_set_to_cpu_domain(obj, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret != -EIO);
219 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
222 if (obj->madv == I915_MADV_DONTNEED)
226 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
227 char *vaddr = obj->phys_handle->vaddr;
230 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
234 page = shmem_read_mapping_page(mapping, i);
238 dst = kmap_atomic(page);
239 drm_clflush_virt_range(vaddr, PAGE_SIZE);
240 memcpy(dst, vaddr, PAGE_SIZE);
243 set_page_dirty(page);
244 if (obj->madv == I915_MADV_WILLNEED)
245 mark_page_accessed(page);
246 page_cache_release(page);
252 sg_free_table(obj->pages);
257 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
259 drm_pci_free(obj->base.dev, obj->phys_handle);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
263 .get_pages = i915_gem_object_get_pages_phys,
264 .put_pages = i915_gem_object_put_pages_phys,
265 .release = i915_gem_object_release_phys,
270 drop_pages(struct drm_i915_gem_object *obj)
272 struct i915_vma *vma, *next;
275 drm_gem_object_reference(&obj->base);
276 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
277 if (i915_vma_unbind(vma))
280 ret = i915_gem_object_put_pages(obj);
281 drm_gem_object_unreference(&obj->base);
287 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
290 drm_dma_handle_t *phys;
293 if (obj->phys_handle) {
294 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
300 if (obj->madv != I915_MADV_WILLNEED)
304 if (obj->base.filp == NULL)
308 ret = drop_pages(obj);
312 /* create a new object */
313 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
317 obj->phys_handle = phys;
319 obj->ops = &i915_gem_phys_ops;
322 return i915_gem_object_get_pages(obj);
326 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
327 struct drm_i915_gem_pwrite *args,
328 struct drm_file *file_priv)
330 struct drm_device *dev = obj->base.dev;
331 void *vaddr = (char *)obj->phys_handle->vaddr + args->offset;
332 char __user *user_data = to_user_ptr(args->data_ptr);
335 /* We manually control the domain here and pretend that it
336 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
338 ret = i915_gem_object_wait_rendering(obj, false);
342 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
343 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
344 unsigned long unwritten;
346 /* The physical object once assigned is fixed for the lifetime
347 * of the obj, so we can safely drop the lock and continue
350 mutex_unlock(&dev->struct_mutex);
351 unwritten = copy_from_user(vaddr, user_data, args->size);
352 mutex_lock(&dev->struct_mutex);
359 drm_clflush_virt_range(vaddr, args->size);
360 i915_gem_chipset_flush(dev);
363 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
367 void *i915_gem_object_alloc(struct drm_device *dev)
369 return kmalloc(sizeof(struct drm_i915_gem_object),
370 M_DRM, M_WAITOK | M_ZERO);
373 void i915_gem_object_free(struct drm_i915_gem_object *obj)
379 i915_gem_create(struct drm_file *file,
380 struct drm_device *dev,
384 struct drm_i915_gem_object *obj;
388 size = roundup(size, PAGE_SIZE);
392 /* Allocate the new object */
393 obj = i915_gem_alloc_object(dev, size);
397 ret = drm_gem_handle_create(file, &obj->base, &handle);
398 /* drop reference from allocate - handle holds it now */
399 drm_gem_object_unreference_unlocked(&obj->base);
408 i915_gem_dumb_create(struct drm_file *file,
409 struct drm_device *dev,
410 struct drm_mode_create_dumb *args)
412 /* have to work out size/pitch and return them */
413 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
414 args->size = args->pitch * args->height;
415 return i915_gem_create(file, dev,
416 args->size, &args->handle);
420 * Creates a new mm object and returns a handle to it.
423 i915_gem_create_ioctl(struct drm_device *dev, void *data,
424 struct drm_file *file)
426 struct drm_i915_gem_create *args = data;
428 return i915_gem_create(file, dev,
429 args->size, &args->handle);
433 __copy_to_user_swizzled(char __user *cpu_vaddr,
434 const char *gpu_vaddr, int gpu_offset,
437 int ret, cpu_offset = 0;
440 int cacheline_end = ALIGN(gpu_offset + 1, 64);
441 int this_length = min(cacheline_end - gpu_offset, length);
442 int swizzled_gpu_offset = gpu_offset ^ 64;
444 ret = __copy_to_user(cpu_vaddr + cpu_offset,
445 gpu_vaddr + swizzled_gpu_offset,
450 cpu_offset += this_length;
451 gpu_offset += this_length;
452 length -= this_length;
459 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
460 const char __user *cpu_vaddr,
463 int ret, cpu_offset = 0;
466 int cacheline_end = ALIGN(gpu_offset + 1, 64);
467 int this_length = min(cacheline_end - gpu_offset, length);
468 int swizzled_gpu_offset = gpu_offset ^ 64;
470 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
471 cpu_vaddr + cpu_offset,
476 cpu_offset += this_length;
477 gpu_offset += this_length;
478 length -= this_length;
485 * Pins the specified object's pages and synchronizes the object with
486 * GPU accesses. Sets needs_clflush to non-zero if the caller should
487 * flush the object from the CPU cache.
489 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
501 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
502 /* If we're not in the cpu read domain, set ourself into the gtt
503 * read domain and manually flush cachelines (if required). This
504 * optimizes for the case when the gpu will dirty the data
505 * anyway again before the next pread happens. */
506 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
508 ret = i915_gem_object_wait_rendering(obj, true);
513 ret = i915_gem_object_get_pages(obj);
517 i915_gem_object_pin_pages(obj);
522 /* Per-page copy function for the shmem pread fastpath.
523 * Flushes invalid cachelines before reading the target if
524 * needs_clflush is set. */
526 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
527 char __user *user_data,
528 bool page_do_bit17_swizzling, bool needs_clflush)
533 if (unlikely(page_do_bit17_swizzling))
536 vaddr = kmap_atomic(page);
538 drm_clflush_virt_range(vaddr + shmem_page_offset,
540 ret = __copy_to_user_inatomic(user_data,
541 vaddr + shmem_page_offset,
543 kunmap_atomic(vaddr);
545 return ret ? -EFAULT : 0;
549 shmem_clflush_swizzled_range(char *addr, unsigned long length,
552 if (unlikely(swizzled)) {
553 unsigned long start = (unsigned long) addr;
554 unsigned long end = (unsigned long) addr + length;
556 /* For swizzling simply ensure that we always flush both
557 * channels. Lame, but simple and it works. Swizzled
558 * pwrite/pread is far from a hotpath - current userspace
559 * doesn't use it at all. */
560 start = round_down(start, 128);
561 end = round_up(end, 128);
563 drm_clflush_virt_range((void *)start, end - start);
565 drm_clflush_virt_range(addr, length);
570 /* Only difference to the fast-path function is that this can handle bit17
571 * and uses non-atomic copy and kmap functions. */
573 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
574 char __user *user_data,
575 bool page_do_bit17_swizzling, bool needs_clflush)
582 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
584 page_do_bit17_swizzling);
586 if (page_do_bit17_swizzling)
587 ret = __copy_to_user_swizzled(user_data,
588 vaddr, shmem_page_offset,
591 ret = __copy_to_user(user_data,
592 vaddr + shmem_page_offset,
596 return ret ? - EFAULT : 0;
600 i915_gem_shmem_pread(struct drm_device *dev,
601 struct drm_i915_gem_object *obj,
602 struct drm_i915_gem_pread *args,
603 struct drm_file *file)
605 char __user *user_data;
608 int shmem_page_offset, page_length, ret = 0;
609 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
611 int needs_clflush = 0;
612 struct sg_page_iter sg_iter;
614 user_data = to_user_ptr(args->data_ptr);
617 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
619 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
623 offset = args->offset;
625 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
626 offset >> PAGE_SHIFT) {
627 struct vm_page *page = sg_page_iter_page(&sg_iter);
632 /* Operation in this page
634 * shmem_page_offset = offset within page in shmem file
635 * page_length = bytes to copy for this page
637 shmem_page_offset = offset_in_page(offset);
638 page_length = remain;
639 if ((shmem_page_offset + page_length) > PAGE_SIZE)
640 page_length = PAGE_SIZE - shmem_page_offset;
642 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
643 (page_to_phys(page) & (1 << 17)) != 0;
645 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
646 user_data, page_do_bit17_swizzling,
651 mutex_unlock(&dev->struct_mutex);
653 if (likely(!i915.prefault_disable) && !prefaulted) {
654 ret = fault_in_multipages_writeable(user_data, remain);
655 /* Userspace is tricking us, but we've already clobbered
656 * its pages with the prefault and promised to write the
657 * data up to the first fault. Hence ignore any errors
658 * and just continue. */
663 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
664 user_data, page_do_bit17_swizzling,
667 mutex_lock(&dev->struct_mutex);
673 remain -= page_length;
674 user_data += page_length;
675 offset += page_length;
679 i915_gem_object_unpin_pages(obj);
685 * Reads data from the object referenced by handle.
687 * On error, the contents of *data are undefined.
690 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
691 struct drm_file *file)
693 struct drm_i915_gem_pread *args = data;
694 struct drm_i915_gem_object *obj;
700 ret = i915_mutex_lock_interruptible(dev);
704 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
705 if (&obj->base == NULL) {
710 /* Bounds check source. */
711 if (args->offset > obj->base.size ||
712 args->size > obj->base.size - args->offset) {
717 /* prime objects have no backing filp to GEM pread/pwrite
721 trace_i915_gem_object_pread(obj, args->offset, args->size);
723 ret = i915_gem_shmem_pread(dev, obj, args, file);
726 drm_gem_object_unreference(&obj->base);
728 mutex_unlock(&dev->struct_mutex);
732 /* This is the fast write path which cannot handle
733 * page faults in the source data
737 fast_user_write(struct io_mapping *mapping,
738 loff_t page_base, int page_offset,
739 char __user *user_data,
742 void __iomem *vaddr_atomic;
744 unsigned long unwritten;
746 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
747 /* We can use the cpu mem copy function because this is X86. */
748 vaddr = (char __force*)vaddr_atomic + page_offset;
749 unwritten = __copy_from_user_inatomic_nocache(vaddr,
751 io_mapping_unmap_atomic(vaddr_atomic);
756 * This is the fast pwrite path, where we copy the data directly from the
757 * user into the GTT, uncached.
760 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
761 struct drm_i915_gem_object *obj,
762 struct drm_i915_gem_pwrite *args,
763 struct drm_file *file)
765 struct drm_i915_private *dev_priv = dev->dev_private;
767 loff_t offset, page_base;
768 char __user *user_data;
769 int page_offset, page_length, ret;
771 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
775 ret = i915_gem_object_set_to_gtt_domain(obj, true);
779 ret = i915_gem_object_put_fence(obj);
783 user_data = to_user_ptr(args->data_ptr);
786 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
788 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
791 /* Operation in this page
793 * page_base = page offset within aperture
794 * page_offset = offset within page
795 * page_length = bytes to copy for this page
797 page_base = offset & ~PAGE_MASK;
798 page_offset = offset_in_page(offset);
799 page_length = remain;
800 if ((page_offset + remain) > PAGE_SIZE)
801 page_length = PAGE_SIZE - page_offset;
803 /* If we get a fault while copying data, then (presumably) our
804 * source page isn't available. Return the error and we'll
805 * retry in the slow path.
807 if (fast_user_write(dev_priv->gtt.mappable, page_base,
808 page_offset, user_data, page_length)) {
813 remain -= page_length;
814 user_data += page_length;
815 offset += page_length;
819 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
821 i915_gem_object_ggtt_unpin(obj);
826 /* Per-page copy function for the shmem pwrite fastpath.
827 * Flushes invalid cachelines before writing to the target if
828 * needs_clflush_before is set and flushes out any written cachelines after
829 * writing if needs_clflush is set. */
831 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
832 char __user *user_data,
833 bool page_do_bit17_swizzling,
834 bool needs_clflush_before,
835 bool needs_clflush_after)
840 if (unlikely(page_do_bit17_swizzling))
843 vaddr = kmap_atomic(page);
844 if (needs_clflush_before)
845 drm_clflush_virt_range(vaddr + shmem_page_offset,
847 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
848 user_data, page_length);
849 if (needs_clflush_after)
850 drm_clflush_virt_range(vaddr + shmem_page_offset,
852 kunmap_atomic(vaddr);
854 return ret ? -EFAULT : 0;
857 /* Only difference to the fast-path function is that this can handle bit17
858 * and uses non-atomic copy and kmap functions. */
860 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
861 char __user *user_data,
862 bool page_do_bit17_swizzling,
863 bool needs_clflush_before,
864 bool needs_clflush_after)
870 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
871 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
873 page_do_bit17_swizzling);
874 if (page_do_bit17_swizzling)
875 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
879 ret = __copy_from_user(vaddr + shmem_page_offset,
882 if (needs_clflush_after)
883 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
885 page_do_bit17_swizzling);
888 return ret ? -EFAULT : 0;
892 i915_gem_shmem_pwrite(struct drm_device *dev,
893 struct drm_i915_gem_object *obj,
894 struct drm_i915_gem_pwrite *args,
895 struct drm_file *file)
899 char __user *user_data;
900 int shmem_page_offset, page_length, ret = 0;
901 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
902 int hit_slowpath = 0;
903 int needs_clflush_after = 0;
904 int needs_clflush_before = 0;
905 struct sg_page_iter sg_iter;
907 user_data = to_user_ptr(args->data_ptr);
910 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
912 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
913 /* If we're not in the cpu write domain, set ourself into the gtt
914 * write domain and manually flush cachelines (if required). This
915 * optimizes for the case when the gpu will use the data
916 * right away and we therefore have to clflush anyway. */
917 needs_clflush_after = cpu_write_needs_clflush(obj);
918 ret = i915_gem_object_wait_rendering(obj, false);
922 /* Same trick applies to invalidate partially written cachelines read
924 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
925 needs_clflush_before =
926 !cpu_cache_is_coherent(dev, obj->cache_level);
928 ret = i915_gem_object_get_pages(obj);
932 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
934 i915_gem_object_pin_pages(obj);
936 offset = args->offset;
939 VM_OBJECT_LOCK(obj->base.vm_obj);
940 vm_object_pip_add(obj->base.vm_obj, 1);
942 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
943 offset >> PAGE_SHIFT) {
944 struct vm_page *page = sg_page_iter_page(&sg_iter);
945 int partial_cacheline_write;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset = offset_in_page(offset);
957 page_length = remain;
958 if ((shmem_page_offset + page_length) > PAGE_SIZE)
959 page_length = PAGE_SIZE - shmem_page_offset;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write = needs_clflush_before &&
965 ((shmem_page_offset | page_length)
966 & (cpu_clflush_line_size - 1));
968 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
969 (page_to_phys(page) & (1 << 17)) != 0;
971 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
972 user_data, page_do_bit17_swizzling,
973 partial_cacheline_write,
974 needs_clflush_after);
979 mutex_unlock(&dev->struct_mutex);
980 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
981 user_data, page_do_bit17_swizzling,
982 partial_cacheline_write,
983 needs_clflush_after);
985 mutex_lock(&dev->struct_mutex);
991 remain -= page_length;
992 user_data += page_length;
993 offset += page_length;
995 vm_object_pip_wakeup(obj->base.vm_obj);
996 VM_OBJECT_UNLOCK(obj->base.vm_obj);
999 i915_gem_object_unpin_pages(obj);
1003 * Fixup: Flush cpu caches in case we didn't flush the dirty
1004 * cachelines in-line while writing and the object moved
1005 * out of the cpu write domain while we've dropped the lock.
1007 if (!needs_clflush_after &&
1008 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1009 if (i915_gem_clflush_object(obj, obj->pin_display))
1010 needs_clflush_after = true;
1014 if (needs_clflush_after)
1015 i915_gem_chipset_flush(dev);
1017 obj->cache_dirty = true;
1019 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1024 * Writes data to the object referenced by handle.
1026 * On error, the contents of the buffer that were to be modified are undefined.
1029 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1030 struct drm_file *file)
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 struct drm_i915_gem_pwrite *args = data;
1034 struct drm_i915_gem_object *obj;
1037 if (args->size == 0)
1040 if (likely(!i915.prefault_disable)) {
1041 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1047 intel_runtime_pm_get(dev_priv);
1049 ret = i915_mutex_lock_interruptible(dev);
1053 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1054 if (&obj->base == NULL) {
1059 /* Bounds check destination. */
1060 if (args->offset > obj->base.size ||
1061 args->size > obj->base.size - args->offset) {
1066 /* prime objects have no backing filp to GEM pread/pwrite
1070 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1073 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1074 * it would end up going through the fenced access, and we'll get
1075 * different detiling behavior between reading and writing.
1076 * pread/pwrite currently are reading and writing from the CPU
1077 * perspective, requiring manual detiling by the client.
1079 if (obj->tiling_mode == I915_TILING_NONE &&
1080 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1081 cpu_write_needs_clflush(obj)) {
1082 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1083 /* Note that the gtt paths might fail with non-page-backed user
1084 * pointers (e.g. gtt mappings when moving data between
1085 * textures). Fallback to the shmem path in that case. */
1088 if (ret == -EFAULT || ret == -ENOSPC) {
1089 if (obj->phys_handle)
1090 ret = i915_gem_phys_pwrite(obj, args, file);
1092 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1096 drm_gem_object_unreference(&obj->base);
1098 mutex_unlock(&dev->struct_mutex);
1100 intel_runtime_pm_put(dev_priv);
1106 i915_gem_check_wedge(struct i915_gpu_error *error,
1109 if (i915_reset_in_progress(error)) {
1110 /* Non-interruptible callers can't handle -EAGAIN, hence return
1111 * -EIO unconditionally for these. */
1115 /* Recovery complete, but the reset failed ... */
1116 if (i915_terminally_wedged(error))
1120 * Check if GPU Reset is in progress - we need intel_ring_begin
1121 * to work properly to reinit the hw state while the gpu is
1122 * still marked as reset-in-progress. Handle this with a flag.
1124 if (!error->reload_in_reset)
1131 static void fake_irq(unsigned long data)
1133 wakeup_one((void *)data);
1136 static bool missed_irq(struct drm_i915_private *dev_priv,
1137 struct intel_engine_cs *ring)
1139 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1143 static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
1145 unsigned long timeout;
1148 /* When waiting for high frequency requests, e.g. during synchronous
1149 * rendering split between the CPU and GPU, the finite amount of time
1150 * required to set up the irq and wait upon it limits the response
1151 * rate. By busywaiting on the request completion for a short while we
1152 * can service the high frequency waits as quick as possible. However,
1153 * if it is a slow request, we want to sleep as quickly as possible.
1154 * The tradeoff between waiting and sleeping is roughly the time it
1155 * takes to sleep on a request, on the order of a microsecond.
1158 if (req->ring->irq_refcount)
1161 /* Only spin if we know the GPU is processing this request */
1162 if (!i915_gem_request_started(req, true))
1165 timeout = local_clock_us(&cpu) + 5;
1166 while (!need_resched()) {
1167 if (i915_gem_request_completed(req, true))
1170 if (signal_pending_state(state, current))
1173 if (busywait_stop(timeout, cpu))
1176 cpu_relax_lowlatency();
1179 if (i915_gem_request_completed(req, false))
1187 * __i915_wait_request - wait until execution of request has finished
1189 * @reset_counter: reset sequence associated with the given request
1190 * @interruptible: do an interruptible wait (normally yes)
1191 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1193 * Note: It is of utmost importance that the passed in seqno and reset_counter
1194 * values have been read by the caller in an smp safe manner. Where read-side
1195 * locks are involved, it is sufficient to read the reset_counter before
1196 * unlocking the lock that protects the seqno. For lockless tricks, the
1197 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1200 * Returns 0 if the request was found within the alloted time. Else returns the
1201 * errno with remaining time filled in timeout argument.
1203 int __i915_wait_request(struct drm_i915_gem_request *req,
1204 unsigned reset_counter,
1207 struct intel_rps_client *rps)
1209 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1210 struct drm_device *dev = ring->dev;
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 const bool irq_test_in_progress =
1213 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1214 unsigned long timeout_expire;
1216 int ret, sl_timeout = 1;
1218 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1220 if (list_empty(&req->list))
1223 if (i915_gem_request_completed(req, true))
1228 if (WARN_ON(*timeout < 0))
1234 timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
1237 if (INTEL_INFO(dev_priv)->gen >= 6)
1238 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1240 /* Record current time in case interrupted by signal, or wedged */
1241 trace_i915_gem_request_wait_begin(req);
1242 before = ktime_get_raw_ns();
1244 /* Optimistic spin for the next jiffie before touching IRQs */
1246 ret = __i915_spin_request(req);
1251 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1256 lockmgr(&ring->irq_queue.lock, LK_EXCLUSIVE);
1258 struct timer_list timer;
1260 /* We need to check whether any gpu reset happened in between
1261 * the caller grabbing the seqno and now ... */
1262 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1263 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1264 * is truely gone. */
1265 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1271 if (i915_gem_request_completed(req, false)) {
1276 if (interruptible && signal_pending(curthread->td_lwp)) {
1281 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1286 timer.function = NULL;
1287 if (timeout || missed_irq(dev_priv, ring)) {
1288 unsigned long expire;
1290 setup_timer_on_stack(&timer, fake_irq, (unsigned long)&ring->irq_queue);
1291 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1292 sl_timeout = expire - jiffies;
1295 mod_timer(&timer, expire);
1302 if (timer.function) {
1303 del_singleshot_timer_sync(&timer);
1304 destroy_timer_on_stack(&timer);
1307 lksleep(&ring->irq_queue, &ring->irq_queue.lock,
1308 interruptible ? PCATCH : 0, "lwe", sl_timeout);
1310 lockmgr(&ring->irq_queue.lock, LK_RELEASE);
1311 if (!irq_test_in_progress)
1312 ring->irq_put(ring);
1315 now = ktime_get_raw_ns();
1316 trace_i915_gem_request_wait_end(req);
1319 s64 tres = *timeout - (now - before);
1321 *timeout = tres < 0 ? 0 : tres;
1324 * Apparently ktime isn't accurate enough and occasionally has a
1325 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1326 * things up to make the test happy. We allow up to 1 jiffy.
1328 * This is a regrssion from the timespec->ktime conversion.
1330 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1337 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1338 struct drm_file *file)
1340 struct drm_i915_private *dev_private;
1341 struct drm_i915_file_private *file_priv;
1343 WARN_ON(!req || !file || req->file_priv);
1351 dev_private = req->ring->dev->dev_private;
1352 file_priv = file->driver_priv;
1354 spin_lock(&file_priv->mm.lock);
1355 req->file_priv = file_priv;
1356 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1357 spin_unlock(&file_priv->mm.lock);
1359 req->pid = curproc->p_pid;
1365 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1367 struct drm_i915_file_private *file_priv = request->file_priv;
1372 spin_lock(&file_priv->mm.lock);
1373 list_del(&request->client_list);
1374 request->file_priv = NULL;
1375 spin_unlock(&file_priv->mm.lock);
1378 put_pid(request->pid);
1379 request->pid = NULL;
1383 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1385 trace_i915_gem_request_retire(request);
1387 /* We know the GPU must have read the request to have
1388 * sent us the seqno + interrupt, so use the position
1389 * of tail of the request to update the last known position
1392 * Note this requires that we are always called in request
1395 request->ringbuf->last_retired_head = request->postfix;
1397 list_del_init(&request->list);
1398 i915_gem_request_remove_from_client(request);
1400 i915_gem_request_unreference(request);
1404 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1406 struct intel_engine_cs *engine = req->ring;
1407 struct drm_i915_gem_request *tmp;
1409 lockdep_assert_held(&engine->dev->struct_mutex);
1411 if (list_empty(&req->list))
1415 tmp = list_first_entry(&engine->request_list,
1416 typeof(*tmp), list);
1418 i915_gem_request_retire(tmp);
1419 } while (tmp != req);
1421 WARN_ON(i915_verify_lists(engine->dev));
1425 * Waits for a request to be signaled, and cleans up the
1426 * request and object lists appropriately for that event.
1429 i915_wait_request(struct drm_i915_gem_request *req)
1431 struct drm_device *dev;
1432 struct drm_i915_private *dev_priv;
1436 BUG_ON(req == NULL);
1438 dev = req->ring->dev;
1439 dev_priv = dev->dev_private;
1440 interruptible = dev_priv->mm.interruptible;
1442 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1444 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1448 ret = __i915_wait_request(req,
1449 atomic_read(&dev_priv->gpu_error.reset_counter),
1450 interruptible, NULL, NULL);
1454 __i915_gem_request_retire__upto(req);
1459 * Ensures that all rendering to the object has completed and the object is
1460 * safe to unbind from the GTT or access from the CPU.
1463 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1472 if (obj->last_write_req != NULL) {
1473 ret = i915_wait_request(obj->last_write_req);
1477 i = obj->last_write_req->ring->id;
1478 if (obj->last_read_req[i] == obj->last_write_req)
1479 i915_gem_object_retire__read(obj, i);
1481 i915_gem_object_retire__write(obj);
1484 for (i = 0; i < I915_NUM_RINGS; i++) {
1485 if (obj->last_read_req[i] == NULL)
1488 ret = i915_wait_request(obj->last_read_req[i]);
1492 i915_gem_object_retire__read(obj, i);
1494 RQ_BUG_ON(obj->active);
1501 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1502 struct drm_i915_gem_request *req)
1504 int ring = req->ring->id;
1506 if (obj->last_read_req[ring] == req)
1507 i915_gem_object_retire__read(obj, ring);
1508 else if (obj->last_write_req == req)
1509 i915_gem_object_retire__write(obj);
1511 __i915_gem_request_retire__upto(req);
1514 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1515 * as the object state may change during this call.
1517 static __must_check int
1518 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1519 struct intel_rps_client *rps,
1522 struct drm_device *dev = obj->base.dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1525 unsigned reset_counter;
1528 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1529 BUG_ON(!dev_priv->mm.interruptible);
1534 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1538 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1541 struct drm_i915_gem_request *req;
1543 req = obj->last_write_req;
1547 requests[n++] = i915_gem_request_reference(req);
1549 for (i = 0; i < I915_NUM_RINGS; i++) {
1550 struct drm_i915_gem_request *req;
1552 req = obj->last_read_req[i];
1556 requests[n++] = i915_gem_request_reference(req);
1560 mutex_unlock(&dev->struct_mutex);
1561 for (i = 0; ret == 0 && i < n; i++)
1562 ret = __i915_wait_request(requests[i], reset_counter, true,
1564 mutex_lock(&dev->struct_mutex);
1566 for (i = 0; i < n; i++) {
1568 i915_gem_object_retire_request(obj, requests[i]);
1569 i915_gem_request_unreference(requests[i]);
1575 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1577 struct drm_i915_file_private *fpriv = file->driver_priv;
1582 * Called when user space prepares to use an object with the CPU, either
1583 * through the mmap ioctl's mapping or a GTT mapping.
1586 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1587 struct drm_file *file)
1589 struct drm_i915_gem_set_domain *args = data;
1590 struct drm_i915_gem_object *obj;
1591 uint32_t read_domains = args->read_domains;
1592 uint32_t write_domain = args->write_domain;
1595 /* Only handle setting domains to types used by the CPU. */
1596 if (write_domain & I915_GEM_GPU_DOMAINS)
1599 if (read_domains & I915_GEM_GPU_DOMAINS)
1602 /* Having something in the write domain implies it's in the read
1603 * domain, and only that read domain. Enforce that in the request.
1605 if (write_domain != 0 && read_domains != write_domain)
1608 ret = i915_mutex_lock_interruptible(dev);
1612 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1613 if (&obj->base == NULL) {
1618 /* Try to flush the object off the GPU without holding the lock.
1619 * We will repeat the flush holding the lock in the normal manner
1620 * to catch cases where we are gazumped.
1622 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1623 to_rps_client(file),
1628 if (read_domains & I915_GEM_DOMAIN_GTT)
1629 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1631 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1633 if (write_domain != 0)
1634 intel_fb_obj_invalidate(obj,
1635 write_domain == I915_GEM_DOMAIN_GTT ?
1636 ORIGIN_GTT : ORIGIN_CPU);
1639 drm_gem_object_unreference(&obj->base);
1641 mutex_unlock(&dev->struct_mutex);
1646 * Called when user space has done writes to this buffer
1649 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1650 struct drm_file *file)
1652 struct drm_i915_gem_sw_finish *args = data;
1653 struct drm_i915_gem_object *obj;
1656 ret = i915_mutex_lock_interruptible(dev);
1660 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1661 if (&obj->base == NULL) {
1666 /* Pinned buffers may be scanout, so flush the cache */
1667 if (obj->pin_display)
1668 i915_gem_object_flush_cpu_write_domain(obj);
1670 drm_gem_object_unreference(&obj->base);
1672 mutex_unlock(&dev->struct_mutex);
1677 * Maps the contents of an object, returning the address it is mapped
1680 * While the mapping holds a reference on the contents of the object, it doesn't
1681 * imply a ref on the object itself.
1685 * DRM driver writers who look a this function as an example for how to do GEM
1686 * mmap support, please don't implement mmap support like here. The modern way
1687 * to implement DRM mmap support is with an mmap offset ioctl (like
1688 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1689 * That way debug tooling like valgrind will understand what's going on, hiding
1690 * the mmap call in a driver private ioctl will break that. The i915 driver only
1691 * does cpu mmaps this way because we didn't know better.
1694 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1695 struct drm_file *file)
1697 struct drm_i915_gem_mmap *args = data;
1698 struct drm_gem_object *obj;
1701 struct proc *p = curproc;
1702 vm_map_t map = &p->p_vmspace->vm_map;
1706 if (args->flags & ~(I915_MMAP_WC))
1709 obj = drm_gem_object_lookup(dev, file, args->handle);
1713 if (args->size == 0)
1716 size = round_page(args->size);
1717 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1722 /* prime objects have no backing filp to GEM mmap
1727 * Call hint to ensure that NULL is not returned as a valid address
1728 * and to reduce vm_map traversals. XXX causes instability, use a
1729 * fixed low address as the start point instead to avoid the NULL
1736 * Use 256KB alignment. It is unclear why this matters for a
1737 * virtual address but it appears to fix a number of application/X
1738 * crashes and kms console switching is much faster.
1740 vm_object_hold(obj->vm_obj);
1741 vm_object_reference_locked(obj->vm_obj);
1742 vm_object_drop(obj->vm_obj);
1744 rv = vm_map_find(map, obj->vm_obj, NULL,
1745 args->offset, &addr, args->size,
1746 256 * 1024, /* align */
1748 VM_MAPTYPE_NORMAL, /* maptype */
1749 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1750 VM_PROT_READ | VM_PROT_WRITE, /* max */
1751 MAP_SHARED /* cow */);
1752 if (rv != KERN_SUCCESS) {
1753 vm_object_deallocate(obj->vm_obj);
1754 error = -vm_mmap_to_errno(rv);
1756 args->addr_ptr = (uint64_t)addr;
1759 drm_gem_object_unreference(obj);
1764 * i915_gem_fault - fault a page into the GTT
1766 * vm_obj is locked on entry and expected to be locked on return.
1768 * The vm_pager has placemarked the object with an anonymous memory page
1769 * which we must replace atomically to avoid races against concurrent faults
1770 * on the same page. XXX we currently are unable to do this atomically.
1772 * If we are to return an error we should not touch the anonymous page,
1773 * the caller will deallocate it.
1775 * XXX Most GEM calls appear to be interruptable, but we can't hard loop
1776 * in that case. Release all resources and wait 1 tick before retrying.
1777 * This is a huge problem which needs to be fixed by getting rid of most
1778 * of the interruptability. The linux code does not retry but does appear
1779 * to have some sort of mechanism (VM_FAULT_NOPAGE ?) for the higher level
1780 * to be able to retry.
1783 * @vma: VMA in question
1786 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1787 * from userspace. The fault handler takes care of binding the object to
1788 * the GTT (if needed), allocating and programming a fence register (again,
1789 * only if needed based on whether the old reg is still valid or the object
1790 * is tiled) and inserting a new PTE into the faulting process.
1792 * Note that the faulting process may involve evicting existing objects
1793 * from the GTT and/or fence registers to make room. So performance may
1794 * suffer if the GTT working set is large or there are few fence registers
1797 * vm_obj is locked on entry and expected to be locked on return. The VM
1798 * pager has placed an anonymous memory page at (obj,offset) which we have
1801 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres)
1803 struct drm_i915_gem_object *obj = to_intel_bo(vm_obj->handle);
1804 struct drm_device *dev = obj->base.dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 struct i915_ggtt_view view = i915_ggtt_view_normal;
1807 unsigned long page_offset;
1808 vm_page_t m, oldm = NULL;
1810 bool write = !!(prot & VM_PROT_WRITE);
1812 intel_runtime_pm_get(dev_priv);
1814 /* We don't use vmf->pgoff since that has the fake offset */
1815 page_offset = (unsigned long)offset;
1818 ret = i915_mutex_lock_interruptible(dev);
1822 trace_i915_gem_object_fault(obj, page_offset, true, write);
1824 /* Try to flush the object off the GPU first without holding the lock.
1825 * Upon reacquiring the lock, we will perform our sanity checks and then
1826 * repeat the flush holding the lock in the normal manner to catch cases
1827 * where we are gazumped.
1829 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1833 /* Access to snoopable pages through the GTT is incoherent. */
1834 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1839 /* Use a partial view if the object is bigger than the aperture. */
1840 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1841 obj->tiling_mode == I915_TILING_NONE) {
1843 static const unsigned int chunk_size = 256; // 1 MiB
1845 memset(&view, 0, sizeof(view));
1846 view.type = I915_GGTT_VIEW_PARTIAL;
1847 view.params.partial.offset = rounddown(page_offset, chunk_size);
1848 view.params.partial.size =
1851 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1852 view.params.partial.offset);
1856 /* Now pin it into the GTT if needed */
1857 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1861 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1865 ret = i915_gem_object_get_fence(obj);
1870 * START FREEBSD MAGIC
1872 * Add a pip count to avoid destruction and certain other
1873 * complex operations (such as collapses?) while unlocked.
1875 vm_object_pip_add(vm_obj, 1);
1878 * XXX We must currently remove the placeholder page now to avoid
1879 * a deadlock against a concurrent i915_gem_release_mmap().
1880 * Otherwise concurrent operation will block on the busy page
1881 * while holding locks which we need to obtain.
1883 if (*mres != NULL) {
1885 if ((oldm->flags & PG_BUSY) == 0)
1886 kprintf("i915_gem_fault: Page was not busy\n");
1888 vm_page_remove(oldm);
1898 * Since the object lock was dropped, another thread might have
1899 * faulted on the same GTT address and instantiated the mapping.
1902 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1905 * Try to busy the page, retry on failure (non-zero ret).
1907 if (vm_page_busy_try(m, false)) {
1908 kprintf("i915_gem_fault: PG_BUSY\n");
1918 obj->fault_mappable = true;
1920 /* Finally, remap it using the new GTT offset */
1921 m = vm_phys_fictitious_to_vm_page(dev_priv->gtt.mappable_base +
1922 i915_gem_obj_ggtt_offset_view(obj, &view) + offset);
1927 KASSERT((m->flags & PG_FICTITIOUS) != 0, ("not fictitious %p", m));
1928 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1931 * Try to busy the page. Fails on non-zero return.
1933 if (vm_page_busy_try(m, false)) {
1934 kprintf("i915_gem_fault: PG_BUSY(2)\n");
1938 m->valid = VM_PAGE_BITS_ALL;
1941 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1942 /* Overriding existing pages in partial view does not cause
1943 * us any trouble as TLBs are still valid because the fault
1944 * is due to userspace losing part of the mapping or never
1945 * having accessed it before (at this partials' range).
1947 unsigned long base = vma->vm_start +
1948 (view.params.partial.offset << PAGE_SHIFT);
1951 for (i = 0; i < view.params.partial.size; i++) {
1952 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1957 obj->fault_mappable = true;
1959 if (!obj->fault_mappable) {
1960 unsigned long size = min_t(unsigned long,
1961 vma->vm_end - vma->vm_start,
1965 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1966 ret = vm_insert_pfn(vma,
1967 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1973 obj->fault_mappable = true;
1975 ret = vm_insert_pfn(vma,
1976 (unsigned long)vmf->virtual_address,
1979 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1987 i915_gem_object_ggtt_unpin_view(obj, &view);
1988 mutex_unlock(&dev->struct_mutex);
1993 * ALTERNATIVE ERROR RETURN.
1995 * OBJECT EXPECTED TO BE LOCKED.
1998 i915_gem_object_ggtt_unpin_view(obj, &view);
2000 mutex_unlock(&dev->struct_mutex);
2005 * We eat errors when the gpu is terminally wedged to avoid
2006 * userspace unduly crashing (gl has no provisions for mmaps to
2007 * fail). But any other -EIO isn't ours (e.g. swap in failure)
2008 * and so needs to be reported.
2010 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
2011 // ret = VM_FAULT_SIGBUS;
2016 * EAGAIN means the gpu is hung and we'll wait for the error
2017 * handler to reset everything when re-faulting in
2018 * i915_mutex_lock_interruptible.
2022 VM_OBJECT_UNLOCK(vm_obj);
2024 tsleep(&dummy, 0, "delay", 1); /* XXX */
2025 VM_OBJECT_LOCK(vm_obj);
2028 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2029 ret = VM_PAGER_ERROR;
2036 vm_object_pip_wakeup(vm_obj);
2038 intel_runtime_pm_put(dev_priv);
2043 * i915_gem_release_mmap - remove physical page mappings
2044 * @obj: obj in question
2046 * Preserve the reservation of the mmapping with the DRM core code, but
2047 * relinquish ownership of the pages back to the system.
2049 * It is vital that we remove the page mapping if we have mapped a tiled
2050 * object through the GTT and then lose the fence register due to
2051 * resource pressure. Similarly if the object has been moved out of the
2052 * aperture, than pages mapped into userspace must be revoked. Removing the
2053 * mapping will then trigger a page fault on the next user access, allowing
2054 * fixup by i915_gem_fault().
2057 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2063 if (!obj->fault_mappable)
2066 devobj = cdev_pager_lookup(obj);
2067 if (devobj != NULL) {
2068 page_count = OFF_TO_IDX(obj->base.size);
2070 VM_OBJECT_LOCK(devobj);
2071 for (i = 0; i < page_count; i++) {
2072 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
2075 cdev_pager_free_page(devobj, m);
2077 VM_OBJECT_UNLOCK(devobj);
2078 vm_object_deallocate(devobj);
2081 obj->fault_mappable = false;
2085 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
2087 struct drm_i915_gem_object *obj;
2089 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
2090 i915_gem_release_mmap(obj);
2094 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
2098 if (INTEL_INFO(dev)->gen >= 4 ||
2099 tiling_mode == I915_TILING_NONE)
2102 /* Previous chips need a power-of-two fence region when tiling */
2103 if (INTEL_INFO(dev)->gen == 3)
2104 gtt_size = 1024*1024;
2106 gtt_size = 512*1024;
2108 while (gtt_size < size)
2115 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2116 * @obj: object to check
2118 * Return the required GTT alignment for an object, taking into account
2119 * potential fence register mapping.
2122 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2123 int tiling_mode, bool fenced)
2126 * Minimum alignment is 4k (GTT page size), but might be greater
2127 * if a fence register is needed for the object.
2129 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2130 tiling_mode == I915_TILING_NONE)
2134 * Previous chips need to be aligned to the size of the smallest
2135 * fence register that can contain the object.
2137 return i915_gem_get_gtt_size(dev, size, tiling_mode);
2140 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2142 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2146 if (drm_vma_node_has_offset(&obj->base.vma_node))
2150 dev_priv->mm.shrinker_no_lock_stealing = true;
2152 ret = drm_gem_create_mmap_offset(&obj->base);
2156 /* Badly fragmented mmap space? The only way we can recover
2157 * space is by destroying unwanted objects. We can't randomly release
2158 * mmap_offsets as userspace expects them to be persistent for the
2159 * lifetime of the objects. The closest we can is to release the
2160 * offsets on purgeable objects by truncating it and marking it purged,
2161 * which prevents userspace from ever using that object again.
2163 i915_gem_shrink(dev_priv,
2164 obj->base.size >> PAGE_SHIFT,
2166 I915_SHRINK_UNBOUND |
2167 I915_SHRINK_PURGEABLE);
2168 ret = drm_gem_create_mmap_offset(&obj->base);
2172 i915_gem_shrink_all(dev_priv);
2173 ret = drm_gem_create_mmap_offset(&obj->base);
2175 dev_priv->mm.shrinker_no_lock_stealing = false;
2180 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2182 drm_gem_free_mmap_offset(&obj->base);
2186 i915_gem_mmap_gtt(struct drm_file *file,
2187 struct drm_device *dev,
2191 struct drm_i915_gem_object *obj;
2194 ret = i915_mutex_lock_interruptible(dev);
2198 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2199 if (&obj->base == NULL) {
2204 if (obj->madv != I915_MADV_WILLNEED) {
2205 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2210 ret = i915_gem_object_create_mmap_offset(obj);
2214 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
2215 DRM_GEM_MAPPING_KEY;
2218 drm_gem_object_unreference(&obj->base);
2220 mutex_unlock(&dev->struct_mutex);
2225 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2227 * @data: GTT mapping ioctl data
2228 * @file: GEM object info
2230 * Simply returns the fake offset to userspace so it can mmap it.
2231 * The mmap call will end up in drm_gem_mmap(), which will set things
2232 * up so we can get faults in the handler above.
2234 * The fault handler will take care of binding the object into the GTT
2235 * (since it may have been evicted to make room for something), allocating
2236 * a fence register, and mapping the appropriate aperture address into
2240 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *file)
2243 struct drm_i915_gem_mmap_gtt *args = data;
2245 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2248 /* Immediately discard the backing storage */
2250 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2254 vm_obj = obj->base.vm_obj;
2255 VM_OBJECT_LOCK(vm_obj);
2256 vm_object_page_remove(vm_obj, 0, 0, false);
2257 VM_OBJECT_UNLOCK(vm_obj);
2259 obj->madv = __I915_MADV_PURGED;
2262 /* Try to discard unwanted pages */
2264 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2267 struct address_space *mapping;
2270 switch (obj->madv) {
2271 case I915_MADV_DONTNEED:
2272 i915_gem_object_truncate(obj);
2273 case __I915_MADV_PURGED:
2278 if (obj->base.filp == NULL)
2281 mapping = file_inode(obj->base.filp)->i_mapping,
2282 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2287 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2289 struct sg_page_iter sg_iter;
2292 BUG_ON(obj->madv == __I915_MADV_PURGED);
2294 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2296 /* In the event of a disaster, abandon all caches and
2297 * hope for the best.
2299 WARN_ON(ret != -EIO);
2300 i915_gem_clflush_object(obj, true);
2301 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2304 i915_gem_gtt_finish_object(obj);
2306 if (i915_gem_object_needs_bit17_swizzle(obj))
2307 i915_gem_object_save_bit_17_swizzle(obj);
2309 if (obj->madv == I915_MADV_DONTNEED)
2312 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2313 struct vm_page *page = sg_page_iter_page(&sg_iter);
2316 set_page_dirty(page);
2318 if (obj->madv == I915_MADV_WILLNEED)
2319 mark_page_accessed(page);
2321 vm_page_busy_wait(page, FALSE, "i915gem");
2322 vm_page_unwire(page, 1);
2323 vm_page_wakeup(page);
2327 sg_free_table(obj->pages);
2332 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2334 const struct drm_i915_gem_object_ops *ops = obj->ops;
2336 if (obj->pages == NULL)
2339 if (obj->pages_pin_count)
2342 BUG_ON(i915_gem_obj_bound_any(obj));
2344 /* ->put_pages might need to allocate memory for the bit17 swizzle
2345 * array, hence protect them from being reaped by removing them from gtt
2347 list_del(&obj->global_list);
2349 ops->put_pages(obj);
2352 i915_gem_object_invalidate(obj);
2358 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2360 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2363 struct sg_table *st;
2364 struct scatterlist *sg;
2365 struct sg_page_iter sg_iter;
2366 struct vm_page *page;
2367 unsigned long last_pfn = 0; /* suppress gcc warning */
2370 /* Assert that the object is not currently in any GPU domain. As it
2371 * wasn't in the GTT, there shouldn't be any way it could have been in
2374 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2375 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2377 st = kmalloc(sizeof(*st), M_DRM, M_WAITOK);
2381 page_count = obj->base.size / PAGE_SIZE;
2382 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2387 /* Get the list of pages out of our struct file. They'll be pinned
2388 * at this point until we release them.
2390 * Fail silently without starting the shrinker
2392 vm_obj = obj->base.vm_obj;
2393 VM_OBJECT_LOCK(vm_obj);
2396 for (i = 0; i < page_count; i++) {
2397 page = shmem_read_mapping_page(vm_obj, i);
2399 i915_gem_shrink(dev_priv,
2402 I915_SHRINK_UNBOUND |
2403 I915_SHRINK_PURGEABLE);
2404 page = shmem_read_mapping_page(vm_obj, i);
2407 /* We've tried hard to allocate the memory by reaping
2408 * our own buffer, now let the real VM do its job and
2409 * go down in flames if truly OOM.
2411 i915_gem_shrink_all(dev_priv);
2412 page = shmem_read_mapping_page(vm_obj, i);
2414 ret = PTR_ERR(page);
2418 #ifdef CONFIG_SWIOTLB
2419 if (swiotlb_nr_tbl()) {
2421 sg_set_page(sg, page, PAGE_SIZE, 0);
2426 if (!i || page_to_pfn(page) != last_pfn + 1) {
2430 sg_set_page(sg, page, PAGE_SIZE, 0);
2432 sg->length += PAGE_SIZE;
2434 last_pfn = page_to_pfn(page);
2436 /* Check that the i965g/gm workaround works. */
2438 #ifdef CONFIG_SWIOTLB
2439 if (!swiotlb_nr_tbl())
2443 VM_OBJECT_UNLOCK(vm_obj);
2445 ret = i915_gem_gtt_prepare_object(obj);
2449 if (i915_gem_object_needs_bit17_swizzle(obj))
2450 i915_gem_object_do_bit_17_swizzle(obj);
2452 if (obj->tiling_mode != I915_TILING_NONE &&
2453 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2454 i915_gem_object_pin_pages(obj);
2460 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2461 page = sg_page_iter_page(&sg_iter);
2462 vm_page_busy_wait(page, FALSE, "i915gem");
2463 vm_page_unwire(page, 0);
2464 vm_page_wakeup(page);
2466 VM_OBJECT_UNLOCK(vm_obj);
2470 /* shmemfs first checks if there is enough memory to allocate the page
2471 * and reports ENOSPC should there be insufficient, along with the usual
2472 * ENOMEM for a genuine allocation failure.
2474 * We use ENOSPC in our driver to mean that we have run out of aperture
2475 * space and so want to translate the error from shmemfs back to our
2476 * usual understanding of ENOMEM.
2484 /* Ensure that the associated pages are gathered from the backing storage
2485 * and pinned into our object. i915_gem_object_get_pages() may be called
2486 * multiple times before they are released by a single call to
2487 * i915_gem_object_put_pages() - once the pages are no longer referenced
2488 * either as a result of memory pressure (reaping pages under the shrinker)
2489 * or as the object is itself released.
2492 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2494 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2495 const struct drm_i915_gem_object_ops *ops = obj->ops;
2501 if (obj->madv != I915_MADV_WILLNEED) {
2502 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2506 BUG_ON(obj->pages_pin_count);
2508 ret = ops->get_pages(obj);
2512 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2514 obj->get_page.sg = obj->pages->sgl;
2515 obj->get_page.last = 0;
2520 void i915_vma_move_to_active(struct i915_vma *vma,
2521 struct drm_i915_gem_request *req)
2523 struct drm_i915_gem_object *obj = vma->obj;
2524 struct intel_engine_cs *ring;
2526 ring = i915_gem_request_get_ring(req);
2528 /* Add a reference if we're newly entering the active list. */
2529 if (obj->active == 0)
2530 drm_gem_object_reference(&obj->base);
2531 obj->active |= intel_ring_flag(ring);
2533 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2534 i915_gem_request_assign(&obj->last_read_req[ring->id], req);
2536 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2540 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2542 RQ_BUG_ON(obj->last_write_req == NULL);
2543 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2545 i915_gem_request_assign(&obj->last_write_req, NULL);
2546 intel_fb_obj_flush(obj, true, ORIGIN_CS);
2550 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2552 struct i915_vma *vma;
2554 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2555 RQ_BUG_ON(!(obj->active & (1 << ring)));
2557 list_del_init(&obj->ring_list[ring]);
2558 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2560 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2561 i915_gem_object_retire__write(obj);
2563 obj->active &= ~(1 << ring);
2567 /* Bump our place on the bound list to keep it roughly in LRU order
2568 * so that we don't steal from recently used but inactive objects
2569 * (unless we are forced to ofc!)
2571 list_move_tail(&obj->global_list,
2572 &to_i915(obj->base.dev)->mm.bound_list);
2574 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2575 if (!list_empty(&vma->mm_list))
2576 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2579 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2580 drm_gem_object_unreference(&obj->base);
2584 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2586 struct drm_i915_private *dev_priv = dev->dev_private;
2587 struct intel_engine_cs *ring;
2590 /* Carefully retire all requests without writing to the rings */
2591 for_each_ring(ring, dev_priv, i) {
2592 ret = intel_ring_idle(ring);
2596 i915_gem_retire_requests(dev);
2598 /* Finally reset hw state */
2599 for_each_ring(ring, dev_priv, i) {
2600 intel_ring_init_seqno(ring, seqno);
2602 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2603 ring->semaphore.sync_seqno[j] = 0;
2609 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2611 struct drm_i915_private *dev_priv = dev->dev_private;
2617 /* HWS page needs to be set less than what we
2618 * will inject to ring
2620 ret = i915_gem_init_seqno(dev, seqno - 1);
2624 /* Carefully set the last_seqno value so that wrap
2625 * detection still works
2627 dev_priv->next_seqno = seqno;
2628 dev_priv->last_seqno = seqno - 1;
2629 if (dev_priv->last_seqno == 0)
2630 dev_priv->last_seqno--;
2636 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2638 struct drm_i915_private *dev_priv = dev->dev_private;
2640 /* reserve 0 for non-seqno */
2641 if (dev_priv->next_seqno == 0) {
2642 int ret = i915_gem_init_seqno(dev, 0);
2646 dev_priv->next_seqno = 1;
2649 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2654 * NB: This function is not allowed to fail. Doing so would mean the the
2655 * request is not being tracked for completion but the work itself is
2656 * going to happen on the hardware. This would be a Bad Thing(tm).
2658 void __i915_add_request(struct drm_i915_gem_request *request,
2659 struct drm_i915_gem_object *obj,
2662 struct intel_engine_cs *ring;
2663 struct drm_i915_private *dev_priv;
2664 struct intel_ringbuffer *ringbuf;
2668 if (WARN_ON(request == NULL))
2671 ring = request->ring;
2672 dev_priv = ring->dev->dev_private;
2673 ringbuf = request->ringbuf;
2676 * To ensure that this call will not fail, space for its emissions
2677 * should already have been reserved in the ring buffer. Let the ring
2678 * know that it is time to use that space up.
2680 intel_ring_reserved_space_use(ringbuf);
2682 request_start = intel_ring_get_tail(ringbuf);
2684 * Emit any outstanding flushes - execbuf can fail to emit the flush
2685 * after having emitted the batchbuffer command. Hence we need to fix
2686 * things up similar to emitting the lazy request. The difference here
2687 * is that the flush _must_ happen before the next request, no matter
2691 if (i915.enable_execlists)
2692 ret = logical_ring_flush_all_caches(request);
2694 ret = intel_ring_flush_all_caches(request);
2695 /* Not allowed to fail! */
2696 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2699 /* Record the position of the start of the request so that
2700 * should we detect the updated seqno part-way through the
2701 * GPU processing the request, we never over-estimate the
2702 * position of the head.
2704 request->postfix = intel_ring_get_tail(ringbuf);
2706 if (i915.enable_execlists)
2707 ret = ring->emit_request(request);
2709 ret = ring->add_request(request);
2711 request->tail = intel_ring_get_tail(ringbuf);
2714 /* Not allowed to fail! */
2715 WARN(ret, "emit|add_request failed: %d!\n", ret);
2717 request->head = request_start;
2719 /* Whilst this request exists, batch_obj will be on the
2720 * active_list, and so will hold the active reference. Only when this
2721 * request is retired will the the batch_obj be moved onto the
2722 * inactive_list and lose its active reference. Hence we do not need
2723 * to explicitly hold another reference here.
2725 request->batch_obj = obj;
2727 request->emitted_jiffies = jiffies;
2728 request->previous_seqno = ring->last_submitted_seqno;
2729 ring->last_submitted_seqno = request->seqno;
2730 list_add_tail(&request->list, &ring->request_list);
2732 trace_i915_gem_request_add(request);
2734 i915_queue_hangcheck(ring->dev);
2736 queue_delayed_work(dev_priv->wq,
2737 &dev_priv->mm.retire_work,
2738 round_jiffies_up_relative(HZ));
2739 intel_mark_busy(dev_priv->dev);
2741 /* Sanity check that the reserved size was large enough. */
2742 intel_ring_reserved_space_end(ringbuf);
2745 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2746 const struct intel_context *ctx)
2748 unsigned long elapsed;
2750 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2752 if (ctx->hang_stats.banned)
2755 if (ctx->hang_stats.ban_period_seconds &&
2756 elapsed <= ctx->hang_stats.ban_period_seconds) {
2757 if (!i915_gem_context_is_default(ctx)) {
2758 DRM_DEBUG("context hanging too fast, banning!\n");
2760 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2761 if (i915_stop_ring_allow_warn(dev_priv))
2762 DRM_ERROR("gpu hanging too fast, banning!\n");
2770 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2771 struct intel_context *ctx,
2774 struct i915_ctx_hang_stats *hs;
2779 hs = &ctx->hang_stats;
2782 hs->banned = i915_context_is_banned(dev_priv, ctx);
2784 hs->guilty_ts = get_seconds();
2786 hs->batch_pending++;
2790 void i915_gem_request_free(struct kref *req_ref)
2792 struct drm_i915_gem_request *req = container_of(req_ref,
2794 struct intel_context *ctx = req->ctx;
2797 i915_gem_request_remove_from_client(req);
2800 if (i915.enable_execlists) {
2801 if (ctx != req->ring->default_context)
2802 intel_lr_context_unpin(req);
2805 i915_gem_context_unreference(ctx);
2811 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2812 struct intel_context *ctx,
2813 struct drm_i915_gem_request **req_out)
2815 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2816 struct drm_i915_gem_request *req;
2824 req = kzalloc(sizeof(*req), GFP_KERNEL);
2828 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2832 kref_init(&req->ref);
2833 req->i915 = dev_priv;
2836 i915_gem_context_reference(req->ctx);
2838 if (i915.enable_execlists)
2839 ret = intel_logical_ring_alloc_request_extras(req);
2841 ret = intel_ring_alloc_request_extras(req);
2843 i915_gem_context_unreference(req->ctx);
2848 * Reserve space in the ring buffer for all the commands required to
2849 * eventually emit this request. This is to guarantee that the
2850 * i915_add_request() call can't fail. Note that the reserve may need
2851 * to be redone if the request is not actually submitted straight
2852 * away, e.g. because a GPU scheduler has deferred it.
2854 if (i915.enable_execlists)
2855 ret = intel_logical_ring_reserve_space(req);
2857 ret = intel_ring_reserve_space(req);
2860 * At this point, the request is fully allocated even if not
2861 * fully prepared. Thus it can be cleaned up using the proper
2864 i915_gem_request_cancel(req);
2876 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2878 intel_ring_reserved_space_cancel(req->ringbuf);
2880 i915_gem_request_unreference(req);
2883 struct drm_i915_gem_request *
2884 i915_gem_find_active_request(struct intel_engine_cs *ring)
2886 struct drm_i915_gem_request *request;
2888 list_for_each_entry(request, &ring->request_list, list) {
2889 if (i915_gem_request_completed(request, false))
2898 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2899 struct intel_engine_cs *ring)
2901 struct drm_i915_gem_request *request;
2904 request = i915_gem_find_active_request(ring);
2906 if (request == NULL)
2909 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2911 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2913 list_for_each_entry_continue(request, &ring->request_list, list)
2914 i915_set_reset_status(dev_priv, request->ctx, false);
2917 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2918 struct intel_engine_cs *ring)
2920 while (!list_empty(&ring->active_list)) {
2921 struct drm_i915_gem_object *obj;
2923 obj = list_first_entry(&ring->active_list,
2924 struct drm_i915_gem_object,
2925 ring_list[ring->id]);
2927 i915_gem_object_retire__read(obj, ring->id);
2931 * Clear the execlists queue up before freeing the requests, as those
2932 * are the ones that keep the context and ringbuffer backing objects
2935 while (!list_empty(&ring->execlist_queue)) {
2936 struct drm_i915_gem_request *submit_req;
2938 submit_req = list_first_entry(&ring->execlist_queue,
2939 struct drm_i915_gem_request,
2941 list_del(&submit_req->execlist_link);
2943 if (submit_req->ctx != ring->default_context)
2944 intel_lr_context_unpin(submit_req);
2946 i915_gem_request_unreference(submit_req);
2950 * We must free the requests after all the corresponding objects have
2951 * been moved off active lists. Which is the same order as the normal
2952 * retire_requests function does. This is important if object hold
2953 * implicit references on things like e.g. ppgtt address spaces through
2956 while (!list_empty(&ring->request_list)) {
2957 struct drm_i915_gem_request *request;
2959 request = list_first_entry(&ring->request_list,
2960 struct drm_i915_gem_request,
2963 i915_gem_request_retire(request);
2967 void i915_gem_reset(struct drm_device *dev)
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 struct intel_engine_cs *ring;
2974 * Before we free the objects from the requests, we need to inspect
2975 * them for finding the guilty party. As the requests only borrow
2976 * their reference to the objects, the inspection must be done first.
2978 for_each_ring(ring, dev_priv, i)
2979 i915_gem_reset_ring_status(dev_priv, ring);
2981 for_each_ring(ring, dev_priv, i)
2982 i915_gem_reset_ring_cleanup(dev_priv, ring);
2984 i915_gem_context_reset(dev);
2986 i915_gem_restore_fences(dev);
2988 WARN_ON(i915_verify_lists(dev));
2992 * This function clears the request list as sequence numbers are passed.
2995 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2997 WARN_ON(i915_verify_lists(ring->dev));
2999 /* Retire requests first as we use it above for the early return.
3000 * If we retire requests last, we may use a later seqno and so clear
3001 * the requests lists without clearing the active list, leading to
3004 while (!list_empty(&ring->request_list)) {
3005 struct drm_i915_gem_request *request;
3007 request = list_first_entry(&ring->request_list,
3008 struct drm_i915_gem_request,
3011 if (!i915_gem_request_completed(request, true))
3014 i915_gem_request_retire(request);
3017 /* Move any buffers on the active list that are no longer referenced
3018 * by the ringbuffer to the flushing/inactive lists as appropriate,
3019 * before we free the context associated with the requests.
3021 while (!list_empty(&ring->active_list)) {
3022 struct drm_i915_gem_object *obj;
3024 obj = list_first_entry(&ring->active_list,
3025 struct drm_i915_gem_object,
3026 ring_list[ring->id]);
3028 if (!list_empty(&obj->last_read_req[ring->id]->list))
3031 i915_gem_object_retire__read(obj, ring->id);
3034 if (unlikely(ring->trace_irq_req &&
3035 i915_gem_request_completed(ring->trace_irq_req, true))) {
3036 ring->irq_put(ring);
3037 i915_gem_request_assign(&ring->trace_irq_req, NULL);
3040 WARN_ON(i915_verify_lists(ring->dev));
3044 i915_gem_retire_requests(struct drm_device *dev)
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_engine_cs *ring;
3051 for_each_ring(ring, dev_priv, i) {
3052 i915_gem_retire_requests_ring(ring);
3053 idle &= list_empty(&ring->request_list);
3054 if (i915.enable_execlists) {
3055 unsigned long flags;
3057 spin_lock_irqsave(&ring->execlist_lock, flags);
3058 idle &= list_empty(&ring->execlist_queue);
3059 spin_unlock_irqrestore(&ring->execlist_lock, flags);
3061 intel_execlists_retire_requests(ring);
3066 mod_delayed_work(dev_priv->wq,
3067 &dev_priv->mm.idle_work,
3068 msecs_to_jiffies(100));
3074 i915_gem_retire_work_handler(struct work_struct *work)
3076 struct drm_i915_private *dev_priv =
3077 container_of(work, typeof(*dev_priv), mm.retire_work.work);
3078 struct drm_device *dev = dev_priv->dev;
3081 /* Come back later if the device is busy... */
3083 if (mutex_trylock(&dev->struct_mutex)) {
3084 idle = i915_gem_retire_requests(dev);
3085 mutex_unlock(&dev->struct_mutex);
3088 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3089 round_jiffies_up_relative(HZ));
3093 i915_gem_idle_work_handler(struct work_struct *work)
3095 struct drm_i915_private *dev_priv =
3096 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3097 struct drm_device *dev = dev_priv->dev;
3098 struct intel_engine_cs *ring;
3101 for_each_ring(ring, dev_priv, i)
3102 if (!list_empty(&ring->request_list))
3105 intel_mark_idle(dev);
3107 if (mutex_trylock(&dev->struct_mutex)) {
3108 struct intel_engine_cs *ring;
3111 for_each_ring(ring, dev_priv, i)
3112 i915_gem_batch_pool_fini(&ring->batch_pool);
3114 mutex_unlock(&dev->struct_mutex);
3119 * Ensures that an object will eventually get non-busy by flushing any required
3120 * write domains, emitting any outstanding lazy request and retiring and
3121 * completed requests.
3124 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3131 for (i = 0; i < I915_NUM_RINGS; i++) {
3132 struct drm_i915_gem_request *req;
3134 req = obj->last_read_req[i];
3138 if (list_empty(&req->list))
3141 if (i915_gem_request_completed(req, true)) {
3142 __i915_gem_request_retire__upto(req);
3144 i915_gem_object_retire__read(obj, i);
3152 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3153 * @DRM_IOCTL_ARGS: standard ioctl arguments
3155 * Returns 0 if successful, else an error is returned with the remaining time in
3156 * the timeout parameter.
3157 * -ETIME: object is still busy after timeout
3158 * -ERESTARTSYS: signal interrupted the wait
3159 * -ENONENT: object doesn't exist
3160 * Also possible, but rare:
3161 * -EAGAIN: GPU wedged
3163 * -ENODEV: Internal IRQ fail
3164 * -E?: The add request failed
3166 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3167 * non-zero timeout parameter the wait ioctl will wait for the given number of
3168 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3169 * without holding struct_mutex the object may become re-busied before this
3170 * function completes. A similar but shorter * race condition exists in the busy
3174 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct drm_i915_gem_wait *args = data;
3178 struct drm_i915_gem_object *obj;
3179 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3180 unsigned reset_counter;
3184 if (args->flags != 0)
3187 ret = i915_mutex_lock_interruptible(dev);
3191 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3192 if (&obj->base == NULL) {
3193 mutex_unlock(&dev->struct_mutex);
3197 /* Need to make sure the object gets inactive eventually. */
3198 ret = i915_gem_object_flush_active(obj);
3205 /* Do this after OLR check to make sure we make forward progress polling
3206 * on this IOCTL with a timeout == 0 (like busy ioctl)
3208 if (args->timeout_ns == 0) {
3213 drm_gem_object_unreference(&obj->base);
3214 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3216 for (i = 0; i < I915_NUM_RINGS; i++) {
3217 if (obj->last_read_req[i] == NULL)
3220 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3223 mutex_unlock(&dev->struct_mutex);
3225 for (i = 0; i < n; i++) {
3227 ret = __i915_wait_request(req[i], reset_counter, true,
3228 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3230 i915_gem_request_unreference__unlocked(req[i]);
3235 drm_gem_object_unreference(&obj->base);
3236 mutex_unlock(&dev->struct_mutex);
3241 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3242 struct intel_engine_cs *to,
3243 struct drm_i915_gem_request *from_req,
3244 struct drm_i915_gem_request **to_req)
3246 struct intel_engine_cs *from;
3249 from = i915_gem_request_get_ring(from_req);
3253 if (i915_gem_request_completed(from_req, true))
3256 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3257 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3258 ret = __i915_wait_request(from_req,
3259 atomic_read(&i915->gpu_error.reset_counter),
3260 i915->mm.interruptible,
3262 &i915->rps.semaphores);
3266 i915_gem_object_retire_request(obj, from_req);
3268 int idx = intel_ring_sync_index(from, to);
3269 u32 seqno = i915_gem_request_get_seqno(from_req);
3273 if (seqno <= from->semaphore.sync_seqno[idx])
3276 if (*to_req == NULL) {
3277 ret = i915_gem_request_alloc(to, to->default_context, to_req);
3282 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3283 ret = to->semaphore.sync_to(*to_req, from, seqno);
3287 /* We use last_read_req because sync_to()
3288 * might have just caused seqno wrap under
3291 from->semaphore.sync_seqno[idx] =
3292 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3299 * i915_gem_object_sync - sync an object to a ring.
3301 * @obj: object which may be in use on another ring.
3302 * @to: ring we wish to use the object on. May be NULL.
3303 * @to_req: request we wish to use the object for. See below.
3304 * This will be allocated and returned if a request is
3305 * required but not passed in.
3307 * This code is meant to abstract object synchronization with the GPU.
3308 * Calling with NULL implies synchronizing the object with the CPU
3309 * rather than a particular GPU ring. Conceptually we serialise writes
3310 * between engines inside the GPU. We only allow one engine to write
3311 * into a buffer at any time, but multiple readers. To ensure each has
3312 * a coherent view of memory, we must:
3314 * - If there is an outstanding write request to the object, the new
3315 * request must wait for it to complete (either CPU or in hw, requests
3316 * on the same ring will be naturally ordered).
3318 * - If we are a write request (pending_write_domain is set), the new
3319 * request must wait for outstanding read requests to complete.
3321 * For CPU synchronisation (NULL to) no request is required. For syncing with
3322 * rings to_req must be non-NULL. However, a request does not have to be
3323 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3324 * request will be allocated automatically and returned through *to_req. Note
3325 * that it is not guaranteed that commands will be emitted (because the system
3326 * might already be idle). Hence there is no need to create a request that
3327 * might never have any work submitted. Note further that if a request is
3328 * returned in *to_req, it is the responsibility of the caller to submit
3329 * that request (after potentially adding more work to it).
3331 * Returns 0 if successful, else propagates up the lower layer error.
3334 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3335 struct intel_engine_cs *to,
3336 struct drm_i915_gem_request **to_req)
3338 const bool readonly = obj->base.pending_write_domain == 0;
3339 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3346 return i915_gem_object_wait_rendering(obj, readonly);
3350 if (obj->last_write_req)
3351 req[n++] = obj->last_write_req;
3353 for (i = 0; i < I915_NUM_RINGS; i++)
3354 if (obj->last_read_req[i])
3355 req[n++] = obj->last_read_req[i];
3357 for (i = 0; i < n; i++) {
3358 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3366 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3368 u32 old_write_domain, old_read_domains;
3370 /* Force a pagefault for domain tracking on next user access */
3371 i915_gem_release_mmap(obj);
3373 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3376 /* Wait for any direct GTT access to complete */
3379 old_read_domains = obj->base.read_domains;
3380 old_write_domain = obj->base.write_domain;
3382 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3383 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3385 trace_i915_gem_object_change_domain(obj,
3390 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3392 struct drm_i915_gem_object *obj = vma->obj;
3393 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3396 if (list_empty(&vma->vma_link))
3399 if (!drm_mm_node_allocated(&vma->node)) {
3400 i915_gem_vma_destroy(vma);
3407 BUG_ON(obj->pages == NULL);
3410 ret = i915_gem_object_wait_rendering(obj, false);
3415 if (i915_is_ggtt(vma->vm) &&
3416 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3417 i915_gem_object_finish_gtt(obj);
3419 /* release the fence reg _after_ flushing */
3420 ret = i915_gem_object_put_fence(obj);
3425 trace_i915_vma_unbind(vma);
3427 vma->vm->unbind_vma(vma);
3430 list_del_init(&vma->mm_list);
3431 if (i915_is_ggtt(vma->vm)) {
3432 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3433 obj->map_and_fenceable = false;
3434 } else if (vma->ggtt_view.pages) {
3435 sg_free_table(vma->ggtt_view.pages);
3436 kfree(vma->ggtt_view.pages);
3438 vma->ggtt_view.pages = NULL;
3441 drm_mm_remove_node(&vma->node);
3442 i915_gem_vma_destroy(vma);
3444 /* Since the unbound list is global, only move to that list if
3445 * no more VMAs exist. */
3446 if (list_empty(&obj->vma_list))
3447 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3449 /* And finally now the object is completely decoupled from this vma,
3450 * we can drop its hold on the backing storage and allow it to be
3451 * reaped by the shrinker.
3453 i915_gem_object_unpin_pages(obj);
3458 int i915_vma_unbind(struct i915_vma *vma)
3460 return __i915_vma_unbind(vma, true);
3463 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3465 return __i915_vma_unbind(vma, false);
3468 int i915_gpu_idle(struct drm_device *dev)
3470 struct drm_i915_private *dev_priv = dev->dev_private;
3471 struct intel_engine_cs *ring;
3474 /* Flush everything onto the inactive list. */
3475 for_each_ring(ring, dev_priv, i) {
3476 if (!i915.enable_execlists) {
3477 struct drm_i915_gem_request *req;
3479 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
3483 ret = i915_switch_context(req);
3485 i915_gem_request_cancel(req);
3489 i915_add_request_no_flush(req);
3492 ret = intel_ring_idle(ring);
3497 WARN_ON(i915_verify_lists(dev));
3501 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3502 unsigned long cache_level)
3504 struct drm_mm_node *gtt_space = &vma->node;
3505 struct drm_mm_node *other;
3508 * On some machines we have to be careful when putting differing types
3509 * of snoopable memory together to avoid the prefetcher crossing memory
3510 * domains and dying. During vm initialisation, we decide whether or not
3511 * these constraints apply and set the drm_mm.color_adjust
3514 if (vma->vm->mm.color_adjust == NULL)
3517 if (!drm_mm_node_allocated(gtt_space))
3520 if (list_empty(>t_space->node_list))
3523 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3524 if (other->allocated && !other->hole_follows && other->color != cache_level)
3527 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3528 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3535 * Finds free space in the GTT aperture and binds the object or a view of it
3538 static struct i915_vma *
3539 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3540 struct i915_address_space *vm,
3541 const struct i915_ggtt_view *ggtt_view,
3545 struct drm_device *dev = obj->base.dev;
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547 u32 fence_alignment, unfenced_alignment;
3548 u32 search_flag, alloc_flag;
3550 u64 size, fence_size;
3551 struct i915_vma *vma;
3554 if (i915_is_ggtt(vm)) {
3557 if (WARN_ON(!ggtt_view))
3558 return ERR_PTR(-EINVAL);
3560 view_size = i915_ggtt_view_size(obj, ggtt_view);
3562 fence_size = i915_gem_get_gtt_size(dev,
3565 fence_alignment = i915_gem_get_gtt_alignment(dev,
3569 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3573 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3575 fence_size = i915_gem_get_gtt_size(dev,
3578 fence_alignment = i915_gem_get_gtt_alignment(dev,
3582 unfenced_alignment =
3583 i915_gem_get_gtt_alignment(dev,
3587 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3590 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3592 if (flags & PIN_MAPPABLE)
3593 end = min_t(u64, end, dev_priv->gtt.mappable_end);
3594 if (flags & PIN_ZONE_4G)
3595 end = min_t(u64, end, (1ULL << 32));
3598 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3600 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3601 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3602 ggtt_view ? ggtt_view->type : 0,
3604 return ERR_PTR(-EINVAL);
3607 /* If binding the object/GGTT view requires more space than the entire
3608 * aperture has, reject it early before evicting everything in a vain
3609 * attempt to find space.
3612 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%lu > %s aperture=%lu\n",
3613 ggtt_view ? ggtt_view->type : 0,
3615 flags & PIN_MAPPABLE ? "mappable" : "total",
3617 return ERR_PTR(-E2BIG);
3620 ret = i915_gem_object_get_pages(obj);
3622 return ERR_PTR(ret);
3624 i915_gem_object_pin_pages(obj);
3626 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3627 i915_gem_obj_lookup_or_create_vma(obj, vm);
3632 if (flags & PIN_HIGH) {
3633 search_flag = DRM_MM_SEARCH_BELOW;
3634 alloc_flag = DRM_MM_CREATE_TOP;
3636 search_flag = DRM_MM_SEARCH_DEFAULT;
3637 alloc_flag = DRM_MM_CREATE_DEFAULT;
3641 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3648 ret = i915_gem_evict_something(dev, vm, size, alignment,
3657 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3659 goto err_remove_node;
3662 trace_i915_vma_bind(vma, flags);
3663 ret = i915_vma_bind(vma, obj->cache_level, flags);
3665 goto err_remove_node;
3667 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3668 list_add_tail(&vma->mm_list, &vm->inactive_list);
3673 drm_mm_remove_node(&vma->node);
3675 i915_gem_vma_destroy(vma);
3678 i915_gem_object_unpin_pages(obj);
3683 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3686 /* If we don't have a page list set up, then we're not pinned
3687 * to GPU, and we can ignore the cache flush because it'll happen
3688 * again at bind time.
3690 if (obj->pages == NULL)
3694 * Stolen memory is always coherent with the GPU as it is explicitly
3695 * marked as wc by the system, or the system is cache-coherent.
3697 if (obj->stolen || obj->phys_handle)
3700 /* If the GPU is snooping the contents of the CPU cache,
3701 * we do not need to manually clear the CPU cache lines. However,
3702 * the caches are only snooped when the render cache is
3703 * flushed/invalidated. As we always have to emit invalidations
3704 * and flushes when moving into and out of the RENDER domain, correct
3705 * snooping behaviour occurs naturally as the result of our domain
3708 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3709 obj->cache_dirty = true;
3713 trace_i915_gem_object_clflush(obj);
3714 drm_clflush_sg(obj->pages);
3715 obj->cache_dirty = false;
3720 /** Flushes the GTT write domain for the object if it's dirty. */
3722 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3724 uint32_t old_write_domain;
3726 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3729 /* No actual flushing is required for the GTT write domain. Writes
3730 * to it immediately go to main memory as far as we know, so there's
3731 * no chipset flush. It also doesn't land in render cache.
3733 * However, we do have to enforce the order so that all writes through
3734 * the GTT land before any writes to the device, such as updates to
3739 old_write_domain = obj->base.write_domain;
3740 obj->base.write_domain = 0;
3742 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3744 trace_i915_gem_object_change_domain(obj,
3745 obj->base.read_domains,
3749 /** Flushes the CPU write domain for the object if it's dirty. */
3751 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3753 uint32_t old_write_domain;
3755 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3758 if (i915_gem_clflush_object(obj, obj->pin_display))
3759 i915_gem_chipset_flush(obj->base.dev);
3761 old_write_domain = obj->base.write_domain;
3762 obj->base.write_domain = 0;
3764 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3766 trace_i915_gem_object_change_domain(obj,
3767 obj->base.read_domains,
3772 * Moves a single object to the GTT read, and possibly write domain.
3774 * This function returns when the move is complete, including waiting on
3778 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3780 uint32_t old_write_domain, old_read_domains;
3781 struct i915_vma *vma;
3784 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3787 ret = i915_gem_object_wait_rendering(obj, !write);
3791 /* Flush and acquire obj->pages so that we are coherent through
3792 * direct access in memory with previous cached writes through
3793 * shmemfs and that our cache domain tracking remains valid.
3794 * For example, if the obj->filp was moved to swap without us
3795 * being notified and releasing the pages, we would mistakenly
3796 * continue to assume that the obj remained out of the CPU cached
3799 ret = i915_gem_object_get_pages(obj);
3803 i915_gem_object_flush_cpu_write_domain(obj);
3805 /* Serialise direct access to this object with the barriers for
3806 * coherent writes from the GPU, by effectively invalidating the
3807 * GTT domain upon first access.
3809 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3812 old_write_domain = obj->base.write_domain;
3813 old_read_domains = obj->base.read_domains;
3815 /* It should now be out of any other write domains, and we can update
3816 * the domain values for our changes.
3818 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3819 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3821 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3822 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3826 trace_i915_gem_object_change_domain(obj,
3830 /* And bump the LRU for this access */
3831 vma = i915_gem_obj_to_ggtt(obj);
3832 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3833 list_move_tail(&vma->mm_list,
3834 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3840 * Changes the cache-level of an object across all VMA.
3842 * After this function returns, the object will be in the new cache-level
3843 * across all GTT and the contents of the backing storage will be coherent,
3844 * with respect to the new cache-level. In order to keep the backing storage
3845 * coherent for all users, we only allow a single cache level to be set
3846 * globally on the object and prevent it from being changed whilst the
3847 * hardware is reading from the object. That is if the object is currently
3848 * on the scanout it will be set to uncached (or equivalent display
3849 * cache coherency) and all non-MOCS GPU access will also be uncached so
3850 * that all direct access to the scanout remains coherent.
3852 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3853 enum i915_cache_level cache_level)
3855 struct drm_device *dev = obj->base.dev;
3856 struct i915_vma *vma, *next;
3860 if (obj->cache_level == cache_level)
3863 /* Inspect the list of currently bound VMA and unbind any that would
3864 * be invalid given the new cache-level. This is principally to
3865 * catch the issue of the CS prefetch crossing page boundaries and
3866 * reading an invalid PTE on older architectures.
3868 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3869 if (!drm_mm_node_allocated(&vma->node))
3872 if (vma->pin_count) {
3873 DRM_DEBUG("can not change the cache level of pinned objects\n");
3877 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3878 ret = i915_vma_unbind(vma);
3885 /* We can reuse the existing drm_mm nodes but need to change the
3886 * cache-level on the PTE. We could simply unbind them all and
3887 * rebind with the correct cache-level on next use. However since
3888 * we already have a valid slot, dma mapping, pages etc, we may as
3889 * rewrite the PTE in the belief that doing so tramples upon less
3890 * state and so involves less work.
3893 /* Before we change the PTE, the GPU must not be accessing it.
3894 * If we wait upon the object, we know that all the bound
3895 * VMA are no longer active.
3897 ret = i915_gem_object_wait_rendering(obj, false);
3901 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3902 /* Access to snoopable pages through the GTT is
3903 * incoherent and on some machines causes a hard
3904 * lockup. Relinquish the CPU mmaping to force
3905 * userspace to refault in the pages and we can
3906 * then double check if the GTT mapping is still
3907 * valid for that pointer access.
3909 i915_gem_release_mmap(obj);
3911 /* As we no longer need a fence for GTT access,
3912 * we can relinquish it now (and so prevent having
3913 * to steal a fence from someone else on the next
3914 * fence request). Note GPU activity would have
3915 * dropped the fence as all snoopable access is
3916 * supposed to be linear.
3918 ret = i915_gem_object_put_fence(obj);
3922 /* We either have incoherent backing store and
3923 * so no GTT access or the architecture is fully
3924 * coherent. In such cases, existing GTT mmaps
3925 * ignore the cache bit in the PTE and we can
3926 * rewrite it without confusing the GPU or having
3927 * to force userspace to fault back in its mmaps.
3931 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3932 if (!drm_mm_node_allocated(&vma->node))
3935 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3941 list_for_each_entry(vma, &obj->vma_list, vma_link)
3942 vma->node.color = cache_level;
3943 obj->cache_level = cache_level;
3946 /* Flush the dirty CPU caches to the backing storage so that the
3947 * object is now coherent at its new cache level (with respect
3948 * to the access domain).
3950 if (obj->cache_dirty &&
3951 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3952 cpu_write_needs_clflush(obj)) {
3953 if (i915_gem_clflush_object(obj, true))
3954 i915_gem_chipset_flush(obj->base.dev);
3960 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3961 struct drm_file *file)
3963 struct drm_i915_gem_caching *args = data;
3964 struct drm_i915_gem_object *obj;
3966 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3967 if (&obj->base == NULL)
3970 switch (obj->cache_level) {
3971 case I915_CACHE_LLC:
3972 case I915_CACHE_L3_LLC:
3973 args->caching = I915_CACHING_CACHED;
3977 args->caching = I915_CACHING_DISPLAY;
3981 args->caching = I915_CACHING_NONE;
3985 drm_gem_object_unreference_unlocked(&obj->base);
3989 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3990 struct drm_file *file)
3992 struct drm_i915_private *dev_priv = dev->dev_private;
3993 struct drm_i915_gem_caching *args = data;
3994 struct drm_i915_gem_object *obj;
3995 enum i915_cache_level level;
3998 switch (args->caching) {
3999 case I915_CACHING_NONE:
4000 level = I915_CACHE_NONE;
4002 case I915_CACHING_CACHED:
4004 * Due to a HW issue on BXT A stepping, GPU stores via a
4005 * snooped mapping may leave stale data in a corresponding CPU
4006 * cacheline, whereas normally such cachelines would get
4009 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)
4012 level = I915_CACHE_LLC;
4014 case I915_CACHING_DISPLAY:
4015 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4021 intel_runtime_pm_get(dev_priv);
4023 ret = i915_mutex_lock_interruptible(dev);
4027 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4028 if (&obj->base == NULL) {
4033 ret = i915_gem_object_set_cache_level(obj, level);
4035 drm_gem_object_unreference(&obj->base);
4037 mutex_unlock(&dev->struct_mutex);
4039 intel_runtime_pm_put(dev_priv);
4045 * Prepare buffer for display plane (scanout, cursors, etc).
4046 * Can be called from an uninterruptible phase (modesetting) and allows
4047 * any flushes to be pipelined (for pageflips).
4050 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4052 struct intel_engine_cs *pipelined,
4053 struct drm_i915_gem_request **pipelined_request,
4054 const struct i915_ggtt_view *view)
4056 u32 old_read_domains, old_write_domain;
4059 ret = i915_gem_object_sync(obj, pipelined, pipelined_request);
4063 /* Mark the pin_display early so that we account for the
4064 * display coherency whilst setting up the cache domains.
4068 /* The display engine is not coherent with the LLC cache on gen6. As
4069 * a result, we make sure that the pinning that is about to occur is
4070 * done with uncached PTEs. This is lowest common denominator for all
4073 * However for gen6+, we could do better by using the GFDT bit instead
4074 * of uncaching, which would allow us to flush all the LLC-cached data
4075 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4077 ret = i915_gem_object_set_cache_level(obj,
4078 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4080 goto err_unpin_display;
4082 /* As the user may map the buffer once pinned in the display plane
4083 * (e.g. libkms for the bootup splash), we have to ensure that we
4084 * always use map_and_fenceable for all scanout buffers.
4086 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4087 view->type == I915_GGTT_VIEW_NORMAL ?
4090 goto err_unpin_display;
4092 i915_gem_object_flush_cpu_write_domain(obj);
4094 old_write_domain = obj->base.write_domain;
4095 old_read_domains = obj->base.read_domains;
4097 /* It should now be out of any other write domains, and we can update
4098 * the domain values for our changes.
4100 obj->base.write_domain = 0;
4101 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4103 trace_i915_gem_object_change_domain(obj,
4115 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4116 const struct i915_ggtt_view *view)
4118 if (WARN_ON(obj->pin_display == 0))
4121 i915_gem_object_ggtt_unpin_view(obj, view);
4127 * Moves a single object to the CPU read, and possibly write domain.
4129 * This function returns when the move is complete, including waiting on
4133 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4135 uint32_t old_write_domain, old_read_domains;
4138 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4141 ret = i915_gem_object_wait_rendering(obj, !write);
4145 i915_gem_object_flush_gtt_write_domain(obj);
4147 old_write_domain = obj->base.write_domain;
4148 old_read_domains = obj->base.read_domains;
4150 /* Flush the CPU cache if it's still invalid. */
4151 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4152 i915_gem_clflush_object(obj, false);
4154 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4157 /* It should now be out of any other write domains, and we can update
4158 * the domain values for our changes.
4160 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4162 /* If we're writing through the CPU, then the GPU read domains will
4163 * need to be invalidated at next use.
4166 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4167 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4170 trace_i915_gem_object_change_domain(obj,
4177 /* Throttle our rendering by waiting until the ring has completed our requests
4178 * emitted over 20 msec ago.
4180 * Note that if we were to use the current jiffies each time around the loop,
4181 * we wouldn't escape the function with any frames outstanding if the time to
4182 * render a frame was over 20ms.
4184 * This should get us reasonable parallelism between CPU and GPU but also
4185 * relatively low latency when blocking on a particular request to finish.
4188 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct drm_i915_file_private *file_priv = file->driver_priv;
4192 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4193 struct drm_i915_gem_request *request, *target = NULL;
4194 unsigned reset_counter;
4197 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4201 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4205 spin_lock(&file_priv->mm.lock);
4206 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4207 if (time_after_eq(request->emitted_jiffies, recent_enough))
4211 * Note that the request might not have been submitted yet.
4212 * In which case emitted_jiffies will be zero.
4214 if (!request->emitted_jiffies)
4219 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4221 i915_gem_request_reference(target);
4222 spin_unlock(&file_priv->mm.lock);
4227 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4229 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4231 i915_gem_request_unreference__unlocked(target);
4237 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4239 struct drm_i915_gem_object *obj = vma->obj;
4242 vma->node.start & (alignment - 1))
4245 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4248 if (flags & PIN_OFFSET_BIAS &&
4249 vma->node.start < (flags & PIN_OFFSET_MASK))
4255 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4257 struct drm_i915_gem_object *obj = vma->obj;
4258 bool mappable, fenceable;
4259 u32 fence_size, fence_alignment;
4261 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4264 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4269 fenceable = (vma->node.size == fence_size &&
4270 (vma->node.start & (fence_alignment - 1)) == 0);
4272 mappable = (vma->node.start + fence_size <=
4273 to_i915(obj->base.dev)->gtt.mappable_end);
4275 obj->map_and_fenceable = mappable && fenceable;
4279 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4280 struct i915_address_space *vm,
4281 const struct i915_ggtt_view *ggtt_view,
4285 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4286 struct i915_vma *vma;
4290 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4293 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4296 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4299 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4302 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4303 i915_gem_obj_to_vma(obj, vm);
4306 return PTR_ERR(vma);
4309 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4312 if (i915_vma_misplaced(vma, alignment, flags)) {
4313 WARN(vma->pin_count,
4314 "bo is already pinned in %s with incorrect alignment:"
4315 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4316 " obj->map_and_fenceable=%d\n",
4317 ggtt_view ? "ggtt" : "ppgtt",
4318 upper_32_bits(vma->node.start),
4319 lower_32_bits(vma->node.start),
4321 !!(flags & PIN_MAPPABLE),
4322 obj->map_and_fenceable);
4323 ret = i915_vma_unbind(vma);
4331 bound = vma ? vma->bound : 0;
4332 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4333 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4336 return PTR_ERR(vma);
4338 ret = i915_vma_bind(vma, obj->cache_level, flags);
4343 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4344 (bound ^ vma->bound) & GLOBAL_BIND) {
4345 __i915_vma_set_map_and_fenceable(vma);
4346 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4354 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4355 struct i915_address_space *vm,
4359 return i915_gem_object_do_pin(obj, vm,
4360 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4365 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4366 const struct i915_ggtt_view *view,
4370 if (WARN_ONCE(!view, "no view specified"))
4373 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4374 alignment, flags | PIN_GLOBAL);
4378 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4379 const struct i915_ggtt_view *view)
4381 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4384 WARN_ON(vma->pin_count == 0);
4385 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4391 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4392 struct drm_file *file)
4394 struct drm_i915_gem_busy *args = data;
4395 struct drm_i915_gem_object *obj;
4398 ret = i915_mutex_lock_interruptible(dev);
4402 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4403 if (&obj->base == NULL) {
4408 /* Count all active objects as busy, even if they are currently not used
4409 * by the gpu. Users of this interface expect objects to eventually
4410 * become non-busy without any further actions, therefore emit any
4411 * necessary flushes here.
4413 ret = i915_gem_object_flush_active(obj);
4417 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4418 args->busy = obj->active << 16;
4419 if (obj->last_write_req)
4420 args->busy |= obj->last_write_req->ring->id;
4423 drm_gem_object_unreference(&obj->base);
4425 mutex_unlock(&dev->struct_mutex);
4430 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4431 struct drm_file *file_priv)
4433 return i915_gem_ring_throttle(dev, file_priv);
4437 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4438 struct drm_file *file_priv)
4440 struct drm_i915_private *dev_priv = dev->dev_private;
4441 struct drm_i915_gem_madvise *args = data;
4442 struct drm_i915_gem_object *obj;
4445 switch (args->madv) {
4446 case I915_MADV_DONTNEED:
4447 case I915_MADV_WILLNEED:
4453 ret = i915_mutex_lock_interruptible(dev);
4457 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4458 if (&obj->base == NULL) {
4463 if (i915_gem_obj_is_pinned(obj)) {
4469 obj->tiling_mode != I915_TILING_NONE &&
4470 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4471 if (obj->madv == I915_MADV_WILLNEED)
4472 i915_gem_object_unpin_pages(obj);
4473 if (args->madv == I915_MADV_WILLNEED)
4474 i915_gem_object_pin_pages(obj);
4477 if (obj->madv != __I915_MADV_PURGED)
4478 obj->madv = args->madv;
4480 /* if the object is no longer attached, discard its backing storage */
4481 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4482 i915_gem_object_truncate(obj);
4484 args->retained = obj->madv != __I915_MADV_PURGED;
4487 drm_gem_object_unreference(&obj->base);
4489 mutex_unlock(&dev->struct_mutex);
4493 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4494 const struct drm_i915_gem_object_ops *ops)
4498 INIT_LIST_HEAD(&obj->global_list);
4499 for (i = 0; i < I915_NUM_RINGS; i++)
4500 INIT_LIST_HEAD(&obj->ring_list[i]);
4501 INIT_LIST_HEAD(&obj->obj_exec_link);
4502 INIT_LIST_HEAD(&obj->vma_list);
4503 INIT_LIST_HEAD(&obj->batch_pool_link);
4507 obj->fence_reg = I915_FENCE_REG_NONE;
4508 obj->madv = I915_MADV_WILLNEED;
4510 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4513 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4514 .get_pages = i915_gem_object_get_pages_gtt,
4515 .put_pages = i915_gem_object_put_pages_gtt,
4518 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4521 struct drm_i915_gem_object *obj;
4523 struct address_space *mapping;
4527 obj = i915_gem_object_alloc(dev);
4531 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4532 i915_gem_object_free(obj);
4537 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4538 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4539 /* 965gm cannot relocate objects above 4GiB. */
4540 mask &= ~__GFP_HIGHMEM;
4541 mask |= __GFP_DMA32;
4544 mapping = file_inode(obj->base.filp)->i_mapping;
4545 mapping_set_gfp_mask(mapping, mask);
4548 i915_gem_object_init(obj, &i915_gem_object_ops);
4550 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4551 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4554 /* On some devices, we can have the GPU use the LLC (the CPU
4555 * cache) for about a 10% performance improvement
4556 * compared to uncached. Graphics requests other than
4557 * display scanout are coherent with the CPU in
4558 * accessing this cache. This means in this mode we
4559 * don't need to clflush on the CPU side, and on the
4560 * GPU side we only need to flush internal caches to
4561 * get data visible to the CPU.
4563 * However, we maintain the display planes as UC, and so
4564 * need to rebind when first used as such.
4566 obj->cache_level = I915_CACHE_LLC;
4568 obj->cache_level = I915_CACHE_NONE;
4570 trace_i915_gem_object_create(obj);
4575 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4577 /* If we are the last user of the backing storage (be it shmemfs
4578 * pages or stolen etc), we know that the pages are going to be
4579 * immediately released. In this case, we can then skip copying
4580 * back the contents from the GPU.
4583 if (obj->madv != I915_MADV_WILLNEED)
4586 if (obj->base.vm_obj == NULL)
4589 /* At first glance, this looks racy, but then again so would be
4590 * userspace racing mmap against close. However, the first external
4591 * reference to the filp can only be obtained through the
4592 * i915_gem_mmap_ioctl() which safeguards us against the user
4593 * acquiring such a reference whilst we are in the middle of
4594 * freeing the object.
4597 return atomic_long_read(&obj->base.filp->f_count) == 1;
4603 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4605 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4606 struct drm_device *dev = obj->base.dev;
4607 struct drm_i915_private *dev_priv = dev->dev_private;
4608 struct i915_vma *vma, *next;
4610 intel_runtime_pm_get(dev_priv);
4612 trace_i915_gem_object_destroy(obj);
4614 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4618 ret = i915_vma_unbind(vma);
4619 if (WARN_ON(ret == -ERESTARTSYS)) {
4620 bool was_interruptible;
4622 was_interruptible = dev_priv->mm.interruptible;
4623 dev_priv->mm.interruptible = false;
4625 WARN_ON(i915_vma_unbind(vma));
4627 dev_priv->mm.interruptible = was_interruptible;
4631 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4632 * before progressing. */
4634 i915_gem_object_unpin_pages(obj);
4636 WARN_ON(obj->frontbuffer_bits);
4638 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4639 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4640 obj->tiling_mode != I915_TILING_NONE)
4641 i915_gem_object_unpin_pages(obj);
4643 if (WARN_ON(obj->pages_pin_count))
4644 obj->pages_pin_count = 0;
4645 if (discard_backing_storage(obj))
4646 obj->madv = I915_MADV_DONTNEED;
4647 i915_gem_object_put_pages(obj);
4648 i915_gem_object_free_mmap_offset(obj);
4653 if (obj->base.import_attach)
4654 drm_prime_gem_destroy(&obj->base, NULL);
4657 if (obj->ops->release)
4658 obj->ops->release(obj);
4660 drm_gem_object_release(&obj->base);
4661 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4664 i915_gem_object_free(obj);
4666 intel_runtime_pm_put(dev_priv);
4669 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4670 struct i915_address_space *vm)
4672 struct i915_vma *vma;
4673 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4674 if (i915_is_ggtt(vma->vm) &&
4675 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4683 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4684 const struct i915_ggtt_view *view)
4686 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4687 struct i915_vma *vma;
4689 if (WARN_ONCE(!view, "no view specified"))
4690 return ERR_PTR(-EINVAL);
4692 list_for_each_entry(vma, &obj->vma_list, vma_link)
4693 if (vma->vm == ggtt &&
4694 i915_ggtt_view_equal(&vma->ggtt_view, view))
4699 void i915_gem_vma_destroy(struct i915_vma *vma)
4701 struct i915_address_space *vm = NULL;
4702 WARN_ON(vma->node.allocated);
4704 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4705 if (!list_empty(&vma->exec_list))
4710 if (!i915_is_ggtt(vm))
4711 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4713 list_del(&vma->vma_link);
4719 i915_gem_stop_ringbuffers(struct drm_device *dev)
4721 struct drm_i915_private *dev_priv = dev->dev_private;
4722 struct intel_engine_cs *ring;
4725 for_each_ring(ring, dev_priv, i)
4726 dev_priv->gt.stop_ring(ring);
4730 i915_gem_suspend(struct drm_device *dev)
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4735 mutex_lock(&dev->struct_mutex);
4736 ret = i915_gpu_idle(dev);
4740 i915_gem_retire_requests(dev);
4742 i915_gem_stop_ringbuffers(dev);
4743 mutex_unlock(&dev->struct_mutex);
4745 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4746 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4748 flush_delayed_work(&dev_priv->mm.idle_work);
4751 /* Assert that we sucessfully flushed all the work and
4752 * reset the GPU back to its idle, low power state.
4754 WARN_ON(dev_priv->mm.busy);
4759 mutex_unlock(&dev->struct_mutex);
4763 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4765 struct intel_engine_cs *ring = req->ring;
4766 struct drm_device *dev = ring->dev;
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4769 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4772 if (!HAS_L3_DPF(dev) || !remap_info)
4775 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4780 * Note: We do not worry about the concurrent register cacheline hang
4781 * here because no other code should access these registers other than
4782 * at initialization time.
4784 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4785 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4786 intel_ring_emit(ring, reg_base + i);
4787 intel_ring_emit(ring, remap_info[i/4]);
4790 intel_ring_advance(ring);
4795 void i915_gem_init_swizzling(struct drm_device *dev)
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4799 if (INTEL_INFO(dev)->gen < 5 ||
4800 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4803 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4804 DISP_TILE_SURFACE_SWIZZLING);
4809 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4811 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4812 else if (IS_GEN7(dev))
4813 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4814 else if (IS_GEN8(dev))
4815 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4820 static void init_unused_ring(struct drm_device *dev, u32 base)
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4824 I915_WRITE(RING_CTL(base), 0);
4825 I915_WRITE(RING_HEAD(base), 0);
4826 I915_WRITE(RING_TAIL(base), 0);
4827 I915_WRITE(RING_START(base), 0);
4830 static void init_unused_rings(struct drm_device *dev)
4833 init_unused_ring(dev, PRB1_BASE);
4834 init_unused_ring(dev, SRB0_BASE);
4835 init_unused_ring(dev, SRB1_BASE);
4836 init_unused_ring(dev, SRB2_BASE);
4837 init_unused_ring(dev, SRB3_BASE);
4838 } else if (IS_GEN2(dev)) {
4839 init_unused_ring(dev, SRB0_BASE);
4840 init_unused_ring(dev, SRB1_BASE);
4841 } else if (IS_GEN3(dev)) {
4842 init_unused_ring(dev, PRB1_BASE);
4843 init_unused_ring(dev, PRB2_BASE);
4847 int i915_gem_init_rings(struct drm_device *dev)
4849 struct drm_i915_private *dev_priv = dev->dev_private;
4852 ret = intel_init_render_ring_buffer(dev);
4857 ret = intel_init_bsd_ring_buffer(dev);
4859 goto cleanup_render_ring;
4863 ret = intel_init_blt_ring_buffer(dev);
4865 goto cleanup_bsd_ring;
4868 if (HAS_VEBOX(dev)) {
4869 ret = intel_init_vebox_ring_buffer(dev);
4871 goto cleanup_blt_ring;
4874 if (HAS_BSD2(dev)) {
4875 ret = intel_init_bsd2_ring_buffer(dev);
4877 goto cleanup_vebox_ring;
4883 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4885 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4887 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4888 cleanup_render_ring:
4889 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4895 i915_gem_init_hw(struct drm_device *dev)
4897 struct drm_i915_private *dev_priv = dev->dev_private;
4898 struct intel_engine_cs *ring;
4902 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4906 /* Double layer security blanket, see i915_gem_init() */
4907 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4909 if (dev_priv->ellc_size)
4910 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4912 if (IS_HASWELL(dev))
4913 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4914 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4916 if (HAS_PCH_NOP(dev)) {
4917 if (IS_IVYBRIDGE(dev)) {
4918 u32 temp = I915_READ(GEN7_MSG_CTL);
4919 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4920 I915_WRITE(GEN7_MSG_CTL, temp);
4921 } else if (INTEL_INFO(dev)->gen >= 7) {
4922 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4923 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4924 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4928 i915_gem_init_swizzling(dev);
4931 * At least 830 can leave some of the unused rings
4932 * "active" (ie. head != tail) after resume which
4933 * will prevent c3 entry. Makes sure all unused rings
4936 init_unused_rings(dev);
4938 BUG_ON(!dev_priv->ring[RCS].default_context);
4940 ret = i915_ppgtt_init_hw(dev);
4942 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4946 /* Need to do basic initialisation of all rings first: */
4947 for_each_ring(ring, dev_priv, i) {
4948 ret = ring->init_hw(ring);
4953 /* We can't enable contexts until all firmware is loaded */
4954 if (HAS_GUC_UCODE(dev)) {
4955 #ifndef __DragonFly__
4956 ret = intel_guc_ucode_load(dev);
4962 * If we got an error and GuC submission is enabled, map
4963 * the error to -EIO so the GPU will be declared wedged.
4964 * OTOH, if we didn't intend to use the GuC anyway, just
4965 * discard the error and carry on.
4967 DRM_ERROR("Failed to initialize GuC, error %d%s\n", ret,
4968 i915.enable_guc_submission ? "" :
4970 ret = i915.enable_guc_submission ? -EIO : 0;
4977 * Increment the next seqno by 0x100 so we have a visible break
4978 * on re-initialisation
4980 ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4984 /* Now it is safe to go back round and do everything else: */
4985 for_each_ring(ring, dev_priv, i) {
4986 struct drm_i915_gem_request *req;
4988 WARN_ON(!ring->default_context);
4990 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
4992 i915_gem_cleanup_ringbuffer(dev);
4996 if (ring->id == RCS) {
4997 for (j = 0; j < NUM_L3_SLICES(dev); j++)
4998 i915_gem_l3_remap(req, j);
5001 ret = i915_ppgtt_init_ring(req);
5002 if (ret && ret != -EIO) {
5003 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
5004 i915_gem_request_cancel(req);
5005 i915_gem_cleanup_ringbuffer(dev);
5009 ret = i915_gem_context_enable(req);
5010 if (ret && ret != -EIO) {
5011 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
5012 i915_gem_request_cancel(req);
5013 i915_gem_cleanup_ringbuffer(dev);
5017 i915_add_request_no_flush(req);
5021 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5025 int i915_gem_init(struct drm_device *dev)
5027 struct drm_i915_private *dev_priv = dev->dev_private;
5030 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
5031 i915.enable_execlists);
5033 mutex_lock(&dev->struct_mutex);
5035 if (IS_VALLEYVIEW(dev)) {
5036 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5037 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
5038 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
5039 VLV_GTLC_ALLOWWAKEACK), 10))
5040 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5043 if (!i915.enable_execlists) {
5044 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5045 dev_priv->gt.init_rings = i915_gem_init_rings;
5046 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
5047 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
5049 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5050 dev_priv->gt.init_rings = intel_logical_rings_init;
5051 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
5052 dev_priv->gt.stop_ring = intel_logical_ring_stop;
5055 /* This is just a security blanket to placate dragons.
5056 * On some systems, we very sporadically observe that the first TLBs
5057 * used by the CS may be stale, despite us poking the TLB reset. If
5058 * we hold the forcewake during initialisation these problems
5059 * just magically go away.
5061 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5063 ret = i915_gem_init_userptr(dev);
5067 i915_gem_init_global_gtt(dev);
5069 ret = i915_gem_context_init(dev);
5073 ret = dev_priv->gt.init_rings(dev);
5077 ret = i915_gem_init_hw(dev);
5079 /* Allow ring initialisation to fail by marking the GPU as
5080 * wedged. But we only want to do this where the GPU is angry,
5081 * for all other failure, such as an allocation failure, bail.
5083 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5084 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5089 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5090 mutex_unlock(&dev->struct_mutex);
5096 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 struct intel_engine_cs *ring;
5102 for_each_ring(ring, dev_priv, i)
5103 dev_priv->gt.cleanup_ring(ring);
5105 if (i915.enable_execlists)
5107 * Neither the BIOS, ourselves or any other kernel
5108 * expects the system to be in execlists mode on startup,
5109 * so we need to reset the GPU back to legacy mode.
5111 intel_gpu_reset(dev);
5115 init_ring_lists(struct intel_engine_cs *ring)
5117 INIT_LIST_HEAD(&ring->active_list);
5118 INIT_LIST_HEAD(&ring->request_list);
5122 i915_gem_load(struct drm_device *dev)
5124 struct drm_i915_private *dev_priv = dev->dev_private;
5127 INIT_LIST_HEAD(&dev_priv->vm_list);
5128 INIT_LIST_HEAD(&dev_priv->context_list);
5129 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5130 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5131 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5132 for (i = 0; i < I915_NUM_RINGS; i++)
5133 init_ring_lists(&dev_priv->ring[i]);
5134 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5135 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5136 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5137 i915_gem_retire_work_handler);
5138 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5139 i915_gem_idle_work_handler);
5140 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5142 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5144 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5145 dev_priv->num_fence_regs = 32;
5146 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5147 dev_priv->num_fence_regs = 16;
5149 dev_priv->num_fence_regs = 8;
5151 if (intel_vgpu_active(dev))
5152 dev_priv->num_fence_regs =
5153 I915_READ(vgtif_reg(avail_rs.fence_num));
5156 * Set initial sequence number for requests.
5157 * Using this number allows the wraparound to happen early,
5158 * catching any obvious problems.
5160 dev_priv->next_seqno = ((u32)~0 - 0x1100);
5161 dev_priv->last_seqno = ((u32)~0 - 0x1101);
5163 /* Initialize fence registers to zero */
5164 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5165 i915_gem_restore_fences(dev);
5167 i915_gem_detect_bit_6_swizzle(dev);
5168 init_waitqueue_head(&dev_priv->pending_flip_queue);
5170 dev_priv->mm.interruptible = true;
5172 i915_gem_shrinker_init(dev_priv);
5174 lockinit(&dev_priv->fb_tracking.lock, "drmftl", 0, LK_CANRECURSE);
5177 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5179 struct drm_i915_file_private *file_priv = file->driver_priv;
5181 /* Clean up our request list when the client is going away, so that
5182 * later retire_requests won't dereference our soon-to-be-gone
5185 spin_lock(&file_priv->mm.lock);
5186 while (!list_empty(&file_priv->mm.request_list)) {
5187 struct drm_i915_gem_request *request;
5189 request = list_first_entry(&file_priv->mm.request_list,
5190 struct drm_i915_gem_request,
5192 list_del(&request->client_list);
5193 request->file_priv = NULL;
5195 spin_unlock(&file_priv->mm.lock);
5197 if (!list_empty(&file_priv->rps.link)) {
5198 lockmgr(&to_i915(dev)->rps.client_lock, LK_EXCLUSIVE);
5199 list_del(&file_priv->rps.link);
5200 lockmgr(&to_i915(dev)->rps.client_lock, LK_RELEASE);
5205 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
5206 vm_ooffset_t foff, struct ucred *cred, u_short *color)
5208 *color = 0; /* XXXKIB */
5213 i915_gem_pager_dtor(void *handle)
5215 struct drm_gem_object *obj;
5216 struct drm_device *dev;
5221 mutex_lock(&dev->struct_mutex);
5222 drm_gem_free_mmap_offset(obj);
5223 i915_gem_release_mmap(to_intel_bo(obj));
5224 drm_gem_object_unreference(obj);
5225 mutex_unlock(&dev->struct_mutex);
5228 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5230 struct drm_i915_file_private *file_priv;
5233 DRM_DEBUG_DRIVER("\n");
5235 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5239 file->driver_priv = file_priv;
5240 file_priv->dev_priv = dev->dev_private;
5241 file_priv->file = file;
5242 INIT_LIST_HEAD(&file_priv->rps.link);
5244 spin_init(&file_priv->mm.lock, "i915_priv");
5245 INIT_LIST_HEAD(&file_priv->mm.request_list);
5247 ret = i915_gem_context_open(dev, file);
5255 * i915_gem_track_fb - update frontbuffer tracking
5256 * @old: current GEM buffer for the frontbuffer slots
5257 * @new: new GEM buffer for the frontbuffer slots
5258 * @frontbuffer_bits: bitmask of frontbuffer slots
5260 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5261 * from @old and setting them in @new. Both @old and @new can be NULL.
5263 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5264 struct drm_i915_gem_object *new,
5265 unsigned frontbuffer_bits)
5268 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5269 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5270 old->frontbuffer_bits &= ~frontbuffer_bits;
5274 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5275 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5276 new->frontbuffer_bits |= frontbuffer_bits;
5280 /* All the new VM stuff */
5281 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5282 struct i915_address_space *vm)
5284 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5285 struct i915_vma *vma;
5287 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5289 list_for_each_entry(vma, &o->vma_list, vma_link) {
5290 if (i915_is_ggtt(vma->vm) &&
5291 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5294 return vma->node.start;
5297 WARN(1, "%s vma for this object not found.\n",
5298 i915_is_ggtt(vm) ? "global" : "ppgtt");
5302 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5303 const struct i915_ggtt_view *view)
5305 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5306 struct i915_vma *vma;
5308 list_for_each_entry(vma, &o->vma_list, vma_link)
5309 if (vma->vm == ggtt &&
5310 i915_ggtt_view_equal(&vma->ggtt_view, view))
5311 return vma->node.start;
5313 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5317 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5318 struct i915_address_space *vm)
5320 struct i915_vma *vma;
5322 list_for_each_entry(vma, &o->vma_list, vma_link) {
5323 if (i915_is_ggtt(vma->vm) &&
5324 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5326 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5333 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5334 const struct i915_ggtt_view *view)
5336 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5337 struct i915_vma *vma;
5339 list_for_each_entry(vma, &o->vma_list, vma_link)
5340 if (vma->vm == ggtt &&
5341 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5342 drm_mm_node_allocated(&vma->node))
5348 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5350 struct i915_vma *vma;
5352 list_for_each_entry(vma, &o->vma_list, vma_link)
5353 if (drm_mm_node_allocated(&vma->node))
5359 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5360 struct i915_address_space *vm)
5362 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5363 struct i915_vma *vma;
5365 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5367 BUG_ON(list_empty(&o->vma_list));
5369 list_for_each_entry(vma, &o->vma_list, vma_link) {
5370 if (i915_is_ggtt(vma->vm) &&
5371 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5374 return vma->node.size;
5379 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5381 struct i915_vma *vma;
5382 list_for_each_entry(vma, &obj->vma_list, vma_link)
5383 if (vma->pin_count > 0)
5390 /* Allocate a new GEM object and fill it with the supplied data */
5391 struct drm_i915_gem_object *
5392 i915_gem_object_create_from_data(struct drm_device *dev,
5393 const void *data, size_t size)
5395 struct drm_i915_gem_object *obj;
5396 struct sg_table *sg;
5400 obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5401 if (IS_ERR_OR_NULL(obj))
5404 ret = i915_gem_object_set_to_cpu_domain(obj, true);
5408 ret = i915_gem_object_get_pages(obj);
5412 i915_gem_object_pin_pages(obj);
5414 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5415 i915_gem_object_unpin_pages(obj);
5417 if (WARN_ON(bytes != size)) {
5418 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5426 drm_gem_object_unreference(&obj->base);
5427 return ERR_PTR(ret);