sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, B2, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_ifpoll.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #include <sys/rman.h>
  63 #include <sys/serialize.h>
  64 #include <sys/socket.h>
  65 #include <sys/sockio.h>
  66 #include <sys/sysctl.h>
  67
  68 #include <netinet/ip.h>
  69 #include <netinet/tcp.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_poll.h>
  78 #include <net/if_types.h>
  79 #include <net/ifq_var.h>
  80 #include <net/vlan/if_vlan_var.h>
  81 #include <net/vlan/if_vlan_ether.h>
  82
  83 #include <dev/netif/mii_layer/mii.h>
  84 #include <dev/netif/mii_layer/miivar.h>
  85 #include <dev/netif/mii_layer/brgphyreg.h>
  86
  87 #include <bus/pci/pcireg.h>
  88 #include <bus/pci/pcivar.h>
  89
  90 #include "miibus_if.h"
  91
  92 #include <dev/netif/bce/if_bcereg.h>
  93 #include <dev/netif/bce/if_bcefw.h>
  94
  95 #define BCE_MSI_CKINTVL         ((10 * hz) / 1000)      /* 10ms */
  96
  97 /****************************************************************************/
  98 /* PCI Device ID Table                                                      */
  99 /*                                                                          */
 100 /* Used by bce_probe() to identify the devices supported by this driver.    */
 101 /****************************************************************************/
 102 #define BCE_DEVDESC_MAX         64
 103
 104 static struct bce_type bce_devs[] = {
 105         /* BCM5706C Controllers and OEM boards. */
 106         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 107                 "HP NC370T Multifunction Gigabit Server Adapter" },
 108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 109                 "HP NC370i Multifunction Gigabit Server Adapter" },
 110         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 111                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 112         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 113                 "HP NC371i Multifunction Gigabit Server Adapter" },
 114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 115                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 116
 117         /* BCM5706S controllers and OEM boards. */
 118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 119                 "HP NC370F Multifunction Gigabit Server Adapter" },
 120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 121                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 122
 123         /* BCM5708C controllers and OEM boards. */
 124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 125                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 126         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 127                 "HP NC373i Multifunction Gigabit Server Adapter" },
 128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 129                 "HP NC374m PCIe Multifunction Adapter" },
 130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 131                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 132
 133         /* BCM5708S controllers and OEM boards. */
 134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 135                 "HP NC373m Multifunction Gigabit Server Adapter" },
 136         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 137                 "HP NC373i Multifunction Gigabit Server Adapter" },
 138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 139                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 141                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 142
 143         /* BCM5709C controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 145                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 147                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 149                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 150
 151         /* BCM5709S controllers and OEM boards. */
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 153                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 155                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 157                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 158
 159         /* BCM5716 controllers and OEM boards. */
 160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 161                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 162
 163         { 0, 0, 0, 0, NULL }
 164 };
 165
 166
 167 /****************************************************************************/
 168 /* Supported Flash NVRAM device data.                                       */
 169 /****************************************************************************/
 170 static const struct flash_spec flash_table[] =
 171 {
 172 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 173 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 174
 175         /* Slow EEPROM */
 176         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 177          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 178          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 179          "EEPROM - slow"},
 180         /* Expansion entry 0001 */
 181         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 184          "Entry 0001"},
 185         /* Saifun SA25F010 (non-buffered flash) */
 186         /* strap, cfg1, & write1 need updates */
 187         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 190          "Non-buffered flash (128kB)"},
 191         /* Saifun SA25F020 (non-buffered flash) */
 192         /* strap, cfg1, & write1 need updates */
 193         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 194          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 195          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 196          "Non-buffered flash (256kB)"},
 197         /* Expansion entry 0100 */
 198         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 199          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 200          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 201          "Entry 0100"},
 202         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 203         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 204          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 205          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 206          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 207         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 208         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 209          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 210          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 211          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 212         /* Saifun SA25F005 (non-buffered flash) */
 213         /* strap, cfg1, & write1 need updates */
 214         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 215          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 216          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 217          "Non-buffered flash (64kB)"},
 218         /* Fast EEPROM */
 219         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 220          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 221          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 222          "EEPROM - fast"},
 223         /* Expansion entry 1001 */
 224         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 225          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 226          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 227          "Entry 1001"},
 228         /* Expansion entry 1010 */
 229         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 230          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 231          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 232          "Entry 1010"},
 233         /* ATMEL AT45DB011B (buffered flash) */
 234         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 235          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 236          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 237          "Buffered flash (128kB)"},
 238         /* Expansion entry 1100 */
 239         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 240          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 241          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 242          "Entry 1100"},
 243         /* Expansion entry 1101 */
 244         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 245          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 246          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 247          "Entry 1101"},
 248         /* Ateml Expansion entry 1110 */
 249         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 250          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 251          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 252          "Entry 1110 (Atmel)"},
 253         /* ATMEL AT45DB021B (buffered flash) */
 254         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 255          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 256          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 257          "Buffered flash (256kB)"},
 258 };
 259
 260 /*
 261  * The BCM5709 controllers transparently handle the
 262  * differences between Atmel 264 byte pages and all
 263  * flash devices which use 256 byte pages, so no
 264  * logical-to-physical mapping is required in the
 265  * driver.
 266  */
 267 static struct flash_spec flash_5709 = {
 268         .flags          = BCE_NV_BUFFERED,
 269         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 270         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 271         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 272         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 273         .name           = "5709/5716 buffered flash (256kB)",
 274 };
 275
 276
 277 /****************************************************************************/
 278 /* DragonFly device entry points.                                           */
 279 /****************************************************************************/
 280 static int      bce_probe(device_t);
 281 static int      bce_attach(device_t);
 282 static int      bce_detach(device_t);
 283 static void     bce_shutdown(device_t);
 284 static int      bce_miibus_read_reg(device_t, int, int);
 285 static int      bce_miibus_write_reg(device_t, int, int, int);
 286 static void     bce_miibus_statchg(device_t);
 287
 288 /****************************************************************************/
 289 /* BCE Register/Memory Access Routines                                      */
 290 /****************************************************************************/
 291 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 292 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 293 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 294 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 295 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 296
 297 /****************************************************************************/
 298 /* BCE NVRAM Access Routines                                                */
 299 /****************************************************************************/
 300 static int      bce_acquire_nvram_lock(struct bce_softc *);
 301 static int      bce_release_nvram_lock(struct bce_softc *);
 302 static void     bce_enable_nvram_access(struct bce_softc *);
 303 static void     bce_disable_nvram_access(struct bce_softc *);
 304 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 305                     uint32_t);
 306 static int      bce_init_nvram(struct bce_softc *);
 307 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 308 static int      bce_nvram_test(struct bce_softc *);
 309
 310 /****************************************************************************/
 311 /* BCE DMA Allocate/Free Routines                                           */
 312 /****************************************************************************/
 313 static int      bce_dma_alloc(struct bce_softc *);
 314 static void     bce_dma_free(struct bce_softc *);
 315 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 316
 317 /****************************************************************************/
 318 /* BCE Firmware Synchronization and Load                                    */
 319 /****************************************************************************/
 320 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 321 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 322                     uint32_t, uint32_t);
 323 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 324                     struct fw_info *);
 325 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
 326 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
 327 static void     bce_start_rxp_cpu(struct bce_softc *);
 328 static void     bce_init_rxp_cpu(struct bce_softc *);
 329 static void     bce_init_txp_cpu(struct bce_softc *);
 330 static void     bce_init_tpat_cpu(struct bce_softc *);
 331 static void     bce_init_cp_cpu(struct bce_softc *);
 332 static void     bce_init_com_cpu(struct bce_softc *);
 333 static void     bce_init_cpus(struct bce_softc *);
 334
 335 static void     bce_stop(struct bce_softc *);
 336 static int      bce_reset(struct bce_softc *, uint32_t);
 337 static int      bce_chipinit(struct bce_softc *);
 338 static int      bce_blockinit(struct bce_softc *);
 339 static void     bce_probe_pci_caps(struct bce_softc *);
 340 static void     bce_print_adapter_info(struct bce_softc *);
 341 static void     bce_get_media(struct bce_softc *);
 342 static void     bce_mgmt_init(struct bce_softc *);
 343 static int      bce_init_ctx(struct bce_softc *);
 344 static void     bce_get_mac_addr(struct bce_softc *);
 345 static void     bce_set_mac_addr(struct bce_softc *);
 346 static void     bce_set_rx_mode(struct bce_softc *);
 347 static void     bce_coal_change(struct bce_softc *);
 348 static void     bce_setup_serialize(struct bce_softc *);
 349 static void     bce_serialize_skipmain(struct bce_softc *);
 350 static void     bce_deserialize_skipmain(struct bce_softc *);
 351 static void     bce_set_timer_cpuid(struct bce_softc *, boolean_t);
 352
 353 static int      bce_create_tx_ring(struct bce_tx_ring *);
 354 static void     bce_destroy_tx_ring(struct bce_tx_ring *);
 355 static void     bce_init_tx_context(struct bce_tx_ring *);
 356 static int      bce_init_tx_chain(struct bce_tx_ring *);
 357 static void     bce_free_tx_chain(struct bce_tx_ring *);
 358 static void     bce_xmit(struct bce_tx_ring *);
 359 static int      bce_encap(struct bce_tx_ring *, struct mbuf **, int *);
 360 static int      bce_tso_setup(struct bce_tx_ring *, struct mbuf **,
 361                     uint16_t *, uint16_t *);
 362
 363 static int      bce_create_rx_ring(struct bce_rx_ring *);
 364 static void     bce_destroy_rx_ring(struct bce_rx_ring *);
 365 static void     bce_init_rx_context(struct bce_rx_ring *);
 366 static int      bce_init_rx_chain(struct bce_rx_ring *);
 367 static void     bce_free_rx_chain(struct bce_rx_ring *);
 368 static int      bce_newbuf_std(struct bce_rx_ring *, uint16_t *, uint16_t *,
 369                     uint32_t *, int);
 370 static void     bce_setup_rxdesc_std(struct bce_rx_ring *, uint16_t,
 371                     uint32_t *);
 372
 373 static void     bce_start(struct ifnet *, struct ifaltq_subque *);
 374 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 375 static void     bce_watchdog(struct ifaltq_subque *);
 376 static int      bce_ifmedia_upd(struct ifnet *);
 377 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 378 static void     bce_init(void *);
 379 #ifdef IFPOLL_ENABLE
 380 static void     bce_npoll(struct ifnet *, struct ifpoll_info *);
 381 static void     bce_npoll_rx(struct ifnet *, void *, int);
 382 static void     bce_npoll_tx(struct ifnet *, void *, int);
 383 static void     bce_npoll_status(struct ifnet *);
 384 #endif
 385 static void     bce_serialize(struct ifnet *, enum ifnet_serialize);
 386 static void     bce_deserialize(struct ifnet *, enum ifnet_serialize);
 387 static int      bce_tryserialize(struct ifnet *, enum ifnet_serialize);
 388 #ifdef INVARIANTS
 389 static void     bce_serialize_assert(struct ifnet *, enum ifnet_serialize,
 390                     boolean_t);
 391 #endif
 392
 393 static void     bce_intr(struct bce_softc *);
 394 static void     bce_intr_legacy(void *);
 395 static void     bce_intr_msi(void *);
 396 static void     bce_intr_msi_oneshot(void *);
 397 static void     bce_tx_intr(struct bce_tx_ring *, uint16_t);
 398 static void     bce_rx_intr(struct bce_rx_ring *, int, uint16_t);
 399 static void     bce_phy_intr(struct bce_softc *);
 400 static void     bce_disable_intr(struct bce_softc *);
 401 static void     bce_enable_intr(struct bce_softc *);
 402 static void     bce_reenable_intr(struct bce_rx_ring *);
 403 static void     bce_check_msi(void *);
 404
 405 static void     bce_stats_update(struct bce_softc *);
 406 static void     bce_tick(void *);
 407 static void     bce_tick_serialized(struct bce_softc *);
 408 static void     bce_pulse(void *);
 409
 410 static void     bce_add_sysctls(struct bce_softc *);
 411 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 412 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 413 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 414 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 415 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 416 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 417 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 418 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 419 #ifdef IFPOLL_ENABLE
 420 static int      bce_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
 421 #endif
 422 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 423                     uint32_t *, uint32_t);
 424
 425 /*
 426  * NOTE:
 427  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 428  * takes 1023 as the TX ticks limit.  However, using 1023 will
 429  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 430  * there is _no_ network activity on the NIC.
 431  */
 432 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 433 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 434 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 435 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 436 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 437 static uint32_t bce_rx_bds = 0;                 /* bcm: 6 */
 438 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
 439 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
 440
 441 static int      bce_tx_wreg = 8;
 442
 443 static int      bce_msi_enable = 1;
 444
 445 static int      bce_rx_pages = RX_PAGES_DEFAULT;
 446 static int      bce_tx_pages = TX_PAGES_DEFAULT;
 447
 448 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 449 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 450 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 451 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 452 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 453 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 454 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 455 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 456 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
 457 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 458 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 459 TUNABLE_INT("hw.bce.tx_wreg", &bce_tx_wreg);
 460
 461 /****************************************************************************/
 462 /* DragonFly device dispatch table.                                         */
 463 /****************************************************************************/
 464 static device_method_t bce_methods[] = {
 465         /* Device interface */
 466         DEVMETHOD(device_probe,         bce_probe),
 467         DEVMETHOD(device_attach,        bce_attach),
 468         DEVMETHOD(device_detach,        bce_detach),
 469         DEVMETHOD(device_shutdown,      bce_shutdown),
 470
 471         /* bus interface */
 472         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 473         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 474
 475         /* MII interface */
 476         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 477         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 478         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 479
 480         DEVMETHOD_END
 481 };
 482
 483 static driver_t bce_driver = {
 484         "bce",
 485         bce_methods,
 486         sizeof(struct bce_softc)
 487 };
 488
 489 static devclass_t bce_devclass;
 490
 491
 492 DECLARE_DUMMY_MODULE(if_bce);
 493 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 494 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 495 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 496
 497
 498 /****************************************************************************/
 499 /* Device probe function.                                                   */
 500 /*                                                                          */
 501 /* Compares the device to the driver's list of supported devices and        */
 502 /* reports back to the OS whether this is the right driver for the device.  */
 503 /*                                                                          */
 504 /* Returns:                                                                 */
 505 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 506 /****************************************************************************/
 507 static int
 508 bce_probe(device_t dev)
 509 {
 510         struct bce_type *t;
 511         uint16_t vid, did, svid, sdid;
 512
 513         /* Get the data for the device to be probed. */
 514         vid  = pci_get_vendor(dev);
 515         did  = pci_get_device(dev);
 516         svid = pci_get_subvendor(dev);
 517         sdid = pci_get_subdevice(dev);
 518
 519         /* Look through the list of known devices for a match. */
 520         for (t = bce_devs; t->bce_name != NULL; ++t) {
 521                 if (vid == t->bce_vid && did == t->bce_did &&
 522                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 523                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 524                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 525                         char *descbuf;
 526
 527                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 528
 529                         /* Print out the device identity. */
 530                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 531                                   t->bce_name,
 532                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 533
 534                         device_set_desc_copy(dev, descbuf);
 535                         kfree(descbuf, M_TEMP);
 536                         return 0;
 537                 }
 538         }
 539         return ENXIO;
 540 }
 541
 542
 543 /****************************************************************************/
 544 /* PCI Capabilities Probe Function.                                         */
 545 /*                                                                          */
 546 /* Walks the PCI capabiites list for the device to find what features are   */
 547 /* supported.                                                               */
 548 /*                                                                          */
 549 /* Returns:                                                                 */
 550 /*   None.                                                                  */
 551 /****************************************************************************/
 552 static void
 553 bce_print_adapter_info(struct bce_softc *sc)
 554 {
 555         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 556
 557         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 558                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 559
 560         /* Bus info. */
 561         if (sc->bce_flags & BCE_PCIE_FLAG) {
 562                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 563                 switch (sc->link_speed) {
 564                 case 1:
 565                         kprintf("2.5Gbps); ");
 566                         break;
 567                 case 2:
 568                         kprintf("5Gbps); ");
 569                         break;
 570                 default:
 571                         kprintf("Unknown link speed); ");
 572                         break;
 573                 }
 574         } else {
 575                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 576                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 577                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 578                     sc->bus_speed_mhz);
 579         }
 580
 581         /* Firmware version and device features. */
 582         kprintf("B/C (%s)", sc->bce_bc_ver);
 583
 584         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 585             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 586                 kprintf("; Flags(");
 587                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 588                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 589                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 590                         kprintf(" 2.5G");
 591                 kprintf(")");
 592         }
 593         kprintf("\n");
 594 }
 595
 596
 597 /****************************************************************************/
 598 /* PCI Capabilities Probe Function.                                         */
 599 /*                                                                          */
 600 /* Walks the PCI capabiites list for the device to find what features are   */
 601 /* supported.                                                               */
 602 /*                                                                          */
 603 /* Returns:                                                                 */
 604 /*   None.                                                                  */
 605 /****************************************************************************/
 606 static void
 607 bce_probe_pci_caps(struct bce_softc *sc)
 608 {
 609         device_t dev = sc->bce_dev;
 610         uint8_t ptr;
 611
 612         if (pci_is_pcix(dev))
 613                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 614
 615         ptr = pci_get_pciecap_ptr(dev);
 616         if (ptr) {
 617                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 618
 619                 sc->link_speed = link_status & 0xf;
 620                 sc->link_width = (link_status >> 4) & 0x3f;
 621                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 622                 sc->bce_flags |= BCE_PCIE_FLAG;
 623         }
 624 }
 625
 626
 627 /****************************************************************************/
 628 /* Device attach function.                                                  */
 629 /*                                                                          */
 630 /* Allocates device resources, performs secondary chip identification,      */
 631 /* resets and initializes the hardware, and initializes driver instance     */
 632 /* variables.                                                               */
 633 /*                                                                          */
 634 /* Returns:                                                                 */
 635 /*   0 on success, positive value on failure.                               */
 636 /****************************************************************************/
 637 static int
 638 bce_attach(device_t dev)
 639 {
 640         struct bce_softc *sc = device_get_softc(dev);
 641         struct ifnet *ifp = &sc->arpcom.ac_if;
 642         uint32_t val;
 643         u_int irq_flags;
 644         void (*irq_handle)(void *);
 645         int rid, rc = 0;
 646         int i, j;
 647         struct mii_probe_args mii_args;
 648         uintptr_t mii_priv = 0;
 649 #ifdef IFPOLL_ENABLE
 650         int offset, offset_def;
 651 #endif
 652
 653         sc->bce_dev = dev;
 654         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 655
 656         lwkt_serialize_init(&sc->main_serialize);
 657
 658         pci_enable_busmaster(dev);
 659
 660         bce_probe_pci_caps(sc);
 661
 662         /* Allocate PCI memory resources. */
 663         rid = PCIR_BAR(0);
 664         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 665                                                  RF_ACTIVE | PCI_RF_DENSE);
 666         if (sc->bce_res_mem == NULL) {
 667                 device_printf(dev, "PCI memory allocation failed\n");
 668                 return ENXIO;
 669         }
 670         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 671         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 672
 673         /*
 674          * Configure byte swap and enable indirect register access.
 675          * Rely on CPU to do target byte swapping on big endian systems.
 676          * Access to registers outside of PCI configurtion space are not
 677          * valid until this is done.
 678          */
 679         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 680                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 681                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 682
 683         /* Save ASIC revsion info. */
 684         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 685
 686         /* Weed out any non-production controller revisions. */
 687         switch (BCE_CHIP_ID(sc)) {
 688         case BCE_CHIP_ID_5706_A0:
 689         case BCE_CHIP_ID_5706_A1:
 690         case BCE_CHIP_ID_5708_A0:
 691         case BCE_CHIP_ID_5708_B0:
 692         case BCE_CHIP_ID_5709_A0:
 693         case BCE_CHIP_ID_5709_B0:
 694         case BCE_CHIP_ID_5709_B1:
 695 #ifdef foo
 696         /* 5709C B2 seems to work fine */
 697         case BCE_CHIP_ID_5709_B2:
 698 #endif
 699                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 700                               BCE_CHIP_ID(sc));
 701                 rc = ENODEV;
 702                 goto fail;
 703         }
 704
 705         mii_priv |= BRGPHY_FLAG_WIRESPEED;
 706         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 707                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
 708                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
 709                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
 710         } else {
 711                 mii_priv |= BRGPHY_FLAG_BER_BUG;
 712         }
 713
 714         /*
 715          * Find the base address for shared memory access.
 716          * Newer versions of bootcode use a signature and offset
 717          * while older versions use a fixed address.
 718          */
 719         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 720         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 721             BCE_SHM_HDR_SIGNATURE_SIG) {
 722                 /* Multi-port devices use different offsets in shared memory. */
 723                 sc->bce_shmem_base = REG_RD_IND(sc,
 724                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 725         } else {
 726                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 727         }
 728
 729         /* Fetch the bootcode revision. */
 730         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 731         for (i = 0, j = 0; i < 3; i++) {
 732                 uint8_t num;
 733                 int k, skip0;
 734
 735                 num = (uint8_t)(val >> (24 - (i * 8)));
 736                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 737                         if (num >= k || !skip0 || k == 1) {
 738                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 739                                 skip0 = 0;
 740                         }
 741                 }
 742                 if (i != 2)
 743                         sc->bce_bc_ver[j++] = '.';
 744         }
 745
 746         /* Check if any management firwmare is running. */
 747         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 748         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 749                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 750
 751                 /* Allow time for firmware to enter the running state. */
 752                 for (i = 0; i < 30; i++) {
 753                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 754                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 755                                 break;
 756                         DELAY(10000);
 757                 }
 758         }
 759
 760         /* Check the current bootcode state. */
 761         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 762             BCE_CONDITION_MFW_RUN_MASK;
 763         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 764             val != BCE_CONDITION_MFW_RUN_NONE) {
 765                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 766
 767                 for (i = 0, j = 0; j < 3; j++) {
 768                         val = bce_reg_rd_ind(sc, addr + j * 4);
 769                         val = bswap32(val);
 770                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 771                         i += 4;
 772                 }
 773         }
 774
 775         /* Get PCI bus information (speed and type). */
 776         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 777         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 778                 uint32_t clkreg;
 779
 780                 sc->bce_flags |= BCE_PCIX_FLAG;
 781
 782                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 783                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 784                 switch (clkreg) {
 785                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 786                         sc->bus_speed_mhz = 133;
 787                         break;
 788
 789                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 790                         sc->bus_speed_mhz = 100;
 791                         break;
 792
 793                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 794                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 795                         sc->bus_speed_mhz = 66;
 796                         break;
 797
 798                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 799                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 800                         sc->bus_speed_mhz = 50;
 801                         break;
 802
 803                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 804                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 805                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 806                         sc->bus_speed_mhz = 33;
 807                         break;
 808                 }
 809         } else {
 810                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 811                         sc->bus_speed_mhz = 66;
 812                 else
 813                         sc->bus_speed_mhz = 33;
 814         }
 815
 816         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 817                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 818
 819         /* Reset the controller. */
 820         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 821         if (rc != 0)
 822                 goto fail;
 823
 824         /* Initialize the controller. */
 825         rc = bce_chipinit(sc);
 826         if (rc != 0) {
 827                 device_printf(dev, "Controller initialization failed!\n");
 828                 goto fail;
 829         }
 830
 831         /* Perform NVRAM test. */
 832         rc = bce_nvram_test(sc);
 833         if (rc != 0) {
 834                 device_printf(dev, "NVRAM test failed!\n");
 835                 goto fail;
 836         }
 837
 838         /* Fetch the permanent Ethernet MAC address. */
 839         bce_get_mac_addr(sc);
 840
 841         /*
 842          * Trip points control how many BDs
 843          * should be ready before generating an
 844          * interrupt while ticks control how long
 845          * a BD can sit in the chain before
 846          * generating an interrupt.  Set the default
 847          * values for the RX and TX rings.
 848          */
 849
 850 #ifdef BCE_DRBUG
 851         /* Force more frequent interrupts. */
 852         sc->bce_tx_quick_cons_trip_int = 1;
 853         sc->bce_tx_quick_cons_trip     = 1;
 854         sc->bce_tx_ticks_int           = 0;
 855         sc->bce_tx_ticks               = 0;
 856
 857         sc->bce_rx_quick_cons_trip_int = 1;
 858         sc->bce_rx_quick_cons_trip     = 1;
 859         sc->bce_rx_ticks_int           = 0;
 860         sc->bce_rx_ticks               = 0;
 861 #else
 862         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 863         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 864         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 865         sc->bce_tx_ticks               = bce_tx_ticks;
 866
 867         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 868         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 869         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 870         sc->bce_rx_ticks               = bce_rx_ticks;
 871 #endif
 872
 873         /* Update statistics once every second. */
 874         sc->bce_stats_ticks = 1000000 & 0xffff00;
 875
 876         /* Find the media type for the adapter. */
 877         bce_get_media(sc);
 878
 879         /* Find out RX/TX ring count */
 880         sc->rx_ring_cnt = 1; /* XXX */
 881         sc->tx_ring_cnt = 1; /* XXX */
 882
 883         /* Allocate DMA memory resources. */
 884         rc = bce_dma_alloc(sc);
 885         if (rc != 0) {
 886                 device_printf(dev, "DMA resource allocation failed!\n");
 887                 goto fail;
 888         }
 889
 890 #ifdef IFPOLL_ENABLE
 891         /*
 892          * NPOLLING RX/TX CPU offset
 893          */
 894         if (sc->rx_ring_cnt == ncpus2) {
 895                 offset = 0;
 896         } else {
 897                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 898                 offset = device_getenv_int(dev, "npoll.offset", offset_def);
 899                 if (offset >= ncpus2 ||
 900                     offset % sc->rx_ring_cnt != 0) {
 901                         device_printf(dev, "invalid npoll.offset %d, use %d\n",
 902                             offset, offset_def);
 903                         offset = offset_def;
 904                 }
 905         }
 906         sc->npoll_ofs = offset;
 907 #endif
 908
 909         /* Allocate PCI IRQ resources. */
 910         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
 911             &sc->bce_irq_rid, &irq_flags);
 912
 913         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 914             &sc->bce_irq_rid, irq_flags);
 915         if (sc->bce_res_irq == NULL) {
 916                 device_printf(dev, "PCI map interrupt failed\n");
 917                 rc = ENXIO;
 918                 goto fail;
 919         }
 920
 921         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
 922                 irq_handle = bce_intr_legacy;
 923         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
 924                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 925                         irq_handle = bce_intr_msi_oneshot;
 926                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
 927                 } else {
 928                         irq_handle = bce_intr_msi;
 929                         sc->bce_flags |= BCE_CHECK_MSI_FLAG;
 930                 }
 931         } else {
 932                 panic("%s: unsupported intr type %d",
 933                     device_get_nameunit(dev), sc->bce_irq_type);
 934         }
 935
 936         /* Setup serializer */
 937         bce_setup_serialize(sc);
 938
 939         /* Initialize the ifnet interface. */
 940         ifp->if_softc = sc;
 941         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 942         ifp->if_ioctl = bce_ioctl;
 943         ifp->if_start = bce_start;
 944         ifp->if_init = bce_init;
 945         ifp->if_serialize = bce_serialize;
 946         ifp->if_deserialize = bce_deserialize;
 947         ifp->if_tryserialize = bce_tryserialize;
 948 #ifdef INVARIANTS
 949         ifp->if_serialize_assert = bce_serialize_assert;
 950 #endif
 951 #ifdef IFPOLL_ENABLE
 952         ifp->if_npoll = bce_npoll;
 953 #endif
 954
 955         ifp->if_mtu = ETHERMTU;
 956         ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
 957         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 958         ifp->if_capenable = ifp->if_capabilities;
 959
 960         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 961                 ifp->if_baudrate = IF_Gbps(2.5);
 962         else
 963                 ifp->if_baudrate = IF_Gbps(1);
 964
 965         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(&sc->tx_rings[0]));
 966         ifq_set_ready(&ifp->if_snd);
 967         ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
 968
 969         /*
 970          * Look for our PHY.
 971          */
 972         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
 973         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
 974         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
 975         mii_args.mii_priv = mii_priv;
 976
 977         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
 978         if (rc != 0) {
 979                 device_printf(dev, "PHY probe failed!\n");
 980                 goto fail;
 981         }
 982
 983         /* Attach to the Ethernet interface list. */
 984         ether_ifattach(ifp, sc->eaddr, NULL);
 985
 986         callout_init_mp(&sc->bce_tick_callout);
 987         callout_init_mp(&sc->bce_pulse_callout);
 988         callout_init_mp(&sc->bce_ckmsi_callout);
 989
 990         /* Hookup IRQ last. */
 991         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
 992             &sc->bce_intrhand, &sc->main_serialize);
 993         if (rc != 0) {
 994                 device_printf(dev, "Failed to setup IRQ!\n");
 995                 ether_ifdetach(ifp);
 996                 goto fail;
 997         }
 998
 999         sc->bce_intr_cpuid = rman_get_cpuid(sc->bce_res_irq);
1000
1001         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1002                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1003                 struct bce_tx_ring *txr = &sc->tx_rings[i];
1004
1005                 ifsq_set_cpuid(ifsq, sc->bce_intr_cpuid); /* XXX */
1006                 ifsq_set_priv(ifsq, txr);
1007                 txr->ifsq = ifsq;
1008
1009                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, bce_watchdog);
1010         }
1011
1012         /* Set timer CPUID */
1013         bce_set_timer_cpuid(sc, FALSE);
1014
1015         /* Add the supported sysctls to the kernel. */
1016         bce_add_sysctls(sc);
1017
1018         /*
1019          * The chip reset earlier notified the bootcode that
1020          * a driver is present.  We now need to start our pulse
1021          * routine so that the bootcode is reminded that we're
1022          * still running.
1023          */
1024         bce_pulse(sc);
1025
1026         /* Get the firmware running so IPMI still works */
1027         bce_mgmt_init(sc);
1028
1029         if (bootverbose)
1030                 bce_print_adapter_info(sc);
1031
1032         return 0;
1033 fail:
1034         bce_detach(dev);
1035         return(rc);
1036 }
1037
1038
1039 /****************************************************************************/
1040 /* Device detach function.                                                  */
1041 /*                                                                          */
1042 /* Stops the controller, resets the controller, and releases resources.     */
1043 /*                                                                          */
1044 /* Returns:                                                                 */
1045 /*   0 on success, positive value on failure.                               */
1046 /****************************************************************************/
1047 static int
1048 bce_detach(device_t dev)
1049 {
1050         struct bce_softc *sc = device_get_softc(dev);
1051
1052         if (device_is_attached(dev)) {
1053                 struct ifnet *ifp = &sc->arpcom.ac_if;
1054                 uint32_t msg;
1055
1056                 ifnet_serialize_all(ifp);
1057
1058                 /* Stop and reset the controller. */
1059                 callout_stop(&sc->bce_pulse_callout);
1060                 bce_stop(sc);
1061                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1062                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1063                 else
1064                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1065                 bce_reset(sc, msg);
1066                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1067
1068                 ifnet_deserialize_all(ifp);
1069
1070                 ether_ifdetach(ifp);
1071         }
1072
1073         /* If we have a child device on the MII bus remove it too. */
1074         if (sc->bce_miibus)
1075                 device_delete_child(dev, sc->bce_miibus);
1076         bus_generic_detach(dev);
1077
1078         if (sc->bce_res_irq != NULL) {
1079                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1080                     sc->bce_res_irq);
1081         }
1082
1083         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1084                 pci_release_msi(dev);
1085
1086         if (sc->bce_res_mem != NULL) {
1087                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1088                                      sc->bce_res_mem);
1089         }
1090
1091         bce_dma_free(sc);
1092
1093         if (sc->bce_sysctl_tree != NULL)
1094                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1095
1096         if (sc->serializes != NULL)
1097                 kfree(sc->serializes, M_DEVBUF);
1098
1099         return 0;
1100 }
1101
1102
1103 /****************************************************************************/
1104 /* Device shutdown function.                                                */
1105 /*                                                                          */
1106 /* Stops and resets the controller.                                         */
1107 /*                                                                          */
1108 /* Returns:                                                                 */
1109 /*   Nothing                                                                */
1110 /****************************************************************************/
1111 static void
1112 bce_shutdown(device_t dev)
1113 {
1114         struct bce_softc *sc = device_get_softc(dev);
1115         struct ifnet *ifp = &sc->arpcom.ac_if;
1116         uint32_t msg;
1117
1118         ifnet_serialize_all(ifp);
1119
1120         bce_stop(sc);
1121         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1122                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1123         else
1124                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1125         bce_reset(sc, msg);
1126
1127         ifnet_deserialize_all(ifp);
1128 }
1129
1130
1131 /****************************************************************************/
1132 /* Indirect register read.                                                  */
1133 /*                                                                          */
1134 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1135 /* configuration space.  Using this mechanism avoids issues with posted     */
1136 /* reads but is much slower than memory-mapped I/O.                         */
1137 /*                                                                          */
1138 /* Returns:                                                                 */
1139 /*   The value of the register.                                             */
1140 /****************************************************************************/
1141 static uint32_t
1142 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1143 {
1144         device_t dev = sc->bce_dev;
1145
1146         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1147         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1148 }
1149
1150
1151 /****************************************************************************/
1152 /* Indirect register write.                                                 */
1153 /*                                                                          */
1154 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1155 /* configuration space.  Using this mechanism avoids issues with posted     */
1156 /* writes but is muchh slower than memory-mapped I/O.                       */
1157 /*                                                                          */
1158 /* Returns:                                                                 */
1159 /*   Nothing.                                                               */
1160 /****************************************************************************/
1161 static void
1162 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1163 {
1164         device_t dev = sc->bce_dev;
1165
1166         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1167         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1168 }
1169
1170
1171 /****************************************************************************/
1172 /* Shared memory write.                                                     */
1173 /*                                                                          */
1174 /* Writes NetXtreme II shared memory region.                                */
1175 /*                                                                          */
1176 /* Returns:                                                                 */
1177 /*   Nothing.                                                               */
1178 /****************************************************************************/
1179 static void
1180 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1181 {
1182         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1183 }
1184
1185
1186 /****************************************************************************/
1187 /* Shared memory read.                                                      */
1188 /*                                                                          */
1189 /* Reads NetXtreme II shared memory region.                                 */
1190 /*                                                                          */
1191 /* Returns:                                                                 */
1192 /*   The 32 bit value read.                                                 */
1193 /****************************************************************************/
1194 static u32
1195 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1196 {
1197         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1198 }
1199
1200
1201 /****************************************************************************/
1202 /* Context memory write.                                                    */
1203 /*                                                                          */
1204 /* The NetXtreme II controller uses context memory to track connection      */
1205 /* information for L2 and higher network protocols.                         */
1206 /*                                                                          */
1207 /* Returns:                                                                 */
1208 /*   Nothing.                                                               */
1209 /****************************************************************************/
1210 static void
1211 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1212     uint32_t ctx_val)
1213 {
1214         uint32_t idx, offset = ctx_offset + cid_addr;
1215         uint32_t val, retry_cnt = 5;
1216
1217         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1218             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1219                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1220                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1221
1222                 for (idx = 0; idx < retry_cnt; idx++) {
1223                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1224                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1225                                 break;
1226                         DELAY(5);
1227                 }
1228
1229                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1230                         device_printf(sc->bce_dev,
1231                             "Unable to write CTX memory: "
1232                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1233                             cid_addr, ctx_offset);
1234                 }
1235         } else {
1236                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1237                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1238         }
1239 }
1240
1241
1242 /****************************************************************************/
1243 /* PHY register read.                                                       */
1244 /*                                                                          */
1245 /* Implements register reads on the MII bus.                                */
1246 /*                                                                          */
1247 /* Returns:                                                                 */
1248 /*   The value of the register.                                             */
1249 /****************************************************************************/
1250 static int
1251 bce_miibus_read_reg(device_t dev, int phy, int reg)
1252 {
1253         struct bce_softc *sc = device_get_softc(dev);
1254         uint32_t val;
1255         int i;
1256
1257         /* Make sure we are accessing the correct PHY address. */
1258         KASSERT(phy == sc->bce_phy_addr,
1259             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1260
1261         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1262                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1263                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1264
1265                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1266                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1267
1268                 DELAY(40);
1269         }
1270
1271         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1272               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1273               BCE_EMAC_MDIO_COMM_START_BUSY;
1274         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1275
1276         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1277                 DELAY(10);
1278
1279                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1280                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1281                         DELAY(5);
1282
1283                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1284                         val &= BCE_EMAC_MDIO_COMM_DATA;
1285                         break;
1286                 }
1287         }
1288
1289         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1290                 if_printf(&sc->arpcom.ac_if,
1291                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1292                           phy, reg);
1293                 val = 0x0;
1294         } else {
1295                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1296         }
1297
1298         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1299                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1300                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1301
1302                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1303                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1304
1305                 DELAY(40);
1306         }
1307         return (val & 0xffff);
1308 }
1309
1310
1311 /****************************************************************************/
1312 /* PHY register write.                                                      */
1313 /*                                                                          */
1314 /* Implements register writes on the MII bus.                               */
1315 /*                                                                          */
1316 /* Returns:                                                                 */
1317 /*   The value of the register.                                             */
1318 /****************************************************************************/
1319 static int
1320 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1321 {
1322         struct bce_softc *sc = device_get_softc(dev);
1323         uint32_t val1;
1324         int i;
1325
1326         /* Make sure we are accessing the correct PHY address. */
1327         KASSERT(phy == sc->bce_phy_addr,
1328             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1329
1330         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1331                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1332                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1333
1334                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1335                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1336
1337                 DELAY(40);
1338         }
1339
1340         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1341                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1342                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1343         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1344
1345         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1346                 DELAY(10);
1347
1348                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1349                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1350                         DELAY(5);
1351                         break;
1352                 }
1353         }
1354
1355         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1356                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1357
1358         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1359                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1360                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1361
1362                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1363                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1364
1365                 DELAY(40);
1366         }
1367         return 0;
1368 }
1369
1370
1371 /****************************************************************************/
1372 /* MII bus status change.                                                   */
1373 /*                                                                          */
1374 /* Called by the MII bus driver when the PHY establishes link to set the    */
1375 /* MAC interface registers.                                                 */
1376 /*                                                                          */
1377 /* Returns:                                                                 */
1378 /*   Nothing.                                                               */
1379 /****************************************************************************/
1380 static void
1381 bce_miibus_statchg(device_t dev)
1382 {
1383         struct bce_softc *sc = device_get_softc(dev);
1384         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1385
1386         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1387
1388         /*
1389          * Set MII or GMII interface based on the speed negotiated
1390          * by the PHY.
1391          */
1392         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1393             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1394                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1395         } else {
1396                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1397         }
1398
1399         /*
1400          * Set half or full duplex based on the duplicity negotiated
1401          * by the PHY.
1402          */
1403         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1404                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1405         } else {
1406                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1407         }
1408 }
1409
1410
1411 /****************************************************************************/
1412 /* Acquire NVRAM lock.                                                      */
1413 /*                                                                          */
1414 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1415 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1416 /* for use by the driver.                                                   */
1417 /*                                                                          */
1418 /* Returns:                                                                 */
1419 /*   0 on success, positive value on failure.                               */
1420 /****************************************************************************/
1421 static int
1422 bce_acquire_nvram_lock(struct bce_softc *sc)
1423 {
1424         uint32_t val;
1425         int j;
1426
1427         /* Request access to the flash interface. */
1428         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1429         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1430                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1431                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1432                         break;
1433
1434                 DELAY(5);
1435         }
1436
1437         if (j >= NVRAM_TIMEOUT_COUNT) {
1438                 return EBUSY;
1439         }
1440         return 0;
1441 }
1442
1443
1444 /****************************************************************************/
1445 /* Release NVRAM lock.                                                      */
1446 /*                                                                          */
1447 /* When the caller is finished accessing NVRAM the lock must be released.   */
1448 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1449 /* for use by the driver.                                                   */
1450 /*                                                                          */
1451 /* Returns:                                                                 */
1452 /*   0 on success, positive value on failure.                               */
1453 /****************************************************************************/
1454 static int
1455 bce_release_nvram_lock(struct bce_softc *sc)
1456 {
1457         int j;
1458         uint32_t val;
1459
1460         /*
1461          * Relinquish nvram interface.
1462          */
1463         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1464
1465         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1466                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1467                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1468                         break;
1469
1470                 DELAY(5);
1471         }
1472
1473         if (j >= NVRAM_TIMEOUT_COUNT) {
1474                 return EBUSY;
1475         }
1476         return 0;
1477 }
1478
1479
1480 /****************************************************************************/
1481 /* Enable NVRAM access.                                                     */
1482 /*                                                                          */
1483 /* Before accessing NVRAM for read or write operations the caller must      */
1484 /* enabled NVRAM access.                                                    */
1485 /*                                                                          */
1486 /* Returns:                                                                 */
1487 /*   Nothing.                                                               */
1488 /****************************************************************************/
1489 static void
1490 bce_enable_nvram_access(struct bce_softc *sc)
1491 {
1492         uint32_t val;
1493
1494         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1495         /* Enable both bits, even on read. */
1496         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1497                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1498 }
1499
1500
1501 /****************************************************************************/
1502 /* Disable NVRAM access.                                                    */
1503 /*                                                                          */
1504 /* When the caller is finished accessing NVRAM access must be disabled.     */
1505 /*                                                                          */
1506 /* Returns:                                                                 */
1507 /*   Nothing.                                                               */
1508 /****************************************************************************/
1509 static void
1510 bce_disable_nvram_access(struct bce_softc *sc)
1511 {
1512         uint32_t val;
1513
1514         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1515
1516         /* Disable both bits, even after read. */
1517         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1518                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1519 }
1520
1521
1522 /****************************************************************************/
1523 /* Read a dword (32 bits) from NVRAM.                                       */
1524 /*                                                                          */
1525 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1526 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1527 /*                                                                          */
1528 /* Returns:                                                                 */
1529 /*   0 on success and the 32 bit value read, positive value on failure.     */
1530 /****************************************************************************/
1531 static int
1532 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1533                      uint32_t cmd_flags)
1534 {
1535         uint32_t cmd;
1536         int i, rc = 0;
1537
1538         /* Build the command word. */
1539         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1540
1541         /* Calculate the offset for buffered flash. */
1542         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1543                 offset = ((offset / sc->bce_flash_info->page_size) <<
1544                           sc->bce_flash_info->page_bits) +
1545                          (offset % sc->bce_flash_info->page_size);
1546         }
1547
1548         /*
1549          * Clear the DONE bit separately, set the address to read,
1550          * and issue the read.
1551          */
1552         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1553         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1554         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1555
1556         /* Wait for completion. */
1557         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1558                 uint32_t val;
1559
1560                 DELAY(5);
1561
1562                 val = REG_RD(sc, BCE_NVM_COMMAND);
1563                 if (val & BCE_NVM_COMMAND_DONE) {
1564                         val = REG_RD(sc, BCE_NVM_READ);
1565
1566                         val = be32toh(val);
1567                         memcpy(ret_val, &val, 4);
1568                         break;
1569                 }
1570         }
1571
1572         /* Check for errors. */
1573         if (i >= NVRAM_TIMEOUT_COUNT) {
1574                 if_printf(&sc->arpcom.ac_if,
1575                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1576                           offset);
1577                 rc = EBUSY;
1578         }
1579         return rc;
1580 }
1581
1582
1583 /****************************************************************************/
1584 /* Initialize NVRAM access.                                                 */
1585 /*                                                                          */
1586 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1587 /* access that device.                                                      */
1588 /*                                                                          */
1589 /* Returns:                                                                 */
1590 /*   0 on success, positive value on failure.                               */
1591 /****************************************************************************/
1592 static int
1593 bce_init_nvram(struct bce_softc *sc)
1594 {
1595         uint32_t val;
1596         int j, entry_count, rc = 0;
1597         const struct flash_spec *flash;
1598
1599         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1600             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1601                 sc->bce_flash_info = &flash_5709;
1602                 goto bce_init_nvram_get_flash_size;
1603         }
1604
1605         /* Determine the selected interface. */
1606         val = REG_RD(sc, BCE_NVM_CFG1);
1607
1608         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1609
1610         /*
1611          * Flash reconfiguration is required to support additional
1612          * NVRAM devices not directly supported in hardware.
1613          * Check if the flash interface was reconfigured
1614          * by the bootcode.
1615          */
1616
1617         if (val & 0x40000000) {
1618                 /* Flash interface reconfigured by bootcode. */
1619                 for (j = 0, flash = flash_table; j < entry_count;
1620                      j++, flash++) {
1621                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1622                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1623                                 sc->bce_flash_info = flash;
1624                                 break;
1625                         }
1626                 }
1627         } else {
1628                 /* Flash interface not yet reconfigured. */
1629                 uint32_t mask;
1630
1631                 if (val & (1 << 23))
1632                         mask = FLASH_BACKUP_STRAP_MASK;
1633                 else
1634                         mask = FLASH_STRAP_MASK;
1635
1636                 /* Look for the matching NVRAM device configuration data. */
1637                 for (j = 0, flash = flash_table; j < entry_count;
1638                      j++, flash++) {
1639                         /* Check if the device matches any of the known devices. */
1640                         if ((val & mask) == (flash->strapping & mask)) {
1641                                 /* Found a device match. */
1642                                 sc->bce_flash_info = flash;
1643
1644                                 /* Request access to the flash interface. */
1645                                 rc = bce_acquire_nvram_lock(sc);
1646                                 if (rc != 0)
1647                                         return rc;
1648
1649                                 /* Reconfigure the flash interface. */
1650                                 bce_enable_nvram_access(sc);
1651                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1652                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1653                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1654                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1655                                 bce_disable_nvram_access(sc);
1656                                 bce_release_nvram_lock(sc);
1657                                 break;
1658                         }
1659                 }
1660         }
1661
1662         /* Check if a matching device was found. */
1663         if (j == entry_count) {
1664                 sc->bce_flash_info = NULL;
1665                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1666                 return ENODEV;
1667         }
1668
1669 bce_init_nvram_get_flash_size:
1670         /* Write the flash config data to the shared memory interface. */
1671         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1672             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1673         if (val)
1674                 sc->bce_flash_size = val;
1675         else
1676                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1677
1678         return rc;
1679 }
1680
1681
1682 /****************************************************************************/
1683 /* Read an arbitrary range of data from NVRAM.                              */
1684 /*                                                                          */
1685 /* Prepares the NVRAM interface for access and reads the requested data     */
1686 /* into the supplied buffer.                                                */
1687 /*                                                                          */
1688 /* Returns:                                                                 */
1689 /*   0 on success and the data read, positive value on failure.             */
1690 /****************************************************************************/
1691 static int
1692 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1693                int buf_size)
1694 {
1695         uint32_t cmd_flags, offset32, len32, extra;
1696         int rc = 0;
1697
1698         if (buf_size == 0)
1699                 return 0;
1700
1701         /* Request access to the flash interface. */
1702         rc = bce_acquire_nvram_lock(sc);
1703         if (rc != 0)
1704                 return rc;
1705
1706         /* Enable access to flash interface */
1707         bce_enable_nvram_access(sc);
1708
1709         len32 = buf_size;
1710         offset32 = offset;
1711         extra = 0;
1712
1713         cmd_flags = 0;
1714
1715         /* XXX should we release nvram lock if read_dword() fails? */
1716         if (offset32 & 3) {
1717                 uint8_t buf[4];
1718                 uint32_t pre_len;
1719
1720                 offset32 &= ~3;
1721                 pre_len = 4 - (offset & 3);
1722
1723                 if (pre_len >= len32) {
1724                         pre_len = len32;
1725                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1726                 } else {
1727                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1728                 }
1729
1730                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1731                 if (rc)
1732                         return rc;
1733
1734                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1735
1736                 offset32 += 4;
1737                 ret_buf += pre_len;
1738                 len32 -= pre_len;
1739         }
1740
1741         if (len32 & 3) {
1742                 extra = 4 - (len32 & 3);
1743                 len32 = (len32 + 4) & ~3;
1744         }
1745
1746         if (len32 == 4) {
1747                 uint8_t buf[4];
1748
1749                 if (cmd_flags)
1750                         cmd_flags = BCE_NVM_COMMAND_LAST;
1751                 else
1752                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1753                                     BCE_NVM_COMMAND_LAST;
1754
1755                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1756
1757                 memcpy(ret_buf, buf, 4 - extra);
1758         } else if (len32 > 0) {
1759                 uint8_t buf[4];
1760
1761                 /* Read the first word. */
1762                 if (cmd_flags)
1763                         cmd_flags = 0;
1764                 else
1765                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1766
1767                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1768
1769                 /* Advance to the next dword. */
1770                 offset32 += 4;
1771                 ret_buf += 4;
1772                 len32 -= 4;
1773
1774                 while (len32 > 4 && rc == 0) {
1775                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1776
1777                         /* Advance to the next dword. */
1778                         offset32 += 4;
1779                         ret_buf += 4;
1780                         len32 -= 4;
1781                 }
1782
1783                 if (rc)
1784                         goto bce_nvram_read_locked_exit;
1785
1786                 cmd_flags = BCE_NVM_COMMAND_LAST;
1787                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1788
1789                 memcpy(ret_buf, buf, 4 - extra);
1790         }
1791
1792 bce_nvram_read_locked_exit:
1793         /* Disable access to flash interface and release the lock. */
1794         bce_disable_nvram_access(sc);
1795         bce_release_nvram_lock(sc);
1796
1797         return rc;
1798 }
1799
1800
1801 /****************************************************************************/
1802 /* Verifies that NVRAM is accessible and contains valid data.               */
1803 /*                                                                          */
1804 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1805 /* correct.                                                                 */
1806 /*                                                                          */
1807 /* Returns:                                                                 */
1808 /*   0 on success, positive value on failure.                               */
1809 /****************************************************************************/
1810 static int
1811 bce_nvram_test(struct bce_softc *sc)
1812 {
1813         uint32_t buf[BCE_NVRAM_SIZE / 4];
1814         uint32_t magic, csum;
1815         uint8_t *data = (uint8_t *)buf;
1816         int rc = 0;
1817
1818         /*
1819          * Check that the device NVRAM is valid by reading
1820          * the magic value at offset 0.
1821          */
1822         rc = bce_nvram_read(sc, 0, data, 4);
1823         if (rc != 0)
1824                 return rc;
1825
1826         magic = be32toh(buf[0]);
1827         if (magic != BCE_NVRAM_MAGIC) {
1828                 if_printf(&sc->arpcom.ac_if,
1829                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1830                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1831                 return ENODEV;
1832         }
1833
1834         /*
1835          * Verify that the device NVRAM includes valid
1836          * configuration data.
1837          */
1838         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1839         if (rc != 0)
1840                 return rc;
1841
1842         csum = ether_crc32_le(data, 0x100);
1843         if (csum != BCE_CRC32_RESIDUAL) {
1844                 if_printf(&sc->arpcom.ac_if,
1845                           "Invalid Manufacturing Information NVRAM CRC! "
1846                           "Expected: 0x%08X, Found: 0x%08X\n",
1847                           BCE_CRC32_RESIDUAL, csum);
1848                 return ENODEV;
1849         }
1850
1851         csum = ether_crc32_le(data + 0x100, 0x100);
1852         if (csum != BCE_CRC32_RESIDUAL) {
1853                 if_printf(&sc->arpcom.ac_if,
1854                           "Invalid Feature Configuration Information "
1855                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1856                           BCE_CRC32_RESIDUAL, csum);
1857                 rc = ENODEV;
1858         }
1859         return rc;
1860 }
1861
1862
1863 /****************************************************************************/
1864 /* Identifies the current media type of the controller and sets the PHY     */
1865 /* address.                                                                 */
1866 /*                                                                          */
1867 /* Returns:                                                                 */
1868 /*   Nothing.                                                               */
1869 /****************************************************************************/
1870 static void
1871 bce_get_media(struct bce_softc *sc)
1872 {
1873         uint32_t val;
1874
1875         sc->bce_phy_addr = 1;
1876
1877         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1878             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1879                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1880                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1881                 uint32_t strap;
1882
1883                 /*
1884                  * The BCM5709S is software configurable
1885                  * for Copper or SerDes operation.
1886                  */
1887                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1888                         return;
1889                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1890                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1891                         return;
1892                 }
1893
1894                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1895                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1896                 } else {
1897                         strap =
1898                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1899                 }
1900
1901                 if (pci_get_function(sc->bce_dev) == 0) {
1902                         switch (strap) {
1903                         case 0x4:
1904                         case 0x5:
1905                         case 0x6:
1906                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1907                                 break;
1908                         }
1909                 } else {
1910                         switch (strap) {
1911                         case 0x1:
1912                         case 0x2:
1913                         case 0x4:
1914                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1915                                 break;
1916                         }
1917                 }
1918         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1919                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1920         }
1921
1922         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1923                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1924                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1925                         sc->bce_phy_addr = 2;
1926                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1927                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1928                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1929                 }
1930         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1931             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1932                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1933         }
1934 }
1935
1936
1937 static void
1938 bce_destroy_tx_ring(struct bce_tx_ring *txr)
1939 {
1940         int i;
1941
1942         /* Destroy the TX buffer descriptor DMA stuffs. */
1943         if (txr->tx_bd_chain_tag != NULL) {
1944                 for (i = 0; i < txr->tx_pages; i++) {
1945                         if (txr->tx_bd_chain[i] != NULL) {
1946                                 bus_dmamap_unload(txr->tx_bd_chain_tag,
1947                                     txr->tx_bd_chain_map[i]);
1948                                 bus_dmamem_free(txr->tx_bd_chain_tag,
1949                                     txr->tx_bd_chain[i],
1950                                     txr->tx_bd_chain_map[i]);
1951                         }
1952                 }
1953                 bus_dma_tag_destroy(txr->tx_bd_chain_tag);
1954         }
1955
1956         /* Destroy the TX mbuf DMA stuffs. */
1957         if (txr->tx_mbuf_tag != NULL) {
1958                 for (i = 0; i < TOTAL_TX_BD(txr); i++) {
1959                         /* Must have been unloaded in bce_stop() */
1960                         KKASSERT(txr->tx_mbuf_ptr[i] == NULL);
1961                         bus_dmamap_destroy(txr->tx_mbuf_tag,
1962                             txr->tx_mbuf_map[i]);
1963                 }
1964                 bus_dma_tag_destroy(txr->tx_mbuf_tag);
1965         }
1966
1967         if (txr->tx_bd_chain_map != NULL)
1968                 kfree(txr->tx_bd_chain_map, M_DEVBUF);
1969         if (txr->tx_bd_chain != NULL)
1970                 kfree(txr->tx_bd_chain, M_DEVBUF);
1971         if (txr->tx_bd_chain_paddr != NULL)
1972                 kfree(txr->tx_bd_chain_paddr, M_DEVBUF);
1973
1974         if (txr->tx_mbuf_map != NULL)
1975                 kfree(txr->tx_mbuf_map, M_DEVBUF);
1976         if (txr->tx_mbuf_ptr != NULL)
1977                 kfree(txr->tx_mbuf_ptr, M_DEVBUF);
1978 }
1979
1980
1981 static void
1982 bce_destroy_rx_ring(struct bce_rx_ring *rxr)
1983 {
1984         int i;
1985
1986         /* Destroy the RX buffer descriptor DMA stuffs. */
1987         if (rxr->rx_bd_chain_tag != NULL) {
1988                 for (i = 0; i < rxr->rx_pages; i++) {
1989                         if (rxr->rx_bd_chain[i] != NULL) {
1990                                 bus_dmamap_unload(rxr->rx_bd_chain_tag,
1991                                     rxr->rx_bd_chain_map[i]);
1992                                 bus_dmamem_free(rxr->rx_bd_chain_tag,
1993                                     rxr->rx_bd_chain[i],
1994                                     rxr->rx_bd_chain_map[i]);
1995                         }
1996                 }
1997                 bus_dma_tag_destroy(rxr->rx_bd_chain_tag);
1998         }
1999
2000         /* Destroy the RX mbuf DMA stuffs. */
2001         if (rxr->rx_mbuf_tag != NULL) {
2002                 for (i = 0; i < TOTAL_RX_BD(rxr); i++) {
2003                         /* Must have been unloaded in bce_stop() */
2004                         KKASSERT(rxr->rx_mbuf_ptr[i] == NULL);
2005                         bus_dmamap_destroy(rxr->rx_mbuf_tag,
2006                             rxr->rx_mbuf_map[i]);
2007                 }
2008                 bus_dmamap_destroy(rxr->rx_mbuf_tag, rxr->rx_mbuf_tmpmap);
2009                 bus_dma_tag_destroy(rxr->rx_mbuf_tag);
2010         }
2011
2012         if (rxr->rx_bd_chain_map != NULL)
2013                 kfree(rxr->rx_bd_chain_map, M_DEVBUF);
2014         if (rxr->rx_bd_chain != NULL)
2015                 kfree(rxr->rx_bd_chain, M_DEVBUF);
2016         if (rxr->rx_bd_chain_paddr != NULL)
2017                 kfree(rxr->rx_bd_chain_paddr, M_DEVBUF);
2018
2019         if (rxr->rx_mbuf_map != NULL)
2020                 kfree(rxr->rx_mbuf_map, M_DEVBUF);
2021         if (rxr->rx_mbuf_ptr != NULL)
2022                 kfree(rxr->rx_mbuf_ptr, M_DEVBUF);
2023         if (rxr->rx_mbuf_paddr != NULL)
2024                 kfree(rxr->rx_mbuf_paddr, M_DEVBUF);
2025 }
2026
2027
2028 /****************************************************************************/
2029 /* Free any DMA memory owned by the driver.                                 */
2030 /*                                                                          */
2031 /* Scans through each data structre that requires DMA memory and frees      */
2032 /* the memory if allocated.                                                 */
2033 /*                                                                          */
2034 /* Returns:                                                                 */
2035 /*   Nothing.                                                               */
2036 /****************************************************************************/
2037 static void
2038 bce_dma_free(struct bce_softc *sc)
2039 {
2040         int i;
2041
2042         /* Destroy the status block. */
2043         if (sc->status_tag != NULL) {
2044                 if (sc->status_block != NULL) {
2045                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2046                         bus_dmamem_free(sc->status_tag, sc->status_block,
2047                                         sc->status_map);
2048                 }
2049                 bus_dma_tag_destroy(sc->status_tag);
2050         }
2051
2052         /* Destroy the statistics block. */
2053         if (sc->stats_tag != NULL) {
2054                 if (sc->stats_block != NULL) {
2055                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2056                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2057                                         sc->stats_map);
2058                 }
2059                 bus_dma_tag_destroy(sc->stats_tag);
2060         }
2061
2062         /* Destroy the CTX DMA stuffs. */
2063         if (sc->ctx_tag != NULL) {
2064                 for (i = 0; i < sc->ctx_pages; i++) {
2065                         if (sc->ctx_block[i] != NULL) {
2066                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2067                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2068                                                 sc->ctx_map[i]);
2069                         }
2070                 }
2071                 bus_dma_tag_destroy(sc->ctx_tag);
2072         }
2073
2074         /* Free TX rings */
2075         if (sc->tx_rings != NULL) {
2076                 for (i = 0; i < sc->tx_ring_cnt; ++i)
2077                         bce_destroy_tx_ring(&sc->tx_rings[i]);
2078                 kfree(sc->tx_rings, M_DEVBUF);
2079         }
2080
2081         /* Free RX rings */
2082         if (sc->rx_rings != NULL) {
2083                 for (i = 0; i < sc->rx_ring_cnt; ++i)
2084                         bce_destroy_rx_ring(&sc->rx_rings[i]);
2085                 kfree(sc->rx_rings, M_DEVBUF);
2086         }
2087
2088         /* Destroy the parent tag */
2089         if (sc->parent_tag != NULL)
2090                 bus_dma_tag_destroy(sc->parent_tag);
2091 }
2092
2093
2094 /****************************************************************************/
2095 /* Get DMA memory from the OS.                                              */
2096 /*                                                                          */
2097 /* Validates that the OS has provided DMA buffers in response to a          */
2098 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2099 /* When the callback is used the OS will return 0 for the mapping function  */
2100 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2101 /* failures back to the caller.                                             */
2102 /*                                                                          */
2103 /* Returns:                                                                 */
2104 /*   Nothing.                                                               */
2105 /****************************************************************************/
2106 static void
2107 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2108 {
2109         bus_addr_t *busaddr = arg;
2110
2111         /* Check for an error and signal the caller that an error occurred. */
2112         if (error)
2113                 return;
2114
2115         KASSERT(nseg == 1, ("only one segment is allowed"));
2116         *busaddr = segs->ds_addr;
2117 }
2118
2119
2120 static int
2121 bce_create_tx_ring(struct bce_tx_ring *txr)
2122 {
2123         int pages, rc, i;
2124
2125         lwkt_serialize_init(&txr->tx_serialize);
2126         txr->tx_wreg = bce_tx_wreg;
2127
2128         pages = device_getenv_int(txr->sc->bce_dev, "tx_pages", bce_tx_pages);
2129         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2130                 device_printf(txr->sc->bce_dev, "invalid # of TX pages\n");
2131                 pages = TX_PAGES_DEFAULT;
2132         }
2133         txr->tx_pages = pages;
2134
2135         txr->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * txr->tx_pages,
2136             M_DEVBUF, M_WAITOK | M_ZERO);
2137         txr->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * txr->tx_pages,
2138             M_DEVBUF, M_WAITOK | M_ZERO);
2139         txr->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * txr->tx_pages,
2140             M_DEVBUF, M_WAITOK | M_ZERO);
2141
2142         txr->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(txr),
2143             M_DEVBUF, M_WAITOK | M_ZERO);
2144         txr->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(txr),
2145             M_DEVBUF, M_WAITOK | M_ZERO);
2146
2147         /*
2148          * Create a DMA tag for the TX buffer descriptor chain,
2149          * allocate and clear the  memory, and fetch the
2150          * physical address of the block.
2151          */
2152         rc = bus_dma_tag_create(txr->sc->parent_tag, BCM_PAGE_SIZE, 0,
2153             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2154             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2155             0, &txr->tx_bd_chain_tag);
2156         if (rc != 0) {
2157                 device_printf(txr->sc->bce_dev, "Could not allocate "
2158                     "TX descriptor chain DMA tag!\n");
2159                 return rc;
2160         }
2161
2162         for (i = 0; i < txr->tx_pages; i++) {
2163                 bus_addr_t busaddr;
2164
2165                 rc = bus_dmamem_alloc(txr->tx_bd_chain_tag,
2166                     (void **)&txr->tx_bd_chain[i],
2167                     BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2168                     &txr->tx_bd_chain_map[i]);
2169                 if (rc != 0) {
2170                         device_printf(txr->sc->bce_dev,
2171                             "Could not allocate %dth TX descriptor "
2172                             "chain DMA memory!\n", i);
2173                         return rc;
2174                 }
2175
2176                 rc = bus_dmamap_load(txr->tx_bd_chain_tag,
2177                     txr->tx_bd_chain_map[i],
2178                     txr->tx_bd_chain[i],
2179                     BCE_TX_CHAIN_PAGE_SZ,
2180                     bce_dma_map_addr, &busaddr,
2181                     BUS_DMA_WAITOK);
2182                 if (rc != 0) {
2183                         if (rc == EINPROGRESS) {
2184                                 panic("%s coherent memory loading "
2185                                     "is still in progress!",
2186                                     txr->sc->arpcom.ac_if.if_xname);
2187                         }
2188                         device_printf(txr->sc->bce_dev, "Could not map %dth "
2189                             "TX descriptor chain DMA memory!\n", i);
2190                         bus_dmamem_free(txr->tx_bd_chain_tag,
2191                             txr->tx_bd_chain[i],
2192                             txr->tx_bd_chain_map[i]);
2193                         txr->tx_bd_chain[i] = NULL;
2194                         return rc;
2195                 }
2196
2197                 txr->tx_bd_chain_paddr[i] = busaddr;
2198         }
2199
2200         /* Create a DMA tag for TX mbufs. */
2201         rc = bus_dma_tag_create(txr->sc->parent_tag, 1, 0,
2202             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2203             IP_MAXPACKET + sizeof(struct ether_vlan_header),
2204             BCE_MAX_SEGMENTS, PAGE_SIZE,
2205             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2206             &txr->tx_mbuf_tag);
2207         if (rc != 0) {
2208                 device_printf(txr->sc->bce_dev,
2209                     "Could not allocate TX mbuf DMA tag!\n");
2210                 return rc;
2211         }
2212
2213         /* Create DMA maps for the TX mbufs clusters. */
2214         for (i = 0; i < TOTAL_TX_BD(txr); i++) {
2215                 rc = bus_dmamap_create(txr->tx_mbuf_tag,
2216                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2217                     &txr->tx_mbuf_map[i]);
2218                 if (rc != 0) {
2219                         int j;
2220
2221                         for (j = 0; j < i; ++j) {
2222                                 bus_dmamap_destroy(txr->tx_mbuf_tag,
2223                                     txr->tx_mbuf_map[i]);
2224                         }
2225                         bus_dma_tag_destroy(txr->tx_mbuf_tag);
2226                         txr->tx_mbuf_tag = NULL;
2227
2228                         device_printf(txr->sc->bce_dev, "Unable to create "
2229                             "%dth TX mbuf DMA map!\n", i);
2230                         return rc;
2231                 }
2232         }
2233         return 0;
2234 }
2235
2236
2237 static int
2238 bce_create_rx_ring(struct bce_rx_ring *rxr)
2239 {
2240         int pages, rc, i;
2241
2242         lwkt_serialize_init(&rxr->rx_serialize);
2243
2244         pages = device_getenv_int(rxr->sc->bce_dev, "rx_pages", bce_rx_pages);
2245         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2246                 device_printf(rxr->sc->bce_dev, "invalid # of RX pages\n");
2247                 pages = RX_PAGES_DEFAULT;
2248         }
2249         rxr->rx_pages = pages;
2250
2251         rxr->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * rxr->rx_pages,
2252             M_DEVBUF, M_WAITOK | M_ZERO);
2253         rxr->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * rxr->rx_pages,
2254             M_DEVBUF, M_WAITOK | M_ZERO);
2255         rxr->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * rxr->rx_pages,
2256             M_DEVBUF, M_WAITOK | M_ZERO);
2257
2258         rxr->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(rxr),
2259             M_DEVBUF, M_WAITOK | M_ZERO);
2260         rxr->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(rxr),
2261             M_DEVBUF, M_WAITOK | M_ZERO);
2262         rxr->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(rxr),
2263             M_DEVBUF, M_WAITOK | M_ZERO);
2264
2265         /*
2266          * Create a DMA tag for the RX buffer descriptor chain,
2267          * allocate and clear the  memory, and fetch the physical
2268          * address of the blocks.
2269          */
2270         rc = bus_dma_tag_create(rxr->sc->parent_tag, BCM_PAGE_SIZE, 0,
2271             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2272             BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2273             0, &rxr->rx_bd_chain_tag);
2274         if (rc != 0) {
2275                 device_printf(rxr->sc->bce_dev, "Could not allocate "
2276                     "RX descriptor chain DMA tag!\n");
2277                 return rc;
2278         }
2279
2280         for (i = 0; i < rxr->rx_pages; i++) {
2281                 bus_addr_t busaddr;
2282
2283                 rc = bus_dmamem_alloc(rxr->rx_bd_chain_tag,
2284                     (void **)&rxr->rx_bd_chain[i],
2285                     BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2286                     &rxr->rx_bd_chain_map[i]);
2287                 if (rc != 0) {
2288                         device_printf(rxr->sc->bce_dev,
2289                             "Could not allocate %dth RX descriptor "
2290                             "chain DMA memory!\n", i);
2291                         return rc;
2292                 }
2293
2294                 rc = bus_dmamap_load(rxr->rx_bd_chain_tag,
2295                     rxr->rx_bd_chain_map[i],
2296                     rxr->rx_bd_chain[i],
2297                     BCE_RX_CHAIN_PAGE_SZ,
2298                     bce_dma_map_addr, &busaddr,
2299                     BUS_DMA_WAITOK);
2300                 if (rc != 0) {
2301                         if (rc == EINPROGRESS) {
2302                                 panic("%s coherent memory loading "
2303                                     "is still in progress!",
2304                                     rxr->sc->arpcom.ac_if.if_xname);
2305                         }
2306                         device_printf(rxr->sc->bce_dev,
2307                             "Could not map %dth RX descriptor "
2308                             "chain DMA memory!\n", i);
2309                         bus_dmamem_free(rxr->rx_bd_chain_tag,
2310                             rxr->rx_bd_chain[i],
2311                             rxr->rx_bd_chain_map[i]);
2312                         rxr->rx_bd_chain[i] = NULL;
2313                         return rc;
2314                 }
2315
2316                 rxr->rx_bd_chain_paddr[i] = busaddr;
2317         }
2318
2319         /* Create a DMA tag for RX mbufs. */
2320         rc = bus_dma_tag_create(rxr->sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2321             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2322             MCLBYTES, 1, MCLBYTES,
2323             BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED | BUS_DMA_WAITOK,
2324             &rxr->rx_mbuf_tag);
2325         if (rc != 0) {
2326                 device_printf(rxr->sc->bce_dev,
2327                     "Could not allocate RX mbuf DMA tag!\n");
2328                 return rc;
2329         }
2330
2331         /* Create tmp DMA map for RX mbuf clusters. */
2332         rc = bus_dmamap_create(rxr->rx_mbuf_tag, BUS_DMA_WAITOK,
2333             &rxr->rx_mbuf_tmpmap);
2334         if (rc != 0) {
2335                 bus_dma_tag_destroy(rxr->rx_mbuf_tag);
2336                 rxr->rx_mbuf_tag = NULL;
2337
2338                 device_printf(rxr->sc->bce_dev,
2339                     "Could not create RX mbuf tmp DMA map!\n");
2340                 return rc;
2341         }
2342
2343         /* Create DMA maps for the RX mbuf clusters. */
2344         for (i = 0; i < TOTAL_RX_BD(rxr); i++) {
2345                 rc = bus_dmamap_create(rxr->rx_mbuf_tag, BUS_DMA_WAITOK,
2346                     &rxr->rx_mbuf_map[i]);
2347                 if (rc != 0) {
2348                         int j;
2349
2350                         for (j = 0; j < i; ++j) {
2351                                 bus_dmamap_destroy(rxr->rx_mbuf_tag,
2352                                     rxr->rx_mbuf_map[j]);
2353                         }
2354                         bus_dma_tag_destroy(rxr->rx_mbuf_tag);
2355                         rxr->rx_mbuf_tag = NULL;
2356
2357                         device_printf(rxr->sc->bce_dev, "Unable to create "
2358                             "%dth RX mbuf DMA map!\n", i);
2359                         return rc;
2360                 }
2361         }
2362         return 0;
2363 }
2364
2365
2366 /****************************************************************************/
2367 /* Allocate any DMA memory needed by the driver.                            */
2368 /*                                                                          */
2369 /* Allocates DMA memory needed for the various global structures needed by  */
2370 /* hardware.                                                                */
2371 /*                                                                          */
2372 /* Memory alignment requirements:                                           */
2373 /* -----------------+----------+----------+----------+----------+           */
2374 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2375 /* -----------------+----------+----------+----------+----------+           */
2376 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2377 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2378 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2379 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2380 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2381 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2382 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2383 /* -----------------+----------+----------+----------+----------+           */
2384 /*                                                                          */
2385 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2386 /*                                                                          */
2387 /* Returns:                                                                 */
2388 /*   0 for success, positive value for failure.                             */
2389 /****************************************************************************/
2390 static int
2391 bce_dma_alloc(struct bce_softc *sc)
2392 {
2393         struct ifnet *ifp = &sc->arpcom.ac_if;
2394         int i, rc = 0;
2395         bus_addr_t busaddr, max_busaddr;
2396         bus_size_t status_align, stats_align;
2397
2398         /*
2399          * The embedded PCIe to PCI-X bridge (EPB)
2400          * in the 5708 cannot address memory above
2401          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2402          */
2403         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2404                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2405         else
2406                 max_busaddr = BUS_SPACE_MAXADDR;
2407
2408         /*
2409          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2410          */
2411         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2412             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2413                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2414                 if (sc->ctx_pages == 0)
2415                         sc->ctx_pages = 1;
2416                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2417                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2418                             sc->ctx_pages);
2419                         return ENOMEM;
2420                 }
2421                 status_align = 16;
2422                 stats_align = 16;
2423         } else {
2424                 status_align = 8;
2425                 stats_align = 8;
2426         }
2427
2428         /*
2429          * Allocate the parent bus DMA tag appropriate for PCI.
2430          */
2431         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2432                                 max_busaddr, BUS_SPACE_MAXADDR,
2433                                 NULL, NULL,
2434                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2435                                 BUS_SPACE_MAXSIZE_32BIT,
2436                                 0, &sc->parent_tag);
2437         if (rc != 0) {
2438                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2439                 return rc;
2440         }
2441
2442         /*
2443          * Allocate status block.
2444          */
2445         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2446                                 status_align, BCE_STATUS_BLK_SZ,
2447                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2448                                 &sc->status_tag, &sc->status_map,
2449                                 &sc->status_block_paddr);
2450         if (sc->status_block == NULL) {
2451                 if_printf(ifp, "Could not allocate status block!\n");
2452                 return ENOMEM;
2453         }
2454
2455         /*
2456          * Allocate statistics block.
2457          */
2458         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2459                                 stats_align, BCE_STATS_BLK_SZ,
2460                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2461                                 &sc->stats_tag, &sc->stats_map,
2462                                 &sc->stats_block_paddr);
2463         if (sc->stats_block == NULL) {
2464                 if_printf(ifp, "Could not allocate statistics block!\n");
2465                 return ENOMEM;
2466         }
2467
2468         /*
2469          * Allocate context block, if needed
2470          */
2471         if (sc->ctx_pages != 0) {
2472                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2473                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2474                                         NULL, NULL,
2475                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2476                                         0, &sc->ctx_tag);
2477                 if (rc != 0) {
2478                         if_printf(ifp, "Could not allocate "
2479                                   "context block DMA tag!\n");
2480                         return rc;
2481                 }
2482
2483                 for (i = 0; i < sc->ctx_pages; i++) {
2484                         rc = bus_dmamem_alloc(sc->ctx_tag,
2485                                               (void **)&sc->ctx_block[i],
2486                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2487                                               BUS_DMA_COHERENT,
2488                                               &sc->ctx_map[i]);
2489                         if (rc != 0) {
2490                                 if_printf(ifp, "Could not allocate %dth context "
2491                                           "DMA memory!\n", i);
2492                                 return rc;
2493                         }
2494
2495                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2496                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2497                                              bce_dma_map_addr, &busaddr,
2498                                              BUS_DMA_WAITOK);
2499                         if (rc != 0) {
2500                                 if (rc == EINPROGRESS) {
2501                                         panic("%s coherent memory loading "
2502                                               "is still in progress!", ifp->if_xname);
2503                                 }
2504                                 if_printf(ifp, "Could not map %dth context "
2505                                           "DMA memory!\n", i);
2506                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2507                                                 sc->ctx_map[i]);
2508                                 sc->ctx_block[i] = NULL;
2509                                 return rc;
2510                         }
2511                         sc->ctx_paddr[i] = busaddr;
2512                 }
2513         }
2514
2515         sc->tx_rings = kmalloc_cachealign(
2516             sizeof(struct bce_tx_ring) * sc->tx_ring_cnt, M_DEVBUF,
2517             M_WAITOK | M_ZERO);
2518         for (i = 0; i < sc->tx_ring_cnt; ++i) {
2519                 sc->tx_rings[i].sc = sc;
2520
2521                 /*
2522                  * TODO
2523                  */
2524                 sc->tx_rings[i].tx_cid = TX_CID;
2525                 sc->tx_rings[i].tx_hw_cons =
2526                     &sc->status_block->status_tx_quick_consumer_index0;
2527
2528                 rc = bce_create_tx_ring(&sc->tx_rings[i]);
2529                 if (rc != 0) {
2530                         device_printf(sc->bce_dev,
2531                             "can't create %dth tx ring\n", i);
2532                         return rc;
2533                 }
2534         }
2535
2536         sc->rx_rings = kmalloc_cachealign(
2537             sizeof(struct bce_rx_ring) * sc->rx_ring_cnt, M_DEVBUF,
2538             M_WAITOK | M_ZERO);
2539         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2540                 sc->rx_rings[i].sc = sc;
2541
2542                 /*
2543                  * TODO
2544                  */
2545                 sc->rx_rings[i].rx_cid = RX_CID;
2546                 sc->rx_rings[i].rx_hw_cons =
2547                     &sc->status_block->status_rx_quick_consumer_index0;
2548                 sc->rx_rings[i].hw_status_idx =
2549                     &sc->status_block->status_idx;
2550
2551                 rc = bce_create_rx_ring(&sc->rx_rings[i]);
2552                 if (rc != 0) {
2553                         device_printf(sc->bce_dev,
2554                             "can't create %dth rx ring\n", i);
2555                         return rc;
2556                 }
2557         }
2558
2559         return 0;
2560 }
2561
2562
2563 /****************************************************************************/
2564 /* Firmware synchronization.                                                */
2565 /*                                                                          */
2566 /* Before performing certain events such as a chip reset, synchronize with  */
2567 /* the firmware first.                                                      */
2568 /*                                                                          */
2569 /* Returns:                                                                 */
2570 /*   0 for success, positive value for failure.                             */
2571 /****************************************************************************/
2572 static int
2573 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2574 {
2575         int i, rc = 0;
2576         uint32_t val;
2577
2578         /* Don't waste any time if we've timed out before. */
2579         if (sc->bce_fw_timed_out)
2580                 return EBUSY;
2581
2582         /* Increment the message sequence number. */
2583         sc->bce_fw_wr_seq++;
2584         msg_data |= sc->bce_fw_wr_seq;
2585
2586         /* Send the message to the bootcode driver mailbox. */
2587         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2588
2589         /* Wait for the bootcode to acknowledge the message. */
2590         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2591                 /* Check for a response in the bootcode firmware mailbox. */
2592                 val = bce_shmem_rd(sc, BCE_FW_MB);
2593                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2594                         break;
2595                 DELAY(1000);
2596         }
2597
2598         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2599         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2600             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2601                 if_printf(&sc->arpcom.ac_if,
2602                           "Firmware synchronization timeout! "
2603                           "msg_data = 0x%08X\n", msg_data);
2604
2605                 msg_data &= ~BCE_DRV_MSG_CODE;
2606                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2607
2608                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2609
2610                 sc->bce_fw_timed_out = 1;
2611                 rc = EBUSY;
2612         }
2613         return rc;
2614 }
2615
2616
2617 /****************************************************************************/
2618 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2619 /*                                                                          */
2620 /* Returns:                                                                 */
2621 /*   Nothing.                                                               */
2622 /****************************************************************************/
2623 static void
2624 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2625                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2626 {
2627         int i;
2628         uint32_t val;
2629
2630         for (i = 0; i < rv2p_code_len; i += 8) {
2631                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2632                 rv2p_code++;
2633                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2634                 rv2p_code++;
2635
2636                 if (rv2p_proc == RV2P_PROC1) {
2637                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2638                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2639                 } else {
2640                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2641                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2642                 }
2643         }
2644
2645         /* Reset the processor, un-stall is done later. */
2646         if (rv2p_proc == RV2P_PROC1)
2647                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2648         else
2649                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2650 }
2651
2652
2653 /****************************************************************************/
2654 /* Load RISC processor firmware.                                            */
2655 /*                                                                          */
2656 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2657 /* associated with a particular processor.                                  */
2658 /*                                                                          */
2659 /* Returns:                                                                 */
2660 /*   Nothing.                                                               */
2661 /****************************************************************************/
2662 static void
2663 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2664                 struct fw_info *fw)
2665 {
2666         uint32_t offset;
2667         int j;
2668
2669         bce_halt_cpu(sc, cpu_reg);
2670
2671         /* Load the Text area. */
2672         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2673         if (fw->text) {
2674                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2675                         REG_WR_IND(sc, offset, fw->text[j]);
2676         }
2677
2678         /* Load the Data area. */
2679         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2680         if (fw->data) {
2681                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2682                         REG_WR_IND(sc, offset, fw->data[j]);
2683         }
2684
2685         /* Load the SBSS area. */
2686         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2687         if (fw->sbss) {
2688                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2689                         REG_WR_IND(sc, offset, fw->sbss[j]);
2690         }
2691
2692         /* Load the BSS area. */
2693         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2694         if (fw->bss) {
2695                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2696                         REG_WR_IND(sc, offset, fw->bss[j]);
2697         }
2698
2699         /* Load the Read-Only area. */
2700         offset = cpu_reg->spad_base +
2701                 (fw->rodata_addr - cpu_reg->mips_view_base);
2702         if (fw->rodata) {
2703                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2704                         REG_WR_IND(sc, offset, fw->rodata[j]);
2705         }
2706
2707         /* Clear the pre-fetch instruction and set the FW start address. */
2708         REG_WR_IND(sc, cpu_reg->inst, 0);
2709         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2710 }
2711
2712
2713 /****************************************************************************/
2714 /* Starts the RISC processor.                                               */
2715 /*                                                                          */
2716 /* Assumes the CPU starting address has already been set.                   */
2717 /*                                                                          */
2718 /* Returns:                                                                 */
2719 /*   Nothing.                                                               */
2720 /****************************************************************************/
2721 static void
2722 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2723 {
2724         uint32_t val;
2725
2726         /* Start the CPU. */
2727         val = REG_RD_IND(sc, cpu_reg->mode);
2728         val &= ~cpu_reg->mode_value_halt;
2729         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2730         REG_WR_IND(sc, cpu_reg->mode, val);
2731 }
2732
2733
2734 /****************************************************************************/
2735 /* Halts the RISC processor.                                                */
2736 /*                                                                          */
2737 /* Returns:                                                                 */
2738 /*   Nothing.                                                               */
2739 /****************************************************************************/
2740 static void
2741 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2742 {
2743         uint32_t val;
2744
2745         /* Halt the CPU. */
2746         val = REG_RD_IND(sc, cpu_reg->mode);
2747         val |= cpu_reg->mode_value_halt;
2748         REG_WR_IND(sc, cpu_reg->mode, val);
2749         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2750 }
2751
2752
2753 /****************************************************************************/
2754 /* Start the RX CPU.                                                        */
2755 /*                                                                          */
2756 /* Returns:                                                                 */
2757 /*   Nothing.                                                               */
2758 /****************************************************************************/
2759 static void
2760 bce_start_rxp_cpu(struct bce_softc *sc)
2761 {
2762         struct cpu_reg cpu_reg;
2763
2764         cpu_reg.mode = BCE_RXP_CPU_MODE;
2765         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2766         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2767         cpu_reg.state = BCE_RXP_CPU_STATE;
2768         cpu_reg.state_value_clear = 0xffffff;
2769         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2770         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2771         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2772         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2773         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2774         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2775         cpu_reg.mips_view_base = 0x8000000;
2776
2777         bce_start_cpu(sc, &cpu_reg);
2778 }
2779
2780
2781 /****************************************************************************/
2782 /* Initialize the RX CPU.                                                   */
2783 /*                                                                          */
2784 /* Returns:                                                                 */
2785 /*   Nothing.                                                               */
2786 /****************************************************************************/
2787 static void
2788 bce_init_rxp_cpu(struct bce_softc *sc)
2789 {
2790         struct cpu_reg cpu_reg;
2791         struct fw_info fw;
2792
2793         cpu_reg.mode = BCE_RXP_CPU_MODE;
2794         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2795         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2796         cpu_reg.state = BCE_RXP_CPU_STATE;
2797         cpu_reg.state_value_clear = 0xffffff;
2798         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2799         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2800         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2801         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2802         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2803         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2804         cpu_reg.mips_view_base = 0x8000000;
2805
2806         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2807             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2808                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2809                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2810                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2811                 fw.start_addr = bce_RXP_b09FwStartAddr;
2812
2813                 fw.text_addr = bce_RXP_b09FwTextAddr;
2814                 fw.text_len = bce_RXP_b09FwTextLen;
2815                 fw.text_index = 0;
2816                 fw.text = bce_RXP_b09FwText;
2817
2818                 fw.data_addr = bce_RXP_b09FwDataAddr;
2819                 fw.data_len = bce_RXP_b09FwDataLen;
2820                 fw.data_index = 0;
2821                 fw.data = bce_RXP_b09FwData;
2822
2823                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2824                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2825                 fw.sbss_index = 0;
2826                 fw.sbss = bce_RXP_b09FwSbss;
2827
2828                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2829                 fw.bss_len = bce_RXP_b09FwBssLen;
2830                 fw.bss_index = 0;
2831                 fw.bss = bce_RXP_b09FwBss;
2832
2833                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2834                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2835                 fw.rodata_index = 0;
2836                 fw.rodata = bce_RXP_b09FwRodata;
2837         } else {
2838                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2839                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2840                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2841                 fw.start_addr = bce_RXP_b06FwStartAddr;
2842
2843                 fw.text_addr = bce_RXP_b06FwTextAddr;
2844                 fw.text_len = bce_RXP_b06FwTextLen;
2845                 fw.text_index = 0;
2846                 fw.text = bce_RXP_b06FwText;
2847
2848                 fw.data_addr = bce_RXP_b06FwDataAddr;
2849                 fw.data_len = bce_RXP_b06FwDataLen;
2850                 fw.data_index = 0;
2851                 fw.data = bce_RXP_b06FwData;
2852
2853                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2854                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2855                 fw.sbss_index = 0;
2856                 fw.sbss = bce_RXP_b06FwSbss;
2857
2858                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2859                 fw.bss_len = bce_RXP_b06FwBssLen;
2860                 fw.bss_index = 0;
2861                 fw.bss = bce_RXP_b06FwBss;
2862
2863                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2864                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2865                 fw.rodata_index = 0;
2866                 fw.rodata = bce_RXP_b06FwRodata;
2867         }
2868
2869         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2870         /* Delay RXP start until initialization is complete. */
2871 }
2872
2873
2874 /****************************************************************************/
2875 /* Initialize the TX CPU.                                                   */
2876 /*                                                                          */
2877 /* Returns:                                                                 */
2878 /*   Nothing.                                                               */
2879 /****************************************************************************/
2880 static void
2881 bce_init_txp_cpu(struct bce_softc *sc)
2882 {
2883         struct cpu_reg cpu_reg;
2884         struct fw_info fw;
2885
2886         cpu_reg.mode = BCE_TXP_CPU_MODE;
2887         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2888         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2889         cpu_reg.state = BCE_TXP_CPU_STATE;
2890         cpu_reg.state_value_clear = 0xffffff;
2891         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2892         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2893         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2894         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2895         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2896         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2897         cpu_reg.mips_view_base = 0x8000000;
2898
2899         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2900             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2901                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2902                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2903                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2904                 fw.start_addr = bce_TXP_b09FwStartAddr;
2905
2906                 fw.text_addr = bce_TXP_b09FwTextAddr;
2907                 fw.text_len = bce_TXP_b09FwTextLen;
2908                 fw.text_index = 0;
2909                 fw.text = bce_TXP_b09FwText;
2910
2911                 fw.data_addr = bce_TXP_b09FwDataAddr;
2912                 fw.data_len = bce_TXP_b09FwDataLen;
2913                 fw.data_index = 0;
2914                 fw.data = bce_TXP_b09FwData;
2915
2916                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2917                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2918                 fw.sbss_index = 0;
2919                 fw.sbss = bce_TXP_b09FwSbss;
2920
2921                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2922                 fw.bss_len = bce_TXP_b09FwBssLen;
2923                 fw.bss_index = 0;
2924                 fw.bss = bce_TXP_b09FwBss;
2925
2926                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2927                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2928                 fw.rodata_index = 0;
2929                 fw.rodata = bce_TXP_b09FwRodata;
2930         } else {
2931                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2932                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2933                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2934                 fw.start_addr = bce_TXP_b06FwStartAddr;
2935
2936                 fw.text_addr = bce_TXP_b06FwTextAddr;
2937                 fw.text_len = bce_TXP_b06FwTextLen;
2938                 fw.text_index = 0;
2939                 fw.text = bce_TXP_b06FwText;
2940
2941                 fw.data_addr = bce_TXP_b06FwDataAddr;
2942                 fw.data_len = bce_TXP_b06FwDataLen;
2943                 fw.data_index = 0;
2944                 fw.data = bce_TXP_b06FwData;
2945
2946                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2947                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2948                 fw.sbss_index = 0;
2949                 fw.sbss = bce_TXP_b06FwSbss;
2950
2951                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2952                 fw.bss_len = bce_TXP_b06FwBssLen;
2953                 fw.bss_index = 0;
2954                 fw.bss = bce_TXP_b06FwBss;
2955
2956                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2957                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2958                 fw.rodata_index = 0;
2959                 fw.rodata = bce_TXP_b06FwRodata;
2960         }
2961
2962         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2963         bce_start_cpu(sc, &cpu_reg);
2964 }
2965
2966
2967 /****************************************************************************/
2968 /* Initialize the TPAT CPU.                                                 */
2969 /*                                                                          */
2970 /* Returns:                                                                 */
2971 /*   Nothing.                                                               */
2972 /****************************************************************************/
2973 static void
2974 bce_init_tpat_cpu(struct bce_softc *sc)
2975 {
2976         struct cpu_reg cpu_reg;
2977         struct fw_info fw;
2978
2979         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2980         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2981         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2982         cpu_reg.state = BCE_TPAT_CPU_STATE;
2983         cpu_reg.state_value_clear = 0xffffff;
2984         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2985         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2986         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2987         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2988         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2989         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2990         cpu_reg.mips_view_base = 0x8000000;
2991
2992         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2993             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2994                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2995                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2996                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2997                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2998
2999                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3000                 fw.text_len = bce_TPAT_b09FwTextLen;
3001                 fw.text_index = 0;
3002                 fw.text = bce_TPAT_b09FwText;
3003
3004                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3005                 fw.data_len = bce_TPAT_b09FwDataLen;
3006                 fw.data_index = 0;
3007                 fw.data = bce_TPAT_b09FwData;
3008
3009                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3010                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3011                 fw.sbss_index = 0;
3012                 fw.sbss = bce_TPAT_b09FwSbss;
3013
3014                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3015                 fw.bss_len = bce_TPAT_b09FwBssLen;
3016                 fw.bss_index = 0;
3017                 fw.bss = bce_TPAT_b09FwBss;
3018
3019                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3020                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3021                 fw.rodata_index = 0;
3022                 fw.rodata = bce_TPAT_b09FwRodata;
3023         } else {
3024                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3025                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3026                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3027                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3028
3029                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3030                 fw.text_len = bce_TPAT_b06FwTextLen;
3031                 fw.text_index = 0;
3032                 fw.text = bce_TPAT_b06FwText;
3033
3034                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3035                 fw.data_len = bce_TPAT_b06FwDataLen;
3036                 fw.data_index = 0;
3037                 fw.data = bce_TPAT_b06FwData;
3038
3039                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3040                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3041                 fw.sbss_index = 0;
3042                 fw.sbss = bce_TPAT_b06FwSbss;
3043
3044                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3045                 fw.bss_len = bce_TPAT_b06FwBssLen;
3046                 fw.bss_index = 0;
3047                 fw.bss = bce_TPAT_b06FwBss;
3048
3049                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3050                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3051                 fw.rodata_index = 0;
3052                 fw.rodata = bce_TPAT_b06FwRodata;
3053         }
3054
3055         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3056         bce_start_cpu(sc, &cpu_reg);
3057 }
3058
3059
3060 /****************************************************************************/
3061 /* Initialize the CP CPU.                                                   */
3062 /*                                                                          */
3063 /* Returns:                                                                 */
3064 /*   Nothing.                                                               */
3065 /****************************************************************************/
3066 static void
3067 bce_init_cp_cpu(struct bce_softc *sc)
3068 {
3069         struct cpu_reg cpu_reg;
3070         struct fw_info fw;
3071
3072         cpu_reg.mode = BCE_CP_CPU_MODE;
3073         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3074         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3075         cpu_reg.state = BCE_CP_CPU_STATE;
3076         cpu_reg.state_value_clear = 0xffffff;
3077         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3078         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3079         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3080         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3081         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3082         cpu_reg.spad_base = BCE_CP_SCRATCH;
3083         cpu_reg.mips_view_base = 0x8000000;
3084
3085         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3086             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3087                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3088                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3089                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3090                 fw.start_addr = bce_CP_b09FwStartAddr;
3091
3092                 fw.text_addr = bce_CP_b09FwTextAddr;
3093                 fw.text_len = bce_CP_b09FwTextLen;
3094                 fw.text_index = 0;
3095                 fw.text = bce_CP_b09FwText;
3096
3097                 fw.data_addr = bce_CP_b09FwDataAddr;
3098                 fw.data_len = bce_CP_b09FwDataLen;
3099                 fw.data_index = 0;
3100                 fw.data = bce_CP_b09FwData;
3101
3102                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3103                 fw.sbss_len = bce_CP_b09FwSbssLen;
3104                 fw.sbss_index = 0;
3105                 fw.sbss = bce_CP_b09FwSbss;
3106
3107                 fw.bss_addr = bce_CP_b09FwBssAddr;
3108                 fw.bss_len = bce_CP_b09FwBssLen;
3109                 fw.bss_index = 0;
3110                 fw.bss = bce_CP_b09FwBss;
3111
3112                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3113                 fw.rodata_len = bce_CP_b09FwRodataLen;
3114                 fw.rodata_index = 0;
3115                 fw.rodata = bce_CP_b09FwRodata;
3116         } else {
3117                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3118                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3119                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3120                 fw.start_addr = bce_CP_b06FwStartAddr;
3121
3122                 fw.text_addr = bce_CP_b06FwTextAddr;
3123                 fw.text_len = bce_CP_b06FwTextLen;
3124                 fw.text_index = 0;
3125                 fw.text = bce_CP_b06FwText;
3126
3127                 fw.data_addr = bce_CP_b06FwDataAddr;
3128                 fw.data_len = bce_CP_b06FwDataLen;
3129                 fw.data_index = 0;
3130                 fw.data = bce_CP_b06FwData;
3131
3132                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3133                 fw.sbss_len = bce_CP_b06FwSbssLen;
3134                 fw.sbss_index = 0;
3135                 fw.sbss = bce_CP_b06FwSbss;
3136
3137                 fw.bss_addr = bce_CP_b06FwBssAddr;
3138                 fw.bss_len = bce_CP_b06FwBssLen;
3139                 fw.bss_index = 0;
3140                 fw.bss = bce_CP_b06FwBss;
3141
3142                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3143                 fw.rodata_len = bce_CP_b06FwRodataLen;
3144                 fw.rodata_index = 0;
3145                 fw.rodata = bce_CP_b06FwRodata;
3146         }
3147
3148         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3149         bce_start_cpu(sc, &cpu_reg);
3150 }
3151
3152
3153 /****************************************************************************/
3154 /* Initialize the COM CPU.                                                 */
3155 /*                                                                          */
3156 /* Returns:                                                                 */
3157 /*   Nothing.                                                               */
3158 /****************************************************************************/
3159 static void
3160 bce_init_com_cpu(struct bce_softc *sc)
3161 {
3162         struct cpu_reg cpu_reg;
3163         struct fw_info fw;
3164
3165         cpu_reg.mode = BCE_COM_CPU_MODE;
3166         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3167         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3168         cpu_reg.state = BCE_COM_CPU_STATE;
3169         cpu_reg.state_value_clear = 0xffffff;
3170         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3171         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3172         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3173         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3174         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3175         cpu_reg.spad_base = BCE_COM_SCRATCH;
3176         cpu_reg.mips_view_base = 0x8000000;
3177
3178         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3179             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3180                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3181                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3182                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3183                 fw.start_addr = bce_COM_b09FwStartAddr;
3184
3185                 fw.text_addr = bce_COM_b09FwTextAddr;
3186                 fw.text_len = bce_COM_b09FwTextLen;
3187                 fw.text_index = 0;
3188                 fw.text = bce_COM_b09FwText;
3189
3190                 fw.data_addr = bce_COM_b09FwDataAddr;
3191                 fw.data_len = bce_COM_b09FwDataLen;
3192                 fw.data_index = 0;
3193                 fw.data = bce_COM_b09FwData;
3194
3195                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3196                 fw.sbss_len = bce_COM_b09FwSbssLen;
3197                 fw.sbss_index = 0;
3198                 fw.sbss = bce_COM_b09FwSbss;
3199
3200                 fw.bss_addr = bce_COM_b09FwBssAddr;
3201                 fw.bss_len = bce_COM_b09FwBssLen;
3202                 fw.bss_index = 0;
3203                 fw.bss = bce_COM_b09FwBss;
3204
3205                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3206                 fw.rodata_len = bce_COM_b09FwRodataLen;
3207                 fw.rodata_index = 0;
3208                 fw.rodata = bce_COM_b09FwRodata;
3209         } else {
3210                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3211                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3212                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3213                 fw.start_addr = bce_COM_b06FwStartAddr;
3214
3215                 fw.text_addr = bce_COM_b06FwTextAddr;
3216                 fw.text_len = bce_COM_b06FwTextLen;
3217                 fw.text_index = 0;
3218                 fw.text = bce_COM_b06FwText;
3219
3220                 fw.data_addr = bce_COM_b06FwDataAddr;
3221                 fw.data_len = bce_COM_b06FwDataLen;
3222                 fw.data_index = 0;
3223                 fw.data = bce_COM_b06FwData;
3224
3225                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3226                 fw.sbss_len = bce_COM_b06FwSbssLen;
3227                 fw.sbss_index = 0;
3228                 fw.sbss = bce_COM_b06FwSbss;
3229
3230                 fw.bss_addr = bce_COM_b06FwBssAddr;
3231                 fw.bss_len = bce_COM_b06FwBssLen;
3232                 fw.bss_index = 0;
3233                 fw.bss = bce_COM_b06FwBss;
3234
3235                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3236                 fw.rodata_len = bce_COM_b06FwRodataLen;
3237                 fw.rodata_index = 0;
3238                 fw.rodata = bce_COM_b06FwRodata;
3239         }
3240
3241         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3242         bce_start_cpu(sc, &cpu_reg);
3243 }
3244
3245
3246 /****************************************************************************/
3247 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3248 /*                                                                          */
3249 /* Loads the firmware for each CPU and starts the CPU.                      */
3250 /*                                                                          */
3251 /* Returns:                                                                 */
3252 /*   Nothing.                                                               */
3253 /****************************************************************************/
3254 static void
3255 bce_init_cpus(struct bce_softc *sc)
3256 {
3257         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3258             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3259                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3260                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3261                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3262                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3263                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3264                 } else {
3265                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3266                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3267                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3268                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3269                 }
3270         } else {
3271                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3272                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3273                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3274                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3275         }
3276
3277         bce_init_rxp_cpu(sc);
3278         bce_init_txp_cpu(sc);
3279         bce_init_tpat_cpu(sc);
3280         bce_init_com_cpu(sc);
3281         bce_init_cp_cpu(sc);
3282 }
3283
3284
3285 /****************************************************************************/
3286 /* Initialize context memory.                                               */
3287 /*                                                                          */
3288 /* Clears the memory associated with each Context ID (CID).                 */
3289 /*                                                                          */
3290 /* Returns:                                                                 */
3291 /*   Nothing.                                                               */
3292 /****************************************************************************/
3293 static int
3294 bce_init_ctx(struct bce_softc *sc)
3295 {
3296         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3297             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3298                 /* DRC: Replace this constant value with a #define. */
3299                 int i, retry_cnt = 10;
3300                 uint32_t val;
3301
3302                 /*
3303                  * BCM5709 context memory may be cached
3304                  * in host memory so prepare the host memory
3305                  * for access.
3306                  */
3307                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3308                     (1 << 12);
3309                 val |= (BCM_PAGE_BITS - 8) << 16;
3310                 REG_WR(sc, BCE_CTX_COMMAND, val);
3311
3312                 /* Wait for mem init command to complete. */
3313                 for (i = 0; i < retry_cnt; i++) {
3314                         val = REG_RD(sc, BCE_CTX_COMMAND);
3315                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3316                                 break;
3317                         DELAY(2);
3318                 }
3319                 if (i == retry_cnt) {
3320                         device_printf(sc->bce_dev,
3321                             "Context memory initialization failed!\n");
3322                         return ETIMEDOUT;
3323                 }
3324
3325                 for (i = 0; i < sc->ctx_pages; i++) {
3326                         int j;
3327
3328                         /*
3329                          * Set the physical address of the context
3330                          * memory cache.
3331                          */
3332                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3333                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3334                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3335                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3336                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3337                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3338                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3339
3340                         /*
3341                          * Verify that the context memory write was successful.
3342                          */
3343                         for (j = 0; j < retry_cnt; j++) {
3344                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3345                                 if ((val &
3346                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3347                                         break;
3348                                 DELAY(5);
3349                         }
3350                         if (j == retry_cnt) {
3351                                 device_printf(sc->bce_dev,
3352                                     "Failed to initialize context page!\n");
3353                                 return ETIMEDOUT;
3354                         }
3355                 }
3356         } else {
3357                 uint32_t vcid_addr, offset;
3358
3359                 /*
3360                  * For the 5706/5708, context memory is local to
3361                  * the controller, so initialize the controller
3362                  * context memory.
3363                  */
3364
3365                 vcid_addr = GET_CID_ADDR(96);
3366                 while (vcid_addr) {
3367                         vcid_addr -= PHY_CTX_SIZE;
3368
3369                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3370                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3371
3372                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3373                                 CTX_WR(sc, 0x00, offset, 0);
3374
3375                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3376                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3377                 }
3378         }
3379         return 0;
3380 }
3381
3382
3383 /****************************************************************************/
3384 /* Fetch the permanent MAC address of the controller.                       */
3385 /*                                                                          */
3386 /* Returns:                                                                 */
3387 /*   Nothing.                                                               */
3388 /****************************************************************************/
3389 static void
3390 bce_get_mac_addr(struct bce_softc *sc)
3391 {
3392         uint32_t mac_lo = 0, mac_hi = 0;
3393
3394         /*
3395          * The NetXtreme II bootcode populates various NIC
3396          * power-on and runtime configuration items in a
3397          * shared memory area.  The factory configured MAC
3398          * address is available from both NVRAM and the
3399          * shared memory area so we'll read the value from
3400          * shared memory for speed.
3401          */
3402
3403         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3404         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3405
3406         if (mac_lo == 0 && mac_hi == 0) {
3407                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3408         } else {
3409                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3410                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3411                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3412                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3413                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3414                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3415         }
3416 }
3417
3418
3419 /****************************************************************************/
3420 /* Program the MAC address.                                                 */
3421 /*                                                                          */
3422 /* Returns:                                                                 */
3423 /*   Nothing.                                                               */
3424 /****************************************************************************/
3425 static void
3426 bce_set_mac_addr(struct bce_softc *sc)
3427 {
3428         const uint8_t *mac_addr = sc->eaddr;
3429         uint32_t val;
3430
3431         val = (mac_addr[0] << 8) | mac_addr[1];
3432         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3433
3434         val = (mac_addr[2] << 24) |
3435               (mac_addr[3] << 16) |
3436               (mac_addr[4] << 8) |
3437               mac_addr[5];
3438         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3439 }
3440
3441
3442 /****************************************************************************/
3443 /* Stop the controller.                                                     */
3444 /*                                                                          */
3445 /* Returns:                                                                 */
3446 /*   Nothing.                                                               */
3447 /****************************************************************************/
3448 static void
3449 bce_stop(struct bce_softc *sc)
3450 {
3451         struct ifnet *ifp = &sc->arpcom.ac_if;
3452         int i;
3453
3454         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3455
3456         callout_stop(&sc->bce_tick_callout);
3457
3458         /* Disable the transmit/receive blocks. */
3459         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3460         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3461         DELAY(20);
3462
3463         bce_disable_intr(sc);
3464
3465         ifp->if_flags &= ~IFF_RUNNING;
3466         for (i = 0; i < sc->tx_ring_cnt; ++i) {
3467                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
3468                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
3469         }
3470
3471         /* Free the RX lists. */
3472         for (i = 0; i < sc->rx_ring_cnt; ++i)
3473                 bce_free_rx_chain(&sc->rx_rings[i]);
3474
3475         /* Free TX buffers. */
3476         for (i = 0; i < sc->tx_ring_cnt; ++i)
3477                 bce_free_tx_chain(&sc->tx_rings[i]);
3478
3479         sc->bce_link = 0;
3480         sc->bce_coalchg_mask = 0;
3481 }
3482
3483
3484 static int
3485 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3486 {
3487         uint32_t val;
3488         int i, rc = 0;
3489
3490         /* Wait for pending PCI transactions to complete. */
3491         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3492                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3493                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3494                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3495                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3496         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3497         DELAY(5);
3498
3499         /* Disable DMA */
3500         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3501             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3502                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3503                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3504                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3505         }
3506
3507         /* Assume bootcode is running. */
3508         sc->bce_fw_timed_out = 0;
3509         sc->bce_drv_cardiac_arrest = 0;
3510
3511         /* Give the firmware a chance to prepare for the reset. */
3512         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3513         if (rc) {
3514                 if_printf(&sc->arpcom.ac_if,
3515                           "Firmware is not ready for reset\n");
3516                 return rc;
3517         }
3518
3519         /* Set a firmware reminder that this is a soft reset. */
3520         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3521             BCE_DRV_RESET_SIGNATURE_MAGIC);
3522
3523         /* Dummy read to force the chip to complete all current transactions. */
3524         val = REG_RD(sc, BCE_MISC_ID);
3525
3526         /* Chip reset. */
3527         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3528             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3529                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3530                 REG_RD(sc, BCE_MISC_COMMAND);
3531                 DELAY(5);
3532
3533                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3534                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3535
3536                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3537         } else {
3538                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3539                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3540                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3541                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3542
3543                 /* Allow up to 30us for reset to complete. */
3544                 for (i = 0; i < 10; i++) {
3545                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3546                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3547                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3548                                 break;
3549                         DELAY(10);
3550                 }
3551
3552                 /* Check that reset completed successfully. */
3553                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3554                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3555                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3556                         return EBUSY;
3557                 }
3558         }
3559
3560         /* Make sure byte swapping is properly configured. */
3561         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3562         if (val != 0x01020304) {
3563                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3564                 return ENODEV;
3565         }
3566
3567         /* Just completed a reset, assume that firmware is running again. */
3568         sc->bce_fw_timed_out = 0;
3569         sc->bce_drv_cardiac_arrest = 0;
3570
3571         /* Wait for the firmware to finish its initialization. */
3572         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3573         if (rc) {
3574                 if_printf(&sc->arpcom.ac_if,
3575                           "Firmware did not complete initialization!\n");
3576         }
3577         return rc;
3578 }
3579
3580
3581 static int
3582 bce_chipinit(struct bce_softc *sc)
3583 {
3584         uint32_t val;
3585         int rc = 0;
3586
3587         /* Make sure the interrupt is not active. */
3588         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3589         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3590
3591         /*
3592          * Initialize DMA byte/word swapping, configure the number of DMA
3593          * channels and PCI clock compensation delay.
3594          */
3595         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3596               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3597 #if BYTE_ORDER == BIG_ENDIAN
3598               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3599 #endif
3600               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3601               DMA_READ_CHANS << 12 |
3602               DMA_WRITE_CHANS << 16;
3603
3604         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3605
3606         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3607                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3608
3609         /*
3610          * This setting resolves a problem observed on certain Intel PCI
3611          * chipsets that cannot handle multiple outstanding DMA operations.
3612          * See errata E9_5706A1_65.
3613          */
3614         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3615             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3616             !(sc->bce_flags & BCE_PCIX_FLAG))
3617                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3618
3619         REG_WR(sc, BCE_DMA_CONFIG, val);
3620
3621         /* Enable the RX_V2P and Context state machines before access. */
3622         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3623                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3624                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3625                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3626
3627         /* Initialize context mapping and zero out the quick contexts. */
3628         rc = bce_init_ctx(sc);
3629         if (rc != 0)
3630                 return rc;
3631
3632         /* Initialize the on-boards CPUs */
3633         bce_init_cpus(sc);
3634
3635         /* Enable management frames (NC-SI) to flow to the MCP. */
3636         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3637                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3638                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3639                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3640         }
3641
3642         /* Prepare NVRAM for access. */
3643         rc = bce_init_nvram(sc);
3644         if (rc != 0)
3645                 return rc;
3646
3647         /* Set the kernel bypass block size */
3648         val = REG_RD(sc, BCE_MQ_CONFIG);
3649         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3650         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3651
3652         /* Enable bins used on the 5709/5716. */
3653         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3654             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3655                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3656                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3657                         val |= BCE_MQ_CONFIG_HALT_DIS;
3658         }
3659
3660         REG_WR(sc, BCE_MQ_CONFIG, val);
3661
3662         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3663         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3664         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3665
3666         /* Set the page size and clear the RV2P processor stall bits. */
3667         val = (BCM_PAGE_BITS - 8) << 24;
3668         REG_WR(sc, BCE_RV2P_CONFIG, val);
3669
3670         /* Configure page size. */
3671         val = REG_RD(sc, BCE_TBDR_CONFIG);
3672         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3673         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3674         REG_WR(sc, BCE_TBDR_CONFIG, val);
3675
3676         /* Set the perfect match control register to default. */
3677         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3678
3679         return 0;
3680 }
3681
3682
3683 /****************************************************************************/
3684 /* Initialize the controller in preparation to send/receive traffic.        */
3685 /*                                                                          */
3686 /* Returns:                                                                 */
3687 /*   0 for success, positive value for failure.                             */
3688 /****************************************************************************/
3689 static int
3690 bce_blockinit(struct bce_softc *sc)
3691 {
3692         uint32_t reg, val;
3693
3694         /* Load the hardware default MAC address. */
3695         bce_set_mac_addr(sc);
3696
3697         /* Set the Ethernet backoff seed value */
3698         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3699               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3700         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3701
3702         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3703
3704         /* Set up link change interrupt generation. */
3705         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3706
3707         /* Program the physical address of the status block. */
3708         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3709         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3710
3711         /* Program the physical address of the statistics block. */
3712         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3713                BCE_ADDR_LO(sc->stats_block_paddr));
3714         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3715                BCE_ADDR_HI(sc->stats_block_paddr));
3716
3717         /* Program various host coalescing parameters. */
3718         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3719                (sc->bce_tx_quick_cons_trip_int << 16) |
3720                sc->bce_tx_quick_cons_trip);
3721         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3722                (sc->bce_rx_quick_cons_trip_int << 16) |
3723                sc->bce_rx_quick_cons_trip);
3724         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3725                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3726         REG_WR(sc, BCE_HC_TX_TICKS,
3727                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3728         REG_WR(sc, BCE_HC_RX_TICKS,
3729                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3730         REG_WR(sc, BCE_HC_COM_TICKS,
3731                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3732         REG_WR(sc, BCE_HC_CMD_TICKS,
3733                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3734         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3735         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3736
3737         val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3738         if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3739                 if (bootverbose)
3740                         if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3741                 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3742         }
3743         REG_WR(sc, BCE_HC_CONFIG, val);
3744
3745         /* Clear the internal statistics counters. */
3746         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3747
3748         /* Verify that bootcode is running. */
3749         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3750
3751         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3752             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3753                 if_printf(&sc->arpcom.ac_if,
3754                           "Bootcode not running! Found: 0x%08X, "
3755                           "Expected: 08%08X\n",
3756                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3757                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3758                 return ENODEV;
3759         }
3760
3761         /* Enable DMA */
3762         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3763             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3764                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3765                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3766                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3767         }
3768
3769         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3770         bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3771
3772         /* Enable link state change interrupt generation. */
3773         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3774
3775         /* Enable the RXP. */
3776         bce_start_rxp_cpu(sc);
3777
3778         /* Disable management frames (NC-SI) from flowing to the MCP. */
3779         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3780                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3781                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3782                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3783         }
3784
3785         /* Enable all remaining blocks in the MAC. */
3786         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3787             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3788                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3789                     BCE_MISC_ENABLE_DEFAULT_XI);
3790         } else {
3791                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3792         }
3793         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3794         DELAY(20);
3795
3796         /* Save the current host coalescing block settings. */
3797         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3798
3799         return 0;
3800 }
3801
3802
3803 /****************************************************************************/
3804 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3805 /*                                                                          */
3806 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3807 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3808 /* necessary.                                                               */
3809 /*                                                                          */
3810 /* Returns:                                                                 */
3811 /*   0 for success, positive value for failure.                             */
3812 /****************************************************************************/
3813 static int
3814 bce_newbuf_std(struct bce_rx_ring *rxr, uint16_t *prod, uint16_t *chain_prod,
3815     uint32_t *prod_bseq, int init)
3816 {
3817         bus_dmamap_t map;
3818         bus_dma_segment_t seg;
3819         struct mbuf *m_new;
3820         int error, nseg;
3821
3822         /* This is a new mbuf allocation. */
3823         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3824         if (m_new == NULL)
3825                 return ENOBUFS;
3826
3827         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3828
3829         /* Map the mbuf cluster into device memory. */
3830         error = bus_dmamap_load_mbuf_segment(rxr->rx_mbuf_tag,
3831             rxr->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg, BUS_DMA_NOWAIT);
3832         if (error) {
3833                 m_freem(m_new);
3834                 if (init) {
3835                         if_printf(&rxr->sc->arpcom.ac_if,
3836                             "Error mapping mbuf into RX chain!\n");
3837                 }
3838                 return error;
3839         }
3840
3841         if (rxr->rx_mbuf_ptr[*chain_prod] != NULL) {
3842                 bus_dmamap_unload(rxr->rx_mbuf_tag,
3843                     rxr->rx_mbuf_map[*chain_prod]);
3844         }
3845
3846         map = rxr->rx_mbuf_map[*chain_prod];
3847         rxr->rx_mbuf_map[*chain_prod] = rxr->rx_mbuf_tmpmap;
3848         rxr->rx_mbuf_tmpmap = map;
3849
3850         /* Save the mbuf and update our counter. */
3851         rxr->rx_mbuf_ptr[*chain_prod] = m_new;
3852         rxr->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3853         rxr->free_rx_bd--;
3854
3855         bce_setup_rxdesc_std(rxr, *chain_prod, prod_bseq);
3856
3857         return 0;
3858 }
3859
3860
3861 static void
3862 bce_setup_rxdesc_std(struct bce_rx_ring *rxr, uint16_t chain_prod,
3863     uint32_t *prod_bseq)
3864 {
3865         struct rx_bd *rxbd;
3866         bus_addr_t paddr;
3867         int len;
3868
3869         paddr = rxr->rx_mbuf_paddr[chain_prod];
3870         len = rxr->rx_mbuf_ptr[chain_prod]->m_len;
3871
3872         /* Setup the rx_bd for the first segment. */
3873         rxbd = &rxr->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3874
3875         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3876         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3877         rxbd->rx_bd_len = htole32(len);
3878         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3879         *prod_bseq += len;
3880
3881         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3882 }
3883
3884
3885 /****************************************************************************/
3886 /* Initialize the TX context memory.                                        */
3887 /*                                                                          */
3888 /* Returns:                                                                 */
3889 /*   Nothing                                                                */
3890 /****************************************************************************/
3891 static void
3892 bce_init_tx_context(struct bce_tx_ring *txr)
3893 {
3894         uint32_t val;
3895
3896         /* Initialize the context ID for an L2 TX chain. */
3897         if (BCE_CHIP_NUM(txr->sc) == BCE_CHIP_NUM_5709 ||
3898             BCE_CHIP_NUM(txr->sc) == BCE_CHIP_NUM_5716) {
3899                 /* Set the CID type to support an L2 connection. */
3900                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3901                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3902                     BCE_L2CTX_TX_TYPE_XI, val);
3903                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3904                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3905                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
3906
3907                 /* Point the hardware to the first page in the chain. */
3908                 val = BCE_ADDR_HI(txr->tx_bd_chain_paddr[0]);
3909                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3910                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3911                 val = BCE_ADDR_LO(txr->tx_bd_chain_paddr[0]);
3912                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3913                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3914         } else {
3915                 /* Set the CID type to support an L2 connection. */
3916                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3917                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3918                     BCE_L2CTX_TX_TYPE, val);
3919                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3920                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3921                     BCE_L2CTX_TX_CMD_TYPE, val);
3922
3923                 /* Point the hardware to the first page in the chain. */
3924                 val = BCE_ADDR_HI(txr->tx_bd_chain_paddr[0]);
3925                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3926                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3927                 val = BCE_ADDR_LO(txr->tx_bd_chain_paddr[0]);
3928                 CTX_WR(txr->sc, GET_CID_ADDR(txr->tx_cid),
3929                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3930         }
3931 }
3932
3933
3934 /****************************************************************************/
3935 /* Allocate memory and initialize the TX data structures.                   */
3936 /*                                                                          */
3937 /* Returns:                                                                 */
3938 /*   0 for success, positive value for failure.                             */
3939 /****************************************************************************/
3940 static int
3941 bce_init_tx_chain(struct bce_tx_ring *txr)
3942 {
3943         struct tx_bd *txbd;
3944         int i, rc = 0;
3945
3946         /* Set the initial TX producer/consumer indices. */
3947         txr->tx_prod = 0;
3948         txr->tx_cons = 0;
3949         txr->tx_prod_bseq = 0;
3950         txr->used_tx_bd = 0;
3951         txr->max_tx_bd = USABLE_TX_BD(txr);
3952
3953         /*
3954          * The NetXtreme II supports a linked-list structre called
3955          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3956          * consists of a series of 1 or more chain pages, each of which
3957          * consists of a fixed number of BD entries.
3958          * The last BD entry on each page is a pointer to the next page
3959          * in the chain, and the last pointer in the BD chain
3960          * points back to the beginning of the chain.
3961          */
3962
3963         /* Set the TX next pointer chain entries. */
3964         for (i = 0; i < txr->tx_pages; i++) {
3965                 int j;
3966
3967                 txbd = &txr->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3968
3969                 /* Check if we've reached the last page. */
3970                 if (i == (txr->tx_pages - 1))
3971                         j = 0;
3972                 else
3973                         j = i + 1;
3974
3975                 txbd->tx_bd_haddr_hi =
3976                     htole32(BCE_ADDR_HI(txr->tx_bd_chain_paddr[j]));
3977                 txbd->tx_bd_haddr_lo =
3978                     htole32(BCE_ADDR_LO(txr->tx_bd_chain_paddr[j]));
3979         }
3980         bce_init_tx_context(txr);
3981
3982         return(rc);
3983 }
3984
3985
3986 /****************************************************************************/
3987 /* Free memory and clear the TX data structures.                            */
3988 /*                                                                          */
3989 /* Returns:                                                                 */
3990 /*   Nothing.                                                               */
3991 /****************************************************************************/
3992 static void
3993 bce_free_tx_chain(struct bce_tx_ring *txr)
3994 {
3995         int i;
3996
3997         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3998         for (i = 0; i < TOTAL_TX_BD(txr); i++) {
3999                 if (txr->tx_mbuf_ptr[i] != NULL) {
4000                         bus_dmamap_unload(txr->tx_mbuf_tag,
4001                             txr->tx_mbuf_map[i]);
4002                         m_freem(txr->tx_mbuf_ptr[i]);
4003                         txr->tx_mbuf_ptr[i] = NULL;
4004                 }
4005         }
4006
4007         /* Clear each TX chain page. */
4008         for (i = 0; i < txr->tx_pages; i++)
4009                 bzero(txr->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4010         txr->used_tx_bd = 0;
4011 }
4012
4013
4014 /****************************************************************************/
4015 /* Initialize the RX context memory.                                        */
4016 /*                                                                          */
4017 /* Returns:                                                                 */
4018 /*   Nothing                                                                */
4019 /****************************************************************************/
4020 static void
4021 bce_init_rx_context(struct bce_rx_ring *rxr)
4022 {
4023         uint32_t val;
4024
4025         /* Initialize the context ID for an L2 RX chain. */
4026         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4027             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4028
4029         /*
4030          * Set the level for generating pause frames
4031          * when the number of available rx_bd's gets
4032          * too low (the low watermark) and the level
4033          * when pause frames can be stopped (the high
4034          * watermark).
4035          */
4036         if (BCE_CHIP_NUM(rxr->sc) == BCE_CHIP_NUM_5709 ||
4037             BCE_CHIP_NUM(rxr->sc) == BCE_CHIP_NUM_5716) {
4038                 uint32_t lo_water, hi_water;
4039
4040                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4041                 hi_water = USABLE_RX_BD(rxr) / 4;
4042
4043                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4044                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4045
4046                 if (hi_water > 0xf)
4047                         hi_water = 0xf;
4048                 else if (hi_water == 0)
4049                         lo_water = 0;
4050                 val |= lo_water |
4051                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4052         }
4053
4054         CTX_WR(rxr->sc, GET_CID_ADDR(rxr->rx_cid),
4055             BCE_L2CTX_RX_CTX_TYPE, val);
4056
4057         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4058         if (BCE_CHIP_NUM(rxr->sc) == BCE_CHIP_NUM_5709 ||
4059             BCE_CHIP_NUM(rxr->sc) == BCE_CHIP_NUM_5716) {
4060                 val = REG_RD(rxr->sc, BCE_MQ_MAP_L2_5);
4061                 REG_WR(rxr->sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4062         }
4063
4064         /* Point the hardware to the first page in the chain. */
4065         val = BCE_ADDR_HI(rxr->rx_bd_chain_paddr[0]);
4066         CTX_WR(rxr->sc, GET_CID_ADDR(rxr->rx_cid),
4067             BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4068         val = BCE_ADDR_LO(rxr->rx_bd_chain_paddr[0]);
4069         CTX_WR(rxr->sc, GET_CID_ADDR(rxr->rx_cid),
4070             BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4071 }
4072
4073
4074 /****************************************************************************/
4075 /* Allocate memory and initialize the RX data structures.                   */
4076 /*                                                                          */
4077 /* Returns:                                                                 */
4078 /*   0 for success, positive value for failure.                             */
4079 /****************************************************************************/
4080 static int
4081 bce_init_rx_chain(struct bce_rx_ring *rxr)
4082 {
4083         struct rx_bd *rxbd;
4084         int i, rc = 0;
4085         uint16_t prod, chain_prod;
4086         uint32_t prod_bseq;
4087
4088         /* Initialize the RX producer and consumer indices. */
4089         rxr->rx_prod = 0;
4090         rxr->rx_cons = 0;
4091         rxr->rx_prod_bseq = 0;
4092         rxr->free_rx_bd = USABLE_RX_BD(rxr);
4093         rxr->max_rx_bd = USABLE_RX_BD(rxr);
4094
4095         /* Clear cache status index */
4096         rxr->last_status_idx = 0;
4097
4098         /* Initialize the RX next pointer chain entries. */
4099         for (i = 0; i < rxr->rx_pages; i++) {
4100                 int j;
4101
4102                 rxbd = &rxr->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4103
4104                 /* Check if we've reached the last page. */
4105                 if (i == (rxr->rx_pages - 1))
4106                         j = 0;
4107                 else
4108                         j = i + 1;
4109
4110                 /* Setup the chain page pointers. */
4111                 rxbd->rx_bd_haddr_hi =
4112                     htole32(BCE_ADDR_HI(rxr->rx_bd_chain_paddr[j]));
4113                 rxbd->rx_bd_haddr_lo =
4114                     htole32(BCE_ADDR_LO(rxr->rx_bd_chain_paddr[j]));
4115         }
4116
4117         /* Allocate mbuf clusters for the rx_bd chain. */
4118         prod = prod_bseq = 0;
4119         while (prod < TOTAL_RX_BD(rxr)) {
4120                 chain_prod = RX_CHAIN_IDX(rxr, prod);
4121                 if (bce_newbuf_std(rxr, &prod, &chain_prod, &prod_bseq, 1)) {
4122                         if_printf(&rxr->sc->arpcom.ac_if,
4123                             "Error filling RX chain: rx_bd[0x%04X]!\n",
4124                             chain_prod);
4125                         rc = ENOBUFS;
4126                         break;
4127                 }
4128                 prod = NEXT_RX_BD(prod);
4129         }
4130
4131         /* Save the RX chain producer index. */
4132         rxr->rx_prod = prod;
4133         rxr->rx_prod_bseq = prod_bseq;
4134
4135         /* Tell the chip about the waiting rx_bd's. */
4136         REG_WR16(rxr->sc, MB_GET_CID_ADDR(rxr->rx_cid) + BCE_L2MQ_RX_HOST_BDIDX,
4137             rxr->rx_prod);
4138         REG_WR(rxr->sc, MB_GET_CID_ADDR(rxr->rx_cid) + BCE_L2MQ_RX_HOST_BSEQ,
4139             rxr->rx_prod_bseq);
4140
4141         bce_init_rx_context(rxr);
4142
4143         return(rc);
4144 }
4145
4146
4147 /****************************************************************************/
4148 /* Free memory and clear the RX data structures.                            */
4149 /*                                                                          */
4150 /* Returns:                                                                 */
4151 /*   Nothing.                                                               */
4152 /****************************************************************************/
4153 static void
4154 bce_free_rx_chain(struct bce_rx_ring *rxr)
4155 {
4156         int i;
4157
4158         /* Free any mbufs still in the RX mbuf chain. */
4159         for (i = 0; i < TOTAL_RX_BD(rxr); i++) {
4160                 if (rxr->rx_mbuf_ptr[i] != NULL) {
4161                         bus_dmamap_unload(rxr->rx_mbuf_tag,
4162                             rxr->rx_mbuf_map[i]);
4163                         m_freem(rxr->rx_mbuf_ptr[i]);
4164                         rxr->rx_mbuf_ptr[i] = NULL;
4165                 }
4166         }
4167
4168         /* Clear each RX chain page. */
4169         for (i = 0; i < rxr->rx_pages; i++)
4170                 bzero(rxr->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4171 }
4172
4173
4174 /****************************************************************************/
4175 /* Set media options.                                                       */
4176 /*                                                                          */
4177 /* Returns:                                                                 */
4178 /*   0 for success, positive value for failure.                             */
4179 /****************************************************************************/
4180 static int
4181 bce_ifmedia_upd(struct ifnet *ifp)
4182 {
4183         struct bce_softc *sc = ifp->if_softc;
4184         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4185         int error = 0;
4186
4187         /*
4188          * 'mii' will be NULL, when this function is called on following
4189          * code path: bce_attach() -> bce_mgmt_init()
4190          */
4191         if (mii != NULL) {
4192                 /* Make sure the MII bus has been enumerated. */
4193                 sc->bce_link = 0;
4194                 if (mii->mii_instance) {
4195                         struct mii_softc *miisc;
4196
4197                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4198                                 mii_phy_reset(miisc);
4199                 }
4200                 error = mii_mediachg(mii);
4201         }
4202         return error;
4203 }
4204
4205
4206 /****************************************************************************/
4207 /* Reports current media status.                                            */
4208 /*                                                                          */
4209 /* Returns:                                                                 */
4210 /*   Nothing.                                                               */
4211 /****************************************************************************/
4212 static void
4213 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4214 {
4215         struct bce_softc *sc = ifp->if_softc;
4216         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4217
4218         mii_pollstat(mii);
4219         ifmr->ifm_active = mii->mii_media_active;
4220         ifmr->ifm_status = mii->mii_media_status;
4221 }
4222
4223
4224 /****************************************************************************/
4225 /* Handles PHY generated interrupt events.                                  */
4226 /*                                                                          */
4227 /* Returns:                                                                 */
4228 /*   Nothing.                                                               */
4229 /****************************************************************************/
4230 static void
4231 bce_phy_intr(struct bce_softc *sc)
4232 {
4233         uint32_t new_link_state, old_link_state;
4234         struct ifnet *ifp = &sc->arpcom.ac_if;
4235
4236         ASSERT_SERIALIZED(&sc->main_serialize);
4237
4238         new_link_state = sc->status_block->status_attn_bits &
4239                          STATUS_ATTN_BITS_LINK_STATE;
4240         old_link_state = sc->status_block->status_attn_bits_ack &
4241                          STATUS_ATTN_BITS_LINK_STATE;
4242
4243         /* Handle any changes if the link state has changed. */
4244         if (new_link_state != old_link_state) { /* XXX redundant? */
4245                 /* Update the status_attn_bits_ack field in the status block. */
4246                 if (new_link_state) {
4247                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4248                                STATUS_ATTN_BITS_LINK_STATE);
4249                         if (bootverbose)
4250                                 if_printf(ifp, "Link is now UP.\n");
4251                 } else {
4252                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4253                                STATUS_ATTN_BITS_LINK_STATE);
4254                         if (bootverbose)
4255                                 if_printf(ifp, "Link is now DOWN.\n");
4256                 }
4257
4258                 /*
4259                  * Assume link is down and allow tick routine to
4260                  * update the state based on the actual media state.
4261                  */
4262                 sc->bce_link = 0;
4263                 callout_stop(&sc->bce_tick_callout);
4264                 bce_tick_serialized(sc);
4265         }
4266
4267         /* Acknowledge the link change interrupt. */
4268         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4269 }
4270
4271
4272 /****************************************************************************/
4273 /* Reads the receive consumer value from the status block (skipping over    */
4274 /* chain page pointer if necessary).                                        */
4275 /*                                                                          */
4276 /* Returns:                                                                 */
4277 /*   hw_cons                                                                */
4278 /****************************************************************************/
4279 static __inline uint16_t
4280 bce_get_hw_rx_cons(struct bce_rx_ring *rxr)
4281 {
4282         uint16_t hw_cons = *rxr->rx_hw_cons;
4283
4284         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4285                 hw_cons++;
4286         return hw_cons;
4287 }
4288
4289
4290 /****************************************************************************/
4291 /* Handles received frame interrupt events.                                 */
4292 /*                                                                          */
4293 /* Returns:                                                                 */
4294 /*   Nothing.                                                               */
4295 /****************************************************************************/
4296 static void
4297 bce_rx_intr(struct bce_rx_ring *rxr, int count, uint16_t hw_cons)
4298 {
4299         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
4300         uint16_t sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4301         uint32_t sw_prod_bseq;
4302
4303         ASSERT_SERIALIZED(&rxr->rx_serialize);
4304
4305         /* Get working copies of the driver's view of the RX indices. */
4306         sw_cons = rxr->rx_cons;
4307         sw_prod = rxr->rx_prod;
4308         sw_prod_bseq = rxr->rx_prod_bseq;
4309
4310         /* Scan through the receive chain as long as there is work to do. */
4311         while (sw_cons != hw_cons) {
4312                 struct mbuf *m = NULL;
4313                 struct l2_fhdr *l2fhdr = NULL;
4314                 unsigned int len;
4315                 uint32_t status = 0;
4316
4317 #ifdef IFPOLL_ENABLE
4318                 if (count >= 0 && count-- == 0)
4319                         break;
4320 #endif
4321
4322                 /*
4323                  * Convert the producer/consumer indices
4324                  * to an actual rx_bd index.
4325                  */
4326                 sw_chain_cons = RX_CHAIN_IDX(rxr, sw_cons);
4327                 sw_chain_prod = RX_CHAIN_IDX(rxr, sw_prod);
4328
4329                 rxr->free_rx_bd++;
4330
4331                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4332                 if (rxr->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4333                         if (sw_chain_cons != sw_chain_prod) {
4334                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4335                                     "drop!\n", sw_chain_cons, sw_chain_prod);
4336                                 IFNET_STAT_INC(ifp, ierrors, 1);
4337
4338                                 bce_setup_rxdesc_std(rxr, sw_chain_cons,
4339                                     &sw_prod_bseq);
4340                                 m = NULL;
4341                                 goto bce_rx_int_next_rx;
4342                         }
4343
4344                         /* Unmap the mbuf from DMA space. */
4345                         bus_dmamap_sync(rxr->rx_mbuf_tag,
4346                             rxr->rx_mbuf_map[sw_chain_cons],
4347                             BUS_DMASYNC_POSTREAD);
4348
4349                         /* Save the mbuf from the driver's chain. */
4350                         m = rxr->rx_mbuf_ptr[sw_chain_cons];
4351
4352                         /*
4353                          * Frames received on the NetXteme II are prepended
4354                          * with an l2_fhdr structure which provides status
4355                          * information about the received frame (including
4356                          * VLAN tags and checksum info).  The frames are also
4357                          * automatically adjusted to align the IP header
4358                          * (i.e. two null bytes are inserted before the
4359                          * Ethernet header).  As a result the data DMA'd by
4360                          * the controller into the mbuf is as follows:
4361                          *
4362                          * +---------+-----+---------------------+-----+
4363                          * | l2_fhdr | pad | packet data         | FCS |
4364                          * +---------+-----+---------------------+-----+
4365                          *
4366                          * The l2_fhdr needs to be checked and skipped and the
4367                          * FCS needs to be stripped before sending the packet
4368                          * up the stack.
4369                          */
4370                         l2fhdr = mtod(m, struct l2_fhdr *);
4371
4372                         len = l2fhdr->l2_fhdr_pkt_len;
4373                         status = l2fhdr->l2_fhdr_status;
4374
4375                         len -= ETHER_CRC_LEN;
4376
4377                         /* Check the received frame for errors. */
4378                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4379                                       L2_FHDR_ERRORS_PHY_DECODE |
4380                                       L2_FHDR_ERRORS_ALIGNMENT |
4381                                       L2_FHDR_ERRORS_TOO_SHORT |
4382                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4383                                 IFNET_STAT_INC(ifp, ierrors, 1);
4384
4385                                 /* Reuse the mbuf for a new frame. */
4386                                 bce_setup_rxdesc_std(rxr, sw_chain_prod,
4387                                     &sw_prod_bseq);
4388                                 m = NULL;
4389                                 goto bce_rx_int_next_rx;
4390                         }
4391
4392                         /*
4393                          * Get a new mbuf for the rx_bd.   If no new
4394                          * mbufs are available then reuse the current mbuf,
4395                          * log an ierror on the interface, and generate
4396                          * an error in the system log.
4397                          */
4398                         if (bce_newbuf_std(rxr, &sw_prod, &sw_chain_prod,
4399                             &sw_prod_bseq, 0)) {
4400                                 IFNET_STAT_INC(ifp, ierrors, 1);
4401
4402                                 /* Try and reuse the exisitng mbuf. */
4403                                 bce_setup_rxdesc_std(rxr, sw_chain_prod,
4404                                     &sw_prod_bseq);
4405                                 m = NULL;
4406                                 goto bce_rx_int_next_rx;
4407                         }
4408
4409                         /*
4410                          * Skip over the l2_fhdr when passing
4411                          * the data up the stack.
4412                          */
4413                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4414
4415                         m->m_pkthdr.len = m->m_len = len;
4416                         m->m_pkthdr.rcvif = ifp;
4417
4418                         /* Validate the checksum if offload enabled. */
4419                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4420                                 /* Check for an IP datagram. */
4421                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4422                                         m->m_pkthdr.csum_flags |=
4423                                                 CSUM_IP_CHECKED;
4424
4425                                         /* Check if the IP checksum is valid. */
4426                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4427                                              0xffff) == 0) {
4428                                                 m->m_pkthdr.csum_flags |=
4429                                                         CSUM_IP_VALID;
4430                                         }
4431                                 }
4432
4433                                 /* Check for a valid TCP/UDP frame. */
4434                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4435                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4436
4437                                         /* Check for a good TCP/UDP checksum. */
4438                                         if ((status &
4439                                              (L2_FHDR_ERRORS_TCP_XSUM |
4440                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4441                                                 m->m_pkthdr.csum_data =
4442                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4443                                                 m->m_pkthdr.csum_flags |=
4444                                                         CSUM_DATA_VALID |
4445                                                         CSUM_PSEUDO_HDR;
4446                                         }
4447                                 }
4448                         }
4449
4450                         IFNET_STAT_INC(ifp, ipackets, 1);
4451 bce_rx_int_next_rx:
4452                         sw_prod = NEXT_RX_BD(sw_prod);
4453                 }
4454
4455                 sw_cons = NEXT_RX_BD(sw_cons);
4456
4457                 /* If we have a packet, pass it up the stack */
4458                 if (m) {
4459                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4460                                 m->m_flags |= M_VLANTAG;
4461                                 m->m_pkthdr.ether_vlantag =
4462                                         l2fhdr->l2_fhdr_vlan_tag;
4463                         }
4464                         ifp->if_input(ifp, m);
4465                 }
4466         }
4467
4468         rxr->rx_cons = sw_cons;
4469         rxr->rx_prod = sw_prod;
4470         rxr->rx_prod_bseq = sw_prod_bseq;
4471
4472         REG_WR16(rxr->sc, MB_GET_CID_ADDR(rxr->rx_cid) + BCE_L2MQ_RX_HOST_BDIDX,
4473             rxr->rx_prod);
4474         REG_WR(rxr->sc, MB_GET_CID_ADDR(rxr->rx_cid) + BCE_L2MQ_RX_HOST_BSEQ,
4475             rxr->rx_prod_bseq);
4476 }
4477
4478
4479 /****************************************************************************/
4480 /* Reads the transmit consumer value from the status block (skipping over   */
4481 /* chain page pointer if necessary).                                        */
4482 /*                                                                          */
4483 /* Returns:                                                                 */
4484 /*   hw_cons                                                                */
4485 /****************************************************************************/
4486 static __inline uint16_t
4487 bce_get_hw_tx_cons(struct bce_tx_ring *txr)
4488 {
4489         uint16_t hw_cons = *txr->tx_hw_cons;
4490
4491         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4492                 hw_cons++;
4493         return hw_cons;
4494 }
4495
4496
4497 /****************************************************************************/
4498 /* Handles transmit completion interrupt events.                            */
4499 /*                                                                          */
4500 /* Returns:                                                                 */
4501 /*   Nothing.                                                               */
4502 /****************************************************************************/
4503 static void
4504 bce_tx_intr(struct bce_tx_ring *txr, uint16_t hw_tx_cons)
4505 {
4506         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
4507         uint16_t sw_tx_cons, sw_tx_chain_cons;
4508
4509         ASSERT_SERIALIZED(&txr->tx_serialize);
4510
4511         /* Get the hardware's view of the TX consumer index. */
4512         sw_tx_cons = txr->tx_cons;
4513
4514         /* Cycle through any completed TX chain page entries. */
4515         while (sw_tx_cons != hw_tx_cons) {
4516                 sw_tx_chain_cons = TX_CHAIN_IDX(txr, sw_tx_cons);
4517
4518                 /*
4519                  * Free the associated mbuf. Remember
4520                  * that only the last tx_bd of a packet
4521                  * has an mbuf pointer and DMA map.
4522                  */
4523                 if (txr->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4524                         /* Unmap the mbuf. */
4525                         bus_dmamap_unload(txr->tx_mbuf_tag,
4526                             txr->tx_mbuf_map[sw_tx_chain_cons]);
4527
4528                         /* Free the mbuf. */
4529                         m_freem(txr->tx_mbuf_ptr[sw_tx_chain_cons]);
4530                         txr->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4531
4532                         IFNET_STAT_INC(ifp, opackets, 1);
4533                 }
4534
4535                 txr->used_tx_bd--;
4536                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4537         }
4538
4539         if (txr->used_tx_bd == 0) {
4540                 /* Clear the TX timeout timer. */
4541                 txr->tx_watchdog.wd_timer = 0;
4542         }
4543
4544         /* Clear the tx hardware queue full flag. */
4545         if (txr->max_tx_bd - txr->used_tx_bd >= BCE_TX_SPARE_SPACE)
4546                 ifsq_clr_oactive(txr->ifsq);
4547         txr->tx_cons = sw_tx_cons;
4548 }
4549
4550
4551 /****************************************************************************/
4552 /* Disables interrupt generation.                                           */
4553 /*                                                                          */
4554 /* Returns:                                                                 */
4555 /*   Nothing.                                                               */
4556 /****************************************************************************/
4557 static void
4558 bce_disable_intr(struct bce_softc *sc)
4559 {
4560         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4561         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4562
4563         callout_stop(&sc->bce_ckmsi_callout);
4564         sc->bce_msi_maylose = FALSE;
4565         sc->bce_check_rx_cons = 0;
4566         sc->bce_check_tx_cons = 0;
4567         sc->bce_check_status_idx = 0xffff;
4568
4569         lwkt_serialize_handler_disable(&sc->main_serialize);
4570 }
4571
4572
4573 /****************************************************************************/
4574 /* Enables interrupt generation.                                            */
4575 /*                                                                          */
4576 /* Returns:                                                                 */
4577 /*   Nothing.                                                               */
4578 /****************************************************************************/
4579 static void
4580 bce_enable_intr(struct bce_softc *sc)
4581 {
4582         struct bce_rx_ring *rxr = &sc->rx_rings[0]; /* XXX */
4583
4584         lwkt_serialize_handler_enable(&sc->main_serialize);
4585
4586         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4587                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4588                BCE_PCICFG_INT_ACK_CMD_MASK_INT | rxr->last_status_idx);
4589         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4590                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | rxr->last_status_idx);
4591
4592         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4593
4594         if (sc->bce_flags & BCE_CHECK_MSI_FLAG) {
4595                 sc->bce_msi_maylose = FALSE;
4596                 sc->bce_check_rx_cons = 0;
4597                 sc->bce_check_tx_cons = 0;
4598                 sc->bce_check_status_idx = 0xffff;
4599
4600                 if (bootverbose)
4601                         if_printf(&sc->arpcom.ac_if, "check msi\n");
4602
4603                 callout_reset_bycpu(&sc->bce_ckmsi_callout, BCE_MSI_CKINTVL,
4604                     bce_check_msi, sc, sc->bce_intr_cpuid);
4605         }
4606 }
4607
4608
4609 /****************************************************************************/
4610 /* Reenables interrupt generation during interrupt handling.                */
4611 /*                                                                          */
4612 /* Returns:                                                                 */
4613 /*   Nothing.                                                               */
4614 /****************************************************************************/
4615 static void
4616 bce_reenable_intr(struct bce_rx_ring *rxr)
4617 {
4618         REG_WR(rxr->sc, BCE_PCICFG_INT_ACK_CMD,
4619                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | rxr->last_status_idx);
4620 }
4621
4622
4623 /****************************************************************************/
4624 /* Handles controller initialization.                                       */
4625 /*                                                                          */
4626 /* Returns:                                                                 */
4627 /*   Nothing.                                                               */
4628 /****************************************************************************/
4629 static void
4630 bce_init(void *xsc)
4631 {
4632         struct bce_softc *sc = xsc;
4633         struct ifnet *ifp = &sc->arpcom.ac_if;
4634         uint32_t ether_mtu;
4635         int error, i;
4636         boolean_t polling;
4637
4638         ASSERT_IFNET_SERIALIZED_ALL(ifp);
4639
4640         /* Check if the driver is still running and bail out if it is. */
4641         if (ifp->if_flags & IFF_RUNNING)
4642                 return;
4643
4644         bce_stop(sc);
4645
4646         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4647         if (error) {
4648                 if_printf(ifp, "Controller reset failed!\n");
4649                 goto back;
4650         }
4651
4652         error = bce_chipinit(sc);
4653         if (error) {
4654                 if_printf(ifp, "Controller initialization failed!\n");
4655                 goto back;
4656         }
4657
4658         error = bce_blockinit(sc);
4659         if (error) {
4660                 if_printf(ifp, "Block initialization failed!\n");
4661                 goto back;
4662         }
4663
4664         /* Load our MAC address. */
4665         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4666         bce_set_mac_addr(sc);
4667
4668         /* Calculate and program the Ethernet MTU size. */
4669         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4670
4671         /*
4672          * Program the mtu, enabling jumbo frame
4673          * support if necessary.  Also set the mbuf
4674          * allocation count for RX frames.
4675          */
4676         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4677 #ifdef notyet
4678                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4679                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4680                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4681 #else
4682                 panic("jumbo buffer is not supported yet");
4683 #endif
4684         } else {
4685                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4686         }
4687
4688         /* Program appropriate promiscuous/multicast filtering. */
4689         bce_set_rx_mode(sc);
4690
4691         /* Init RX buffer descriptor chain. */
4692         for (i = 0; i < sc->rx_ring_cnt; ++i)
4693                 bce_init_rx_chain(&sc->rx_rings[i]);    /* XXX return value */
4694
4695         /* Init TX buffer descriptor chain. */
4696         for (i = 0; i < sc->tx_ring_cnt; ++i)
4697                 bce_init_tx_chain(&sc->tx_rings[i]);
4698
4699         polling = FALSE;
4700 #ifdef IFPOLL_ENABLE
4701         if (ifp->if_flags & IFF_NPOLLING)
4702                 polling = TRUE;
4703 #endif
4704
4705         if (polling) {
4706                 /* Disable interrupts if we are polling. */
4707                 bce_disable_intr(sc);
4708
4709                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4710                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4711                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4712                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4713         } else {
4714                 /* Enable host interrupts. */
4715                 bce_enable_intr(sc);
4716         }
4717         bce_set_timer_cpuid(sc, polling);
4718
4719         bce_ifmedia_upd(ifp);
4720
4721         ifp->if_flags |= IFF_RUNNING;
4722         for (i = 0; i < sc->tx_ring_cnt; ++i) {
4723                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
4724                 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
4725         }
4726
4727         callout_reset_bycpu(&sc->bce_tick_callout, hz, bce_tick, sc,
4728             sc->bce_timer_cpuid);
4729 back:
4730         if (error)
4731                 bce_stop(sc);
4732 }
4733
4734
4735 /****************************************************************************/
4736 /* Initialize the controller just enough so that any management firmware    */
4737 /* running on the device will continue to operate corectly.                 */
4738 /*                                                                          */
4739 /* Returns:                                                                 */
4740 /*   Nothing.                                                               */
4741 /****************************************************************************/
4742 static void
4743 bce_mgmt_init(struct bce_softc *sc)
4744 {
4745         struct ifnet *ifp = &sc->arpcom.ac_if;
4746
4747         /* Bail out if management firmware is not running. */
4748         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4749                 return;
4750
4751         /* Enable all critical blocks in the MAC. */
4752         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4753             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4754                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4755                     BCE_MISC_ENABLE_DEFAULT_XI);
4756         } else {
4757                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4758         }
4759         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4760         DELAY(20);
4761
4762         bce_ifmedia_upd(ifp);
4763 }
4764
4765
4766 /****************************************************************************/
4767 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4768 /* memory visible to the controller.                                        */
4769 /*                                                                          */
4770 /* Returns:                                                                 */
4771 /*   0 for success, positive value for failure.                             */
4772 /****************************************************************************/
4773 static int
4774 bce_encap(struct bce_tx_ring *txr, struct mbuf **m_head, int *nsegs_used)
4775 {
4776         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4777         bus_dmamap_t map, tmp_map;
4778         struct mbuf *m0 = *m_head;
4779         struct tx_bd *txbd = NULL;
4780         uint16_t vlan_tag = 0, flags = 0, mss = 0;
4781         uint16_t chain_prod, chain_prod_start, prod;
4782         uint32_t prod_bseq;
4783         int i, error, maxsegs, nsegs;
4784
4785         /* Transfer any checksum offload flags to the bd. */
4786         if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
4787                 error = bce_tso_setup(txr, m_head, &flags, &mss);
4788                 if (error)
4789                         return ENOBUFS;
4790                 m0 = *m_head;
4791         } else if (m0->m_pkthdr.csum_flags & BCE_CSUM_FEATURES) {
4792                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4793                         flags |= TX_BD_FLAGS_IP_CKSUM;
4794                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4795                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4796         }
4797
4798         /* Transfer any VLAN tags to the bd. */
4799         if (m0->m_flags & M_VLANTAG) {
4800                 flags |= TX_BD_FLAGS_VLAN_TAG;
4801                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4802         }
4803
4804         prod = txr->tx_prod;
4805         chain_prod_start = chain_prod = TX_CHAIN_IDX(txr, prod);
4806
4807         /* Map the mbuf into DMAable memory. */
4808         map = txr->tx_mbuf_map[chain_prod_start];
4809
4810         maxsegs = txr->max_tx_bd - txr->used_tx_bd;
4811         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4812                 ("not enough segments %d", maxsegs));
4813         if (maxsegs > BCE_MAX_SEGMENTS)
4814                 maxsegs = BCE_MAX_SEGMENTS;
4815
4816         /* Map the mbuf into our DMA address space. */
4817         error = bus_dmamap_load_mbuf_defrag(txr->tx_mbuf_tag, map, m_head,
4818                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4819         if (error)
4820                 goto back;
4821         bus_dmamap_sync(txr->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4822
4823         *nsegs_used += nsegs;
4824
4825         /* Reset m0 */
4826         m0 = *m_head;
4827
4828         /* prod points to an empty tx_bd at this point. */
4829         prod_bseq  = txr->tx_prod_bseq;
4830
4831         /*
4832          * Cycle through each mbuf segment that makes up
4833          * the outgoing frame, gathering the mapping info
4834          * for that segment and creating a tx_bd to for
4835          * the mbuf.
4836          */
4837         for (i = 0; i < nsegs; i++) {
4838                 chain_prod = TX_CHAIN_IDX(txr, prod);
4839                 txbd =
4840                 &txr->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4841
4842                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4843                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4844                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
4845                     htole16(segs[i].ds_len);
4846                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4847                 txbd->tx_bd_flags = htole16(flags);
4848
4849                 prod_bseq += segs[i].ds_len;
4850                 if (i == 0)
4851                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4852                 prod = NEXT_TX_BD(prod);
4853         }
4854
4855         /* Set the END flag on the last TX buffer descriptor. */
4856         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4857
4858         /*
4859          * Ensure that the mbuf pointer for this transmission
4860          * is placed at the array index of the last
4861          * descriptor in this chain.  This is done
4862          * because a single map is used for all
4863          * segments of the mbuf and we don't want to
4864          * unload the map before all of the segments
4865          * have been freed.
4866          */
4867         txr->tx_mbuf_ptr[chain_prod] = m0;
4868
4869         tmp_map = txr->tx_mbuf_map[chain_prod];
4870         txr->tx_mbuf_map[chain_prod] = map;
4871         txr->tx_mbuf_map[chain_prod_start] = tmp_map;
4872
4873         txr->used_tx_bd += nsegs;
4874
4875         /* prod points to the next free tx_bd at this point. */
4876         txr->tx_prod = prod;
4877         txr->tx_prod_bseq = prod_bseq;
4878 back:
4879         if (error) {
4880                 m_freem(*m_head);
4881                 *m_head = NULL;
4882         }
4883         return error;
4884 }
4885
4886
4887 static void
4888 bce_xmit(struct bce_tx_ring *txr)
4889 {
4890         /* Start the transmit. */
4891         REG_WR16(txr->sc, MB_GET_CID_ADDR(txr->tx_cid) + BCE_L2CTX_TX_HOST_BIDX,
4892             txr->tx_prod);
4893         REG_WR(txr->sc, MB_GET_CID_ADDR(txr->tx_cid) + BCE_L2CTX_TX_HOST_BSEQ,
4894             txr->tx_prod_bseq);
4895 }
4896
4897
4898 /****************************************************************************/
4899 /* Main transmit routine when called from another routine with a lock.      */
4900 /*                                                                          */
4901 /* Returns:                                                                 */
4902 /*   Nothing.                                                               */
4903 /****************************************************************************/
4904 static void
4905 bce_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
4906 {
4907         struct bce_softc *sc = ifp->if_softc;
4908         struct bce_tx_ring *txr = ifsq_get_priv(ifsq);
4909         int count = 0;
4910
4911         KKASSERT(txr->ifsq == ifsq);
4912         ASSERT_SERIALIZED(&txr->tx_serialize);
4913
4914         /* If there's no link or the transmit queue is empty then just exit. */
4915         if (!sc->bce_link) {
4916                 ifsq_purge(ifsq);
4917                 return;
4918         }
4919
4920         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
4921                 return;
4922
4923         for (;;) {
4924                 struct mbuf *m_head;
4925
4926                 /*
4927                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4928                  * unlikely to fail.
4929                  */
4930                 if (txr->max_tx_bd - txr->used_tx_bd < BCE_TX_SPARE_SPACE) {
4931                         ifsq_set_oactive(ifsq);
4932                         break;
4933                 }
4934
4935                 /* Check for any frames to send. */
4936                 m_head = ifsq_dequeue(ifsq, NULL);
4937                 if (m_head == NULL)
4938                         break;
4939
4940                 /*
4941                  * Pack the data into the transmit ring. If we
4942                  * don't have room, place the mbuf back at the
4943                  * head of the queue and set the OACTIVE flag
4944                  * to wait for the NIC to drain the chain.
4945                  */
4946                 if (bce_encap(txr, &m_head, &count)) {
4947                         IFNET_STAT_INC(ifp, oerrors, 1);
4948                         if (txr->used_tx_bd == 0) {
4949                                 continue;
4950                         } else {
4951                                 ifsq_set_oactive(ifsq);
4952                                 break;
4953                         }
4954                 }
4955
4956                 if (count >= txr->tx_wreg) {
4957                         bce_xmit(txr);
4958                         count = 0;
4959                 }
4960
4961                 /* Send a copy of the frame to any BPF listeners. */
4962                 ETHER_BPF_MTAP(ifp, m_head);
4963
4964                 /* Set the tx timeout. */
4965                 txr->tx_watchdog.wd_timer = BCE_TX_TIMEOUT;
4966         }
4967         if (count > 0)
4968                 bce_xmit(txr);
4969 }
4970
4971
4972 /****************************************************************************/
4973 /* Handles any IOCTL calls from the operating system.                       */
4974 /*                                                                          */
4975 /* Returns:                                                                 */
4976 /*   0 for success, positive value for failure.                             */
4977 /****************************************************************************/
4978 static int
4979 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4980 {
4981         struct bce_softc *sc = ifp->if_softc;
4982         struct ifreq *ifr = (struct ifreq *)data;
4983         struct mii_data *mii;
4984         int mask, error = 0;
4985
4986         ASSERT_IFNET_SERIALIZED_ALL(ifp);
4987
4988         switch(command) {
4989         case SIOCSIFMTU:
4990                 /* Check that the MTU setting is supported. */
4991                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4992 #ifdef notyet
4993                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4994 #else
4995                     ifr->ifr_mtu > ETHERMTU
4996 #endif
4997                    ) {
4998                         error = EINVAL;
4999                         break;
5000                 }
5001
5002                 ifp->if_mtu = ifr->ifr_mtu;
5003                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5004                 bce_init(sc);
5005                 break;
5006
5007         case SIOCSIFFLAGS:
5008                 if (ifp->if_flags & IFF_UP) {
5009                         if (ifp->if_flags & IFF_RUNNING) {
5010                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5011
5012                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5013                                         bce_set_rx_mode(sc);
5014                         } else {
5015                                 bce_init(sc);
5016                         }
5017                 } else if (ifp->if_flags & IFF_RUNNING) {
5018                         bce_stop(sc);
5019
5020                         /* If MFW is running, restart the controller a bit. */
5021                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5022                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5023                                 bce_chipinit(sc);
5024                                 bce_mgmt_init(sc);
5025                         }
5026                 }
5027                 sc->bce_if_flags = ifp->if_flags;
5028                 break;
5029
5030         case SIOCADDMULTI:
5031         case SIOCDELMULTI:
5032                 if (ifp->if_flags & IFF_RUNNING)
5033                         bce_set_rx_mode(sc);
5034                 break;
5035
5036         case SIOCSIFMEDIA:
5037         case SIOCGIFMEDIA:
5038                 mii = device_get_softc(sc->bce_miibus);
5039                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5040                 break;
5041
5042         case SIOCSIFCAP:
5043                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5044                 if (mask & IFCAP_HWCSUM) {
5045                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5046                         if (ifp->if_capenable & IFCAP_TXCSUM)
5047                                 ifp->if_hwassist |= BCE_CSUM_FEATURES;
5048                         else
5049                                 ifp->if_hwassist &= ~BCE_CSUM_FEATURES;
5050                 }
5051                 if (mask & IFCAP_TSO) {
5052                         ifp->if_capenable ^= IFCAP_TSO;
5053                         if (ifp->if_capenable & IFCAP_TSO)
5054                                 ifp->if_hwassist |= CSUM_TSO;
5055                         else
5056                                 ifp->if_hwassist &= ~CSUM_TSO;
5057                 }
5058                 break;
5059
5060         default:
5061                 error = ether_ioctl(ifp, command, data);
5062                 break;
5063         }
5064         return error;
5065 }
5066
5067
5068 /****************************************************************************/
5069 /* Transmit timeout handler.                                                */
5070 /*                                                                          */
5071 /* Returns:                                                                 */
5072 /*   Nothing.                                                               */
5073 /****************************************************************************/
5074 static void
5075 bce_watchdog(struct ifaltq_subque *ifsq)
5076 {
5077         struct ifnet *ifp = ifsq_get_ifp(ifsq);
5078         struct bce_softc *sc = ifp->if_softc;
5079         int i;
5080
5081         ASSERT_IFNET_SERIALIZED_ALL(ifp);
5082
5083         /*
5084          * If we are in this routine because of pause frames, then
5085          * don't reset the hardware.
5086          */
5087         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5088                 return;
5089
5090         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5091
5092         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5093         bce_init(sc);
5094
5095         IFNET_STAT_INC(ifp, oerrors, 1);
5096
5097         for (i = 0; i < sc->tx_ring_cnt; ++i)
5098                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
5099 }
5100
5101
5102 #ifdef IFPOLL_ENABLE
5103
5104 static void
5105 bce_npoll_status(struct ifnet *ifp)
5106 {
5107         struct bce_softc *sc = ifp->if_softc;
5108         struct status_block *sblk = sc->status_block;
5109         uint32_t status_attn_bits;
5110
5111         ASSERT_SERIALIZED(&sc->main_serialize);
5112
5113         status_attn_bits = sblk->status_attn_bits;
5114
5115         /* Was it a link change interrupt? */
5116         if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5117             (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5118                 bce_phy_intr(sc);
5119
5120                 /*
5121                  * Clear any transient status updates during link state change.
5122                  */
5123                 REG_WR(sc, BCE_HC_COMMAND,
5124                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5125                 REG_RD(sc, BCE_HC_COMMAND);
5126         }
5127
5128         /*
5129          * If any other attention is asserted then the chip is toast.
5130          */
5131         if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5132              (sblk->status_attn_bits_ack & ~STATUS_ATTN_BITS_LINK_STATE)) {
5133                 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5134                     sblk->status_attn_bits);
5135                 bce_serialize_skipmain(sc);
5136                 bce_init(sc);
5137                 bce_deserialize_skipmain(sc);
5138         }
5139 }
5140
5141 static void
5142 bce_npoll_rx(struct ifnet *ifp, void *arg, int count)
5143 {
5144         struct bce_rx_ring *rxr = arg;
5145         uint16_t hw_rx_cons;
5146
5147         ASSERT_SERIALIZED(&rxr->rx_serialize);
5148
5149         /*
5150          * Save the status block index value for use when enabling
5151          * the interrupt.
5152          */
5153         rxr->last_status_idx = *rxr->hw_status_idx;
5154
5155         /* Make sure status index is extracted before RX/TX cons */
5156         cpu_lfence();
5157
5158         hw_rx_cons = bce_get_hw_rx_cons(rxr);
5159
5160         /* Check for any completed RX frames. */
5161         if (hw_rx_cons != rxr->rx_cons)
5162                 bce_rx_intr(rxr, count, hw_rx_cons);
5163 }
5164
5165 static void
5166 bce_npoll_tx(struct ifnet *ifp, void *arg, int count __unused)
5167 {
5168         struct bce_tx_ring *txr = arg;
5169         uint16_t hw_tx_cons;
5170
5171         ASSERT_SERIALIZED(&txr->tx_serialize);
5172
5173         hw_tx_cons = bce_get_hw_tx_cons(txr);
5174
5175         /* Check for any completed TX frames. */
5176         if (hw_tx_cons != txr->tx_cons) {
5177                 bce_tx_intr(txr, hw_tx_cons);
5178                 if (!ifsq_is_empty(txr->ifsq))
5179                         ifsq_devstart(txr->ifsq);
5180         }
5181 }
5182
5183 static void
5184 bce_npoll(struct ifnet *ifp, struct ifpoll_info *info)
5185 {
5186         struct bce_softc *sc = ifp->if_softc;
5187         int i;
5188
5189         ASSERT_IFNET_SERIALIZED_ALL(ifp);
5190
5191         if (info != NULL) {
5192                 info->ifpi_status.status_func = bce_npoll_status;
5193                 info->ifpi_status.serializer = &sc->main_serialize;
5194
5195                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
5196                         struct bce_tx_ring *txr = &sc->tx_rings[i];
5197                         int idx = i + sc->npoll_ofs;
5198
5199                         KKASSERT(idx < ncpus2);
5200                         info->ifpi_tx[idx].poll_func = bce_npoll_tx;
5201                         info->ifpi_tx[idx].arg = txr;
5202                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
5203                         ifsq_set_cpuid(txr->ifsq, idx);
5204                 }
5205
5206                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
5207                         struct bce_rx_ring *rxr = &sc->rx_rings[i];
5208                         int idx = i + sc->npoll_ofs;
5209
5210                         KKASSERT(idx < ncpus2);
5211                         info->ifpi_rx[idx].poll_func = bce_npoll_rx;
5212                         info->ifpi_rx[idx].arg = rxr;
5213                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
5214                 }
5215
5216                 if (ifp->if_flags & IFF_RUNNING) {
5217                         bce_set_timer_cpuid(sc, TRUE);
5218                         bce_disable_intr(sc);
5219
5220                         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5221                                (1 << 16) | sc->bce_rx_quick_cons_trip);
5222                         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5223                                (1 << 16) | sc->bce_tx_quick_cons_trip);
5224                 }
5225         } else {
5226                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
5227                         ifsq_set_cpuid(sc->tx_rings[i].ifsq,
5228                             sc->bce_intr_cpuid); /* XXX */
5229                 }
5230
5231                 if (ifp->if_flags & IFF_RUNNING) {
5232                         bce_set_timer_cpuid(sc, FALSE);
5233                         bce_enable_intr(sc);
5234
5235                         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5236                                (sc->bce_tx_quick_cons_trip_int << 16) |
5237                                sc->bce_tx_quick_cons_trip);
5238                         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5239                                (sc->bce_rx_quick_cons_trip_int << 16) |
5240                                sc->bce_rx_quick_cons_trip);
5241                 }
5242         }
5243 }
5244
5245 #endif  /* IFPOLL_ENABLE */
5246
5247
5248 /*
5249  * Interrupt handler.
5250  */
5251 /****************************************************************************/
5252 /* Main interrupt entry point.  Verifies that the controller generated the  */
5253 /* interrupt and then calls a separate routine for handle the various       */
5254 /* interrupt causes (PHY, TX, RX).                                          */
5255 /*                                                                          */
5256 /* Returns:                                                                 */
5257 /*   0 for success, positive value for failure.                             */
5258 /****************************************************************************/
5259 static void
5260 bce_intr(struct bce_softc *sc)
5261 {
5262         struct ifnet *ifp = &sc->arpcom.ac_if;
5263         struct status_block *sblk;
5264         uint16_t hw_rx_cons, hw_tx_cons;
5265         uint32_t status_attn_bits;
5266         struct bce_tx_ring *txr = &sc->tx_rings[0];
5267         struct bce_rx_ring *rxr = &sc->rx_rings[0];
5268
5269         ASSERT_SERIALIZED(&sc->main_serialize);
5270
5271         sblk = sc->status_block;
5272
5273         /*
5274          * Save the status block index value for use during
5275          * the next interrupt.
5276          */
5277         rxr->last_status_idx = *rxr->hw_status_idx;
5278
5279         /* Make sure status index is extracted before RX/TX cons */
5280         cpu_lfence();
5281
5282         /* Check if the hardware has finished any work. */
5283         hw_rx_cons = bce_get_hw_rx_cons(rxr);
5284         hw_tx_cons = bce_get_hw_tx_cons(txr);
5285
5286         status_attn_bits = sblk->status_attn_bits;
5287
5288         /* Was it a link change interrupt? */
5289         if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5290             (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5291                 bce_phy_intr(sc);
5292
5293                 /*
5294                  * Clear any transient status updates during link state
5295                  * change.
5296                  */
5297                 REG_WR(sc, BCE_HC_COMMAND,
5298                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5299                 REG_RD(sc, BCE_HC_COMMAND);
5300         }
5301
5302         /*
5303          * If any other attention is asserted then
5304          * the chip is toast.
5305          */
5306         if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5307             (sblk->status_attn_bits_ack & ~STATUS_ATTN_BITS_LINK_STATE)) {
5308                 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5309                           sblk->status_attn_bits);
5310                 bce_serialize_skipmain(sc);
5311                 bce_init(sc);
5312                 bce_deserialize_skipmain(sc);
5313                 return;
5314         }
5315
5316         /* Check for any completed RX frames. */
5317         lwkt_serialize_enter(&rxr->rx_serialize);
5318         if (hw_rx_cons != rxr->rx_cons)
5319                 bce_rx_intr(rxr, -1, hw_rx_cons);
5320         lwkt_serialize_exit(&rxr->rx_serialize);
5321
5322         /* Check for any completed TX frames. */
5323         lwkt_serialize_enter(&txr->tx_serialize);
5324         if (hw_tx_cons != txr->tx_cons) {
5325                 bce_tx_intr(txr, hw_tx_cons);
5326                 if (!ifsq_is_empty(txr->ifsq))
5327                         ifsq_devstart(txr->ifsq);
5328         }
5329         lwkt_serialize_exit(&txr->tx_serialize);
5330 }
5331
5332 static void
5333 bce_intr_legacy(void *xsc)
5334 {
5335         struct bce_softc *sc = xsc;
5336         struct bce_rx_ring *rxr = &sc->rx_rings[0];
5337         struct status_block *sblk;
5338
5339         sblk = sc->status_block;
5340
5341         /*
5342          * If the hardware status block index matches the last value
5343          * read by the driver and we haven't asserted our interrupt
5344          * then there's nothing to do.
5345          */
5346         if (sblk->status_idx == rxr->last_status_idx &&
5347             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5348              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5349                 return;
5350
5351         /* Ack the interrupt and stop others from occuring. */
5352         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5353                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5354                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5355
5356         /*
5357          * Read back to deassert IRQ immediately to avoid too
5358          * many spurious interrupts.
5359          */
5360         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5361
5362         bce_intr(sc);
5363
5364         /* Re-enable interrupts. */
5365         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5366                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
5367                BCE_PCICFG_INT_ACK_CMD_MASK_INT | rxr->last_status_idx);
5368         bce_reenable_intr(rxr);
5369 }
5370
5371 static void
5372 bce_intr_msi(void *xsc)
5373 {
5374         struct bce_softc *sc = xsc;
5375
5376         /* Ack the interrupt and stop others from occuring. */
5377         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5378                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5379                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5380
5381         bce_intr(sc);
5382
5383         /* Re-enable interrupts */
5384         bce_reenable_intr(&sc->rx_rings[0]);
5385 }
5386
5387 static void
5388 bce_intr_msi_oneshot(void *xsc)
5389 {
5390         struct bce_softc *sc = xsc;
5391
5392         bce_intr(sc);
5393
5394         /* Re-enable interrupts */
5395         bce_reenable_intr(&sc->rx_rings[0]);
5396 }
5397
5398
5399 /****************************************************************************/
5400 /* Programs the various packet receive modes (broadcast and multicast).     */
5401 /*                                                                          */
5402 /* Returns:                                                                 */
5403 /*   Nothing.                                                               */
5404 /****************************************************************************/
5405 static void
5406 bce_set_rx_mode(struct bce_softc *sc)
5407 {
5408         struct ifnet *ifp = &sc->arpcom.ac_if;
5409         struct ifmultiaddr *ifma;
5410         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5411         uint32_t rx_mode, sort_mode;
5412         int h, i;
5413
5414         ASSERT_IFNET_SERIALIZED_ALL(ifp);
5415
5416         /* Initialize receive mode default settings. */
5417         rx_mode = sc->rx_mode &
5418                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5419                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5420         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5421
5422         /*
5423          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5424          * be enbled.
5425          */
5426         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5427             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5428                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5429
5430         /*
5431          * Check for promiscuous, all multicast, or selected
5432          * multicast address filtering.
5433          */
5434         if (ifp->if_flags & IFF_PROMISC) {
5435                 /* Enable promiscuous mode. */
5436                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5437                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5438         } else if (ifp->if_flags & IFF_ALLMULTI) {
5439                 /* Enable all multicast addresses. */
5440                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5441                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5442                                0xffffffff);
5443                 }
5444                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5445         } else {
5446                 /* Accept one or more multicast(s). */
5447                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5448                         if (ifma->ifma_addr->sa_family != AF_LINK)
5449                                 continue;
5450                         h = ether_crc32_le(
5451                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5452                             ETHER_ADDR_LEN) & 0xFF;
5453                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5454                 }
5455
5456                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5457                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5458                                hashes[i]);
5459                 }
5460                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5461         }
5462
5463         /* Only make changes if the recive mode has actually changed. */
5464         if (rx_mode != sc->rx_mode) {
5465                 sc->rx_mode = rx_mode;
5466                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5467         }
5468
5469         /* Disable and clear the exisitng sort before enabling a new sort. */
5470         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5471         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5472         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5473 }
5474
5475
5476 /****************************************************************************/
5477 /* Called periodically to updates statistics from the controllers           */
5478 /* statistics block.                                                        */
5479 /*                                                                          */
5480 /* Returns:                                                                 */
5481 /*   Nothing.                                                               */
5482 /****************************************************************************/
5483 static void
5484 bce_stats_update(struct bce_softc *sc)
5485 {
5486         struct ifnet *ifp = &sc->arpcom.ac_if;
5487         struct statistics_block *stats = sc->stats_block;
5488
5489         ASSERT_SERIALIZED(&sc->main_serialize);
5490
5491         /*
5492          * Certain controllers don't report carrier sense errors correctly.
5493          * See errata E11_5708CA0_1165.
5494          */
5495         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5496             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5497                 IFNET_STAT_INC(ifp, oerrors,
5498                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors);
5499         }
5500
5501         /*
5502          * Update the sysctl statistics from the hardware statistics.
5503          */
5504         sc->stat_IfHCInOctets =
5505                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5506                  (uint64_t)stats->stat_IfHCInOctets_lo;
5507
5508         sc->stat_IfHCInBadOctets =
5509                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5510                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5511
5512         sc->stat_IfHCOutOctets =
5513                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5514                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5515
5516         sc->stat_IfHCOutBadOctets =
5517                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5518                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5519
5520         sc->stat_IfHCInUcastPkts =
5521                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5522                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5523
5524         sc->stat_IfHCInMulticastPkts =
5525                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5526                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5527
5528         sc->stat_IfHCInBroadcastPkts =
5529                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5530                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5531
5532         sc->stat_IfHCOutUcastPkts =
5533                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5534                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5535
5536         sc->stat_IfHCOutMulticastPkts =
5537                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5538                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5539
5540         sc->stat_IfHCOutBroadcastPkts =
5541                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5542                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5543
5544         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5545                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5546
5547         sc->stat_Dot3StatsCarrierSenseErrors =
5548                 stats->stat_Dot3StatsCarrierSenseErrors;
5549
5550         sc->stat_Dot3StatsFCSErrors =
5551                 stats->stat_Dot3StatsFCSErrors;
5552
5553         sc->stat_Dot3StatsAlignmentErrors =
5554                 stats->stat_Dot3StatsAlignmentErrors;
5555
5556         sc->stat_Dot3StatsSingleCollisionFrames =
5557                 stats->stat_Dot3StatsSingleCollisionFrames;
5558
5559         sc->stat_Dot3StatsMultipleCollisionFrames =
5560                 stats->stat_Dot3StatsMultipleCollisionFrames;
5561
5562         sc->stat_Dot3StatsDeferredTransmissions =
5563                 stats->stat_Dot3StatsDeferredTransmissions;
5564
5565         sc->stat_Dot3StatsExcessiveCollisions =
5566                 stats->stat_Dot3StatsExcessiveCollisions;
5567
5568         sc->stat_Dot3StatsLateCollisions =
5569                 stats->stat_Dot3StatsLateCollisions;
5570
5571         sc->stat_EtherStatsCollisions =
5572                 stats->stat_EtherStatsCollisions;
5573
5574         sc->stat_EtherStatsFragments =
5575                 stats->stat_EtherStatsFragments;
5576
5577         sc->stat_EtherStatsJabbers =
5578                 stats->stat_EtherStatsJabbers;
5579
5580         sc->stat_EtherStatsUndersizePkts =
5581                 stats->stat_EtherStatsUndersizePkts;
5582
5583         sc->stat_EtherStatsOverrsizePkts =
5584                 stats->stat_EtherStatsOverrsizePkts;
5585
5586         sc->stat_EtherStatsPktsRx64Octets =
5587                 stats->stat_EtherStatsPktsRx64Octets;
5588
5589         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5590                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5591
5592         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5593                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5594
5595         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5596                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5597
5598         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5599                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5600
5601         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5602                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5603
5604         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5605                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5606
5607         sc->stat_EtherStatsPktsTx64Octets =
5608                 stats->stat_EtherStatsPktsTx64Octets;
5609
5610         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5611                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5612
5613         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5614                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5615
5616         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5617                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5618
5619         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5620                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5621
5622         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5623                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5624
5625         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5626                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5627
5628         sc->stat_XonPauseFramesReceived =
5629                 stats->stat_XonPauseFramesReceived;
5630
5631         sc->stat_XoffPauseFramesReceived =
5632                 stats->stat_XoffPauseFramesReceived;
5633
5634         sc->stat_OutXonSent =
5635                 stats->stat_OutXonSent;
5636
5637         sc->stat_OutXoffSent =
5638                 stats->stat_OutXoffSent;
5639
5640         sc->stat_FlowControlDone =
5641                 stats->stat_FlowControlDone;
5642
5643         sc->stat_MacControlFramesReceived =
5644                 stats->stat_MacControlFramesReceived;
5645
5646         sc->stat_XoffStateEntered =
5647                 stats->stat_XoffStateEntered;
5648
5649         sc->stat_IfInFramesL2FilterDiscards =
5650                 stats->stat_IfInFramesL2FilterDiscards;
5651
5652         sc->stat_IfInRuleCheckerDiscards =
5653                 stats->stat_IfInRuleCheckerDiscards;
5654
5655         sc->stat_IfInFTQDiscards =
5656                 stats->stat_IfInFTQDiscards;
5657
5658         sc->stat_IfInMBUFDiscards =
5659                 stats->stat_IfInMBUFDiscards;
5660
5661         sc->stat_IfInRuleCheckerP4Hit =
5662                 stats->stat_IfInRuleCheckerP4Hit;
5663
5664         sc->stat_CatchupInRuleCheckerDiscards =
5665                 stats->stat_CatchupInRuleCheckerDiscards;
5666
5667         sc->stat_CatchupInFTQDiscards =
5668                 stats->stat_CatchupInFTQDiscards;
5669
5670         sc->stat_CatchupInMBUFDiscards =
5671                 stats->stat_CatchupInMBUFDiscards;
5672
5673         sc->stat_CatchupInRuleCheckerP4Hit =
5674                 stats->stat_CatchupInRuleCheckerP4Hit;
5675
5676         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5677
5678         /*
5679          * Update the interface statistics from the
5680          * hardware statistics.
5681          */
5682         IFNET_STAT_SET(ifp, collisions, (u_long)sc->stat_EtherStatsCollisions);
5683
5684         IFNET_STAT_SET(ifp, ierrors, (u_long)sc->stat_EtherStatsUndersizePkts +
5685             (u_long)sc->stat_EtherStatsOverrsizePkts +
5686             (u_long)sc->stat_IfInMBUFDiscards +
5687             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5688             (u_long)sc->stat_Dot3StatsFCSErrors +
5689             (u_long)sc->stat_IfInRuleCheckerDiscards +
5690             (u_long)sc->stat_IfInFTQDiscards +
5691             (u_long)sc->com_no_buffers);
5692
5693         IFNET_STAT_SET(ifp, oerrors,
5694             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5695             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5696             (u_long)sc->stat_Dot3StatsLateCollisions);
5697 }
5698
5699
5700 /****************************************************************************/
5701 /* Periodic function to notify the bootcode that the driver is still        */
5702 /* present.                                                                 */
5703 /*                                                                          */
5704 /* Returns:                                                                 */
5705 /*   Nothing.                                                               */
5706 /****************************************************************************/
5707 static void
5708 bce_pulse(void *xsc)
5709 {
5710         struct bce_softc *sc = xsc;
5711         struct ifnet *ifp = &sc->arpcom.ac_if;
5712         uint32_t msg;
5713
5714         lwkt_serialize_enter(&sc->main_serialize);
5715
5716         /* Tell the firmware that the driver is still running. */
5717         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5718         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5719
5720         /* Update the bootcode condition. */
5721         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5722
5723         /* Report whether the bootcode still knows the driver is running. */
5724         if (!sc->bce_drv_cardiac_arrest) {
5725                 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5726                         sc->bce_drv_cardiac_arrest = 1;
5727                         if_printf(ifp, "Bootcode lost the driver pulse! "
5728                             "(bc_state = 0x%08X)\n", sc->bc_state);
5729                 }
5730         } else {
5731                 /*
5732                  * Not supported by all bootcode versions.
5733                  * (v5.0.11+ and v5.2.1+)  Older bootcode
5734                  * will require the driver to reset the
5735                  * controller to clear this condition.
5736                  */
5737                 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5738                         sc->bce_drv_cardiac_arrest = 0;
5739                         if_printf(ifp, "Bootcode found the driver pulse! "
5740                             "(bc_state = 0x%08X)\n", sc->bc_state);
5741                 }
5742         }
5743
5744         /* Schedule the next pulse. */
5745         callout_reset_bycpu(&sc->bce_pulse_callout, hz, bce_pulse, sc,
5746             sc->bce_timer_cpuid);
5747
5748         lwkt_serialize_exit(&sc->main_serialize);
5749 }
5750
5751
5752 /****************************************************************************/
5753 /* Periodic function to check whether MSI is lost                           */
5754 /*                                                                          */
5755 /* Returns:                                                                 */
5756 /*   Nothing.                                                               */
5757 /****************************************************************************/
5758 static void
5759 bce_check_msi(void *xsc)
5760 {
5761         struct bce_softc *sc = xsc;
5762         struct ifnet *ifp = &sc->arpcom.ac_if;
5763         struct status_block *sblk = sc->status_block;
5764         struct bce_tx_ring *txr = &sc->tx_rings[0];
5765         struct bce_rx_ring *rxr = &sc->rx_rings[0];
5766
5767         lwkt_serialize_enter(&sc->main_serialize);
5768
5769         KKASSERT(mycpuid == sc->bce_intr_cpuid);
5770
5771         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
5772                 lwkt_serialize_exit(&sc->main_serialize);
5773                 return;
5774         }
5775
5776         if (bce_get_hw_rx_cons(rxr) != rxr->rx_cons ||
5777             bce_get_hw_tx_cons(txr) != txr->tx_cons ||
5778             (sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5779             (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5780                 if (sc->bce_check_rx_cons == rxr->rx_cons &&
5781                     sc->bce_check_tx_cons == txr->tx_cons &&
5782                     sc->bce_check_status_idx == rxr->last_status_idx) {
5783                         uint32_t msi_ctrl;
5784
5785                         if (!sc->bce_msi_maylose) {
5786                                 sc->bce_msi_maylose = TRUE;
5787                                 goto done;
5788                         }
5789
5790                         msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
5791                         if (msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) {
5792                                 if (bootverbose)
5793                                         if_printf(ifp, "lost MSI\n");
5794
5795                                 REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
5796                                     msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
5797                                 REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
5798
5799                                 bce_intr_msi(sc);
5800                         } else if (bootverbose) {
5801                                 if_printf(ifp, "MSI may be lost\n");
5802                         }
5803                 }
5804         }
5805         sc->bce_msi_maylose = FALSE;
5806         sc->bce_check_rx_cons = rxr->rx_cons;
5807         sc->bce_check_tx_cons = txr->tx_cons;
5808         sc->bce_check_status_idx = rxr->last_status_idx;
5809
5810 done:
5811         callout_reset(&sc->bce_ckmsi_callout, BCE_MSI_CKINTVL,
5812             bce_check_msi, sc);
5813         lwkt_serialize_exit(&sc->main_serialize);
5814 }
5815
5816
5817 /****************************************************************************/
5818 /* Periodic function to perform maintenance tasks.                          */
5819 /*                                                                          */
5820 /* Returns:                                                                 */
5821 /*   Nothing.                                                               */
5822 /****************************************************************************/
5823 static void
5824 bce_tick_serialized(struct bce_softc *sc)
5825 {
5826         struct mii_data *mii;
5827
5828         ASSERT_SERIALIZED(&sc->main_serialize);
5829
5830         /* Update the statistics from the hardware statistics block. */
5831         bce_stats_update(sc);
5832
5833         /* Schedule the next tick. */
5834         callout_reset_bycpu(&sc->bce_tick_callout, hz, bce_tick, sc,
5835             sc->bce_timer_cpuid);
5836
5837         /* If link is up already up then we're done. */
5838         if (sc->bce_link)
5839                 return;
5840
5841         mii = device_get_softc(sc->bce_miibus);
5842         mii_tick(mii);
5843
5844         /* Check if the link has come up. */
5845         if ((mii->mii_media_status & IFM_ACTIVE) &&
5846             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5847                 int i;
5848
5849                 sc->bce_link++;
5850                 /* Now that link is up, handle any outstanding TX traffic. */
5851                 for (i = 0; i < sc->tx_ring_cnt; ++i)
5852                         ifsq_devstart_sched(sc->tx_rings[i].ifsq);
5853         }
5854 }
5855
5856
5857 static void
5858 bce_tick(void *xsc)
5859 {
5860         struct bce_softc *sc = xsc;
5861
5862         lwkt_serialize_enter(&sc->main_serialize);
5863         bce_tick_serialized(sc);
5864         lwkt_serialize_exit(&sc->main_serialize);
5865 }
5866
5867
5868 /****************************************************************************/
5869 /* Adds any sysctl parameters for tuning or debugging purposes.             */
5870 /*                                                                          */
5871 /* Returns:                                                                 */
5872 /*   0 for success, positive value for failure.                             */
5873 /****************************************************************************/
5874 static void
5875 bce_add_sysctls(struct bce_softc *sc)
5876 {
5877         struct sysctl_ctx_list *ctx;
5878         struct sysctl_oid_list *children;
5879
5880         sysctl_ctx_init(&sc->bce_sysctl_ctx);
5881         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5882                                               SYSCTL_STATIC_CHILDREN(_hw),
5883                                               OID_AUTO,
5884                                               device_get_nameunit(sc->bce_dev),
5885                                               CTLFLAG_RD, 0, "");
5886         if (sc->bce_sysctl_tree == NULL) {
5887                 device_printf(sc->bce_dev, "can't add sysctl node\n");
5888                 return;
5889         }
5890
5891         ctx = &sc->bce_sysctl_ctx;
5892         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5893
5894         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5895                         CTLTYPE_INT | CTLFLAG_RW,
5896                         sc, 0, bce_sysctl_tx_bds_int, "I",
5897                         "Send max coalesced BD count during interrupt");
5898         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5899                         CTLTYPE_INT | CTLFLAG_RW,
5900                         sc, 0, bce_sysctl_tx_bds, "I",
5901                         "Send max coalesced BD count");
5902         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5903                         CTLTYPE_INT | CTLFLAG_RW,
5904                         sc, 0, bce_sysctl_tx_ticks_int, "I",
5905                         "Send coalescing ticks during interrupt");
5906         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5907                         CTLTYPE_INT | CTLFLAG_RW,
5908                         sc, 0, bce_sysctl_tx_ticks, "I",
5909                         "Send coalescing ticks");
5910
5911         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5912                         CTLTYPE_INT | CTLFLAG_RW,
5913                         sc, 0, bce_sysctl_rx_bds_int, "I",
5914                         "Receive max coalesced BD count during interrupt");
5915         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5916                         CTLTYPE_INT | CTLFLAG_RW,
5917                         sc, 0, bce_sysctl_rx_bds, "I",
5918                         "Receive max coalesced BD count");
5919         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5920                         CTLTYPE_INT | CTLFLAG_RW,
5921                         sc, 0, bce_sysctl_rx_ticks_int, "I",
5922                         "Receive coalescing ticks during interrupt");
5923         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5924                         CTLTYPE_INT | CTLFLAG_RW,
5925                         sc, 0, bce_sysctl_rx_ticks, "I",
5926                         "Receive coalescing ticks");
5927
5928         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
5929                 CTLFLAG_RD, &sc->rx_rings[0].rx_pages, 0, "# of RX pages");
5930         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
5931                 CTLFLAG_RD, &sc->tx_rings[0].tx_pages, 0, "# of TX pages");
5932
5933         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_wreg",
5934                 CTLFLAG_RW, &sc->tx_rings[0].tx_wreg, 0,
5935                 "# segments before write to hardware registers");
5936
5937 #ifdef IFPOLL_ENABLE
5938         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "npoll_offset",
5939             CTLTYPE_INT|CTLFLAG_RW, sc, 0, bce_sysctl_npoll_offset,
5940             "I", "NPOLLING cpu offset");
5941 #endif
5942
5943         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5944                 "stat_IfHCInOctets",
5945                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
5946                 "Bytes received");
5947
5948         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5949                 "stat_IfHCInBadOctets",
5950                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
5951                 "Bad bytes received");
5952
5953         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5954                 "stat_IfHCOutOctets",
5955                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
5956                 "Bytes sent");
5957
5958         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5959                 "stat_IfHCOutBadOctets",
5960                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
5961                 "Bad bytes sent");
5962
5963         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5964                 "stat_IfHCInUcastPkts",
5965                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
5966                 "Unicast packets received");
5967
5968         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5969                 "stat_IfHCInMulticastPkts",
5970                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
5971                 "Multicast packets received");
5972
5973         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5974                 "stat_IfHCInBroadcastPkts",
5975                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
5976                 "Broadcast packets received");
5977
5978         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5979                 "stat_IfHCOutUcastPkts",
5980                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
5981                 "Unicast packets sent");
5982
5983         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5984                 "stat_IfHCOutMulticastPkts",
5985                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
5986                 "Multicast packets sent");
5987
5988         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5989                 "stat_IfHCOutBroadcastPkts",
5990                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
5991                 "Broadcast packets sent");
5992
5993         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5994                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
5995                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
5996                 0, "Internal MAC transmit errors");
5997
5998         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5999                 "stat_Dot3StatsCarrierSenseErrors",
6000                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6001                 0, "Carrier sense errors");
6002
6003         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6004                 "stat_Dot3StatsFCSErrors",
6005                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6006                 0, "Frame check sequence errors");
6007
6008         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6009                 "stat_Dot3StatsAlignmentErrors",
6010                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6011                 0, "Alignment errors");
6012
6013         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6014                 "stat_Dot3StatsSingleCollisionFrames",
6015                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6016                 0, "Single Collision Frames");
6017
6018         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6019                 "stat_Dot3StatsMultipleCollisionFrames",
6020                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6021                 0, "Multiple Collision Frames");
6022
6023         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6024                 "stat_Dot3StatsDeferredTransmissions",
6025                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6026                 0, "Deferred Transmissions");
6027
6028         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6029                 "stat_Dot3StatsExcessiveCollisions",
6030                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6031                 0, "Excessive Collisions");
6032
6033         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6034                 "stat_Dot3StatsLateCollisions",
6035                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6036                 0, "Late Collisions");
6037
6038         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6039                 "stat_EtherStatsCollisions",
6040                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6041                 0, "Collisions");
6042
6043         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6044                 "stat_EtherStatsFragments",
6045                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6046                 0, "Fragments");
6047
6048         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6049                 "stat_EtherStatsJabbers",
6050                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6051                 0, "Jabbers");
6052
6053         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6054                 "stat_EtherStatsUndersizePkts",
6055                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6056                 0, "Undersize packets");
6057
6058         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6059                 "stat_EtherStatsOverrsizePkts",
6060                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6061                 0, "stat_EtherStatsOverrsizePkts");
6062
6063         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6064                 "stat_EtherStatsPktsRx64Octets",
6065                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6066                 0, "Bytes received in 64 byte packets");
6067
6068         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6069                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6070                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6071                 0, "Bytes received in 65 to 127 byte packets");
6072
6073         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6074                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6075                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6076                 0, "Bytes received in 128 to 255 byte packets");
6077
6078         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6079                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6080                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6081                 0, "Bytes received in 256 to 511 byte packets");
6082
6083         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6084                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6085                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6086                 0, "Bytes received in 512 to 1023 byte packets");
6087
6088         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6089                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6090                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6091                 0, "Bytes received in 1024 t0 1522 byte packets");
6092
6093         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6094                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6095                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6096                 0, "Bytes received in 1523 to 9022 byte packets");
6097
6098         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6099                 "stat_EtherStatsPktsTx64Octets",
6100                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6101                 0, "Bytes sent in 64 byte packets");
6102
6103         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6104                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6105                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6106                 0, "Bytes sent in 65 to 127 byte packets");
6107
6108         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6109                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6110                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6111                 0, "Bytes sent in 128 to 255 byte packets");
6112
6113         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6114                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6115                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6116                 0, "Bytes sent in 256 to 511 byte packets");
6117
6118         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6119                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6120                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6121                 0, "Bytes sent in 512 to 1023 byte packets");
6122
6123         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6124                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6125                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6126                 0, "Bytes sent in 1024 to 1522 byte packets");
6127
6128         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6129                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6130                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6131                 0, "Bytes sent in 1523 to 9022 byte packets");
6132
6133         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6134                 "stat_XonPauseFramesReceived",
6135                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6136                 0, "XON pause frames receved");
6137
6138         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6139                 "stat_XoffPauseFramesReceived",
6140                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6141                 0, "XOFF pause frames received");
6142
6143         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6144                 "stat_OutXonSent",
6145                 CTLFLAG_RD, &sc->stat_OutXonSent,
6146                 0, "XON pause frames sent");
6147
6148         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6149                 "stat_OutXoffSent",
6150                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6151                 0, "XOFF pause frames sent");
6152
6153         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6154                 "stat_FlowControlDone",
6155                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6156                 0, "Flow control done");
6157
6158         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6159                 "stat_MacControlFramesReceived",
6160                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6161                 0, "MAC control frames received");
6162
6163         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6164                 "stat_XoffStateEntered",
6165                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6166                 0, "XOFF state entered");
6167
6168         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6169                 "stat_IfInFramesL2FilterDiscards",
6170                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6171                 0, "Received L2 packets discarded");
6172
6173         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6174                 "stat_IfInRuleCheckerDiscards",
6175                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6176                 0, "Received packets discarded by rule");
6177
6178         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6179                 "stat_IfInFTQDiscards",
6180                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6181                 0, "Received packet FTQ discards");
6182
6183         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6184                 "stat_IfInMBUFDiscards",
6185                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6186                 0, "Received packets discarded due to lack of controller buffer memory");
6187
6188         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6189                 "stat_IfInRuleCheckerP4Hit",
6190                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6191                 0, "Received packets rule checker hits");
6192
6193         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6194                 "stat_CatchupInRuleCheckerDiscards",
6195                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6196                 0, "Received packets discarded in Catchup path");
6197
6198         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6199                 "stat_CatchupInFTQDiscards",
6200                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6201                 0, "Received packets discarded in FTQ in Catchup path");
6202
6203         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6204                 "stat_CatchupInMBUFDiscards",
6205                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6206                 0, "Received packets discarded in controller buffer memory in Catchup path");
6207
6208         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6209                 "stat_CatchupInRuleCheckerP4Hit",
6210                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6211                 0, "Received packets rule checker hits in Catchup path");
6212
6213         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6214                 "com_no_buffers",
6215                 CTLFLAG_RD, &sc->com_no_buffers,
6216                 0, "Valid packets received but no RX buffers available");
6217 }
6218
6219 static int
6220 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
6221 {
6222         struct bce_softc *sc = arg1;
6223
6224         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6225                         &sc->bce_tx_quick_cons_trip_int,
6226                         BCE_COALMASK_TX_BDS_INT);
6227 }
6228
6229 static int
6230 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
6231 {
6232         struct bce_softc *sc = arg1;
6233
6234         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6235                         &sc->bce_tx_quick_cons_trip,
6236                         BCE_COALMASK_TX_BDS);
6237 }
6238
6239 static int
6240 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
6241 {
6242         struct bce_softc *sc = arg1;
6243
6244         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6245                         &sc->bce_tx_ticks_int,
6246                         BCE_COALMASK_TX_TICKS_INT);
6247 }
6248
6249 static int
6250 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
6251 {
6252         struct bce_softc *sc = arg1;
6253
6254         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6255                         &sc->bce_tx_ticks,
6256                         BCE_COALMASK_TX_TICKS);
6257 }
6258
6259 static int
6260 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
6261 {
6262         struct bce_softc *sc = arg1;
6263
6264         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6265                         &sc->bce_rx_quick_cons_trip_int,
6266                         BCE_COALMASK_RX_BDS_INT);
6267 }
6268
6269 static int
6270 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
6271 {
6272         struct bce_softc *sc = arg1;
6273
6274         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6275                         &sc->bce_rx_quick_cons_trip,
6276                         BCE_COALMASK_RX_BDS);
6277 }
6278
6279 static int
6280 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
6281 {
6282         struct bce_softc *sc = arg1;
6283
6284         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6285                         &sc->bce_rx_ticks_int,
6286                         BCE_COALMASK_RX_TICKS_INT);
6287 }
6288
6289 static int
6290 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
6291 {
6292         struct bce_softc *sc = arg1;
6293
6294         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
6295                         &sc->bce_rx_ticks,
6296                         BCE_COALMASK_RX_TICKS);
6297 }
6298
6299 static int
6300 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
6301                        uint32_t coalchg_mask)
6302 {
6303         struct bce_softc *sc = arg1;
6304         struct ifnet *ifp = &sc->arpcom.ac_if;
6305         int error = 0, v;
6306
6307         ifnet_serialize_all(ifp);
6308
6309         v = *coal;
6310         error = sysctl_handle_int(oidp, &v, 0, req);
6311         if (!error && req->newptr != NULL) {
6312                 if (v < 0) {
6313                         error = EINVAL;
6314                 } else {
6315                         *coal = v;
6316                         sc->bce_coalchg_mask |= coalchg_mask;
6317
6318                         /* Commit changes */
6319                         bce_coal_change(sc);
6320                 }
6321         }
6322
6323         ifnet_deserialize_all(ifp);
6324         return error;
6325 }
6326
6327 static void
6328 bce_coal_change(struct bce_softc *sc)
6329 {
6330         struct ifnet *ifp = &sc->arpcom.ac_if;
6331
6332         ASSERT_SERIALIZED(&sc->main_serialize);
6333
6334         if ((ifp->if_flags & IFF_RUNNING) == 0) {
6335                 sc->bce_coalchg_mask = 0;
6336                 return;
6337         }
6338
6339         if (sc->bce_coalchg_mask &
6340             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
6341                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
6342                        (sc->bce_tx_quick_cons_trip_int << 16) |
6343                        sc->bce_tx_quick_cons_trip);
6344                 if (bootverbose) {
6345                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
6346                                   sc->bce_tx_quick_cons_trip,
6347                                   sc->bce_tx_quick_cons_trip_int);
6348                 }
6349         }
6350
6351         if (sc->bce_coalchg_mask &
6352             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
6353                 REG_WR(sc, BCE_HC_TX_TICKS,
6354                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
6355                 if (bootverbose) {
6356                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
6357                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
6358                 }
6359         }
6360
6361         if (sc->bce_coalchg_mask &
6362             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
6363                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
6364                        (sc->bce_rx_quick_cons_trip_int << 16) |
6365                        sc->bce_rx_quick_cons_trip);
6366                 if (bootverbose) {
6367                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
6368                                   sc->bce_rx_quick_cons_trip,
6369                                   sc->bce_rx_quick_cons_trip_int);
6370                 }
6371         }
6372
6373         if (sc->bce_coalchg_mask &
6374             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
6375                 REG_WR(sc, BCE_HC_RX_TICKS,
6376                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
6377                 if (bootverbose) {
6378                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
6379                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
6380                 }
6381         }
6382
6383         sc->bce_coalchg_mask = 0;
6384 }
6385
6386 static int
6387 bce_tso_setup(struct bce_tx_ring *txr, struct mbuf **mp,
6388     uint16_t *flags0, uint16_t *mss0)
6389 {
6390         struct mbuf *m;
6391         uint16_t flags;
6392         int thoff, iphlen, hoff;
6393
6394         m = *mp;
6395         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
6396
6397         hoff = m->m_pkthdr.csum_lhlen;
6398         iphlen = m->m_pkthdr.csum_iphlen;
6399         thoff = m->m_pkthdr.csum_thlen;
6400
6401         KASSERT(hoff >= sizeof(struct ether_header),
6402             ("invalid ether header len %d", hoff));
6403         KASSERT(iphlen >= sizeof(struct ip),
6404             ("invalid ip header len %d", iphlen));
6405         KASSERT(thoff >= sizeof(struct tcphdr),
6406             ("invalid tcp header len %d", thoff));
6407
6408         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
6409                 m = m_pullup(m, hoff + iphlen + thoff);
6410                 if (m == NULL) {
6411                         *mp = NULL;
6412                         return ENOBUFS;
6413                 }
6414                 *mp = m;
6415         }
6416
6417         /* Set the LSO flag in the TX BD */
6418         flags = TX_BD_FLAGS_SW_LSO;
6419
6420         /* Set the length of IP + TCP options (in 32 bit words) */
6421         flags |= (((iphlen + thoff -
6422             sizeof(struct ip) - sizeof(struct tcphdr)) >> 2) << 8);
6423
6424         *mss0 = htole16(m->m_pkthdr.tso_segsz);
6425         *flags0 = flags;
6426
6427         return 0;
6428 }
6429
6430 static void
6431 bce_setup_serialize(struct bce_softc *sc)
6432 {
6433         int i, j;
6434
6435         /*
6436          * Allocate serializer array
6437          */
6438
6439         /* Main + TX + RX */
6440         sc->serialize_cnt = 1 + sc->tx_ring_cnt + sc->rx_ring_cnt;
6441
6442         sc->serializes =
6443             kmalloc(sc->serialize_cnt * sizeof(struct lwkt_serialize *),
6444                 M_DEVBUF, M_WAITOK | M_ZERO);
6445
6446         /*
6447          * Setup serializers
6448          *
6449          * NOTE: Order is critical
6450          */
6451
6452         i = 0;
6453         KKASSERT(i < sc->serialize_cnt);
6454         sc->serializes[i++] = &sc->main_serialize;
6455
6456         sc->rx_serialize = i;
6457         for (j = 0; j < sc->rx_ring_cnt; ++j) {
6458                 KKASSERT(i < sc->serialize_cnt);
6459                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
6460         }
6461
6462         sc->tx_serialize = i;
6463         for (j = 0; j < sc->tx_ring_cnt; ++j) {
6464                 KKASSERT(i < sc->serialize_cnt);
6465                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
6466         }
6467
6468         KKASSERT(i == sc->serialize_cnt);
6469 }
6470
6471 static void
6472 bce_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
6473 {
6474         struct bce_softc *sc = ifp->if_softc;
6475
6476         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
6477             sc->tx_serialize, sc->rx_serialize, slz);
6478 }
6479
6480 static void
6481 bce_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
6482 {
6483         struct bce_softc *sc = ifp->if_softc;
6484
6485         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
6486             sc->tx_serialize, sc->rx_serialize, slz);
6487 }
6488
6489 static int
6490 bce_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
6491 {
6492         struct bce_softc *sc = ifp->if_softc;
6493
6494         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
6495             sc->tx_serialize, sc->rx_serialize, slz);
6496 }
6497
6498 #ifdef INVARIANTS
6499
6500 static void
6501 bce_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
6502     boolean_t serialized)
6503 {
6504         struct bce_softc *sc = ifp->if_softc;
6505
6506         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
6507             sc->tx_serialize, sc->rx_serialize, slz, serialized);
6508 }
6509
6510 #endif  /* INVARIANTS */
6511
6512 static void
6513 bce_serialize_skipmain(struct bce_softc *sc)
6514 {
6515         lwkt_serialize_array_enter(sc->serializes, sc->serialize_cnt, 1);
6516 }
6517
6518 static void
6519 bce_deserialize_skipmain(struct bce_softc *sc)
6520 {
6521         lwkt_serialize_array_exit(sc->serializes, sc->serialize_cnt, 1);
6522 }
6523
6524 #ifdef IFPOLL_ENABLE
6525
6526 static int
6527 bce_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS)
6528 {
6529         struct bce_softc *sc = (void *)arg1;
6530         struct ifnet *ifp = &sc->arpcom.ac_if;
6531         int error, off;
6532
6533         off = sc->npoll_ofs;
6534         error = sysctl_handle_int(oidp, &off, 0, req);
6535         if (error || req->newptr == NULL)
6536                 return error;
6537         if (off < 0)
6538                 return EINVAL;
6539
6540         ifnet_serialize_all(ifp);
6541         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
6542                 error = EINVAL;
6543         } else {
6544                 error = 0;
6545                 sc->npoll_ofs = off;
6546         }
6547         ifnet_deserialize_all(ifp);
6548
6549         return error;
6550 }
6551
6552 #endif  /* IFPOLL_ENABLE */
6553
6554 static void
6555 bce_set_timer_cpuid(struct bce_softc *sc, boolean_t polling)
6556 {
6557         if (polling)
6558                 sc->bce_timer_cpuid = 0; /* XXX */
6559         else
6560                 sc->bce_timer_cpuid = rman_get_cpuid(sc->bce_res_irq);
6561 }