sys/dev/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  *
  23  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_pm.c 254885 2013-08-25 19:37:15Z dumbbell $
  24  */
  25
  26 #include <sys/power.h>
  27 #include <drm/drmP.h>
  28 #include <sys/sensors.h>
  29 #include "radeon.h"
  30 #include "avivod.h"
  31 #include "atom.h"
  32
  33 #define RADEON_IDLE_LOOP_MS 100
  34 #define RADEON_RECLOCK_DELAY_MS 200
  35 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  36
  37 static const char *radeon_pm_state_type_name[5] = {
  38         "",
  39         "Powersave",
  40         "Battery",
  41         "Balanced",
  42         "Performance",
  43 };
  44
  45 #ifdef DUMBBELL_WIP
  46 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  47 #endif /* DUMBBELL_WIP */
  48 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  49 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  51 static void radeon_pm_update_profile(struct radeon_device *rdev);
  52 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  53
  54 int radeon_pm_get_type_index(struct radeon_device *rdev,
  55                              enum radeon_pm_state_type ps_type,
  56                              int instance)
  57 {
  58         int i;
  59         int found_instance = -1;
  60
  61         for (i = 0; i < rdev->pm.num_power_states; i++) {
  62                 if (rdev->pm.power_state[i].type == ps_type) {
  63                         found_instance++;
  64                         if (found_instance == instance)
  65                                 return i;
  66                 }
  67         }
  68         /* return default if no match */
  69         return rdev->pm.default_power_state_index;
  70 }
  71
  72 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  73 {
  74         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  75                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  76                         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
  77                         radeon_pm_update_profile(rdev);
  78                         radeon_pm_set_clocks(rdev);
  79                         lockmgr(&rdev->pm.mutex, LK_RELEASE);
  80                 }
  81         }
  82 }
  83
  84 static void radeon_pm_update_profile(struct radeon_device *rdev)
  85 {
  86         switch (rdev->pm.profile) {
  87         case PM_PROFILE_DEFAULT:
  88                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  89                 break;
  90         case PM_PROFILE_AUTO:
  91                 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) {
  92                         if (rdev->pm.active_crtc_count > 1)
  93                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  94                         else
  95                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  96                 } else {
  97                         if (rdev->pm.active_crtc_count > 1)
  98                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  99                         else
 100                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 101                 }
 102                 break;
 103         case PM_PROFILE_LOW:
 104                 if (rdev->pm.active_crtc_count > 1)
 105                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 106                 else
 107                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 108                 break;
 109         case PM_PROFILE_MID:
 110                 if (rdev->pm.active_crtc_count > 1)
 111                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 112                 else
 113                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 114                 break;
 115         case PM_PROFILE_HIGH:
 116                 if (rdev->pm.active_crtc_count > 1)
 117                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 118                 else
 119                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 120                 break;
 121         }
 122
 123         if (rdev->pm.active_crtc_count == 0) {
 124                 rdev->pm.requested_power_state_index =
 125                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 126                 rdev->pm.requested_clock_mode_index =
 127                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 128         } else {
 129                 rdev->pm.requested_power_state_index =
 130                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 131                 rdev->pm.requested_clock_mode_index =
 132                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 133         }
 134 }
 135
 136 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 137 {
 138         struct radeon_bo *bo, *n;
 139
 140         if (list_empty(&rdev->gem.objects))
 141                 return;
 142
 143         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 144                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 145                         ttm_bo_unmap_virtual(&bo->tbo);
 146         }
 147 }
 148
 149 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 150 {
 151         if (rdev->pm.active_crtcs) {
 152                 rdev->pm.vblank_sync = false;
 153 #ifdef DUMBBELL_WIP
 154                 wait_event_timeout(
 155                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 156                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 157 #endif /* DUMBBELL_WIP */
 158         }
 159 }
 160
 161 static void radeon_set_power_state(struct radeon_device *rdev)
 162 {
 163         u32 sclk, mclk;
 164         bool misc_after = false;
 165
 166         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 167             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 168                 return;
 169
 170         if (radeon_gui_idle(rdev)) {
 171                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 172                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 173                 if (sclk > rdev->pm.default_sclk)
 174                         sclk = rdev->pm.default_sclk;
 175
 176                 /* starting with BTC, there is one state that is used for both
 177                  * MH and SH.  Difference is that we always use the high clock index for
 178                  * mclk and vddci.
 179                  */
 180                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 181                     (rdev->family >= CHIP_BARTS) &&
 182                     rdev->pm.active_crtc_count &&
 183                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 184                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 185                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 186                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 187                 else
 188                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 189                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 190
 191                 if (mclk > rdev->pm.default_mclk)
 192                         mclk = rdev->pm.default_mclk;
 193
 194                 /* upvolt before raising clocks, downvolt after lowering clocks */
 195                 if (sclk < rdev->pm.current_sclk)
 196                         misc_after = true;
 197
 198                 radeon_sync_with_vblank(rdev);
 199
 200                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 201                         if (!radeon_pm_in_vbl(rdev))
 202                                 return;
 203                 }
 204
 205                 radeon_pm_prepare(rdev);
 206
 207                 if (!misc_after)
 208                         /* voltage, pcie lanes, etc.*/
 209                         radeon_pm_misc(rdev);
 210
 211                 /* set engine clock */
 212                 if (sclk != rdev->pm.current_sclk) {
 213                         radeon_pm_debug_check_in_vbl(rdev, false);
 214                         radeon_set_engine_clock(rdev, sclk);
 215                         radeon_pm_debug_check_in_vbl(rdev, true);
 216                         rdev->pm.current_sclk = sclk;
 217                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 218                 }
 219
 220                 /* set memory clock */
 221                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 222                         radeon_pm_debug_check_in_vbl(rdev, false);
 223                         radeon_set_memory_clock(rdev, mclk);
 224                         radeon_pm_debug_check_in_vbl(rdev, true);
 225                         rdev->pm.current_mclk = mclk;
 226                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 227                 }
 228
 229                 if (misc_after)
 230                         /* voltage, pcie lanes, etc.*/
 231                         radeon_pm_misc(rdev);
 232
 233                 radeon_pm_finish(rdev);
 234
 235                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 236                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 237         } else
 238                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 239 }
 240
 241 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 242 {
 243         int i, r;
 244
 245         /* no need to take locks, etc. if nothing's going to change */
 246         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 247             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 248                 return;
 249
 250         DRM_LOCK(rdev->ddev);
 251         lockmgr(&rdev->pm.mclk_lock, LK_EXCLUSIVE); // down_write
 252         lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
 253
 254         /* wait for the rings to drain */
 255         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 256                 struct radeon_ring *ring = &rdev->ring[i];
 257                 if (!ring->ready) {
 258                         continue;
 259                 }
 260                 r = radeon_fence_wait_empty_locked(rdev, i);
 261                 if (r) {
 262                         /* needs a GPU reset dont reset here */
 263                         lockmgr(&rdev->ring_lock, LK_RELEASE);
 264                         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); // up_write
 265                         DRM_UNLOCK(rdev->ddev);
 266                         return;
 267                 }
 268         }
 269
 270         radeon_unmap_vram_bos(rdev);
 271
 272         if (rdev->irq.installed) {
 273                 for (i = 0; i < rdev->num_crtc; i++) {
 274                         if (rdev->pm.active_crtcs & (1 << i)) {
 275                                 rdev->pm.req_vblank |= (1 << i);
 276                                 drm_vblank_get(rdev->ddev, i);
 277                         }
 278                 }
 279         }
 280
 281         radeon_set_power_state(rdev);
 282
 283         if (rdev->irq.installed) {
 284                 for (i = 0; i < rdev->num_crtc; i++) {
 285                         if (rdev->pm.req_vblank & (1 << i)) {
 286                                 rdev->pm.req_vblank &= ~(1 << i);
 287                                 drm_vblank_put(rdev->ddev, i);
 288                         }
 289                 }
 290         }
 291
 292         /* update display watermarks based on new power state */
 293         radeon_update_bandwidth_info(rdev);
 294         if (rdev->pm.active_crtc_count)
 295                 radeon_bandwidth_update(rdev);
 296
 297         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 298
 299         lockmgr(&rdev->ring_lock, LK_RELEASE);
 300         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); // up_write
 301         DRM_UNLOCK(rdev->ddev);
 302 }
 303
 304 static void radeon_pm_print_states(struct radeon_device *rdev)
 305 {
 306         int i, j;
 307         struct radeon_power_state *power_state;
 308         struct radeon_pm_clock_info *clock_info;
 309
 310         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 311         for (i = 0; i < rdev->pm.num_power_states; i++) {
 312                 power_state = &rdev->pm.power_state[i];
 313                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 314                         radeon_pm_state_type_name[power_state->type]);
 315                 if (i == rdev->pm.default_power_state_index)
 316                         DRM_DEBUG_DRIVER("\tDefault");
 317                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 318                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 319                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 320                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 321                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 322                 for (j = 0; j < power_state->num_clock_modes; j++) {
 323                         clock_info = &(power_state->clock_info[j]);
 324                         if (rdev->flags & RADEON_IS_IGP)
 325                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 326                                                  j,
 327                                                  clock_info->sclk * 10);
 328                         else
 329                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 330                                                  j,
 331                                                  clock_info->sclk * 10,
 332                                                  clock_info->mclk * 10,
 333                                                  clock_info->voltage.voltage);
 334                 }
 335         }
 336 }
 337
 338 #ifdef DUMBBELL_WIP
 339 static ssize_t radeon_get_pm_profile(struct device *dev,
 340                                      struct device_attribute *attr,
 341                                      char *buf)
 342 {
 343         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 344         struct radeon_device *rdev = ddev->dev_private;
 345         int cp = rdev->pm.profile;
 346
 347         return ksnprintf(buf, PAGE_SIZE, "%s\n",
 348                         (cp == PM_PROFILE_AUTO) ? "auto" :
 349                         (cp == PM_PROFILE_LOW) ? "low" :
 350                         (cp == PM_PROFILE_MID) ? "mid" :
 351                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 352 }
 353
 354 static ssize_t radeon_set_pm_profile(struct device *dev,
 355                                      struct device_attribute *attr,
 356                                      const char *buf,
 357                                      size_t count)
 358 {
 359         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 360         struct radeon_device *rdev = ddev->dev_private;
 361
 362         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 363         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 364                 if (strncmp("default", buf, strlen("default")) == 0)
 365                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 366                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 367                         rdev->pm.profile = PM_PROFILE_AUTO;
 368                 else if (strncmp("low", buf, strlen("low")) == 0)
 369                         rdev->pm.profile = PM_PROFILE_LOW;
 370                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 371                         rdev->pm.profile = PM_PROFILE_MID;
 372                 else if (strncmp("high", buf, strlen("high")) == 0)
 373                         rdev->pm.profile = PM_PROFILE_HIGH;
 374                 else {
 375                         count = -EINVAL;
 376                         goto fail;
 377                 }
 378                 radeon_pm_update_profile(rdev);
 379                 radeon_pm_set_clocks(rdev);
 380         } else
 381                 count = -EINVAL;
 382
 383 fail:
 384         lockmgr(&rdev->pm.mutex, LK_RELEASE);
 385
 386         return count;
 387 }
 388
 389 static ssize_t radeon_get_pm_method(struct device *dev,
 390                                     struct device_attribute *attr,
 391                                     char *buf)
 392 {
 393         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 394         struct radeon_device *rdev = ddev->dev_private;
 395         int pm = rdev->pm.pm_method;
 396
 397         return ksnprintf(buf, PAGE_SIZE, "%s\n",
 398                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
 399                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 400 }
 401
 402 static ssize_t radeon_set_pm_method(struct device *dev,
 403                                     struct device_attribute *attr,
 404                                     const char *buf,
 405                                     size_t count)
 406 {
 407         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 408         struct radeon_device *rdev = ddev->dev_private;
 409
 410         /* we don't support the legacy modes with dpm */
 411         if (rdev->pm.pm_method == PM_METHOD_DPM) {
 412                 count = -EINVAL;
 413                 goto fail;
 414         }
 415
 416         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 417                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 418                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 419                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 420                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 421                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
 422         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 423                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 424                 /* disable dynpm */
 425                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 426                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 427                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 428                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
 429 #ifdef DUMBBELL_WIP
 430                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 431 #endif /* DUMBBELL_WIP */
 432         } else {
 433                 count = -EINVAL;
 434                 goto fail;
 435         }
 436         radeon_pm_compute_clocks(rdev);
 437 fail:
 438         return count;
 439 }
 440
 441 static ssize_t radeon_get_dpm_state(struct device *dev,
 442                                     struct device_attribute *attr,
 443                                     char *buf)
 444 {
 445         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 446         struct radeon_device *rdev = ddev->dev_private;
 447         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 448
 449         return snprintf(buf, PAGE_SIZE, "%s\n",
 450                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 451                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 452 }
 453
 454 static ssize_t radeon_set_dpm_state(struct device *dev,
 455                                     struct device_attribute *attr,
 456                                     const char *buf,
 457                                     size_t count)
 458 {
 459         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 460         struct radeon_device *rdev = ddev->dev_private;
 461
 462         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 463         if (strncmp("battery", buf, strlen("battery")) == 0)
 464                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 465         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 466                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 467         else if (strncmp("performance", buf, strlen("performance")) == 0)
 468                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 469         else {
 470                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
 471                 count = -EINVAL;
 472                 goto fail;
 473         }
 474         lockmgr(&rdev->pm.mutex, LK_RELEASE);
 475         radeon_pm_compute_clocks(rdev);
 476 fail:
 477         return count;
 478 }
 479
 480 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
 481                                                        struct device_attribute *attr,
 482                                                        char *buf)
 483 {
 484         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 485         struct radeon_device *rdev = ddev->dev_private;
 486         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 487
 488         return snprintf(buf, PAGE_SIZE, "%s\n",
 489                         (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 490                         (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 491 }
 492
 493 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
 494                                                        struct device_attribute *attr,
 495                                                        const char *buf,
 496                                                        size_t count)
 497 {
 498         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 499         struct radeon_device *rdev = ddev->dev_private;
 500         enum radeon_dpm_forced_level level;
 501         int ret = 0;
 502
 503         spin_lock(&rdev->pm.mutex);
 504         if (strncmp("low", buf, strlen("low")) == 0) {
 505                 level = RADEON_DPM_FORCED_LEVEL_LOW;
 506         } else if (strncmp("high", buf, strlen("high")) == 0) {
 507                 level = RADEON_DPM_FORCED_LEVEL_HIGH;
 508         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 509                 level = RADEON_DPM_FORCED_LEVEL_AUTO;
 510         } else {
 511                 spin_unlock(&rdev->pm.mutex);
 512                 count = -EINVAL;
 513                 goto fail;
 514         }
 515         if (rdev->asic->dpm.force_performance_level) {
 516                 ret = radeon_dpm_force_performance_level(rdev, level);
 517                 if (ret)
 518                         count = -EINVAL;
 519         }
 520         spin_unlock(&rdev->pm.mutex);
 521 fail:
 522         return count;
 523 }
 524
 525 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 526 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 527 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 528 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 529                    radeon_get_dpm_forced_performance_level,
 530                    radeon_set_dpm_forced_performance_level);
 531
 532 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 533                                       struct device_attribute *attr,
 534                                       char *buf)
 535 {
 536         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 537         struct radeon_device *rdev = ddev->dev_private;
 538         int temp;
 539
 540         if (rdev->asic->pm.get_temperature)
 541                 temp = radeon_get_temperature(rdev);
 542         else
 543                 temp = 0;
 544
 545         return ksnprintf(buf, PAGE_SIZE, "%d\n", temp);
 546 }
 547
 548 static ssize_t radeon_hwmon_show_name(struct device *dev,
 549                                       struct device_attribute *attr,
 550                                       char *buf)
 551 {
 552         return sprintf(buf, "radeon\n");
 553 }
 554
 555 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 556 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 557
 558 static struct attribute *hwmon_attributes[] = {
 559         &sensor_dev_attr_temp1_input.dev_attr.attr,
 560         &sensor_dev_attr_name.dev_attr.attr,
 561         NULL
 562 };
 563
 564 static const struct attribute_group hwmon_attrgroup = {
 565         .attrs = hwmon_attributes,
 566 };
 567 #endif /* DUMBBELL_WIP */
 568
 569 static void
 570 radeon_hwmon_refresh(void *arg)
 571 {
 572         struct radeon_device *rdev = (struct radeon_device *)arg;
 573         struct ksensor *s = rdev->pm.int_sensor;
 574         int temp;
 575
 576         if (rdev->asic->pm.get_temperature)
 577                 temp = radeon_get_temperature(rdev);
 578         else
 579                 temp = 0;
 580
 581         s->value = temp * 1000 + 273150000;
 582 }
 583
 584 static int radeon_hwmon_init(struct radeon_device *rdev)
 585 {
 586         int err = 0;
 587
 588         rdev->pm.int_sensor = NULL;
 589         rdev->pm.int_sensordev = NULL;
 590
 591         switch (rdev->pm.int_thermal_type) {
 592         case THERMAL_TYPE_RV6XX:
 593         case THERMAL_TYPE_RV770:
 594         case THERMAL_TYPE_EVERGREEN:
 595         case THERMAL_TYPE_NI:
 596         case THERMAL_TYPE_SUMO:
 597         case THERMAL_TYPE_SI:
 598                 if (rdev->asic->pm.get_temperature == NULL)
 599                         return err;
 600
 601                 rdev->pm.int_sensor = kmalloc(sizeof(*rdev->pm.int_sensor),
 602                     M_DRM, M_ZERO | M_WAITOK);
 603                 rdev->pm.int_sensordev = kmalloc(
 604                     sizeof(*rdev->pm.int_sensordev), M_DRM,
 605                     M_ZERO | M_WAITOK);
 606                 strlcpy(rdev->pm.int_sensordev->xname,
 607                     device_get_nameunit(rdev->dev),
 608                     sizeof(rdev->pm.int_sensordev->xname));
 609                 rdev->pm.int_sensor->type = SENSOR_TEMP;
 610                 sensor_attach(rdev->pm.int_sensordev, rdev->pm.int_sensor);
 611                 sensor_task_register(rdev, radeon_hwmon_refresh, 5);
 612                 sensordev_install(rdev->pm.int_sensordev);
 613                 break;
 614         default:
 615                 break;
 616         }
 617
 618         return err;
 619 }
 620
 621 static void radeon_hwmon_fini(struct radeon_device *rdev)
 622 {
 623         if (rdev->pm.int_sensor != NULL && rdev->pm.int_sensordev != NULL) {
 624                 sensordev_deinstall(rdev->pm.int_sensordev);
 625                 sensor_task_unregister(rdev);
 626                 kfree(rdev->pm.int_sensor);
 627                 kfree(rdev->pm.int_sensordev);
 628                 rdev->pm.int_sensor = NULL;
 629                 rdev->pm.int_sensordev = NULL;
 630         }
 631 }
 632
 633 static void radeon_dpm_thermal_work_handler(void *arg, int pending)
 634 {
 635         struct radeon_device *rdev = arg;
 636         /* switch to the thermal state */
 637         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 638
 639         if (!rdev->pm.dpm_enabled)
 640                 return;
 641
 642         if (rdev->asic->pm.get_temperature) {
 643                 int temp = radeon_get_temperature(rdev);
 644
 645                 if (temp < rdev->pm.dpm.thermal.min_temp)
 646                         /* switch back the user state */
 647                         dpm_state = rdev->pm.dpm.user_state;
 648         } else {
 649                 if (rdev->pm.dpm.thermal.high_to_low)
 650                         /* switch back the user state */
 651                         dpm_state = rdev->pm.dpm.user_state;
 652         }
 653         radeon_dpm_enable_power_state(rdev, dpm_state);
 654 }
 655
 656 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 657                                                      enum radeon_pm_state_type dpm_state)
 658 {
 659         int i;
 660         struct radeon_ps *ps;
 661         u32 ui_class;
 662         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
 663                 true : false;
 664
 665         /* check if the vblank period is too short to adjust the mclk */
 666         if (single_display && rdev->asic->dpm.vblank_too_short) {
 667                 if (radeon_dpm_vblank_too_short(rdev))
 668                         single_display = false;
 669         }
 670
 671         /* certain older asics have a separare 3D performance state,
 672          * so try that first if the user selected performance
 673          */
 674         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 675                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 676         /* balanced states don't exist at the moment */
 677         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 678                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 679
 680 restart_search:
 681         /* Pick the best power state based on current conditions */
 682         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 683                 ps = &rdev->pm.dpm.ps[i];
 684                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 685                 switch (dpm_state) {
 686                 /* user states */
 687                 case POWER_STATE_TYPE_BATTERY:
 688                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 689                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 690                                         if (single_display)
 691                                                 return ps;
 692                                 } else
 693                                         return ps;
 694                         }
 695                         break;
 696                 case POWER_STATE_TYPE_BALANCED:
 697                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 698                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 699                                         if (single_display)
 700                                                 return ps;
 701                                 } else
 702                                         return ps;
 703                         }
 704                         break;
 705                 case POWER_STATE_TYPE_PERFORMANCE:
 706                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 707                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 708                                         if (single_display)
 709                                                 return ps;
 710                                 } else
 711                                         return ps;
 712                         }
 713                         break;
 714                 /* internal states */
 715                 case POWER_STATE_TYPE_INTERNAL_UVD:
 716                         return rdev->pm.dpm.uvd_ps;
 717                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 718                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 719                                 return ps;
 720                         break;
 721                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 722                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 723                                 return ps;
 724                         break;
 725                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 726                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 727                                 return ps;
 728                         break;
 729                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 730                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 731                                 return ps;
 732                         break;
 733                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 734                         return rdev->pm.dpm.boot_ps;
 735                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 736                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 737                                 return ps;
 738                         break;
 739                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 740                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 741                                 return ps;
 742                         break;
 743                 case POWER_STATE_TYPE_INTERNAL_ULV:
 744                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 745                                 return ps;
 746                         break;
 747                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 748                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 749                                 return ps;
 750                         break;
 751                 default:
 752                         break;
 753                 }
 754         }
 755         /* use a fallback state if we didn't match */
 756         switch (dpm_state) {
 757         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 758         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 759         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 760         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 761                 return rdev->pm.dpm.uvd_ps;
 762         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 763                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 764                 goto restart_search;
 765         case POWER_STATE_TYPE_INTERNAL_ACPI:
 766                 dpm_state = POWER_STATE_TYPE_BATTERY;
 767                 goto restart_search;
 768         case POWER_STATE_TYPE_BATTERY:
 769         case POWER_STATE_TYPE_BALANCED:
 770         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 771                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 772                 goto restart_search;
 773         default:
 774                 break;
 775         }
 776
 777         return NULL;
 778 }
 779
 780 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 781 {
 782         int i;
 783         struct radeon_ps *ps;
 784         enum radeon_pm_state_type dpm_state;
 785         int ret;
 786
 787         /* if dpm init failed */
 788         if (!rdev->pm.dpm_enabled)
 789                 return;
 790
 791         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 792                 /* add other state override checks here */
 793                 if ((!rdev->pm.dpm.thermal_active) &&
 794                     (!rdev->pm.dpm.uvd_active))
 795                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 796         }
 797         dpm_state = rdev->pm.dpm.state;
 798
 799         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
 800         if (ps)
 801                 rdev->pm.dpm.requested_ps = ps;
 802         else
 803                 return;
 804
 805         /* no need to reprogram if nothing changed unless we are on BTC+ */
 806         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
 807                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
 808                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
 809                          * all we need to do is update the display configuration.
 810                          */
 811                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
 812                                 /* update display watermarks based on new power state */
 813                                 radeon_bandwidth_update(rdev);
 814                                 /* update displays */
 815                                 radeon_dpm_display_configuration_changed(rdev);
 816                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 817                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 818                         }
 819                         return;
 820                 } else {
 821                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 822                          * nothing to do, if the num crtcs is > 1 and state is the same,
 823                          * update display configuration.
 824                          */
 825                         if (rdev->pm.dpm.new_active_crtcs ==
 826                             rdev->pm.dpm.current_active_crtcs) {
 827                                 return;
 828                         } else {
 829                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
 830                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
 831                                         /* update display watermarks based on new power state */
 832                                         radeon_bandwidth_update(rdev);
 833                                         /* update displays */
 834                                         radeon_dpm_display_configuration_changed(rdev);
 835                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 836                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 837                                         return;
 838                                 }
 839                         }
 840                 }
 841         }
 842
 843         printk("switching from power state:\n");
 844         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
 845         printk("switching to power state:\n");
 846         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
 847
 848         lockmgr(&rdev->ddev->struct_mutex, LK_EXCLUSIVE);
 849         lockmgr(&rdev->pm.mclk_lock, LK_EXCLUSIVE); // down_write
 850         lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
 851
 852         ret = radeon_dpm_pre_set_power_state(rdev);
 853         if (ret)
 854                 goto done;
 855
 856         /* update display watermarks based on new power state */
 857         radeon_bandwidth_update(rdev);
 858         /* update displays */
 859         radeon_dpm_display_configuration_changed(rdev);
 860
 861         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 862         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 863
 864         /* wait for the rings to drain */
 865         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 866                 struct radeon_ring *ring = &rdev->ring[i];
 867                 if (ring->ready)
 868                         radeon_fence_wait_empty_locked(rdev, i);
 869         }
 870
 871         /* program the new power state */
 872         radeon_dpm_set_power_state(rdev);
 873
 874         /* update current power state */
 875         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 876
 877         radeon_dpm_post_set_power_state(rdev);
 878
 879 done:
 880         lockmgr(&rdev->ring_lock, LK_RELEASE);
 881         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); // up_write
 882         lockmgr(&rdev->ddev->struct_mutex, LK_RELEASE);
 883 }
 884
 885 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
 886                                    enum radeon_pm_state_type dpm_state)
 887 {
 888         if (!rdev->pm.dpm_enabled)
 889                 return;
 890
 891         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 892         switch (dpm_state) {
 893         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 894                 rdev->pm.dpm.thermal_active = true;
 895                 break;
 896         case POWER_STATE_TYPE_INTERNAL_UVD:
 897         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 898         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 899         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 900         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 901                 rdev->pm.dpm.uvd_active = true;
 902                 break;
 903         default:
 904                 rdev->pm.dpm.thermal_active = false;
 905                 rdev->pm.dpm.uvd_active = false;
 906                 break;
 907         }
 908         rdev->pm.dpm.state = dpm_state;
 909         lockmgr(&rdev->pm.mutex, LK_RELEASE);
 910         radeon_pm_compute_clocks(rdev);
 911 }
 912
 913 static void radeon_pm_suspend_old(struct radeon_device *rdev)
 914 {
 915         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 916         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 917                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 918                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 919         }
 920         lockmgr(&rdev->pm.mutex, LK_RELEASE);
 921
 922 #ifdef DUMBBELL_WIP
 923         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 924 #endif /* DUMBBELL_WIP */
 925 }
 926
 927 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
 928 {
 929         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 930         /* disable dpm */
 931         radeon_dpm_disable(rdev);
 932         /* reset the power state */
 933         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 934         rdev->pm.dpm_enabled = false;
 935         lockmgr(&rdev->pm.mutex, LK_RELEASE);
 936 }
 937
 938 void radeon_pm_suspend(struct radeon_device *rdev)
 939 {
 940         if (rdev->pm.pm_method == PM_METHOD_DPM)
 941                 radeon_pm_suspend_dpm(rdev);
 942         else
 943                 radeon_pm_suspend_old(rdev);
 944 }
 945
 946 static void radeon_pm_resume_old(struct radeon_device *rdev)
 947 {
 948         /* set up the default clocks if the MC ucode is loaded */
 949         if ((rdev->family >= CHIP_BARTS) &&
 950             (rdev->family <= CHIP_HAINAN) &&
 951             rdev->mc_fw) {
 952                 if (rdev->pm.default_vddc)
 953                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 954                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 955                 if (rdev->pm.default_vddci)
 956                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 957                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 958                 if (rdev->pm.default_sclk)
 959                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 960                 if (rdev->pm.default_mclk)
 961                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 962         }
 963         /* asic init will reset the default power state */
 964         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 965         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 966         rdev->pm.current_clock_mode_index = 0;
 967         rdev->pm.current_sclk = rdev->pm.default_sclk;
 968         rdev->pm.current_mclk = rdev->pm.default_mclk;
 969         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 970         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 971         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 972             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 973                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 974 #ifdef DUMBBELL_WIP
 975                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 976                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 977 #endif /* DUMBBELL_WIP */
 978         }
 979         lockmgr(&rdev->pm.mutex, LK_RELEASE);
 980         radeon_pm_compute_clocks(rdev);
 981 }
 982
 983 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
 984 {
 985         int ret;
 986
 987         /* asic init will reset to the boot state */
 988         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
 989         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 990         radeon_dpm_setup_asic(rdev);
 991         ret = radeon_dpm_enable(rdev);
 992         lockmgr(&rdev->pm.mutex, LK_RELEASE);
 993         if (ret) {
 994                 DRM_ERROR("radeon: dpm resume failed\n");
 995                 if ((rdev->family >= CHIP_BARTS) &&
 996                     (rdev->family <= CHIP_HAINAN) &&
 997                     rdev->mc_fw) {
 998                         if (rdev->pm.default_vddc)
 999                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1000                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1001                         if (rdev->pm.default_vddci)
1002                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1003                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1004                         if (rdev->pm.default_sclk)
1005                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1006                         if (rdev->pm.default_mclk)
1007                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1008                 }
1009         } else {
1010                 rdev->pm.dpm_enabled = true;
1011                 radeon_pm_compute_clocks(rdev);
1012         }
1013 }
1014
1015 void radeon_pm_resume(struct radeon_device *rdev)
1016 {
1017         if (rdev->pm.pm_method == PM_METHOD_DPM)
1018                 radeon_pm_resume_dpm(rdev);
1019         else
1020                 radeon_pm_resume_old(rdev);
1021 }
1022
1023 static int radeon_pm_init_old(struct radeon_device *rdev)
1024 {
1025         int ret;
1026
1027         rdev->pm.profile = PM_PROFILE_DEFAULT;
1028         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1029         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1030         rdev->pm.dynpm_can_upclock = true;
1031         rdev->pm.dynpm_can_downclock = true;
1032         rdev->pm.default_sclk = rdev->clock.default_sclk;
1033         rdev->pm.default_mclk = rdev->clock.default_mclk;
1034         rdev->pm.current_sclk = rdev->clock.default_sclk;
1035         rdev->pm.current_mclk = rdev->clock.default_mclk;
1036         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1037
1038         if (rdev->bios) {
1039                 if (rdev->is_atom_bios)
1040                         radeon_atombios_get_power_modes(rdev);
1041                 else
1042                         radeon_combios_get_power_modes(rdev);
1043                 radeon_pm_print_states(rdev);
1044                 radeon_pm_init_profile(rdev);
1045                 /* set up the default clocks if the MC ucode is loaded */
1046                 if ((rdev->family >= CHIP_BARTS) &&
1047                     (rdev->family <= CHIP_HAINAN) &&
1048                     rdev->mc_fw) {
1049                         if (rdev->pm.default_vddc)
1050                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1051                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1052                         if (rdev->pm.default_vddci)
1053                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1054                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1055                         if (rdev->pm.default_sclk)
1056                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1057                         if (rdev->pm.default_mclk)
1058                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1059                 }
1060         }
1061
1062         /* set up the internal thermal sensor if applicable */
1063         ret = radeon_hwmon_init(rdev);
1064         if (ret)
1065                 return ret;
1066
1067 #ifdef DUMBBELL_WIP
1068         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1069 #endif /* DUMBBELL_WIP */
1070
1071         if (rdev->pm.num_power_states > 1) {
1072                 /* where's the best place to put these? */
1073 #ifdef DUMBBELL_WIP
1074                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1075 #endif /* DUMBBELL_WIP */
1076                 if (ret)
1077                         DRM_ERROR("failed to create device file for power profile\n");
1078 #ifdef DUMBBELL_WIP
1079                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1080 #endif /* DUMBBELL_WIP */
1081                 if (ret)
1082                         DRM_ERROR("failed to create device file for power method\n");
1083
1084                 if (radeon_debugfs_pm_init(rdev)) {
1085                         DRM_ERROR("Failed to register debugfs file for PM!\n");
1086                 }
1087
1088                 DRM_INFO("radeon: power management initialized\n");
1089         }
1090
1091         return 0;
1092 }
1093
1094 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1095 {
1096         int i;
1097
1098         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1099                 printk("== power state %d ==\n", i);
1100                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1101         }
1102 }
1103
1104 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1105 {
1106         int ret;
1107
1108         /* default to performance state */
1109         rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1110         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1111         rdev->pm.default_sclk = rdev->clock.default_sclk;
1112         rdev->pm.default_mclk = rdev->clock.default_mclk;
1113         rdev->pm.current_sclk = rdev->clock.default_sclk;
1114         rdev->pm.current_mclk = rdev->clock.default_mclk;
1115         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1116
1117         if (rdev->bios && rdev->is_atom_bios)
1118                 radeon_atombios_get_power_modes(rdev);
1119         else
1120                 return -EINVAL;
1121
1122         /* set up the internal thermal sensor if applicable */
1123         ret = radeon_hwmon_init(rdev);
1124         if (ret)
1125                 return ret;
1126
1127         TASK_INIT(&rdev->pm.dpm.thermal.work, 0, radeon_dpm_thermal_work_handler, rdev);
1128         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1129         radeon_dpm_init(rdev);
1130         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1131         radeon_dpm_print_power_states(rdev);
1132         radeon_dpm_setup_asic(rdev);
1133         ret = radeon_dpm_enable(rdev);
1134         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1135         if (ret) {
1136                 rdev->pm.dpm_enabled = false;
1137                 if ((rdev->family >= CHIP_BARTS) &&
1138                     (rdev->family <= CHIP_HAINAN) &&
1139                     rdev->mc_fw) {
1140                         if (rdev->pm.default_vddc)
1141                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1142                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1143                         if (rdev->pm.default_vddci)
1144                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1145                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1146                         if (rdev->pm.default_sclk)
1147                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1148                         if (rdev->pm.default_mclk)
1149                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1150                 }
1151                 DRM_ERROR("radeon: dpm initialization failed\n");
1152                 return ret;
1153         }
1154         rdev->pm.dpm_enabled = true;
1155         radeon_pm_compute_clocks(rdev);
1156
1157 #ifdef TODO_DEVICE_FILE
1158         if (rdev->pm.num_power_states > 1) {
1159                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1160                 if (ret)
1161                         DRM_ERROR("failed to create device file for dpm state\n");
1162                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1163                 if (ret)
1164                         DRM_ERROR("failed to create device file for dpm state\n");
1165                 /* XXX: these are noops for dpm but are here for backwards compat */
1166                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1167                 if (ret)
1168                         DRM_ERROR("failed to create device file for power profile\n");
1169                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1170                 if (ret)
1171                         DRM_ERROR("failed to create device file for power method\n");
1172
1173                 if (radeon_debugfs_pm_init(rdev)) {
1174                         DRM_ERROR("Failed to register debugfs file for dpm!\n");
1175                 }
1176
1177                 DRM_INFO("radeon: dpm initialized\n");
1178         }
1179 #endif
1180
1181         return 0;
1182 }
1183
1184 int radeon_pm_init(struct radeon_device *rdev)
1185 {
1186         /* enable dpm on rv6xx+ */
1187         switch (rdev->family) {
1188         case CHIP_RV610:
1189         case CHIP_RV630:
1190         case CHIP_RV620:
1191         case CHIP_RV635:
1192         case CHIP_RV670:
1193         case CHIP_RS780:
1194         case CHIP_RS880:
1195         case CHIP_RV770:
1196         case CHIP_RV730:
1197         case CHIP_RV710:
1198         case CHIP_RV740:
1199         case CHIP_CEDAR:
1200         case CHIP_REDWOOD:
1201         case CHIP_JUNIPER:
1202         case CHIP_CYPRESS:
1203         case CHIP_HEMLOCK:
1204         case CHIP_PALM:
1205         case CHIP_SUMO:
1206         case CHIP_SUMO2:
1207         case CHIP_BARTS:
1208         case CHIP_TURKS:
1209         case CHIP_CAICOS:
1210         case CHIP_CAYMAN:
1211         case CHIP_ARUBA:
1212         case CHIP_TAHITI:
1213         case CHIP_PITCAIRN:
1214         case CHIP_VERDE:
1215         case CHIP_OLAND:
1216         case CHIP_HAINAN:
1217                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1218                 if (!rdev->rlc_fw)
1219                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1220                 else if ((rdev->family >= CHIP_RV770) &&
1221                          (!(rdev->flags & RADEON_IS_IGP)) &&
1222                          (!rdev->smc_fw))
1223                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1224                 else if (radeon_dpm == 1)
1225                         rdev->pm.pm_method = PM_METHOD_DPM;
1226                 else
1227                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1228                 break;
1229         default:
1230                 /* default to profile method */
1231                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1232                 break;
1233         }
1234
1235         if (rdev->pm.pm_method == PM_METHOD_DPM)
1236                 return radeon_pm_init_dpm(rdev);
1237         else
1238                 return radeon_pm_init_old(rdev);
1239 }
1240
1241 static void radeon_pm_fini_old(struct radeon_device *rdev)
1242 {
1243         if (rdev->pm.num_power_states > 1) {
1244                 DRM_UNLOCK(rdev->ddev); /* Work around LOR. */
1245                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1246                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1247                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1248                         radeon_pm_update_profile(rdev);
1249                         radeon_pm_set_clocks(rdev);
1250                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1251                         /* reset default clocks */
1252                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1253                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1254                         radeon_pm_set_clocks(rdev);
1255                 }
1256                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
1257                 DRM_LOCK(rdev->ddev);
1258
1259 #ifdef DUMBBELL_WIP
1260                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1261
1262                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1263                 device_remove_file(rdev->dev, &dev_attr_power_method);
1264 #endif /* DUMBBELL_WIP */
1265         }
1266
1267         if (rdev->pm.power_state) {
1268                 int i;
1269                 for (i = 0; i < rdev->pm.num_power_states; ++i) {
1270                         kfree(rdev->pm.power_state[i].clock_info);
1271                 }
1272                 kfree(rdev->pm.power_state);
1273                 rdev->pm.power_state = NULL;
1274                 rdev->pm.num_power_states = 0;
1275         }
1276
1277         radeon_hwmon_fini(rdev);
1278 }
1279
1280 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1281 {
1282         if (rdev->pm.num_power_states > 1) {
1283                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1284                 radeon_dpm_disable(rdev);
1285                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
1286
1287 #ifdef TODO_DEVICE_FILE
1288                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1289                 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1290                 /* XXX backwards compat */
1291                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1292                 device_remove_file(rdev->dev, &dev_attr_power_method);
1293 #endif
1294         }
1295         radeon_dpm_fini(rdev);
1296
1297         if (rdev->pm.power_state)
1298                 kfree(rdev->pm.power_state);
1299
1300         radeon_hwmon_fini(rdev);
1301 }
1302
1303 void radeon_pm_fini(struct radeon_device *rdev)
1304 {
1305         if (rdev->pm.pm_method == PM_METHOD_DPM)
1306                 radeon_pm_fini_dpm(rdev);
1307         else
1308                 radeon_pm_fini_old(rdev);
1309 }
1310
1311 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1312 {
1313         struct drm_device *ddev = rdev->ddev;
1314         struct drm_crtc *crtc;
1315         struct radeon_crtc *radeon_crtc;
1316
1317         if (rdev->pm.num_power_states < 2)
1318                 return;
1319
1320         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1321
1322         rdev->pm.active_crtcs = 0;
1323         rdev->pm.active_crtc_count = 0;
1324         list_for_each_entry(crtc,
1325                 &ddev->mode_config.crtc_list, head) {
1326                 radeon_crtc = to_radeon_crtc(crtc);
1327                 if (radeon_crtc->enabled) {
1328                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1329                         rdev->pm.active_crtc_count++;
1330                 }
1331         }
1332
1333         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1334                 radeon_pm_update_profile(rdev);
1335                 radeon_pm_set_clocks(rdev);
1336         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1337                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1338                         if (rdev->pm.active_crtc_count > 1) {
1339                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1340 #ifdef DUMBBELL_WIP
1341                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1342 #endif /* DUMBBELL_WIP */
1343
1344                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1345                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1346                                         radeon_pm_get_dynpm_state(rdev);
1347                                         radeon_pm_set_clocks(rdev);
1348
1349                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1350                                 }
1351                         } else if (rdev->pm.active_crtc_count == 1) {
1352                                 /* TODO: Increase clocks if needed for current mode */
1353
1354                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1355                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1356                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1357                                         radeon_pm_get_dynpm_state(rdev);
1358                                         radeon_pm_set_clocks(rdev);
1359
1360 #ifdef DUMBBELL_WIP
1361                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1362                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1363 #endif /* DUMBBELL_WIP */
1364                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1365                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1366 #ifdef DUMBBELL_WIP
1367                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1368                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1369 #endif /* DUMBBELL_WIP */
1370                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1371                                 }
1372                         } else { /* count == 0 */
1373                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1374 #ifdef DUMBBELL_WIP
1375                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1376 #endif /* DUMBBELL_WIP */
1377
1378                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1379                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1380                                         radeon_pm_get_dynpm_state(rdev);
1381                                         radeon_pm_set_clocks(rdev);
1382                                 }
1383                         }
1384                 }
1385         }
1386
1387         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1388 }
1389
1390 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1391 {
1392         struct drm_device *ddev = rdev->ddev;
1393         struct drm_crtc *crtc;
1394         struct radeon_crtc *radeon_crtc;
1395
1396         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1397
1398         /* update active crtc counts */
1399         rdev->pm.dpm.new_active_crtcs = 0;
1400         rdev->pm.dpm.new_active_crtc_count = 0;
1401         list_for_each_entry(crtc,
1402                 &ddev->mode_config.crtc_list, head) {
1403                 radeon_crtc = to_radeon_crtc(crtc);
1404                 if (crtc->enabled) {
1405                         rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1406                         rdev->pm.dpm.new_active_crtc_count++;
1407                 }
1408         }
1409
1410         /* update battery/ac status */
1411         if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE)
1412                 rdev->pm.dpm.ac_power = true;
1413         else
1414                 rdev->pm.dpm.ac_power = false;
1415
1416         radeon_dpm_change_power_state_locked(rdev);
1417
1418         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1419 }
1420
1421 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1422 {
1423         if (rdev->pm.pm_method == PM_METHOD_DPM)
1424                 radeon_pm_compute_clocks_dpm(rdev);
1425         else
1426                 radeon_pm_compute_clocks_old(rdev);
1427 }
1428
1429 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1430 {
1431         int  crtc, vpos, hpos, vbl_status;
1432         bool in_vbl = true;
1433
1434         /* Iterate over all active crtc's. All crtc's must be in vblank,
1435          * otherwise return in_vbl == false.
1436          */
1437         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1438                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1439                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1440                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1441                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
1442                                 in_vbl = false;
1443                 }
1444         }
1445
1446         return in_vbl;
1447 }
1448
1449 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1450 {
1451         u32 stat_crtc = 0;
1452         bool in_vbl = radeon_pm_in_vbl(rdev);
1453
1454         if (in_vbl == false)
1455                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1456                          finish ? "exit" : "entry");
1457         return in_vbl;
1458 }
1459
1460 #ifdef DUMBBELL_WIP
1461 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1462 {
1463         struct radeon_device *rdev;
1464         int resched;
1465         rdev = container_of(work, struct radeon_device,
1466                                 pm.dynpm_idle_work.work);
1467
1468         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1469         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1470         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1471                 int not_processed = 0;
1472                 int i;
1473
1474                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1475                         struct radeon_ring *ring = &rdev->ring[i];
1476
1477                         if (ring->ready) {
1478                                 not_processed += radeon_fence_count_emitted(rdev, i);
1479                                 if (not_processed >= 3)
1480                                         break;
1481                         }
1482                 }
1483
1484                 if (not_processed >= 3) { /* should upclock */
1485                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1486                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1487                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1488                                    rdev->pm.dynpm_can_upclock) {
1489                                 rdev->pm.dynpm_planned_action =
1490                                         DYNPM_ACTION_UPCLOCK;
1491                                 rdev->pm.dynpm_action_timeout = jiffies +
1492                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1493                         }
1494                 } else if (not_processed == 0) { /* should downclock */
1495                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1496                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1497                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1498                                    rdev->pm.dynpm_can_downclock) {
1499                                 rdev->pm.dynpm_planned_action =
1500                                         DYNPM_ACTION_DOWNCLOCK;
1501                                 rdev->pm.dynpm_action_timeout = jiffies +
1502                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1503                         }
1504                 }
1505
1506                 /* Note, radeon_pm_set_clocks is called with static_switch set
1507                  * to false since we want to wait for vbl to avoid flicker.
1508                  */
1509                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1510                     jiffies > rdev->pm.dynpm_action_timeout) {
1511                         radeon_pm_get_dynpm_state(rdev);
1512                         radeon_pm_set_clocks(rdev);
1513                 }
1514
1515                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1516                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1517         }
1518         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1519         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1520 }
1521 #endif /* DUMBBELL_WIP */
1522
1523 /*
1524  * Debugfs info
1525  */
1526 #if defined(CONFIG_DEBUG_FS)
1527
1528 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1529 {
1530         struct drm_info_node *node = (struct drm_info_node *) m->private;
1531         struct drm_device *dev = node->minor->dev;
1532         struct radeon_device *rdev = dev->dev_private;
1533
1534         if (rdev->pm.dpm_enabled) {
1535                 spin_lock(&rdev->pm.mutex);
1536                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1537                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1538                 else
1539                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1540                 spin_unlock(&rdev->pm.mutex);
1541         } else {
1542                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1543                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1544                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1545                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1546                 else
1547                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1548                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1549                 if (rdev->asic->pm.get_memory_clock)
1550                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1551                 if (rdev->pm.current_vddc)
1552                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1553                 if (rdev->asic->pm.get_pcie_lanes)
1554                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1555         }
1556
1557         return 0;
1558 }
1559
1560 static struct drm_info_list radeon_pm_info_list[] = {
1561         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1562 };
1563 #endif
1564
1565 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1566 {
1567 #if defined(CONFIG_DEBUG_FS)
1568         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1569 #else
1570         return 0;
1571 #endif
1572 }