2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $");
30 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
52 #include <sys/device.h>
54 #include <sys/pciio.h>
55 #include <bus/pci/pcireg.h>
56 #include <bus/pci/pcivar.h>
57 #include <bus/pci/pci_private.h>
63 #include <contrib/dev/acpica/acpi.h>
66 #define ACPI_PWR_FOR_SLEEP(x, y, z)
69 static uint32_t pci_mapbase(unsigned mapreg);
70 static const char *pci_maptype(unsigned mapreg);
71 static int pci_mapsize(unsigned testval);
72 static int pci_maprange(unsigned mapreg);
73 static void pci_fixancient(pcicfgregs *cfg);
75 static int pci_porten(device_t pcib, int b, int s, int f);
76 static int pci_memen(device_t pcib, int b, int s, int f);
77 static void pci_assign_interrupt(device_t bus, device_t dev,
79 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
80 int b, int s, int f, int reg,
81 struct resource_list *rl, int force, int prefetch);
82 static int pci_probe(device_t dev);
83 static int pci_attach(device_t dev);
84 static void pci_load_vendor_data(void);
85 static int pci_describe_parse_line(char **ptr, int *vendor,
86 int *device, char **desc);
87 static char *pci_describe_device(device_t dev);
88 static int pci_modevent(module_t mod, int what, void *arg);
89 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
91 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
92 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
93 int reg, uint32_t *data);
95 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
96 int reg, uint32_t data);
98 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
99 static void pci_disable_msi(device_t dev);
100 static void pci_enable_msi(device_t dev, uint64_t address,
102 static void pci_enable_msix(device_t dev, u_int index,
103 uint64_t address, uint32_t data);
104 static void pci_mask_msix(device_t dev, u_int index);
105 static void pci_unmask_msix(device_t dev, u_int index);
106 static int pci_msi_blacklisted(void);
107 static void pci_resume_msi(device_t dev);
108 static void pci_resume_msix(device_t dev);
110 static device_method_t pci_methods[] = {
111 /* Device interface */
112 DEVMETHOD(device_probe, pci_probe),
113 DEVMETHOD(device_attach, pci_attach),
114 DEVMETHOD(device_detach, bus_generic_detach),
115 DEVMETHOD(device_shutdown, bus_generic_shutdown),
116 DEVMETHOD(device_suspend, pci_suspend),
117 DEVMETHOD(device_resume, pci_resume),
120 DEVMETHOD(bus_print_child, pci_print_child),
121 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
122 DEVMETHOD(bus_read_ivar, pci_read_ivar),
123 DEVMETHOD(bus_write_ivar, pci_write_ivar),
124 DEVMETHOD(bus_driver_added, pci_driver_added),
125 DEVMETHOD(bus_setup_intr, pci_setup_intr),
126 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
128 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
129 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
130 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
131 DEVMETHOD(bus_delete_resource, pci_delete_resource),
132 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
133 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
134 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
135 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
136 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
137 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
140 DEVMETHOD(pci_read_config, pci_read_config_method),
141 DEVMETHOD(pci_write_config, pci_write_config_method),
142 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
143 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
144 DEVMETHOD(pci_enable_io, pci_enable_io_method),
145 DEVMETHOD(pci_disable_io, pci_disable_io_method),
146 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
147 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
148 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
149 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
150 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
151 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
152 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
153 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
154 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
155 DEVMETHOD(pci_release_msi, pci_release_msi_method),
156 DEVMETHOD(pci_msi_count, pci_msi_count_method),
157 DEVMETHOD(pci_msix_count, pci_msix_count_method),
162 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
164 static devclass_t pci_devclass;
165 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
166 MODULE_VERSION(pci, 1);
168 static char *pci_vendordata;
169 static size_t pci_vendordata_size;
173 uint32_t devid; /* Vendor/device of the card */
175 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
176 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
181 struct pci_quirk pci_quirks[] = {
182 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
183 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
184 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
185 /* As does the Serverworks OSB4 (the SMBus mapping register) */
186 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
189 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
190 * or the CMIC-SL (AKA ServerWorks GC_LE).
192 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
193 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
196 * MSI doesn't work on earlier Intel chipsets including
197 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
199 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
200 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
201 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
202 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
203 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
204 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
205 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
211 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
216 /* map register information */
217 #define PCI_MAPMEM 0x01 /* memory map */
218 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
219 #define PCI_MAPPORT 0x04 /* port map */
221 struct devlist pci_devq;
222 uint32_t pci_generation;
223 uint32_t pci_numdevs = 0;
224 static int pcie_chipset, pcix_chipset;
227 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
229 static int pci_enable_io_modes = 1;
230 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
231 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
232 &pci_enable_io_modes, 1,
233 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
234 enable these bits correctly. We'd like to do this all the time, but there\n\
235 are some peripherals that this causes problems with.");
237 static int pci_do_power_nodriver = 0;
238 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
239 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
240 &pci_do_power_nodriver, 0,
241 "Place a function into D3 state when no driver attaches to it. 0 means\n\
242 disable. 1 means conservatively place devices into D3 state. 2 means\n\
243 agressively place devices into D3 state. 3 means put absolutely everything\n\
246 static int pci_do_power_resume = 1;
247 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
248 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
249 &pci_do_power_resume, 1,
250 "Transition from D3 -> D0 on resume.");
252 static int pci_do_msi = 1;
253 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
254 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
255 "Enable support for MSI interrupts");
257 static int pci_do_msix = 1;
258 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
259 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
260 "Enable support for MSI-X interrupts");
262 static int pci_honor_msi_blacklist = 1;
263 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
264 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
265 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
267 /* Find a device_t by bus/slot/function in domain 0 */
270 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
273 return (pci_find_dbsf(0, bus, slot, func));
276 /* Find a device_t by domain/bus/slot/function */
279 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
281 struct pci_devinfo *dinfo;
283 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
284 if ((dinfo->cfg.domain == domain) &&
285 (dinfo->cfg.bus == bus) &&
286 (dinfo->cfg.slot == slot) &&
287 (dinfo->cfg.func == func)) {
288 return (dinfo->cfg.dev);
295 /* Find a device_t by vendor/device ID */
298 pci_find_device(uint16_t vendor, uint16_t device)
300 struct pci_devinfo *dinfo;
302 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
303 if ((dinfo->cfg.vendor == vendor) &&
304 (dinfo->cfg.device == device)) {
305 return (dinfo->cfg.dev);
312 /* return base address of memory or port map */
315 pci_mapbase(uint32_t mapreg)
318 if (PCI_BAR_MEM(mapreg))
319 return (mapreg & PCIM_BAR_MEM_BASE);
321 return (mapreg & PCIM_BAR_IO_BASE);
324 /* return map type of memory or port map */
327 pci_maptype(unsigned mapreg)
330 if (PCI_BAR_IO(mapreg))
332 if (mapreg & PCIM_BAR_MEM_PREFETCH)
333 return ("Prefetchable Memory");
337 /* return log2 of map size decoded for memory or port map */
340 pci_mapsize(uint32_t testval)
344 testval = pci_mapbase(testval);
347 while ((testval & 1) == 0)
356 /* return log2 of address range supported by map register */
359 pci_maprange(unsigned mapreg)
363 if (PCI_BAR_IO(mapreg))
366 switch (mapreg & PCIM_BAR_MEM_TYPE) {
367 case PCIM_BAR_MEM_32:
370 case PCIM_BAR_MEM_1MB:
373 case PCIM_BAR_MEM_64:
380 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
383 pci_fixancient(pcicfgregs *cfg)
385 if (cfg->hdrtype != 0)
388 /* PCI to PCI bridges use header type 1 */
389 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
393 /* extract header type specific config data */
396 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
398 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
399 switch (cfg->hdrtype) {
401 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
402 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
403 cfg->nummaps = PCI_MAXMAPS_0;
406 cfg->nummaps = PCI_MAXMAPS_1;
409 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
410 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
411 cfg->nummaps = PCI_MAXMAPS_2;
417 /* read configuration header into pcicfgregs structure */
419 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
421 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
422 pcicfgregs *cfg = NULL;
423 struct pci_devinfo *devlist_entry;
424 struct devlist *devlist_head;
426 devlist_head = &pci_devq;
428 devlist_entry = NULL;
430 if (REG(PCIR_DEVVENDOR, 4) != -1) {
431 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
432 if (devlist_entry == NULL)
435 cfg = &devlist_entry->cfg;
441 cfg->vendor = REG(PCIR_VENDOR, 2);
442 cfg->device = REG(PCIR_DEVICE, 2);
443 cfg->cmdreg = REG(PCIR_COMMAND, 2);
444 cfg->statreg = REG(PCIR_STATUS, 2);
445 cfg->baseclass = REG(PCIR_CLASS, 1);
446 cfg->subclass = REG(PCIR_SUBCLASS, 1);
447 cfg->progif = REG(PCIR_PROGIF, 1);
448 cfg->revid = REG(PCIR_REVID, 1);
449 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
450 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
451 cfg->lattimer = REG(PCIR_LATTIMER, 1);
452 cfg->intpin = REG(PCIR_INTPIN, 1);
453 cfg->intline = REG(PCIR_INTLINE, 1);
455 cfg->mingnt = REG(PCIR_MINGNT, 1);
456 cfg->maxlat = REG(PCIR_MAXLAT, 1);
458 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
459 cfg->hdrtype &= ~PCIM_MFDEV;
462 pci_hdrtypedata(pcib, b, s, f, cfg);
464 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
465 pci_read_extcap(pcib, cfg);
467 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
469 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
470 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
471 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
472 devlist_entry->conf.pc_sel.pc_func = cfg->func;
473 devlist_entry->conf.pc_hdr = cfg->hdrtype;
475 devlist_entry->conf.pc_subvendor = cfg->subvendor;
476 devlist_entry->conf.pc_subdevice = cfg->subdevice;
477 devlist_entry->conf.pc_vendor = cfg->vendor;
478 devlist_entry->conf.pc_device = cfg->device;
480 devlist_entry->conf.pc_class = cfg->baseclass;
481 devlist_entry->conf.pc_subclass = cfg->subclass;
482 devlist_entry->conf.pc_progif = cfg->progif;
483 devlist_entry->conf.pc_revid = cfg->revid;
488 return (devlist_entry);
493 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
495 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
496 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
497 #if defined(__i386__) || defined(__amd64__)
501 int ptr, nextptr, ptrptr;
503 switch (cfg->hdrtype & PCIM_HDRTYPE) {
506 ptrptr = PCIR_CAP_PTR;
509 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
512 return; /* no extended capabilities support */
514 nextptr = REG(ptrptr, 1); /* sanity check? */
517 * Read capability entries.
519 while (nextptr != 0) {
522 kprintf("illegal PCI extended capability offset %d\n",
526 /* Find the next entry */
528 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
530 /* Process this entry */
531 switch (REG(ptr + PCICAP_ID, 1)) {
532 case PCIY_PMG: /* PCI power management */
533 if (cfg->pp.pp_cap == 0) {
534 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
535 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
536 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
537 if ((nextptr - ptr) > PCIR_POWER_DATA)
538 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
542 #if defined(__i386__) || defined(__amd64__)
543 case PCIY_HT: /* HyperTransport */
544 /* Determine HT-specific capability type. */
545 val = REG(ptr + PCIR_HT_COMMAND, 2);
546 switch (val & PCIM_HTCMD_CAP_MASK) {
547 case PCIM_HTCAP_MSI_MAPPING:
548 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
549 /* Sanity check the mapping window. */
550 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
553 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
555 if (addr != MSI_INTEL_ADDR_BASE)
557 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
558 cfg->domain, cfg->bus,
559 cfg->slot, cfg->func,
562 addr = MSI_INTEL_ADDR_BASE;
564 cfg->ht.ht_msimap = ptr;
565 cfg->ht.ht_msictrl = val;
566 cfg->ht.ht_msiaddr = addr;
571 case PCIY_MSI: /* PCI MSI */
572 cfg->msi.msi_location = ptr;
573 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
574 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
575 PCIM_MSICTRL_MMC_MASK)>>1);
577 case PCIY_MSIX: /* PCI MSI-X */
578 cfg->msix.msix_location = ptr;
579 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
580 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
581 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
582 val = REG(ptr + PCIR_MSIX_TABLE, 4);
583 cfg->msix.msix_table_bar = PCIR_BAR(val &
585 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
586 val = REG(ptr + PCIR_MSIX_PBA, 4);
587 cfg->msix.msix_pba_bar = PCIR_BAR(val &
589 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
592 case PCIY_VPD: /* PCI Vital Product Data */
593 cfg->vpd.vpd_reg = ptr;
596 /* Should always be true. */
597 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
598 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
599 cfg->subvendor = val & 0xffff;
600 cfg->subdevice = val >> 16;
603 case PCIY_PCIX: /* PCI-X */
605 * Assume we have a PCI-X chipset if we have
606 * at least one PCI-PCI bridge with a PCI-X
607 * capability. Note that some systems with
608 * PCI-express or HT chipsets might match on
609 * this check as well.
611 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
614 case PCIY_EXPRESS: /* PCI-express */
616 * Assume we have a PCI-express chipset if we have
617 * at least one PCI-express device.
625 /* REG and WREG use carry through to next functions */
629 * PCI Vital Product Data
632 #define PCI_VPD_TIMEOUT 1000000
635 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
637 int count = PCI_VPD_TIMEOUT;
639 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
641 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
643 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
646 DELAY(1); /* limit looping */
648 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
655 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
657 int count = PCI_VPD_TIMEOUT;
659 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
661 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
662 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
663 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
666 DELAY(1); /* limit looping */
673 #undef PCI_VPD_TIMEOUT
675 struct vpd_readstate {
685 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
690 if (vrs->bytesinval == 0) {
691 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
693 vrs->val = le32toh(reg);
695 byte = vrs->val & 0xff;
698 vrs->val = vrs->val >> 8;
699 byte = vrs->val & 0xff;
709 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
713 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
714 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
715 panic("%s: invalid max read request size 0x%02x\n",
716 device_get_nameunit(dev), rqsize);
718 #warning "this code is incorrect, I think"
719 pci_find_extcap_method(device_get_parent(dev), dev, PCIY_EXPRESS, &expr_ptr);
721 panic("%s: not PCI Express\n", device_get_nameunit(dev));
722 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
723 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
725 device_printf(dev, "adjust device control 0x%04x", val);
726 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
728 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
731 kprintf(" -> 0x%04x\n", val);
736 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
738 struct vpd_readstate vrs;
743 int alloc, off; /* alloc/off for RO/W arrays */
749 /* init vpd reader */
757 name = remain = i = 0; /* shut up stupid gcc */
758 alloc = off = 0; /* shut up stupid gcc */
759 dflen = 0; /* shut up stupid gcc */
762 if (vpd_nextbyte(&vrs, &byte)) {
767 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
768 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
769 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
772 case 0: /* item name */
774 if (vpd_nextbyte(&vrs, &byte2)) {
779 if (vpd_nextbyte(&vrs, &byte2)) {
783 remain |= byte2 << 8;
784 if (remain > (0x7f*4 - vrs.off)) {
787 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
788 cfg->domain, cfg->bus, cfg->slot,
794 name = (byte >> 3) & 0xf;
797 case 0x2: /* String */
798 cfg->vpd.vpd_ident = kmalloc(remain + 1,
806 case 0x10: /* VPD-R */
809 cfg->vpd.vpd_ros = kmalloc(alloc *
810 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
814 case 0x11: /* VPD-W */
817 cfg->vpd.vpd_w = kmalloc(alloc *
818 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
822 default: /* Invalid data, abort */
828 case 1: /* Identifier String */
829 cfg->vpd.vpd_ident[i++] = byte;
832 cfg->vpd.vpd_ident[i] = '\0';
837 case 2: /* VPD-R Keyword Header */
839 cfg->vpd.vpd_ros = kreallocf(cfg->vpd.vpd_ros,
840 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
841 M_DEVBUF, M_WAITOK | M_ZERO);
843 cfg->vpd.vpd_ros[off].keyword[0] = byte;
844 if (vpd_nextbyte(&vrs, &byte2)) {
848 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
849 if (vpd_nextbyte(&vrs, &byte2)) {
855 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
858 * if this happens, we can't trust the rest
862 "pci%d:%d:%d:%d: bad keyword length: %d\n",
863 cfg->domain, cfg->bus, cfg->slot,
868 } else if (dflen == 0) {
869 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
870 sizeof(*cfg->vpd.vpd_ros[off].value),
872 cfg->vpd.vpd_ros[off].value[0] = '\x00';
874 cfg->vpd.vpd_ros[off].value = kmalloc(
876 sizeof(*cfg->vpd.vpd_ros[off].value),
880 /* keep in sync w/ state 3's transistions */
881 if (dflen == 0 && remain == 0)
889 case 3: /* VPD-R Keyword Value */
890 cfg->vpd.vpd_ros[off].value[i++] = byte;
891 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
892 "RV", 2) == 0 && cksumvalid == -1) {
898 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
899 cfg->domain, cfg->bus,
900 cfg->slot, cfg->func,
909 /* keep in sync w/ state 2's transistions */
911 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
912 if (dflen == 0 && remain == 0) {
913 cfg->vpd.vpd_rocnt = off;
914 cfg->vpd.vpd_ros = kreallocf(cfg->vpd.vpd_ros,
915 off * sizeof(*cfg->vpd.vpd_ros),
916 M_DEVBUF, M_WAITOK | M_ZERO);
918 } else if (dflen == 0)
928 case 5: /* VPD-W Keyword Header */
930 cfg->vpd.vpd_w = kreallocf(cfg->vpd.vpd_w,
931 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
932 M_DEVBUF, M_WAITOK | M_ZERO);
934 cfg->vpd.vpd_w[off].keyword[0] = byte;
935 if (vpd_nextbyte(&vrs, &byte2)) {
939 cfg->vpd.vpd_w[off].keyword[1] = byte2;
940 if (vpd_nextbyte(&vrs, &byte2)) {
944 cfg->vpd.vpd_w[off].len = dflen = byte2;
945 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
946 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
947 sizeof(*cfg->vpd.vpd_w[off].value),
951 /* keep in sync w/ state 6's transistions */
952 if (dflen == 0 && remain == 0)
960 case 6: /* VPD-W Keyword Value */
961 cfg->vpd.vpd_w[off].value[i++] = byte;
964 /* keep in sync w/ state 5's transistions */
966 cfg->vpd.vpd_w[off++].value[i++] = '\0';
967 if (dflen == 0 && remain == 0) {
968 cfg->vpd.vpd_wcnt = off;
969 cfg->vpd.vpd_w = kreallocf(cfg->vpd.vpd_w,
970 off * sizeof(*cfg->vpd.vpd_w),
971 M_DEVBUF, M_WAITOK | M_ZERO);
973 } else if (dflen == 0)
978 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
979 cfg->domain, cfg->bus, cfg->slot, cfg->func,
986 if (cksumvalid == 0 || state < -1) {
987 /* read-only data bad, clean up */
988 if (cfg->vpd.vpd_ros != NULL) {
989 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
990 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
991 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
992 cfg->vpd.vpd_ros = NULL;
996 /* I/O error, clean up */
997 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
998 cfg->domain, cfg->bus, cfg->slot, cfg->func);
999 if (cfg->vpd.vpd_ident != NULL) {
1000 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1001 cfg->vpd.vpd_ident = NULL;
1003 if (cfg->vpd.vpd_w != NULL) {
1004 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1005 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1006 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1007 cfg->vpd.vpd_w = NULL;
1010 cfg->vpd.vpd_cached = 1;
1016 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1018 struct pci_devinfo *dinfo = device_get_ivars(child);
1019 pcicfgregs *cfg = &dinfo->cfg;
1021 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1022 pci_read_vpd(device_get_parent(dev), cfg);
1024 *identptr = cfg->vpd.vpd_ident;
1026 if (*identptr == NULL)
1033 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1036 struct pci_devinfo *dinfo = device_get_ivars(child);
1037 pcicfgregs *cfg = &dinfo->cfg;
1040 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1041 pci_read_vpd(device_get_parent(dev), cfg);
1043 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1044 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1045 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1046 *vptr = cfg->vpd.vpd_ros[i].value;
1049 if (i != cfg->vpd.vpd_rocnt)
1057 * Return the offset in configuration space of the requested extended
1058 * capability entry or 0 if the specified capability was not found.
1061 pci_find_extcap_method(device_t dev, device_t child, int capability,
1064 struct pci_devinfo *dinfo = device_get_ivars(child);
1065 pcicfgregs *cfg = &dinfo->cfg;
1070 * Check the CAP_LIST bit of the PCI status register first.
1072 status = pci_read_config(child, PCIR_STATUS, 2);
1073 if (!(status & PCIM_STATUS_CAPPRESENT))
1077 * Determine the start pointer of the capabilities list.
1079 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1085 ptr = PCIR_CAP_PTR_2;
1089 return (ENXIO); /* no extended capabilities support */
1091 ptr = pci_read_config(child, ptr, 1);
1094 * Traverse the capabilities list.
1097 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1102 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1109 * Support for MSI-X message interrupts.
1112 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1114 struct pci_devinfo *dinfo = device_get_ivars(dev);
1115 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1118 KASSERT(msix->msix_table_len > index, ("bogus index"));
1119 offset = msix->msix_table_offset + index * 16;
1120 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1121 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1122 bus_write_4(msix->msix_table_res, offset + 8, data);
1124 /* Enable MSI -> HT mapping. */
1125 pci_ht_map_msi(dev, address);
1129 pci_mask_msix(device_t dev, u_int index)
1131 struct pci_devinfo *dinfo = device_get_ivars(dev);
1132 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1133 uint32_t offset, val;
1135 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1136 offset = msix->msix_table_offset + index * 16 + 12;
1137 val = bus_read_4(msix->msix_table_res, offset);
1138 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1139 val |= PCIM_MSIX_VCTRL_MASK;
1140 bus_write_4(msix->msix_table_res, offset, val);
1145 pci_unmask_msix(device_t dev, u_int index)
1147 struct pci_devinfo *dinfo = device_get_ivars(dev);
1148 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1149 uint32_t offset, val;
1151 KASSERT(msix->msix_table_len > index, ("bogus index"));
1152 offset = msix->msix_table_offset + index * 16 + 12;
1153 val = bus_read_4(msix->msix_table_res, offset);
1154 if (val & PCIM_MSIX_VCTRL_MASK) {
1155 val &= ~PCIM_MSIX_VCTRL_MASK;
1156 bus_write_4(msix->msix_table_res, offset, val);
1161 pci_pending_msix(device_t dev, u_int index)
1163 struct pci_devinfo *dinfo = device_get_ivars(dev);
1164 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1165 uint32_t offset, bit;
1167 KASSERT(msix->msix_table_len > index, ("bogus index"));
1168 offset = msix->msix_pba_offset + (index / 32) * 4;
1169 bit = 1 << index % 32;
1170 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1174 * Restore MSI-X registers and table during resume. If MSI-X is
1175 * enabled then walk the virtual table to restore the actual MSI-X
1179 pci_resume_msix(device_t dev)
1181 struct pci_devinfo *dinfo = device_get_ivars(dev);
1182 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1183 struct msix_table_entry *mte;
1184 struct msix_vector *mv;
1187 if (msix->msix_alloc > 0) {
1188 /* First, mask all vectors. */
1189 for (i = 0; i < msix->msix_msgnum; i++)
1190 pci_mask_msix(dev, i);
1192 /* Second, program any messages with at least one handler. */
1193 for (i = 0; i < msix->msix_table_len; i++) {
1194 mte = &msix->msix_table[i];
1195 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1197 mv = &msix->msix_vectors[mte->mte_vector - 1];
1198 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1199 pci_unmask_msix(dev, i);
1202 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1203 msix->msix_ctrl, 2);
1207 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1208 * returned in *count. After this function returns, each message will be
1209 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1212 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1214 struct pci_devinfo *dinfo = device_get_ivars(child);
1215 pcicfgregs *cfg = &dinfo->cfg;
1216 struct resource_list_entry *rle;
1217 int actual, error, i, irq, max;
1219 /* Don't let count == 0 get us into trouble. */
1223 /* If rid 0 is allocated, then fail. */
1224 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1225 if (rle != NULL && rle->res != NULL)
1228 /* Already have allocated messages? */
1229 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1232 /* If MSI is blacklisted for this system, fail. */
1233 if (pci_msi_blacklisted())
1236 /* MSI-X capability present? */
1237 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1240 /* Make sure the appropriate BARs are mapped. */
1241 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1242 cfg->msix.msix_table_bar);
1243 if (rle == NULL || rle->res == NULL ||
1244 !(rman_get_flags(rle->res) & RF_ACTIVE))
1246 cfg->msix.msix_table_res = rle->res;
1247 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1248 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1249 cfg->msix.msix_pba_bar);
1250 if (rle == NULL || rle->res == NULL ||
1251 !(rman_get_flags(rle->res) & RF_ACTIVE))
1254 cfg->msix.msix_pba_res = rle->res;
1257 device_printf(child,
1258 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1259 *count, cfg->msix.msix_msgnum);
1260 max = min(*count, cfg->msix.msix_msgnum);
1261 for (i = 0; i < max; i++) {
1262 /* Allocate a message. */
1263 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1266 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1272 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1274 device_printf(child, "using IRQ %lu for MSI-X\n",
1280 * Be fancy and try to print contiguous runs of
1281 * IRQ values as ranges. 'irq' is the previous IRQ.
1282 * 'run' is true if we are in a range.
1284 device_printf(child, "using IRQs %lu", rle->start);
1287 for (i = 1; i < actual; i++) {
1288 rle = resource_list_find(&dinfo->resources,
1289 SYS_RES_IRQ, i + 1);
1291 /* Still in a run? */
1292 if (rle->start == irq + 1) {
1298 /* Finish previous range. */
1300 kprintf("-%d", irq);
1304 /* Start new range. */
1305 kprintf(",%lu", rle->start);
1309 /* Unfinished range? */
1311 kprintf("-%d", irq);
1312 kprintf(" for MSI-X\n");
1316 /* Mask all vectors. */
1317 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1318 pci_mask_msix(child, i);
1320 /* Allocate and initialize vector data and virtual table. */
1321 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1322 M_DEVBUF, M_WAITOK | M_ZERO);
1323 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1324 M_DEVBUF, M_WAITOK | M_ZERO);
1325 for (i = 0; i < actual; i++) {
1326 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1327 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1328 cfg->msix.msix_table[i].mte_vector = i + 1;
1331 /* Update control register to enable MSI-X. */
1332 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1333 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1334 cfg->msix.msix_ctrl, 2);
1336 /* Update counts of alloc'd messages. */
1337 cfg->msix.msix_alloc = actual;
1338 cfg->msix.msix_table_len = actual;
1344 * By default, pci_alloc_msix() will assign the allocated IRQ
1345 * resources consecutively to the first N messages in the MSI-X table.
1346 * However, device drivers may want to use different layouts if they
1347 * either receive fewer messages than they asked for, or they wish to
1348 * populate the MSI-X table sparsely. This method allows the driver
1349 * to specify what layout it wants. It must be called after a
1350 * successful pci_alloc_msix() but before any of the associated
1351 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1353 * The 'vectors' array contains 'count' message vectors. The array
1354 * maps directly to the MSI-X table in that index 0 in the array
1355 * specifies the vector for the first message in the MSI-X table, etc.
1356 * The vector value in each array index can either be 0 to indicate
1357 * that no vector should be assigned to a message slot, or it can be a
1358 * number from 1 to N (where N is the count returned from a
1359 * succcessful call to pci_alloc_msix()) to indicate which message
1360 * vector (IRQ) to be used for the corresponding message.
1362 * On successful return, each message with a non-zero vector will have
1363 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1364 * 1. Additionally, if any of the IRQs allocated via the previous
1365 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1366 * will be kfreed back to the system automatically.
1368 * For example, suppose a driver has a MSI-X table with 6 messages and
1369 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1370 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1371 * C. After the call to pci_alloc_msix(), the device will be setup to
1372 * have an MSI-X table of ABC--- (where - means no vector assigned).
1373 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1374 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1375 * be kfreed back to the system. This device will also have valid
1376 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1378 * In any case, the SYS_RES_IRQ rid X will always map to the message
1379 * at MSI-X table index X - 1 and will only be valid if a vector is
1380 * assigned to that table entry.
1383 pci_remap_msix_method(device_t dev, device_t child, int count,
1384 const u_int *vectors)
1386 struct pci_devinfo *dinfo = device_get_ivars(child);
1387 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1388 struct resource_list_entry *rle;
1389 int i, irq, j, *used;
1392 * Have to have at least one message in the table but the
1393 * table can't be bigger than the actual MSI-X table in the
1396 if (count == 0 || count > msix->msix_msgnum)
1399 /* Sanity check the vectors. */
1400 for (i = 0; i < count; i++)
1401 if (vectors[i] > msix->msix_alloc)
1405 * Make sure there aren't any holes in the vectors to be used.
1406 * It's a big pain to support it, and it doesn't really make
1407 * sense anyway. Also, at least one vector must be used.
1409 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1411 for (i = 0; i < count; i++)
1412 if (vectors[i] != 0)
1413 used[vectors[i] - 1] = 1;
1414 for (i = 0; i < msix->msix_alloc - 1; i++)
1415 if (used[i] == 0 && used[i + 1] == 1) {
1416 kfree(used, M_DEVBUF);
1420 kfree(used, M_DEVBUF);
1424 /* Make sure none of the resources are allocated. */
1425 for (i = 0; i < msix->msix_table_len; i++) {
1426 if (msix->msix_table[i].mte_vector == 0)
1428 if (msix->msix_table[i].mte_handlers > 0)
1430 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1431 KASSERT(rle != NULL, ("missing resource"));
1432 if (rle->res != NULL)
1436 /* Free the existing resource list entries. */
1437 for (i = 0; i < msix->msix_table_len; i++) {
1438 if (msix->msix_table[i].mte_vector == 0)
1440 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1444 * Build the new virtual table keeping track of which vectors are
1447 kfree(msix->msix_table, M_DEVBUF);
1448 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1449 M_DEVBUF, M_WAITOK | M_ZERO);
1450 for (i = 0; i < count; i++)
1451 msix->msix_table[i].mte_vector = vectors[i];
1452 msix->msix_table_len = count;
1454 /* Free any unused IRQs and resize the vectors array if necessary. */
1455 j = msix->msix_alloc - 1;
1457 struct msix_vector *vec;
1459 while (used[j] == 0) {
1460 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1461 msix->msix_vectors[j].mv_irq);
1464 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1466 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1468 kfree(msix->msix_vectors, M_DEVBUF);
1469 msix->msix_vectors = vec;
1470 msix->msix_alloc = j + 1;
1472 kfree(used, M_DEVBUF);
1474 /* Map the IRQs onto the rids. */
1475 for (i = 0; i < count; i++) {
1476 if (vectors[i] == 0)
1478 irq = msix->msix_vectors[vectors[i]].mv_irq;
1479 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1484 device_printf(child, "Remapped MSI-X IRQs as: ");
1485 for (i = 0; i < count; i++) {
1488 if (vectors[i] == 0)
1492 msix->msix_vectors[vectors[i]].mv_irq);
1501 pci_release_msix(device_t dev, device_t child)
1503 struct pci_devinfo *dinfo = device_get_ivars(child);
1504 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1505 struct resource_list_entry *rle;
1508 /* Do we have any messages to release? */
1509 if (msix->msix_alloc == 0)
1512 /* Make sure none of the resources are allocated. */
1513 for (i = 0; i < msix->msix_table_len; i++) {
1514 if (msix->msix_table[i].mte_vector == 0)
1516 if (msix->msix_table[i].mte_handlers > 0)
1518 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1519 KASSERT(rle != NULL, ("missing resource"));
1520 if (rle->res != NULL)
1524 /* Update control register to disable MSI-X. */
1525 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1526 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1527 msix->msix_ctrl, 2);
1529 /* Free the resource list entries. */
1530 for (i = 0; i < msix->msix_table_len; i++) {
1531 if (msix->msix_table[i].mte_vector == 0)
1533 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1535 kfree(msix->msix_table, M_DEVBUF);
1536 msix->msix_table_len = 0;
1538 /* Release the IRQs. */
1539 for (i = 0; i < msix->msix_alloc; i++)
1540 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1541 msix->msix_vectors[i].mv_irq);
1542 kfree(msix->msix_vectors, M_DEVBUF);
1543 msix->msix_alloc = 0;
1548 * Return the max supported MSI-X messages this device supports.
1549 * Basically, assuming the MD code can alloc messages, this function
1550 * should return the maximum value that pci_alloc_msix() can return.
1551 * Thus, it is subject to the tunables, etc.
1554 pci_msix_count_method(device_t dev, device_t child)
1556 struct pci_devinfo *dinfo = device_get_ivars(child);
1557 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1559 if (pci_do_msix && msix->msix_location != 0)
1560 return (msix->msix_msgnum);
1565 * HyperTransport MSI mapping control
1568 pci_ht_map_msi(device_t dev, uint64_t addr)
1570 struct pci_devinfo *dinfo = device_get_ivars(dev);
1571 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1576 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1577 ht->ht_msiaddr >> 20 == addr >> 20) {
1578 /* Enable MSI -> HT mapping. */
1579 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1580 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1584 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1585 /* Disable MSI -> HT mapping. */
1586 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1587 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1593 * Support for MSI message signalled interrupts.
1596 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1598 struct pci_devinfo *dinfo = device_get_ivars(dev);
1599 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1601 /* Write data and address values. */
1602 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1603 address & 0xffffffff, 4);
1604 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1605 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1607 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1610 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1613 /* Enable MSI in the control register. */
1614 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1615 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1618 /* Enable MSI -> HT mapping. */
1619 pci_ht_map_msi(dev, address);
1623 pci_disable_msi(device_t dev)
1625 struct pci_devinfo *dinfo = device_get_ivars(dev);
1626 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1628 /* Disable MSI -> HT mapping. */
1629 pci_ht_map_msi(dev, 0);
1631 /* Disable MSI in the control register. */
1632 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1633 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1638 * Restore MSI registers during resume. If MSI is enabled then
1639 * restore the data and address registers in addition to the control
1643 pci_resume_msi(device_t dev)
1645 struct pci_devinfo *dinfo = device_get_ivars(dev);
1646 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1650 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1651 address = msi->msi_addr;
1652 data = msi->msi_data;
1653 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1654 address & 0xffffffff, 4);
1655 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1656 pci_write_config(dev, msi->msi_location +
1657 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1658 pci_write_config(dev, msi->msi_location +
1659 PCIR_MSI_DATA_64BIT, data, 2);
1661 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1664 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1669 pci_remap_msi_irq(device_t dev, u_int irq)
1671 struct pci_devinfo *dinfo = device_get_ivars(dev);
1672 pcicfgregs *cfg = &dinfo->cfg;
1673 struct resource_list_entry *rle;
1674 struct msix_table_entry *mte;
1675 struct msix_vector *mv;
1681 bus = device_get_parent(dev);
1684 * Handle MSI first. We try to find this IRQ among our list
1685 * of MSI IRQs. If we find it, we request updated address and
1686 * data registers and apply the results.
1688 if (cfg->msi.msi_alloc > 0) {
1690 /* If we don't have any active handlers, nothing to do. */
1691 if (cfg->msi.msi_handlers == 0)
1693 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1694 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1696 if (rle->start == irq) {
1697 error = PCIB_MAP_MSI(device_get_parent(bus),
1698 dev, irq, &addr, &data);
1701 pci_disable_msi(dev);
1702 dinfo->cfg.msi.msi_addr = addr;
1703 dinfo->cfg.msi.msi_data = data;
1704 pci_enable_msi(dev, addr, data);
1712 * For MSI-X, we check to see if we have this IRQ. If we do,
1713 * we request the updated mapping info. If that works, we go
1714 * through all the slots that use this IRQ and update them.
1716 if (cfg->msix.msix_alloc > 0) {
1717 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1718 mv = &cfg->msix.msix_vectors[i];
1719 if (mv->mv_irq == irq) {
1720 error = PCIB_MAP_MSI(device_get_parent(bus),
1721 dev, irq, &addr, &data);
1724 mv->mv_address = addr;
1726 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1727 mte = &cfg->msix.msix_table[j];
1728 if (mte->mte_vector != i + 1)
1730 if (mte->mte_handlers == 0)
1732 pci_mask_msix(dev, j);
1733 pci_enable_msix(dev, j, addr, data);
1734 pci_unmask_msix(dev, j);
1745 * Returns true if the specified device is blacklisted because MSI
1749 pci_msi_device_blacklisted(device_t dev)
1751 struct pci_quirk *q;
1753 if (!pci_honor_msi_blacklist)
1756 for (q = &pci_quirks[0]; q->devid; q++) {
1757 if (q->devid == pci_get_devid(dev) &&
1758 q->type == PCI_QUIRK_DISABLE_MSI)
1765 * Determine if MSI is blacklisted globally on this sytem. Currently,
1766 * we just check for blacklisted chipsets as represented by the
1767 * host-PCI bridge at device 0:0:0. In the future, it may become
1768 * necessary to check other system attributes, such as the kenv values
1769 * that give the motherboard manufacturer and model number.
1772 pci_msi_blacklisted(void)
1776 if (!pci_honor_msi_blacklist)
1779 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1780 if (!(pcie_chipset || pcix_chipset))
1783 dev = pci_find_bsf(0, 0, 0);
1785 return (pci_msi_device_blacklisted(dev));
1790 * Attempt to allocate *count MSI messages. The actual number allocated is
1791 * returned in *count. After this function returns, each message will be
1792 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1795 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1797 struct pci_devinfo *dinfo = device_get_ivars(child);
1798 pcicfgregs *cfg = &dinfo->cfg;
1799 struct resource_list_entry *rle;
1800 int actual, error, i, irqs[32];
1803 /* Don't let count == 0 get us into trouble. */
1807 /* If rid 0 is allocated, then fail. */
1808 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1809 if (rle != NULL && rle->res != NULL)
1812 /* Already have allocated messages? */
1813 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1816 /* If MSI is blacklisted for this system, fail. */
1817 if (pci_msi_blacklisted())
1820 /* MSI capability present? */
1821 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1825 device_printf(child,
1826 "attempting to allocate %d MSI vectors (%d supported)\n",
1827 *count, cfg->msi.msi_msgnum);
1829 /* Don't ask for more than the device supports. */
1830 actual = min(*count, cfg->msi.msi_msgnum);
1832 /* Don't ask for more than 32 messages. */
1833 actual = min(actual, 32);
1835 /* MSI requires power of 2 number of messages. */
1836 if (!powerof2(actual))
1840 /* Try to allocate N messages. */
1841 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1842 cfg->msi.msi_msgnum, irqs);
1853 * We now have N actual messages mapped onto SYS_RES_IRQ
1854 * resources in the irqs[] array, so add new resources
1855 * starting at rid 1.
1857 for (i = 0; i < actual; i++)
1858 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1859 irqs[i], irqs[i], 1);
1863 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1868 * Be fancy and try to print contiguous runs
1869 * of IRQ values as ranges. 'run' is true if
1870 * we are in a range.
1872 device_printf(child, "using IRQs %d", irqs[0]);
1874 for (i = 1; i < actual; i++) {
1876 /* Still in a run? */
1877 if (irqs[i] == irqs[i - 1] + 1) {
1882 /* Finish previous range. */
1884 kprintf("-%d", irqs[i - 1]);
1888 /* Start new range. */
1889 kprintf(",%d", irqs[i]);
1892 /* Unfinished range? */
1894 kprintf("-%d", irqs[actual - 1]);
1895 kprintf(" for MSI\n");
1899 /* Update control register with actual count. */
1900 ctrl = cfg->msi.msi_ctrl;
1901 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1902 ctrl |= (ffs(actual) - 1) << 4;
1903 cfg->msi.msi_ctrl = ctrl;
1904 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1906 /* Update counts of alloc'd messages. */
1907 cfg->msi.msi_alloc = actual;
1908 cfg->msi.msi_handlers = 0;
1913 /* Release the MSI messages associated with this device. */
1915 pci_release_msi_method(device_t dev, device_t child)
1917 struct pci_devinfo *dinfo = device_get_ivars(child);
1918 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1919 struct resource_list_entry *rle;
1920 int error, i, irqs[32];
1922 /* Try MSI-X first. */
1923 error = pci_release_msix(dev, child);
1924 if (error != ENODEV)
1927 /* Do we have any messages to release? */
1928 if (msi->msi_alloc == 0)
1930 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1932 /* Make sure none of the resources are allocated. */
1933 if (msi->msi_handlers > 0)
1935 for (i = 0; i < msi->msi_alloc; i++) {
1936 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1937 KASSERT(rle != NULL, ("missing MSI resource"));
1938 if (rle->res != NULL)
1940 irqs[i] = rle->start;
1943 /* Update control register with 0 count. */
1944 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
1945 ("%s: MSI still enabled", __func__));
1946 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
1947 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
1950 /* Release the messages. */
1951 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
1952 for (i = 0; i < msi->msi_alloc; i++)
1953 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1955 /* Update alloc count. */
1963 * Return the max supported MSI messages this device supports.
1964 * Basically, assuming the MD code can alloc messages, this function
1965 * should return the maximum value that pci_alloc_msi() can return.
1966 * Thus, it is subject to the tunables, etc.
1969 pci_msi_count_method(device_t dev, device_t child)
1971 struct pci_devinfo *dinfo = device_get_ivars(child);
1972 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1974 if (pci_do_msi && msi->msi_location != 0)
1975 return (msi->msi_msgnum);
1979 /* kfree pcicfgregs structure and all depending data structures */
1982 pci_freecfg(struct pci_devinfo *dinfo)
1984 struct devlist *devlist_head;
1987 devlist_head = &pci_devq;
1989 if (dinfo->cfg.vpd.vpd_reg) {
1990 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
1991 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
1992 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
1993 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
1994 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
1995 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
1996 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
1998 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
1999 kfree(dinfo, M_DEVBUF);
2001 /* increment the generation count */
2004 /* we're losing one device */
2010 * PCI power manangement
2013 pci_set_powerstate_method(device_t dev, device_t child, int state)
2015 struct pci_devinfo *dinfo = device_get_ivars(child);
2016 pcicfgregs *cfg = &dinfo->cfg;
2018 int result, oldstate, highest, delay;
2020 if (cfg->pp.pp_cap == 0)
2021 return (EOPNOTSUPP);
2024 * Optimize a no state change request away. While it would be OK to
2025 * write to the hardware in theory, some devices have shown odd
2026 * behavior when going from D3 -> D3.
2028 oldstate = pci_get_powerstate(child);
2029 if (oldstate == state)
2033 * The PCI power management specification states that after a state
2034 * transition between PCI power states, system software must
2035 * guarantee a minimal delay before the function accesses the device.
2036 * Compute the worst case delay that we need to guarantee before we
2037 * access the device. Many devices will be responsive much more
2038 * quickly than this delay, but there are some that don't respond
2039 * instantly to state changes. Transitions to/from D3 state require
2040 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2041 * is done below with DELAY rather than a sleeper function because
2042 * this function can be called from contexts where we cannot sleep.
2044 highest = (oldstate > state) ? oldstate : state;
2045 if (highest == PCI_POWERSTATE_D3)
2047 else if (highest == PCI_POWERSTATE_D2)
2051 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2052 & ~PCIM_PSTAT_DMASK;
2055 case PCI_POWERSTATE_D0:
2056 status |= PCIM_PSTAT_D0;
2058 case PCI_POWERSTATE_D1:
2059 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2060 return (EOPNOTSUPP);
2061 status |= PCIM_PSTAT_D1;
2063 case PCI_POWERSTATE_D2:
2064 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2065 return (EOPNOTSUPP);
2066 status |= PCIM_PSTAT_D2;
2068 case PCI_POWERSTATE_D3:
2069 status |= PCIM_PSTAT_D3;
2077 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2078 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2079 dinfo->cfg.func, oldstate, state);
2081 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2088 pci_get_powerstate_method(device_t dev, device_t child)
2090 struct pci_devinfo *dinfo = device_get_ivars(child);
2091 pcicfgregs *cfg = &dinfo->cfg;
2095 if (cfg->pp.pp_cap != 0) {
2096 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2097 switch (status & PCIM_PSTAT_DMASK) {
2099 result = PCI_POWERSTATE_D0;
2102 result = PCI_POWERSTATE_D1;
2105 result = PCI_POWERSTATE_D2;
2108 result = PCI_POWERSTATE_D3;
2111 result = PCI_POWERSTATE_UNKNOWN;
2115 /* No support, device is always at D0 */
2116 result = PCI_POWERSTATE_D0;
2122 * Some convenience functions for PCI device drivers.
2125 static __inline void
2126 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2130 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2132 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2135 static __inline void
2136 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2140 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2142 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2146 pci_enable_busmaster_method(device_t dev, device_t child)
2148 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2153 pci_disable_busmaster_method(device_t dev, device_t child)
2155 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2160 pci_enable_io_method(device_t dev, device_t child, int space)
2170 case SYS_RES_IOPORT:
2171 bit = PCIM_CMD_PORTEN;
2174 case SYS_RES_MEMORY:
2175 bit = PCIM_CMD_MEMEN;
2181 pci_set_command_bit(dev, child, bit);
2182 /* Some devices seem to need a brief stall here, what do to? */
2183 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2186 device_printf(child, "failed to enable %s mapping!\n", error);
2191 pci_disable_io_method(device_t dev, device_t child, int space)
2201 case SYS_RES_IOPORT:
2202 bit = PCIM_CMD_PORTEN;
2205 case SYS_RES_MEMORY:
2206 bit = PCIM_CMD_MEMEN;
2212 pci_clear_command_bit(dev, child, bit);
2213 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2214 if (command & bit) {
2215 device_printf(child, "failed to disable %s mapping!\n", error);
2222 * New style pci driver. Parent device is either a pci-host-bridge or a
2223 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2227 pci_print_verbose(struct pci_devinfo *dinfo)
2231 pcicfgregs *cfg = &dinfo->cfg;
2233 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2234 cfg->vendor, cfg->device, cfg->revid);
2235 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2236 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2237 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2238 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2240 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2241 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2242 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2243 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2244 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2245 if (cfg->intpin > 0)
2246 kprintf("\tintpin=%c, irq=%d\n",
2247 cfg->intpin +'a' -1, cfg->intline);
2248 if (cfg->pp.pp_cap) {
2251 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2252 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2253 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2254 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2255 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2256 status & PCIM_PSTAT_DMASK);
2258 if (cfg->msi.msi_location) {
2261 ctrl = cfg->msi.msi_ctrl;
2262 kprintf("\tMSI supports %d message%s%s%s\n",
2263 cfg->msi.msi_msgnum,
2264 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2265 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2266 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2268 if (cfg->msix.msix_location) {
2269 kprintf("\tMSI-X supports %d message%s ",
2270 cfg->msix.msix_msgnum,
2271 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2272 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2273 kprintf("in map 0x%x\n",
2274 cfg->msix.msix_table_bar);
2276 kprintf("in maps 0x%x and 0x%x\n",
2277 cfg->msix.msix_table_bar,
2278 cfg->msix.msix_pba_bar);
2284 pci_porten(device_t pcib, int b, int s, int f)
2286 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2287 & PCIM_CMD_PORTEN) != 0;
2291 pci_memen(device_t pcib, int b, int s, int f)
2293 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2294 & PCIM_CMD_MEMEN) != 0;
2298 * Add a resource based on a pci map register. Return 1 if the map
2299 * register is a 32bit map register or 2 if it is a 64bit register.
2302 pci_add_map(device_t pcib, device_t bus, device_t dev,
2303 int b, int s, int f, int reg, struct resource_list *rl, int force,
2308 pci_addr_t start, end, count;
2315 struct resource *res;
2317 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2318 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2319 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2320 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2322 if (PCI_BAR_MEM(map)) {
2323 type = SYS_RES_MEMORY;
2324 if (map & PCIM_BAR_MEM_PREFETCH)
2327 type = SYS_RES_IOPORT;
2328 ln2size = pci_mapsize(testval);
2329 ln2range = pci_maprange(testval);
2330 base = pci_mapbase(map);
2331 barlen = ln2range == 64 ? 2 : 1;
2334 * For I/O registers, if bottom bit is set, and the next bit up
2335 * isn't clear, we know we have a BAR that doesn't conform to the
2336 * spec, so ignore it. Also, sanity check the size of the data
2337 * areas to the type of memory involved. Memory must be at least
2338 * 16 bytes in size, while I/O ranges must be at least 4.
2340 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2342 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2343 (type == SYS_RES_IOPORT && ln2size < 2))
2347 /* Read the other half of a 64bit map register */
2348 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2350 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2351 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2352 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2353 kprintf(", port disabled\n");
2354 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2355 kprintf(", memory disabled\n");
2357 kprintf(", enabled\n");
2361 * If base is 0, then we have problems. It is best to ignore
2362 * such entries for the moment. These will be allocated later if
2363 * the driver specifically requests them. However, some
2364 * removable busses look better when all resources are allocated,
2365 * so allow '0' to be overriden.
2367 * Similarly treat maps whose values is the same as the test value
2368 * read back. These maps have had all f's written to them by the
2369 * BIOS in an attempt to disable the resources.
2371 if (!force && (base == 0 || map == testval))
2373 if ((u_long)base != base) {
2375 "pci%d:%d:%d:%d bar %#x too many address bits",
2376 pci_get_domain(dev), b, s, f, reg);
2381 * This code theoretically does the right thing, but has
2382 * undesirable side effects in some cases where peripherals
2383 * respond oddly to having these bits enabled. Let the user
2384 * be able to turn them off (since pci_enable_io_modes is 1 by
2387 if (pci_enable_io_modes) {
2388 /* Turn on resources that have been left off by a lazy BIOS */
2389 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2390 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2391 cmd |= PCIM_CMD_PORTEN;
2392 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2394 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2395 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2396 cmd |= PCIM_CMD_MEMEN;
2397 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2400 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2402 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2406 count = 1 << ln2size;
2407 if (base == 0 || base == pci_mapbase(testval)) {
2408 start = 0; /* Let the parent decide. */
2412 end = base + (1 << ln2size) - 1;
2414 resource_list_add(rl, type, reg, start, end, count);
2417 * Try to allocate the resource for this BAR from our parent
2418 * so that this resource range is already reserved. The
2419 * driver for this device will later inherit this resource in
2420 * pci_alloc_resource().
2422 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2423 prefetch ? RF_PREFETCHABLE : 0);
2426 * If the allocation fails, clear the BAR and delete
2427 * the resource list entry to force
2428 * pci_alloc_resource() to allocate resources from the
2431 resource_list_delete(rl, type, reg);
2434 start = rman_get_start(res);
2435 pci_write_config(dev, reg, start, 4);
2437 pci_write_config(dev, reg + 4, start >> 32, 4);
2442 * For ATA devices we need to decide early what addressing mode to use.
2443 * Legacy demands that the primary and secondary ATA ports sits on the
2444 * same addresses that old ISA hardware did. This dictates that we use
2445 * those addresses and ignore the BAR's if we cannot set PCI native
2449 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2450 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2452 int rid, type, progif;
2454 /* if this device supports PCI native addressing use it */
2455 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2456 if ((progif & 0x8a) == 0x8a) {
2457 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2458 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2459 kprintf("Trying ATA native PCI addressing mode\n");
2460 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2464 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2465 type = SYS_RES_IOPORT;
2466 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2467 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2468 prefetchmask & (1 << 0));
2469 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2470 prefetchmask & (1 << 1));
2473 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2474 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2477 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2478 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2481 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2482 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2483 prefetchmask & (1 << 2));
2484 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2485 prefetchmask & (1 << 3));
2488 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2489 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2492 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2493 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2496 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2497 prefetchmask & (1 << 4));
2498 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2499 prefetchmask & (1 << 5));
2503 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2505 struct pci_devinfo *dinfo = device_get_ivars(dev);
2506 pcicfgregs *cfg = &dinfo->cfg;
2507 char tunable_name[64];
2510 /* Has to have an intpin to have an interrupt. */
2511 if (cfg->intpin == 0)
2514 /* Let the user override the IRQ with a tunable. */
2515 irq = PCI_INVALID_IRQ;
2516 ksnprintf(tunable_name, sizeof(tunable_name),
2517 "hw.pci%d.%d.%d.INT%c.irq",
2518 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2519 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2520 irq = PCI_INVALID_IRQ;
2523 * If we didn't get an IRQ via the tunable, then we either use the
2524 * IRQ value in the intline register or we ask the bus to route an
2525 * interrupt for us. If force_route is true, then we only use the
2526 * value in the intline register if the bus was unable to assign an
2529 if (!PCI_INTERRUPT_VALID(irq)) {
2530 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2531 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2532 if (!PCI_INTERRUPT_VALID(irq))
2536 /* If after all that we don't have an IRQ, just bail. */
2537 if (!PCI_INTERRUPT_VALID(irq))
2540 /* Update the config register if it changed. */
2541 if (irq != cfg->intline) {
2543 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2546 /* Add this IRQ as rid 0 interrupt resource. */
2547 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2551 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2553 struct pci_devinfo *dinfo = device_get_ivars(dev);
2554 pcicfgregs *cfg = &dinfo->cfg;
2555 struct resource_list *rl = &dinfo->resources;
2556 struct pci_quirk *q;
2563 /* ATA devices needs special map treatment */
2564 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2565 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2566 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2567 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2568 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2569 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2571 for (i = 0; i < cfg->nummaps;)
2572 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2573 rl, force, prefetchmask & (1 << i));
2576 * Add additional, quirked resources.
2578 for (q = &pci_quirks[0]; q->devid; q++) {
2579 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2580 && q->type == PCI_QUIRK_MAP_REG)
2581 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2585 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2586 #ifdef __PCI_REROUTE_INTERRUPT
2588 * Try to re-route interrupts. Sometimes the BIOS or
2589 * firmware may leave bogus values in these registers.
2590 * If the re-route fails, then just stick with what we
2593 pci_assign_interrupt(bus, dev, 1);
2595 pci_assign_interrupt(bus, dev, 0);
2601 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2603 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2604 device_t pcib = device_get_parent(dev);
2605 struct pci_devinfo *dinfo;
2607 int s, f, pcifunchigh;
2610 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2611 ("dinfo_size too small"));
2612 maxslots = PCIB_MAXSLOTS(pcib);
2613 for (s = 0; s <= maxslots; s++) {
2617 hdrtype = REG(PCIR_HDRTYPE, 1);
2618 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2620 if (hdrtype & PCIM_MFDEV)
2621 pcifunchigh = PCI_FUNCMAX;
2622 for (f = 0; f <= pcifunchigh; f++) {
2623 dinfo = pci_read_device(pcib, domain, busno, s, f,
2625 if (dinfo != NULL) {
2626 pci_add_child(dev, dinfo);
2634 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2638 pcib = device_get_parent(bus);
2639 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2640 device_set_ivars(dinfo->cfg.dev, dinfo);
2641 resource_list_init(&dinfo->resources);
2642 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2643 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2644 pci_print_verbose(dinfo);
2645 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2649 pci_probe(device_t dev)
2651 device_set_desc(dev, "PCI bus");
2653 /* Allow other subclasses to override this driver. */
2658 pci_attach(device_t dev)
2663 * Since there can be multiple independantly numbered PCI
2664 * busses on systems with multiple PCI domains, we can't use
2665 * the unit number to decide which bus we are probing. We ask
2666 * the parent pcib what our domain and bus numbers are.
2668 domain = pcib_get_domain(dev);
2669 busno = pcib_get_bus(dev);
2671 device_printf(dev, "domain=%d, physical bus=%d\n",
2674 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2676 return (bus_generic_attach(dev));
2680 pci_suspend(device_t dev)
2682 int dstate, error, i, numdevs;
2683 device_t acpi_dev, child, *devlist;
2684 struct pci_devinfo *dinfo;
2687 * Save the PCI configuration space for each child and set the
2688 * device in the appropriate power state for this sleep state.
2691 if (pci_do_power_resume)
2692 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2693 device_get_children(dev, &devlist, &numdevs);
2694 for (i = 0; i < numdevs; i++) {
2696 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2697 pci_cfg_save(child, dinfo, 0);
2700 /* Suspend devices before potentially powering them down. */
2701 error = bus_generic_suspend(dev);
2703 kfree(devlist, M_TEMP);
2708 * Always set the device to D3. If ACPI suggests a different
2709 * power state, use it instead. If ACPI is not present, the
2710 * firmware is responsible for managing device power. Skip
2711 * children who aren't attached since they are powered down
2712 * separately. Only manage type 0 devices for now.
2714 for (i = 0; acpi_dev && i < numdevs; i++) {
2716 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2717 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2718 dstate = PCI_POWERSTATE_D3;
2719 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2720 pci_set_powerstate(child, dstate);
2723 kfree(devlist, M_TEMP);
2728 pci_resume(device_t dev)
2731 device_t acpi_dev, child, *devlist;
2732 struct pci_devinfo *dinfo;
2735 * Set each child to D0 and restore its PCI configuration space.
2738 if (pci_do_power_resume)
2739 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2740 device_get_children(dev, &devlist, &numdevs);
2741 for (i = 0; i < numdevs; i++) {
2743 * Notify ACPI we're going to D0 but ignore the result. If
2744 * ACPI is not present, the firmware is responsible for
2745 * managing device power. Only manage type 0 devices for now.
2748 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2749 if (acpi_dev && device_is_attached(child) &&
2750 dinfo->cfg.hdrtype == 0) {
2751 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2752 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2755 /* Now the device is powered up, restore its config space. */
2756 pci_cfg_restore(child, dinfo);
2758 kfree(devlist, M_TEMP);
2759 return (bus_generic_resume(dev));
2763 pci_load_vendor_data(void)
2765 caddr_t vendordata, info;
2767 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2768 info = preload_search_info(vendordata, MODINFO_ADDR);
2769 pci_vendordata = *(char **)info;
2770 info = preload_search_info(vendordata, MODINFO_SIZE);
2771 pci_vendordata_size = *(size_t *)info;
2772 /* terminate the database */
2773 pci_vendordata[pci_vendordata_size] = '\n';
2778 pci_driver_added(device_t dev, driver_t *driver)
2783 struct pci_devinfo *dinfo;
2787 device_printf(dev, "driver added\n");
2788 DEVICE_IDENTIFY(driver, dev);
2789 device_get_children(dev, &devlist, &numdevs);
2790 for (i = 0; i < numdevs; i++) {
2792 if (device_get_state(child) != DS_NOTPRESENT)
2794 dinfo = device_get_ivars(child);
2795 pci_print_verbose(dinfo);
2797 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2798 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2800 pci_cfg_restore(child, dinfo);
2801 if (device_probe_and_attach(child) != 0)
2802 pci_cfg_save(child, dinfo, 1);
2804 kfree(devlist, M_TEMP);
2808 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2809 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2812 struct pci_devinfo *dinfo;
2813 struct msix_table_entry *mte;
2814 struct msix_vector *mv;
2820 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
2821 arg, &cookie, serializer);
2825 /* If this is not a direct child, just bail out. */
2826 if (device_get_parent(child) != dev) {
2831 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2833 rid = rman_get_rid(irq);
2835 /* Make sure that INTx is enabled */
2836 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2839 * Check to see if the interrupt is MSI or MSI-X.
2840 * Ask our parent to map the MSI and give
2841 * us the address and data register values.
2842 * If we fail for some reason, teardown the
2843 * interrupt handler.
2845 dinfo = device_get_ivars(child);
2846 if (dinfo->cfg.msi.msi_alloc > 0) {
2847 if (dinfo->cfg.msi.msi_addr == 0) {
2848 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
2849 ("MSI has handlers, but vectors not mapped"));
2850 error = PCIB_MAP_MSI(device_get_parent(dev),
2851 child, rman_get_start(irq), &addr, &data);
2854 dinfo->cfg.msi.msi_addr = addr;
2855 dinfo->cfg.msi.msi_data = data;
2856 pci_enable_msi(child, addr, data);
2858 dinfo->cfg.msi.msi_handlers++;
2860 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2861 ("No MSI or MSI-X interrupts allocated"));
2862 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2863 ("MSI-X index too high"));
2864 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2865 KASSERT(mte->mte_vector != 0, ("no message vector"));
2866 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
2867 KASSERT(mv->mv_irq == rman_get_start(irq),
2869 if (mv->mv_address == 0) {
2870 KASSERT(mte->mte_handlers == 0,
2871 ("MSI-X table entry has handlers, but vector not mapped"));
2872 error = PCIB_MAP_MSI(device_get_parent(dev),
2873 child, rman_get_start(irq), &addr, &data);
2876 mv->mv_address = addr;
2879 if (mte->mte_handlers == 0) {
2880 pci_enable_msix(child, rid - 1, mv->mv_address,
2882 pci_unmask_msix(child, rid - 1);
2884 mte->mte_handlers++;
2887 /* Make sure that INTx is disabled if we are using MSI/MSIX */
2888 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2891 (void)bus_generic_teardown_intr(dev, child, irq,
2902 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
2906 struct msix_table_entry *mte;
2907 struct resource_list_entry *rle;
2908 struct pci_devinfo *dinfo;
2912 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
2915 /* If this isn't a direct child, just bail out */
2916 if (device_get_parent(child) != dev)
2917 return(bus_generic_teardown_intr(dev, child, irq, cookie));
2919 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2921 rid = rman_get_rid(irq);
2924 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2927 * Check to see if the interrupt is MSI or MSI-X. If so,
2928 * decrement the appropriate handlers count and mask the
2929 * MSI-X message, or disable MSI messages if the count
2932 dinfo = device_get_ivars(child);
2933 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
2934 if (rle->res != irq)
2936 if (dinfo->cfg.msi.msi_alloc > 0) {
2937 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
2938 ("MSI-X index too high"));
2939 if (dinfo->cfg.msi.msi_handlers == 0)
2941 dinfo->cfg.msi.msi_handlers--;
2942 if (dinfo->cfg.msi.msi_handlers == 0)
2943 pci_disable_msi(child);
2945 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2946 ("No MSI or MSI-X interrupts allocated"));
2947 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2948 ("MSI-X index too high"));
2949 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2950 if (mte->mte_handlers == 0)
2952 mte->mte_handlers--;
2953 if (mte->mte_handlers == 0)
2954 pci_mask_msix(child, rid - 1);
2957 error = bus_generic_teardown_intr(dev, child, irq, cookie);
2960 ("%s: generic teardown failed for MSI/MSI-X", __func__));
2962 error = bus_generic_teardown_intr(dev, child, irq, cookie);
2967 pci_print_child(device_t dev, device_t child)
2969 struct pci_devinfo *dinfo;
2970 struct resource_list *rl;
2973 dinfo = device_get_ivars(child);
2974 rl = &dinfo->resources;
2976 retval += bus_print_child_header(dev, child);
2978 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
2979 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
2980 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
2981 if (device_get_flags(dev))
2982 retval += kprintf(" flags %#x", device_get_flags(dev));
2984 retval += kprintf(" at device %d.%d", pci_get_slot(child),
2985 pci_get_function(child));
2987 retval += bus_print_child_footer(dev, child);
2997 } pci_nomatch_tab[] = {
2998 {PCIC_OLD, -1, "old"},
2999 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3000 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3001 {PCIC_STORAGE, -1, "mass storage"},
3002 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3003 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3004 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3005 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3006 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3007 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3008 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3009 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3010 {PCIC_NETWORK, -1, "network"},
3011 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3012 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3013 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3014 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3015 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3016 {PCIC_DISPLAY, -1, "display"},
3017 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3018 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3019 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3020 {PCIC_MULTIMEDIA, -1, "multimedia"},
3021 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3022 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3023 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3024 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3025 {PCIC_MEMORY, -1, "memory"},
3026 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3027 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3028 {PCIC_BRIDGE, -1, "bridge"},
3029 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3030 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3031 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3032 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3033 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3034 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3035 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3036 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3037 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3038 {PCIC_SIMPLECOMM, -1, "simple comms"},
3039 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3040 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3041 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3042 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3043 {PCIC_BASEPERIPH, -1, "base peripheral"},
3044 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3045 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3046 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3047 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3048 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3049 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3050 {PCIC_INPUTDEV, -1, "input device"},
3051 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3052 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3053 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3054 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3055 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3056 {PCIC_DOCKING, -1, "docking station"},
3057 {PCIC_PROCESSOR, -1, "processor"},
3058 {PCIC_SERIALBUS, -1, "serial bus"},
3059 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3060 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3061 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3062 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3063 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3064 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3065 {PCIC_WIRELESS, -1, "wireless controller"},
3066 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3067 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3068 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3069 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3070 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3071 {PCIC_SATCOM, -1, "satellite communication"},
3072 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3073 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3074 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3075 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3076 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3077 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3078 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3079 {PCIC_DASP, -1, "dasp"},
3080 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3085 pci_probe_nomatch(device_t dev, device_t child)
3088 char *cp, *scp, *device;
3091 * Look for a listing for this device in a loaded device database.
3093 if ((device = pci_describe_device(child)) != NULL) {
3094 device_printf(dev, "<%s>", device);
3095 kfree(device, M_DEVBUF);
3098 * Scan the class/subclass descriptions for a general
3103 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3104 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3105 if (pci_nomatch_tab[i].subclass == -1) {
3106 cp = pci_nomatch_tab[i].desc;
3107 } else if (pci_nomatch_tab[i].subclass ==
3108 pci_get_subclass(child)) {
3109 scp = pci_nomatch_tab[i].desc;
3113 device_printf(dev, "<%s%s%s>",
3115 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3118 kprintf(" at device %d.%d (no driver attached)\n",
3119 pci_get_slot(child), pci_get_function(child));
3120 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3125 * Parse the PCI device database, if loaded, and return a pointer to a
3126 * description of the device.
3128 * The database is flat text formatted as follows:
3130 * Any line not in a valid format is ignored.
3131 * Lines are terminated with newline '\n' characters.
3133 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3136 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3137 * - devices cannot be listed without a corresponding VENDOR line.
3138 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3139 * another TAB, then the device name.
3143 * Assuming (ptr) points to the beginning of a line in the database,
3144 * return the vendor or device and description of the next entry.
3145 * The value of (vendor) or (device) inappropriate for the entry type
3146 * is set to -1. Returns nonzero at the end of the database.
3148 * Note that this is slightly unrobust in the face of corrupt data;
3149 * we attempt to safeguard against this by spamming the end of the
3150 * database with a newline when we initialise.
3153 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3162 left = pci_vendordata_size - (cp - pci_vendordata);
3170 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3174 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3177 /* skip to next line */
3178 while (*cp != '\n' && left > 0) {
3187 /* skip to next line */
3188 while (*cp != '\n' && left > 0) {
3192 if (*cp == '\n' && left > 0)
3199 pci_describe_device(device_t dev)
3202 char *desc, *vp, *dp, *line;
3204 desc = vp = dp = NULL;
3207 * If we have no vendor data, we can't do anything.
3209 if (pci_vendordata == NULL)
3213 * Scan the vendor data looking for this device
3215 line = pci_vendordata;
3216 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3219 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3221 if (vendor == pci_get_vendor(dev))
3224 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3227 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3235 if (device == pci_get_device(dev))
3239 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3240 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3242 ksprintf(desc, "%s, %s", vp, dp);
3245 kfree(vp, M_DEVBUF);
3247 kfree(dp, M_DEVBUF);
3252 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3254 struct pci_devinfo *dinfo;
3257 dinfo = device_get_ivars(child);
3261 case PCI_IVAR_ETHADDR:
3263 * The generic accessor doesn't deal with failure, so
3264 * we set the return value, then return an error.
3266 *((uint8_t **) result) = NULL;
3268 case PCI_IVAR_SUBVENDOR:
3269 *result = cfg->subvendor;
3271 case PCI_IVAR_SUBDEVICE:
3272 *result = cfg->subdevice;
3274 case PCI_IVAR_VENDOR:
3275 *result = cfg->vendor;
3277 case PCI_IVAR_DEVICE:
3278 *result = cfg->device;
3280 case PCI_IVAR_DEVID:
3281 *result = (cfg->device << 16) | cfg->vendor;
3283 case PCI_IVAR_CLASS:
3284 *result = cfg->baseclass;
3286 case PCI_IVAR_SUBCLASS:
3287 *result = cfg->subclass;
3289 case PCI_IVAR_PROGIF:
3290 *result = cfg->progif;
3292 case PCI_IVAR_REVID:
3293 *result = cfg->revid;
3295 case PCI_IVAR_INTPIN:
3296 *result = cfg->intpin;
3299 *result = cfg->intline;
3301 case PCI_IVAR_DOMAIN:
3302 *result = cfg->domain;
3308 *result = cfg->slot;
3310 case PCI_IVAR_FUNCTION:
3311 *result = cfg->func;
3313 case PCI_IVAR_CMDREG:
3314 *result = cfg->cmdreg;
3316 case PCI_IVAR_CACHELNSZ:
3317 *result = cfg->cachelnsz;
3319 case PCI_IVAR_MINGNT:
3320 *result = cfg->mingnt;
3322 case PCI_IVAR_MAXLAT:
3323 *result = cfg->maxlat;
3325 case PCI_IVAR_LATTIMER:
3326 *result = cfg->lattimer;
3335 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3337 struct pci_devinfo *dinfo;
3339 dinfo = device_get_ivars(child);
3342 case PCI_IVAR_INTPIN:
3343 dinfo->cfg.intpin = value;
3345 case PCI_IVAR_ETHADDR:
3346 case PCI_IVAR_SUBVENDOR:
3347 case PCI_IVAR_SUBDEVICE:
3348 case PCI_IVAR_VENDOR:
3349 case PCI_IVAR_DEVICE:
3350 case PCI_IVAR_DEVID:
3351 case PCI_IVAR_CLASS:
3352 case PCI_IVAR_SUBCLASS:
3353 case PCI_IVAR_PROGIF:
3354 case PCI_IVAR_REVID:
3356 case PCI_IVAR_DOMAIN:
3359 case PCI_IVAR_FUNCTION:
3360 return (EINVAL); /* disallow for now */
3367 #include "opt_ddb.h"
3369 #include <ddb/ddb.h>
3370 #include <sys/cons.h>
3373 * List resources based on pci map registers, used for within ddb
3376 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3378 struct pci_devinfo *dinfo;
3379 struct devlist *devlist_head;
3382 int i, error, none_count;
3385 /* get the head of the device queue */
3386 devlist_head = &pci_devq;
3389 * Go through the list of devices and print out devices
3391 for (error = 0, i = 0,
3392 dinfo = STAILQ_FIRST(devlist_head);
3393 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3394 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3396 /* Populate pd_name and pd_unit */
3399 name = device_get_name(dinfo->cfg.dev);
3402 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3403 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3404 (name && *name) ? name : "none",
3405 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3407 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3408 p->pc_sel.pc_func, (p->pc_class << 16) |
3409 (p->pc_subclass << 8) | p->pc_progif,
3410 (p->pc_subdevice << 16) | p->pc_subvendor,
3411 (p->pc_device << 16) | p->pc_vendor,
3412 p->pc_revid, p->pc_hdr);
3418 static struct resource *
3419 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3420 u_long start, u_long end, u_long count, u_int flags)
3422 struct pci_devinfo *dinfo = device_get_ivars(child);
3423 struct resource_list *rl = &dinfo->resources;
3424 struct resource_list_entry *rle;
3425 struct resource *res;
3426 pci_addr_t map, testval;
3430 * Weed out the bogons, and figure out how large the BAR/map
3431 * is. Bars that read back 0 here are bogus and unimplemented.
3432 * Note: atapci in legacy mode are special and handled elsewhere
3433 * in the code. If you have a atapci device in legacy mode and
3434 * it fails here, that other code is broken.
3437 map = pci_read_config(child, *rid, 4);
3438 pci_write_config(child, *rid, 0xffffffff, 4);
3439 testval = pci_read_config(child, *rid, 4);
3440 if (pci_maprange(testval) == 64)
3441 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3442 if (pci_mapbase(testval) == 0)
3446 * Restore the original value of the BAR. We may have reprogrammed
3447 * the BAR of the low-level console device and when booting verbose,
3448 * we need the console device addressable.
3450 pci_write_config(child, *rid, map, 4);
3452 if (PCI_BAR_MEM(testval)) {
3453 if (type != SYS_RES_MEMORY) {
3456 "child %s requested type %d for rid %#x,"
3457 " but the BAR says it is an memio\n",
3458 device_get_nameunit(child), type, *rid);
3462 if (type != SYS_RES_IOPORT) {
3465 "child %s requested type %d for rid %#x,"
3466 " but the BAR says it is an ioport\n",
3467 device_get_nameunit(child), type, *rid);
3472 * For real BARs, we need to override the size that
3473 * the driver requests, because that's what the BAR
3474 * actually uses and we would otherwise have a
3475 * situation where we might allocate the excess to
3476 * another driver, which won't work.
3478 mapsize = pci_mapsize(testval);
3479 count = 1UL << mapsize;
3480 if (RF_ALIGNMENT(flags) < mapsize)
3481 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3482 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3483 flags |= RF_PREFETCHABLE;
3486 * Allocate enough resource, and then write back the
3487 * appropriate bar for that resource.
3489 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3490 start, end, count, flags);
3492 device_printf(child,
3493 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3494 count, *rid, type, start, end);
3497 resource_list_add(rl, type, *rid, start, end, count);
3498 rle = resource_list_find(rl, type, *rid);
3500 panic("pci_alloc_map: unexpectedly can't find resource.");
3502 rle->start = rman_get_start(res);
3503 rle->end = rman_get_end(res);
3506 device_printf(child,
3507 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3508 count, *rid, type, rman_get_start(res));
3509 map = rman_get_start(res);
3511 pci_write_config(child, *rid, map, 4);
3512 if (pci_maprange(testval) == 64)
3513 pci_write_config(child, *rid + 4, map >> 32, 4);
3519 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3520 u_long start, u_long end, u_long count, u_int flags)
3522 struct pci_devinfo *dinfo = device_get_ivars(child);
3523 struct resource_list *rl = &dinfo->resources;
3524 struct resource_list_entry *rle;
3525 pcicfgregs *cfg = &dinfo->cfg;
3526 //kprintf("%s on %s: requesting resource\n", device_get_desc(child), device_get_desc(dev));
3528 * Perform lazy resource allocation
3530 if (device_get_parent(child) == dev) {
3534 * Can't alloc legacy interrupt once MSI messages
3535 * have been allocated.
3538 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3539 cfg->msix.msix_alloc > 0))
3543 * If the child device doesn't have an
3544 * interrupt routed and is deserving of an
3545 * interrupt, try to assign it one.
3547 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3549 pci_assign_interrupt(dev, child, 0);
3551 case SYS_RES_IOPORT:
3552 case SYS_RES_MEMORY:
3553 if (*rid < PCIR_BAR(cfg->nummaps)) {
3555 * Enable the I/O mode. We should
3556 * also be assigning resources too
3557 * when none are present. The
3558 * resource_list_alloc kind of sorta does
3561 if (PCI_ENABLE_IO(dev, child, type))
3564 rle = resource_list_find(rl, type, *rid);
3566 return (pci_alloc_map(dev, child, type, rid,
3567 start, end, count, flags));
3571 * If we've already allocated the resource, then
3572 * return it now. But first we may need to activate
3573 * it, since we don't allocate the resource as active
3574 * above. Normally this would be done down in the
3575 * nexus, but since we short-circuit that path we have
3576 * to do its job here. Not sure if we should kfree the
3577 * resource if it fails to activate.
3579 rle = resource_list_find(rl, type, *rid);
3580 if (rle != NULL && rle->res != NULL) {
3582 device_printf(child,
3583 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3584 rman_get_size(rle->res), *rid, type,
3585 rman_get_start(rle->res));
3586 if ((flags & RF_ACTIVE) &&
3587 bus_generic_activate_resource(dev, child, type,
3588 *rid, rle->res) != 0)
3593 return (resource_list_alloc(rl, dev, child, type, rid,
3594 start, end, count, flags));
3598 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3600 struct pci_devinfo *dinfo;
3601 struct resource_list *rl;
3602 struct resource_list_entry *rle;
3604 if (device_get_parent(child) != dev)
3607 dinfo = device_get_ivars(child);
3608 rl = &dinfo->resources;
3609 rle = resource_list_find(rl, type, rid);
3612 if (rman_get_device(rle->res) != dev ||
3613 rman_get_flags(rle->res) & RF_ACTIVE) {
3614 device_printf(dev, "delete_resource: "
3615 "Resource still owned by child, oops. "
3616 "(type=%d, rid=%d, addr=%lx)\n",
3617 rle->type, rle->rid,
3618 rman_get_start(rle->res));
3621 bus_release_resource(dev, type, rid, rle->res);
3623 resource_list_delete(rl, type, rid);
3626 * Why do we turn off the PCI configuration BAR when we delete a
3629 pci_write_config(child, rid, 0, 4);
3630 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3633 struct resource_list *
3634 pci_get_resource_list (device_t dev, device_t child)
3636 struct pci_devinfo *dinfo = device_get_ivars(child);
3638 return (&dinfo->resources);
3642 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3644 struct pci_devinfo *dinfo = device_get_ivars(child);
3645 pcicfgregs *cfg = &dinfo->cfg;
3647 return (PCIB_READ_CONFIG(device_get_parent(dev),
3648 cfg->bus, cfg->slot, cfg->func, reg, width));
3652 pci_write_config_method(device_t dev, device_t child, int reg,
3653 uint32_t val, int width)
3655 struct pci_devinfo *dinfo = device_get_ivars(child);
3656 pcicfgregs *cfg = &dinfo->cfg;
3658 PCIB_WRITE_CONFIG(device_get_parent(dev),
3659 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3663 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3667 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3668 pci_get_function(child));
3673 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3676 struct pci_devinfo *dinfo;
3679 dinfo = device_get_ivars(child);
3681 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3682 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3683 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3689 pci_assign_interrupt_method(device_t dev, device_t child)
3691 struct pci_devinfo *dinfo = device_get_ivars(child);
3692 pcicfgregs *cfg = &dinfo->cfg;
3694 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3699 pci_modevent(module_t mod, int what, void *arg)
3701 static struct cdev *pci_cdev;
3702 extern struct dev_ops pcic_ops;
3706 STAILQ_INIT(&pci_devq);
3708 dev_ops_add(&pcic_ops, -1, 0);
3709 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3711 pci_load_vendor_data();
3715 destroy_dev(pci_cdev);
3723 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3728 * Only do header type 0 devices. Type 1 devices are bridges,
3729 * which we know need special treatment. Type 2 devices are
3730 * cardbus bridges which also require special treatment.
3731 * Other types are unknown, and we err on the side of safety
3734 if (dinfo->cfg.hdrtype != 0)
3738 * Restore the device to full power mode. We must do this
3739 * before we restore the registers because moving from D3 to
3740 * D0 will cause the chip's BARs and some other registers to
3741 * be reset to some unknown power on reset values. Cut down
3742 * the noise on boot by doing nothing if we are already in
3745 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3746 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3748 for (i = 0; i < dinfo->cfg.nummaps; i++)
3749 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3750 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3751 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3752 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3753 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3754 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3755 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3756 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3757 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3758 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3759 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3761 /* Restore MSI and MSI-X configurations if they are present. */
3762 if (dinfo->cfg.msi.msi_location != 0)
3763 pci_resume_msi(dev);
3764 if (dinfo->cfg.msix.msix_location != 0)
3765 pci_resume_msix(dev);
3769 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3776 * Only do header type 0 devices. Type 1 devices are bridges, which
3777 * we know need special treatment. Type 2 devices are cardbus bridges
3778 * which also require special treatment. Other types are unknown, and
3779 * we err on the side of safety by ignoring them. Powering down
3780 * bridges should not be undertaken lightly.
3782 if (dinfo->cfg.hdrtype != 0)
3784 for (i = 0; i < dinfo->cfg.nummaps; i++)
3785 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3786 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3789 * Some drivers apparently write to these registers w/o updating our
3790 * cached copy. No harm happens if we update the copy, so do so here
3791 * so we can restore them. The COMMAND register is modified by the
3792 * bus w/o updating the cache. This should represent the normally
3793 * writable portion of the 'defined' part of type 0 headers. In
3794 * theory we also need to save/restore the PCI capability structures
3795 * we know about, but apart from power we don't know any that are
3798 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3799 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3800 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3801 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3802 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3803 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3804 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3805 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3806 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3807 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3808 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3809 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3810 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3811 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3812 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3815 * don't set the state for display devices, base peripherals and
3816 * memory devices since bad things happen when they are powered down.
3817 * We should (a) have drivers that can easily detach and (b) use
3818 * generic drivers for these devices so that some device actually
3819 * attaches. We need to make sure that when we implement (a) we don't
3820 * power the device down on a reattach.
3822 cls = pci_get_class(dev);
3825 switch (pci_do_power_nodriver)
3827 case 0: /* NO powerdown at all */
3829 case 1: /* Conservative about what to power down */
3830 if (cls == PCIC_STORAGE)
3833 case 2: /* Agressive about what to power down */
3834 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
3835 cls == PCIC_BASEPERIPH)
3838 case 3: /* Power down everything */
3842 * PCI spec says we can only go into D3 state from D0 state.
3843 * Transition from D[12] into D0 before going to D3 state.
3845 ps = pci_get_powerstate(dev);
3846 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
3847 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3848 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
3849 pci_set_powerstate(dev, PCI_POWERSTATE_D3);