3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
39 * RealTek 8169S/8110S/8168/8111/8101E PCI NIC driver
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Networking Software Engineer
47 * This driver is designed to support RealTek's next generation of
48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
49 * seven devices in this family: the the RTL8169, the RTL8169S, RTL8110S,
50 * the RTL8168, the RTL8111 and the RTL8101E.
52 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC:
54 * o Descriptor based DMA mechanism. Each descriptor represents
55 * a single packet fragment. Data buffers may be aligned on
60 * o TCP/IP checksum offload for both RX and TX.
62 * o High and normal priority transmit DMA rings.
64 * o VLAN tag insertion and extraction.
66 * o TCP large send (segmentation offload).
72 * o GMII and TBI ports/registers for interfacing with copper
75 * o RX and TX DMA rings can have up to 1024 descriptors.
77 * The 8169 does not have a built-in PHY. Most reference boards use a
78 * Marvell 88E1000 'Alaska' copper gigE PHY. 8169/8110 is _no longer_
81 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
82 * (the 'S' stands for 'single-chip'). These devices have the same
83 * programming API as the older 8169, but also have some vendor-specific
84 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
85 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
87 * This driver takes advantage of the RX and TX checksum offload and
88 * VLAN tag insertion/extraction features. It also implements
89 * interrupt moderation using the timer interrupt registers, which
90 * significantly reduces interrupt load.
95 #include "opt_ifpoll.h"
97 #include <sys/param.h>
99 #include <sys/endian.h>
100 #include <sys/kernel.h>
101 #include <sys/in_cksum.h>
102 #include <sys/interrupt.h>
103 #include <sys/malloc.h>
104 #include <sys/mbuf.h>
105 #include <sys/rman.h>
106 #include <sys/serialize.h>
107 #include <sys/socket.h>
108 #include <sys/sockio.h>
109 #include <sys/sysctl.h>
112 #include <net/ethernet.h>
114 #include <net/ifq_var.h>
115 #include <net/if_arp.h>
116 #include <net/if_dl.h>
117 #include <net/if_media.h>
118 #include <net/if_poll.h>
119 #include <net/if_types.h>
120 #include <net/vlan/if_vlan_var.h>
121 #include <net/vlan/if_vlan_ether.h>
123 #include <netinet/ip.h>
126 #include <bus/pci/pcireg.h>
127 #include <bus/pci/pcivar.h>
129 #include <dev/netif/re/if_rereg.h>
130 #include <dev/netif/re/if_revar.h>
131 #include <dev/netif/re/re.h>
132 #include <dev/netif/re/re_dragonfly.h>
135 * Various supported device vendors/types and their names.
137 static const struct re_type {
142 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
143 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
145 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
146 "RealTek 810x PCIe 10/100baseTX" },
148 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
149 "RealTek 8111/8168 PCIe Gigabit Ethernet" },
151 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168_1,
152 "RealTek 8168 PCIe Gigabit Ethernet" },
156 * This driver now only supports built-in PHYs.
158 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
159 "RealTek 8110/8169 Gigabit Ethernet" },
162 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
163 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
165 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
166 "Corega CG-LAPCIGT Gigabit Ethernet" },
168 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
169 "Linksys EG1032 Gigabit Ethernet" },
171 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
172 "US Robotics 997902 Gigabit Ethernet" },
174 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
175 "TTTech MC322 Gigabit Ethernet" },
180 static int re_probe(device_t);
181 static int re_attach(device_t);
182 static int re_detach(device_t);
183 static int re_suspend(device_t);
184 static int re_resume(device_t);
185 static void re_shutdown(device_t);
187 static int re_allocmem(device_t);
188 static void re_freemem(device_t);
189 static void re_freebufmem(struct re_softc *, int, int);
190 static int re_encap(struct re_softc *, struct mbuf **, int *);
191 static int re_newbuf_std(struct re_softc *, int, int);
193 static int re_newbuf_jumbo(struct re_softc *, int, int);
195 static void re_setup_rxdesc(struct re_softc *, int);
196 static int re_rx_list_init(struct re_softc *);
197 static int re_tx_list_init(struct re_softc *);
198 static int re_rxeof(struct re_softc *);
199 static int re_txeof(struct re_softc *);
200 static int re_tx_collect(struct re_softc *);
201 static void re_intr(void *);
202 static void re_tick(void *);
203 static void re_tick_serialized(void *);
204 static void re_disable_aspm(device_t);
205 static void re_link_up(struct re_softc *);
206 static void re_link_down(struct re_softc *);
208 static void re_start(struct ifnet *, struct ifaltq_subque *);
209 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
210 static void re_init(void *);
211 static void re_stop(struct re_softc *, boolean_t);
212 static void re_watchdog(struct ifnet *);
214 static void re_setup_hw_im(struct re_softc *);
215 static void re_setup_sim_im(struct re_softc *);
216 static void re_disable_hw_im(struct re_softc *);
217 static void re_disable_sim_im(struct re_softc *);
218 static void re_config_imtype(struct re_softc *, int);
219 static void re_setup_intr(struct re_softc *, int, int);
221 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
222 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
223 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
224 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
225 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
227 static int re_jpool_alloc(struct re_softc *);
228 static void re_jpool_free(struct re_softc *);
230 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
231 static void re_jbuf_free(void *);
232 static void re_jbuf_ref(void *);
236 static void re_npoll(struct ifnet *, struct ifpoll_info *);
237 static void re_npoll_compat(struct ifnet *, void *, int);
240 static device_method_t re_methods[] = {
241 /* Device interface */
242 DEVMETHOD(device_probe, re_probe),
243 DEVMETHOD(device_attach, re_attach),
244 DEVMETHOD(device_detach, re_detach),
245 DEVMETHOD(device_suspend, re_suspend),
246 DEVMETHOD(device_resume, re_resume),
247 DEVMETHOD(device_shutdown, re_shutdown),
251 static driver_t re_driver = {
254 sizeof(struct re_softc)
257 static devclass_t re_devclass;
259 DECLARE_DUMMY_MODULE(if_re);
260 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL);
261 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL);
263 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF;
264 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF;
265 static int re_msi_enable = 1;
267 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
268 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
269 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable);
272 re_free_rxchain(struct re_softc *sc)
274 if (sc->re_head != NULL) {
275 m_freem(sc->re_head);
276 sc->re_head = sc->re_tail = NULL;
281 re_probe(device_t dev)
283 const struct re_type *t;
284 uint16_t vendor, product;
286 vendor = pci_get_vendor(dev);
287 product = pci_get_device(dev);
290 * Only attach to rev.3 of the Linksys EG1032 adapter.
291 * Rev.2 is supported by sk(4).
293 if (vendor == PCI_VENDOR_LINKSYS &&
294 product == PCI_PRODUCT_LINKSYS_EG1032 &&
295 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
298 for (t = re_devs; t->re_name != NULL; t++) {
299 if (product == t->re_did && vendor == t->re_vid)
302 if (t->re_name == NULL)
305 device_set_desc(dev, t->re_name);
310 re_allocmem(device_t dev)
312 struct re_softc *sc = device_get_softc(dev);
319 sc->re_ldata.re_tx_mbuf =
320 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
321 M_DEVBUF, M_ZERO | M_WAITOK);
323 sc->re_ldata.re_rx_mbuf =
324 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
325 M_DEVBUF, M_ZERO | M_WAITOK);
327 sc->re_ldata.re_rx_paddr =
328 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
329 M_DEVBUF, M_ZERO | M_WAITOK);
331 sc->re_ldata.re_tx_dmamap =
332 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
333 M_DEVBUF, M_ZERO | M_WAITOK);
335 sc->re_ldata.re_rx_dmamap =
336 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
337 M_DEVBUF, M_ZERO | M_WAITOK);
340 * Allocate the parent bus DMA tag appropriate for PCI.
342 error = bus_dma_tag_create(NULL, /* parent */
343 1, 0, /* alignment, boundary */
344 BUS_SPACE_MAXADDR, /* lowaddr */
345 BUS_SPACE_MAXADDR, /* highaddr */
346 NULL, NULL, /* filter, filterarg */
347 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
349 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
353 device_printf(dev, "could not allocate parent dma tag\n");
357 /* Allocate TX descriptor list. */
358 error = bus_dmamem_coherent(sc->re_parent_tag,
360 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
361 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
364 device_printf(dev, "could not allocate TX ring\n");
367 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag;
368 sc->re_ldata.re_tx_list_map = dmem.dmem_map;
369 sc->re_ldata.re_tx_list = dmem.dmem_addr;
370 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr;
372 /* Allocate RX descriptor list. */
373 error = bus_dmamem_coherent(sc->re_parent_tag,
375 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
376 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
379 device_printf(dev, "could not allocate RX ring\n");
382 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag;
383 sc->re_ldata.re_rx_list_map = dmem.dmem_map;
384 sc->re_ldata.re_rx_list = dmem.dmem_addr;
385 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr;
387 /* Allocate maps for TX mbufs. */
388 error = bus_dma_tag_create(sc->re_parent_tag,
390 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
392 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
393 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
394 &sc->re_ldata.re_tx_mtag);
396 device_printf(dev, "could not allocate TX buf dma tag\n");
400 /* Create DMA maps for TX buffers */
401 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
402 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag,
403 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
404 &sc->re_ldata.re_tx_dmamap[i]);
406 device_printf(dev, "can't create DMA map for TX buf\n");
407 re_freebufmem(sc, i, 0);
412 /* Allocate maps for RX mbufs. */
413 error = bus_dma_tag_create(sc->re_parent_tag,
415 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
417 MCLBYTES, 1, MCLBYTES,
418 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,
419 &sc->re_ldata.re_rx_mtag);
421 device_printf(dev, "could not allocate RX buf dma tag\n");
425 /* Create spare DMA map for RX */
426 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK,
427 &sc->re_ldata.re_rx_spare);
429 device_printf(dev, "can't create spare DMA map for RX\n");
430 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
431 sc->re_ldata.re_rx_mtag = NULL;
435 /* Create DMA maps for RX buffers */
436 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
437 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag,
438 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]);
440 device_printf(dev, "can't create DMA map for RX buf\n");
441 re_freebufmem(sc, sc->re_tx_desc_cnt, i);
446 /* Create jumbo buffer pool for RX if required */
447 if (sc->re_caps & RE_C_CONTIGRX) {
448 error = re_jpool_alloc(sc);
452 /* Disable jumbo frame support */
453 sc->re_maxmtu = ETHERMTU;
461 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
465 /* Destroy all the RX and TX buffer maps */
466 if (sc->re_ldata.re_tx_mtag) {
467 for (i = 0; i < tx_cnt; i++) {
468 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag,
469 sc->re_ldata.re_tx_dmamap[i]);
471 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag);
472 sc->re_ldata.re_tx_mtag = NULL;
475 if (sc->re_ldata.re_rx_mtag) {
476 for (i = 0; i < rx_cnt; i++) {
477 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
478 sc->re_ldata.re_rx_dmamap[i]);
480 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
481 sc->re_ldata.re_rx_spare);
482 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
483 sc->re_ldata.re_rx_mtag = NULL;
488 re_freemem(device_t dev)
490 struct re_softc *sc = device_get_softc(dev);
492 /* Unload and free the RX DMA ring memory and map */
493 if (sc->re_ldata.re_rx_list_tag) {
494 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
495 sc->re_ldata.re_rx_list_map);
496 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
497 sc->re_ldata.re_rx_list,
498 sc->re_ldata.re_rx_list_map);
499 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
502 /* Unload and free the TX DMA ring memory and map */
503 if (sc->re_ldata.re_tx_list_tag) {
504 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
505 sc->re_ldata.re_tx_list_map);
506 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
507 sc->re_ldata.re_tx_list,
508 sc->re_ldata.re_tx_list_map);
509 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
512 /* Free RX/TX buf DMA stuffs */
513 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
515 /* Unload and free the stats buffer and map */
516 if (sc->re_ldata.re_stag) {
517 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap);
518 bus_dmamem_free(sc->re_ldata.re_stag,
519 sc->re_ldata.re_stats,
520 sc->re_ldata.re_smap);
521 bus_dma_tag_destroy(sc->re_ldata.re_stag);
524 if (sc->re_caps & RE_C_CONTIGRX)
527 if (sc->re_parent_tag)
528 bus_dma_tag_destroy(sc->re_parent_tag);
530 if (sc->re_ldata.re_tx_mbuf != NULL)
531 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
532 if (sc->re_ldata.re_rx_mbuf != NULL)
533 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
534 if (sc->re_ldata.re_rx_paddr != NULL)
535 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
536 if (sc->re_ldata.re_tx_dmamap != NULL)
537 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
538 if (sc->re_ldata.re_rx_dmamap != NULL)
539 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
543 re_is_faste(struct re_softc *sc)
545 if (pci_get_vendor(sc->dev) == PCI_VENDOR_REALTEK) {
546 switch (sc->re_device_id) {
547 case PCI_PRODUCT_REALTEK_RT8169:
548 case PCI_PRODUCT_REALTEK_RT8169SC:
549 case PCI_PRODUCT_REALTEK_RT8168:
550 case PCI_PRODUCT_REALTEK_RT8168_1:
561 * Attach the interface. Allocate softc structures, do ifmedia
562 * setup and ethernet/BPF attach.
565 re_attach(device_t dev)
567 struct re_softc *sc = device_get_softc(dev);
569 struct sysctl_ctx_list *ctx;
570 struct sysctl_oid *tree;
571 uint8_t eaddr[ETHER_ADDR_LEN];
572 int error = 0, qlen, msi_enable;
575 callout_init_mp(&sc->re_timer);
577 sc->re_device_id = pci_get_device(dev);
578 sc->re_unit = device_get_unit(dev);
579 ifmedia_init(&sc->media, IFM_IMASK, rtl_ifmedia_upd, rtl_ifmedia_sts);
581 sc->re_caps = RE_C_HWIM;
583 sc->re_rx_desc_cnt = re_rx_desc_count;
584 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
585 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
587 sc->re_tx_desc_cnt = re_tx_desc_count;
588 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
589 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
591 qlen = RE_IFQ_MAXLEN;
592 if (sc->re_tx_desc_cnt > qlen)
593 qlen = sc->re_tx_desc_cnt;
595 sc->re_rxbuf_size = MCLBYTES;
596 sc->re_newbuf = re_newbuf_std;
599 * Hardware interrupt moderation settings.
600 * XXX does not seem correct, undocumented.
602 sc->re_tx_time = 5; /* 125us */
603 sc->re_rx_time = 2; /* 50us */
605 /* Simulated interrupt moderation setting. */
606 sc->re_sim_time = 150; /* 150us */
608 /* Use simulated interrupt moderation by default. */
609 sc->re_imtype = RE_IMTYPE_SIM;
610 re_config_imtype(sc, sc->re_imtype);
612 ctx = device_get_sysctl_ctx(dev);
613 tree = device_get_sysctl_tree(dev);
614 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
615 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
617 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
618 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
620 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "sim_time",
621 CTLTYPE_INT | CTLFLAG_RW,
622 sc, 0, re_sysctl_simtime, "I",
623 "Simulated interrupt moderation time (usec).");
624 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "imtype",
625 CTLTYPE_INT | CTLFLAG_RW,
626 sc, 0, re_sysctl_imtype, "I",
627 "Interrupt moderation type -- "
628 "0:disable, 1:simulated, "
629 "2:hardware(if supported)");
630 if (sc->re_caps & RE_C_HWIM) {
631 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
632 OID_AUTO, "hw_rxtime",
633 CTLTYPE_INT | CTLFLAG_RW,
634 sc, 0, re_sysctl_rxtime, "I",
635 "Hardware interrupt moderation time "
637 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
638 OID_AUTO, "hw_txtime",
639 CTLTYPE_INT | CTLFLAG_RW,
640 sc, 0, re_sysctl_txtime, "I",
641 "Hardware interrupt moderation time "
647 * Handle power management nonsense.
650 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
651 uint32_t membase, irq;
653 /* Save important PCI config data. */
654 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
655 irq = pci_read_config(dev, PCIR_INTLINE, 4);
657 /* Reset the power state. */
658 device_printf(dev, "chip is in D%d power mode "
659 "-- setting to D0\n", pci_get_powerstate(dev));
661 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
663 /* Restore PCI config data. */
664 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
665 pci_write_config(dev, PCIR_INTLINE, irq, 4);
669 * Map control/status registers.
671 pci_enable_busmaster(dev);
673 if (pci_is_pcie(dev)) {
674 sc->re_res_rid = PCIR_BAR(2);
675 sc->re_res_type = SYS_RES_MEMORY;
677 sc->re_res_rid = PCIR_BAR(0);
678 sc->re_res_type = SYS_RES_IOPORT;
680 sc->re_res = bus_alloc_resource_any(dev, sc->re_res_type,
681 &sc->re_res_rid, RF_ACTIVE);
682 if (sc->re_res == NULL) {
683 device_printf(dev, "couldn't map IO\n");
688 sc->re_btag = rman_get_bustag(sc->re_res);
689 sc->re_bhandle = rman_get_bushandle(sc->re_res);
691 error = rtl_check_mac_version(sc);
693 device_printf(dev, "check mac version failed\n");
697 rtl_init_software_variable(sc);
698 if (pci_is_pcie(dev))
699 sc->re_if_flags |= RL_FLAG_PCIE;
701 sc->re_if_flags &= ~RL_FLAG_PCIE;
702 device_printf(dev, "MAC version 0x%08x, MACFG %u%s%s%s\n",
703 (CSR_READ_4(sc, RE_TXCFG) & 0xFCF00000), sc->re_type,
704 sc->re_coalesce_tx_pkt ? ", software TX defrag" : "",
705 sc->re_pad_runt ? ", pad runt" : "",
706 sc->re_hw_enable_msi_msix ? ", support MSI" : "");
711 if (pci_is_pcie(dev) && sc->re_hw_enable_msi_msix)
712 msi_enable = re_msi_enable;
715 sc->re_irq_type = pci_alloc_1intr(dev, msi_enable,
716 &sc->re_irq_rid, &irq_flags);
718 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid,
720 if (sc->re_irq == NULL) {
721 device_printf(dev, "couldn't map interrupt\n");
727 re_disable_aspm(dev);
732 /* Reset the adapter. */
735 rtl_get_hw_mac_address(sc, eaddr);
736 if (sc->re_type == MACFG_3) /* Change PCI Latency time*/
737 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
739 /* Allocate DMA stuffs */
740 error = re_allocmem(dev);
744 if (pci_is_pcie(dev)) {
745 sc->re_bus_speed = 125;
749 cfg2 = CSR_READ_1(sc, RE_CFG2);
750 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
751 case RE_CFG2_PCICLK_33MHZ:
752 sc->re_bus_speed = 33;
754 case RE_CFG2_PCICLK_66MHZ:
755 sc->re_bus_speed = 66;
758 device_printf(dev, "unknown bus speed, assume 33MHz\n");
759 sc->re_bus_speed = 33;
763 device_printf(dev, "bus speed %dMHz\n", sc->re_bus_speed);
765 rtl_phy_power_up(sc);
766 rtl_hw_phy_config(sc);
769 /* TODO: jumbo frame */
770 CSR_WRITE_2(sc, RE_RxMaxSize, sc->re_rxbuf_size);
772 /* Enable hardware checksum if available. */
776 ifp = &sc->arpcom.ac_if;
778 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
779 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
780 ifp->if_ioctl = re_ioctl;
781 ifp->if_start = re_start;
783 ifp->if_npoll = re_npoll;
785 ifp->if_watchdog = re_watchdog;
786 ifp->if_init = re_init;
787 if (!re_is_faste(sc))
788 ifp->if_baudrate = 1000000000;
790 ifp->if_baudrate = 100000000;
791 ifp->if_nmbclusters = sc->re_rx_desc_cnt;
792 ifq_set_maxlen(&ifp->if_snd, qlen);
793 ifq_set_ready(&ifp->if_snd);
795 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
796 IFCAP_RXCSUM | IFCAP_TXCSUM;
797 ifp->if_capenable = ifp->if_capabilities;
798 /* NOTE: if_hwassist will be setup after the interface is up. */
801 * Call MI attach routine.
803 ether_ifattach(ifp, eaddr, NULL);
805 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq));
808 ifpoll_compat_setup(&sc->re_npoll, ctx, (struct sysctl_oid *)tree,
809 device_get_unit(dev), ifp->if_serializer);
812 /* Hook interrupt last to avoid having to lock softc */
813 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE | INTR_HIFREQ,
814 re_intr, sc, &sc->re_intrhand, ifp->if_serializer);
816 device_printf(dev, "couldn't set up irq\n");
821 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
822 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
823 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
824 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
825 if (!re_is_faste(sc)) {
826 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
829 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
830 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
831 rtl_ifmedia_upd(ifp);
841 * Shutdown hardware and free up resources. This can be called any
842 * time after the mutex has been initialized. It is called in both
843 * the error case in attach and the normal detach case so it needs
844 * to be careful about only freeing resources that have actually been
848 re_detach(device_t dev)
850 struct re_softc *sc = device_get_softc(dev);
851 struct ifnet *ifp = &sc->arpcom.ac_if;
853 /* These should only be active if attach succeeded */
854 if (device_is_attached(dev)) {
855 lwkt_serialize_enter(ifp->if_serializer);
857 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
858 lwkt_serialize_exit(ifp->if_serializer);
862 ifmedia_removeall(&sc->media);
865 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid,
868 if (sc->re_irq_type == PCI_INTR_TYPE_MSI)
869 pci_release_msi(dev);
872 bus_release_resource(dev, sc->re_res_type, sc->re_res_rid,
877 /* Free DMA stuffs */
884 re_setup_rxdesc(struct re_softc *sc, int idx)
890 paddr = sc->re_ldata.re_rx_paddr[idx];
891 d = &sc->re_ldata.re_rx_list[idx];
893 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
894 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
896 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
897 if (idx == (sc->re_rx_desc_cnt - 1))
898 cmdstat |= RE_RDESC_CMD_EOR;
899 d->re_cmdstat = htole32(cmdstat);
903 re_newbuf_std(struct re_softc *sc, int idx, int init)
905 bus_dma_segment_t seg;
910 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
915 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
921 m->m_len = m->m_pkthdr.len = MCLBYTES;
925 * re(4) chips need address of the receive buffer to be 8-byte
926 * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
929 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag,
930 sc->re_ldata.re_rx_spare, m,
931 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
935 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
943 bus_dmamap_sync(sc->re_ldata.re_rx_mtag,
944 sc->re_ldata.re_rx_dmamap[idx],
945 BUS_DMASYNC_POSTREAD);
946 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
947 sc->re_ldata.re_rx_dmamap[idx]);
949 sc->re_ldata.re_rx_mbuf[idx] = m;
950 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
952 map = sc->re_ldata.re_rx_dmamap[idx];
953 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
954 sc->re_ldata.re_rx_spare = map;
956 re_setup_rxdesc(sc, idx);
962 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
965 struct re_jbuf *jbuf;
968 MGETHDR(m, init ? M_WAITOK : M_NOWAIT, MT_DATA);
972 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
979 jbuf = re_jbuf_alloc(sc);
985 if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
992 m->m_ext.ext_arg = jbuf;
993 m->m_ext.ext_buf = jbuf->re_buf;
994 m->m_ext.ext_free = re_jbuf_free;
995 m->m_ext.ext_ref = re_jbuf_ref;
996 m->m_ext.ext_size = sc->re_rxbuf_size;
998 m->m_data = m->m_ext.ext_buf;
1000 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1004 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1005 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1008 sc->re_ldata.re_rx_mbuf[idx] = m;
1009 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1011 re_setup_rxdesc(sc, idx);
1014 #endif /* RE_JUMBO */
1017 re_tx_list_init(struct re_softc *sc)
1019 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1021 sc->re_ldata.re_tx_prodidx = 0;
1022 sc->re_ldata.re_tx_considx = 0;
1023 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1029 re_rx_list_init(struct re_softc *sc)
1033 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1035 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1036 error = sc->re_newbuf(sc, i, 1);
1041 sc->re_ldata.re_rx_prodidx = 0;
1042 sc->re_head = sc->re_tail = NULL;
1047 #define RE_IP4_PACKET 0x1
1048 #define RE_TCP_PACKET 0x2
1049 #define RE_UDP_PACKET 0x4
1051 static __inline uint8_t
1052 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1054 uint8_t packet_type = 0;
1056 if (sc->re_if_flags & RL_FLAG_DESCV2) {
1057 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1058 packet_type |= RE_IP4_PACKET;
1060 if (rxstat & RE_RDESC_STAT_PROTOID)
1061 packet_type |= RE_IP4_PACKET;
1063 if (RE_TCPPKT(rxstat))
1064 packet_type |= RE_TCP_PACKET;
1065 else if (RE_UDPPKT(rxstat))
1066 packet_type |= RE_UDP_PACKET;
1071 * RX handler for C+ and 8169. For the gigE chips, we support
1072 * the reception of jumbo frames that have been fragmented
1073 * across multiple 2K mbuf cluster buffers.
1076 re_rxeof(struct re_softc *sc)
1078 struct ifnet *ifp = &sc->arpcom.ac_if;
1080 struct re_desc *cur_rx;
1081 uint32_t rxstat, rxctrl;
1082 int i, total_len, rx = 0;
1084 for (i = sc->re_ldata.re_rx_prodidx;
1085 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1086 cur_rx = &sc->re_ldata.re_rx_list[i];
1087 m = sc->re_ldata.re_rx_mbuf[i];
1088 total_len = RE_RXBYTES(cur_rx);
1089 rxstat = le32toh(cur_rx->re_cmdstat);
1090 rxctrl = le32toh(cur_rx->re_control);
1095 if (sc->re_flags & RE_F_USE_JPOOL)
1096 KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1099 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1100 if (sc->re_flags & RE_F_DROP_RXFRAG) {
1101 re_setup_rxdesc(sc, i);
1105 if (sc->re_newbuf(sc, i, 0)) {
1106 /* Drop upcoming fragments */
1107 sc->re_flags |= RE_F_DROP_RXFRAG;
1111 m->m_len = MCLBYTES;
1112 if (sc->re_head == NULL) {
1113 sc->re_head = sc->re_tail = m;
1115 sc->re_tail->m_next = m;
1119 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1121 * Last fragment of a multi-fragment packet.
1123 * Since error already happened, this fragment
1124 * must be dropped as well as the fragment chain.
1126 re_setup_rxdesc(sc, i);
1127 re_free_rxchain(sc);
1128 sc->re_flags &= ~RE_F_DROP_RXFRAG;
1133 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1134 IFNET_STAT_INC(ifp, ierrors, 1);
1136 * If this is part of a multi-fragment packet,
1137 * discard all the pieces.
1139 re_free_rxchain(sc);
1140 re_setup_rxdesc(sc, i);
1145 * If allocating a replacement mbuf fails,
1146 * reload the current one.
1149 if (sc->re_newbuf(sc, i, 0)) {
1150 IFNET_STAT_INC(ifp, ierrors, 1);
1154 if (sc->re_head != NULL) {
1155 m->m_len = total_len % MCLBYTES;
1157 * Special case: if there's 4 bytes or less
1158 * in this buffer, the mbuf can be discarded:
1159 * the last 4 bytes is the CRC, which we don't
1160 * care about anyway.
1162 if (m->m_len <= ETHER_CRC_LEN) {
1163 sc->re_tail->m_len -=
1164 (ETHER_CRC_LEN - m->m_len);
1167 m->m_len -= ETHER_CRC_LEN;
1168 sc->re_tail->m_next = m;
1171 sc->re_head = sc->re_tail = NULL;
1172 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1174 m->m_pkthdr.len = m->m_len =
1175 (total_len - ETHER_CRC_LEN);
1178 IFNET_STAT_INC(ifp, ipackets, 1);
1179 m->m_pkthdr.rcvif = ifp;
1181 /* Do RX checksumming if enabled */
1183 if (ifp->if_capenable & IFCAP_RXCSUM) {
1184 uint8_t packet_type;
1186 packet_type = re_packet_type(sc, rxstat, rxctrl);
1188 /* Check IP header checksum */
1189 if (packet_type & RE_IP4_PACKET) {
1190 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1191 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1192 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1195 /* Check TCP/UDP checksum */
1196 if (((packet_type & RE_TCP_PACKET) &&
1197 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1198 ((packet_type & RE_UDP_PACKET) &&
1199 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
1200 m->m_pkthdr.csum_flags |=
1201 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1202 CSUM_FRAG_NOT_CHECKED;
1203 m->m_pkthdr.csum_data = 0xffff;
1207 if (rxctrl & RE_RDESC_CTL_HASTAG) {
1208 m->m_flags |= M_VLANTAG;
1209 m->m_pkthdr.ether_vlantag =
1210 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
1212 ifp->if_input(ifp, m, NULL, -1);
1215 sc->re_ldata.re_rx_prodidx = i;
1220 #undef RE_IP4_PACKET
1221 #undef RE_TCP_PACKET
1222 #undef RE_UDP_PACKET
1225 re_tx_collect(struct re_softc *sc)
1227 struct ifnet *ifp = &sc->arpcom.ac_if;
1231 for (idx = sc->re_ldata.re_tx_considx;
1232 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
1233 RE_TXDESC_INC(sc, idx)) {
1234 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1235 if (txstat & RE_TDESC_CMD_OWN)
1240 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1243 * We only stash mbufs in the last descriptor
1244 * in a fragment chain, which also happens to
1245 * be the only place where the TX status bits
1248 if (txstat & RE_TDESC_CMD_EOF) {
1249 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
1250 sc->re_ldata.re_tx_dmamap[idx]);
1251 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1252 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1253 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1254 RE_TDESC_STAT_COLCNT))
1255 IFNET_STAT_INC(ifp, collisions, 1);
1256 if (txstat & RE_TDESC_STAT_TXERRSUM)
1257 IFNET_STAT_INC(ifp, oerrors, 1);
1259 IFNET_STAT_INC(ifp, opackets, 1);
1261 sc->re_ldata.re_tx_free++;
1263 sc->re_ldata.re_tx_considx = idx;
1269 re_txeof(struct re_softc *sc)
1271 struct ifnet *ifp = &sc->arpcom.ac_if;
1274 tx = re_tx_collect(sc);
1276 /* There is enough free TX descs */
1277 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
1278 ifq_clr_oactive(&ifp->if_snd);
1281 * Some chips will ignore a second TX request issued while an
1282 * existing transmission is in progress. If the transmitter goes
1283 * idle but there are still packets waiting to be sent, we need
1284 * to restart the channel here to flush them out. This only seems
1285 * to be required with the PCIe devices.
1287 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
1288 CSR_WRITE_1(sc, RE_TPPOLL, RE_NPQ);
1298 struct re_softc *sc = xsc;
1300 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1301 re_tick_serialized(xsc);
1302 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1306 re_tick_serialized(void *xsc)
1308 struct re_softc *sc = xsc;
1309 struct ifnet *ifp = &sc->arpcom.ac_if;
1311 ASSERT_SERIALIZED(ifp->if_serializer);
1313 if ((ifp->if_flags & IFF_RUNNING) == 0)
1316 if (rtl_link_ok(sc)) {
1317 if ((sc->re_flags & RE_F_LINKED) == 0)
1319 } else if (sc->re_flags & RE_F_LINKED) {
1322 callout_reset(&sc->re_timer, hz, re_tick, sc);
1325 #ifdef IFPOLL_ENABLE
1328 re_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1330 struct re_softc *sc = ifp->if_softc;
1332 ASSERT_SERIALIZED(ifp->if_serializer);
1334 if (sc->re_npoll.ifpc_stcount-- == 0) {
1337 sc->re_npoll.ifpc_stcount = sc->re_npoll.ifpc_stfrac;
1339 status = CSR_READ_2(sc, RE_ISR);
1341 CSR_WRITE_2(sc, RE_ISR, status);
1344 * XXX check behaviour on receiver stalls.
1347 if (status & RE_ISR_SYSTEM_ERR) {
1355 sc->rxcycles = count;
1359 if (!ifq_is_empty(&ifp->if_snd))
1364 re_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1366 struct re_softc *sc = ifp->if_softc;
1368 ASSERT_SERIALIZED(ifp->if_serializer);
1371 int cpuid = sc->re_npoll.ifpc_cpuid;
1373 info->ifpi_rx[cpuid].poll_func = re_npoll_compat;
1374 info->ifpi_rx[cpuid].arg = NULL;
1375 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1377 if (ifp->if_flags & IFF_RUNNING)
1378 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
1379 ifq_set_cpuid(&ifp->if_snd, cpuid);
1381 if (ifp->if_flags & IFF_RUNNING)
1382 re_setup_intr(sc, 1, sc->re_imtype);
1383 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq));
1386 #endif /* IFPOLL_ENABLE */
1391 struct re_softc *sc = arg;
1392 struct ifnet *ifp = &sc->arpcom.ac_if;
1396 ASSERT_SERIALIZED(ifp->if_serializer);
1398 if ((sc->re_flags & RE_F_SUSPENDED) ||
1399 (ifp->if_flags & IFF_RUNNING) == 0)
1402 /* Disable interrupts. */
1403 CSR_WRITE_2(sc, RE_IMR, 0);
1405 status = CSR_READ_2(sc, RE_ISR);
1409 CSR_WRITE_2(sc, RE_ISR, status);
1410 if (status & sc->re_intrs) {
1411 if (status & RE_ISR_SYSTEM_ERR) {
1417 proc |= re_rxeof(sc);
1418 proc |= re_txeof(sc);
1421 if (sc->re_imtype == RE_IMTYPE_SIM) {
1422 if ((sc->re_flags & RE_F_TIMER_INTR)) {
1425 * Nothing needs to be processed, fallback
1426 * to use TX/RX interrupts.
1428 * NOTE: This will re-enable interrupts.
1430 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
1433 * Recollect, mainly to avoid the possible
1434 * race introduced by changing interrupt
1440 /* Re-enable interrupts. */
1441 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1442 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
1446 * Assume that using simulated interrupt moderation
1447 * (hardware timer based) could reduce the interript
1450 * NOTE: This will re-enable interrupts.
1452 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
1454 /* Re-enable interrupts. */
1455 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1458 status = CSR_READ_2(sc, RE_ISR);
1459 if (status & sc->re_intrs) {
1460 if (!ifq_is_empty(&ifp->if_snd))
1462 /* NOTE: Interrupts are still disabled. */
1465 /* Re-enable interrupts. */
1466 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1469 if (!ifq_is_empty(&ifp->if_snd))
1474 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
1476 struct mbuf *m = *m_head;
1477 bus_dma_segment_t segs[RE_MAXSEGS];
1479 int error, maxsegs, idx, i, nsegs;
1480 struct re_desc *d, *tx_ring;
1481 uint32_t cmd_csum, ctl_csum, vlantag;
1483 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
1484 ("not enough free TX desc"));
1486 if (sc->re_coalesce_tx_pkt && m->m_pkthdr.len != m->m_len) {
1489 m_new = m_defrag(m, M_NOWAIT);
1490 if (m_new == NULL) {
1494 *m_head = m = m_new;
1495 if (m->m_pkthdr.len != m->m_len) {
1496 /* Still not configuous; give up. */
1503 map = sc->re_ldata.re_tx_dmamap[*idx0];
1506 * Set up checksum offload. Note: checksum offload bits must
1507 * appear in all descriptors of a multi-descriptor transmit
1508 * attempt. (This is according to testing done with an 8169
1509 * chip. I'm not sure if this is a requirement or a bug.)
1511 cmd_csum = ctl_csum = 0;
1512 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1513 cmd_csum |= RE_TDESC_CMD_IPCSUM;
1514 ctl_csum |= RE_TDESC_CTL_IPCSUM;
1516 if (m->m_pkthdr.csum_flags & CSUM_TCP) {
1517 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
1518 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
1520 if (m->m_pkthdr.csum_flags & CSUM_UDP) {
1521 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
1522 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
1525 /* For version2 descriptor, csum flags are set on re_control */
1526 if (sc->re_if_flags & RL_FLAG_DESCV2)
1531 if (sc->re_pad_runt) {
1533 * With some of the RealTek chips, using the checksum offload
1534 * support in conjunction with the autopadding feature results
1535 * in the transmission of corrupt frames. For example, if we
1536 * need to send a really small IP fragment that's less than 60
1537 * bytes in size, and IP header checksumming is enabled, the
1538 * resulting ethernet frame that appears on the wire will
1539 * have garbled payload. To work around this, if TX checksum
1540 * offload is enabled, we always manually pad short frames out
1541 * to the minimum ethernet frame size.
1543 * Note: this appears unnecessary for TCP, and doing it for TCP
1544 * with PCIe adapters seems to result in bad checksums.
1546 if ((m->m_pkthdr.csum_flags &
1547 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
1548 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
1549 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
1550 error = m_devpad(m, RE_MIN_FRAMELEN);
1557 if (m->m_flags & M_VLANTAG) {
1558 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
1559 RE_TDESC_CTL_INSTAG;
1562 maxsegs = sc->re_ldata.re_tx_free;
1563 if (maxsegs > RE_MAXSEGS)
1564 maxsegs = RE_MAXSEGS;
1566 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map,
1567 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1572 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE);
1575 * Map the segment array into descriptors. We also keep track
1576 * of the end of the ring and set the end-of-ring bits as needed,
1577 * and we set the ownership bits in all except the very first
1578 * descriptor, whose ownership bits will be turned on later.
1580 tx_ring = sc->re_ldata.re_tx_list;
1588 cmdstat = segs[i].ds_len;
1589 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
1590 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
1592 cmdstat |= RE_TDESC_CMD_SOF;
1594 cmdstat |= RE_TDESC_CMD_OWN;
1595 if (idx == (sc->re_tx_desc_cnt - 1))
1596 cmdstat |= RE_TDESC_CMD_EOR;
1597 d->re_cmdstat = htole32(cmdstat | cmd_csum);
1598 d->re_control = htole32(ctl_csum | vlantag);
1603 RE_TXDESC_INC(sc, idx);
1605 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
1607 /* Transfer ownership of packet to the chip. */
1608 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
1610 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
1613 * Insure that the map for this transmission
1614 * is placed at the array index of the last descriptor
1617 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
1618 sc->re_ldata.re_tx_dmamap[idx] = map;
1620 sc->re_ldata.re_tx_mbuf[idx] = m;
1621 sc->re_ldata.re_tx_free -= nsegs;
1623 RE_TXDESC_INC(sc, idx);
1634 * Main transmit routine for C+ and gigE NICs.
1638 re_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1640 struct re_softc *sc = ifp->if_softc;
1641 struct mbuf *m_head;
1642 int idx, need_trans, oactive, error;
1644 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1645 ASSERT_SERIALIZED(ifp->if_serializer);
1647 if ((sc->re_flags & RE_F_LINKED) == 0) {
1648 ifq_purge(&ifp->if_snd);
1652 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1655 idx = sc->re_ldata.re_tx_prodidx;
1659 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1660 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
1662 if (re_tx_collect(sc)) {
1667 ifq_set_oactive(&ifp->if_snd);
1671 m_head = ifq_dequeue(&ifp->if_snd);
1675 error = re_encap(sc, &m_head, &idx);
1677 /* m_head is freed by re_encap(), if we reach here */
1678 IFNET_STAT_INC(ifp, oerrors, 1);
1680 if (error == EFBIG && !oactive) {
1681 if (re_tx_collect(sc)) {
1686 ifq_set_oactive(&ifp->if_snd);
1694 * If there's a BPF listener, bounce a copy of this frame
1697 ETHER_BPF_MTAP(ifp, m_head);
1701 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible
1702 * for OACTIVE to not be properly set when we also do not
1703 * have sufficient free tx descriptors, leaving packet in
1704 * ifp->if_snd. This can cause if_start_dispatch() to loop
1705 * infinitely so make sure OACTIVE is set properly.
1707 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
1708 if (!ifq_is_oactive(&ifp->if_snd)) {
1710 if_printf(ifp, "Debug: OACTIVE was not set when "
1711 "re_tx_free was below minimum!\n");
1713 ifq_set_oactive(&ifp->if_snd);
1719 sc->re_ldata.re_tx_prodidx = idx;
1722 * RealTek put the TX poll request register in a different
1723 * location on the 8169 gigE chip. I don't know why.
1725 CSR_WRITE_1(sc, RE_TPPOLL, RE_NPQ);
1728 * Set a timeout in case the chip goes out to lunch.
1734 re_link_up(struct re_softc *sc)
1736 struct ifnet *ifp = &sc->arpcom.ac_if;
1739 ASSERT_SERIALIZED(ifp->if_serializer);
1741 rtl_link_on_patch(sc);
1745 error = re_rx_list_init(sc);
1750 error = re_tx_list_init(sc);
1757 * Load the addresses of the RX and TX lists into the chip.
1759 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
1760 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
1761 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
1762 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
1764 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
1765 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
1766 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
1767 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
1771 #ifdef IFPOLL_ENABLE
1773 * Disable interrupts if we are polling.
1775 if (ifp->if_flags & IFF_NPOLLING)
1776 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
1777 else /* otherwise ... */
1778 #endif /* IFPOLL_ENABLE */
1780 * Enable interrupts.
1782 re_setup_intr(sc, 1, sc->re_imtype);
1783 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
1785 sc->re_flags |= RE_F_LINKED;
1786 ifp->if_link_state = LINK_STATE_UP;
1787 if_link_state_change(ifp);
1790 if_printf(ifp, "link UP\n");
1792 if (!ifq_is_empty(&ifp->if_snd))
1797 re_link_down(struct re_softc *sc)
1799 struct ifnet *ifp = &sc->arpcom.ac_if;
1801 /* NOTE: re_stop() will reset RE_F_LINKED. */
1802 ifp->if_link_state = LINK_STATE_DOWN;
1803 if_link_state_change(ifp);
1806 rtl_ifmedia_upd(ifp);
1809 if_printf(ifp, "link DOWN\n");
1815 struct re_softc *sc = xsc;
1816 struct ifnet *ifp = &sc->arpcom.ac_if;
1818 ASSERT_SERIALIZED(ifp->if_serializer);
1821 if (rtl_link_ok(sc)) {
1823 if_printf(ifp, "link is UP in if_init\n");
1827 ifp->if_flags |= IFF_RUNNING;
1828 ifq_clr_oactive(&ifp->if_snd);
1830 callout_reset(&sc->re_timer, hz, re_tick, sc);
1834 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1836 struct re_softc *sc = ifp->if_softc;
1837 struct ifreq *ifr = (struct ifreq *)data;
1838 int error = 0, mask;
1840 ASSERT_SERIALIZED(ifp->if_serializer);
1845 if (ifr->ifr_mtu > sc->re_maxmtu) {
1847 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1848 ifp->if_mtu = ifr->ifr_mtu;
1849 if (ifp->if_flags & IFF_RUNNING)
1858 if (ifp->if_flags & IFF_UP) {
1859 if (ifp->if_flags & IFF_RUNNING) {
1860 if ((ifp->if_flags ^ sc->re_saved_ifflags) &
1861 (IFF_PROMISC | IFF_ALLMULTI))
1862 rtl_set_rx_packet_filter(sc);
1866 } else if (ifp->if_flags & IFF_RUNNING) {
1869 sc->re_saved_ifflags = ifp->if_flags;
1874 rtl_set_rx_packet_filter(sc);
1879 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1883 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
1884 ifp->if_capabilities;
1885 ifp->if_capenable ^= mask;
1887 /* NOTE: re_init will setup if_hwassist. */
1888 ifp->if_hwassist = 0;
1890 /* Setup flags for the backend. */
1891 if (ifp->if_capenable & IFCAP_RXCSUM)
1892 sc->re_rx_cstag = 1;
1894 sc->re_rx_cstag = 0;
1895 if (ifp->if_capenable & IFCAP_TXCSUM)
1896 sc->re_tx_cstag = 1;
1898 sc->re_tx_cstag = 0;
1900 if (mask && (ifp->if_flags & IFF_RUNNING))
1905 error = ether_ioctl(ifp, command, data);
1912 re_watchdog(struct ifnet *ifp)
1914 struct re_softc *sc = ifp->if_softc;
1916 ASSERT_SERIALIZED(ifp->if_serializer);
1918 IFNET_STAT_INC(ifp, oerrors, 1);
1923 if (sc->re_ldata.re_tx_free != sc->re_tx_desc_cnt) {
1924 if_printf(ifp, "watchdog timeout, txd free %d\n",
1925 sc->re_ldata.re_tx_free);
1932 * Stop the adapter and free any mbufs allocated to the
1936 re_stop(struct re_softc *sc, boolean_t full_stop)
1938 struct ifnet *ifp = &sc->arpcom.ac_if;
1941 ASSERT_SERIALIZED(ifp->if_serializer);
1943 /* Stop the adapter. */
1948 callout_stop(&sc->re_timer);
1949 ifp->if_flags &= ~IFF_RUNNING;
1951 ifq_clr_oactive(&ifp->if_snd);
1952 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
1954 re_free_rxchain(sc);
1956 /* Free the TX list buffers. */
1957 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1958 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
1959 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
1960 sc->re_ldata.re_tx_dmamap[i]);
1961 m_freem(sc->re_ldata.re_tx_mbuf[i]);
1962 sc->re_ldata.re_tx_mbuf[i] = NULL;
1966 /* Free the RX list buffers. */
1967 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1968 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
1969 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
1970 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1971 sc->re_ldata.re_rx_dmamap[i]);
1973 m_freem(sc->re_ldata.re_rx_mbuf[i]);
1974 sc->re_ldata.re_rx_mbuf[i] = NULL;
1980 * Device suspend routine. Stop the interface and save some PCI
1981 * settings in case the BIOS doesn't restore them properly on
1985 re_suspend(device_t dev)
1987 #ifndef BURN_BRIDGES
1990 struct re_softc *sc = device_get_softc(dev);
1991 struct ifnet *ifp = &sc->arpcom.ac_if;
1993 lwkt_serialize_enter(ifp->if_serializer);
1997 #ifndef BURN_BRIDGES
1998 for (i = 0; i < 5; i++)
1999 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2000 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2001 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2002 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2003 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2006 sc->re_flags |= RE_F_SUSPENDED;
2008 lwkt_serialize_exit(ifp->if_serializer);
2014 * Device resume routine. Restore some PCI settings in case the BIOS
2015 * doesn't, re-enable busmastering, and restart the interface if
2019 re_resume(device_t dev)
2021 struct re_softc *sc = device_get_softc(dev);
2022 struct ifnet *ifp = &sc->arpcom.ac_if;
2023 #ifndef BURN_BRIDGES
2027 lwkt_serialize_enter(ifp->if_serializer);
2029 #ifndef BURN_BRIDGES
2030 /* better way to do this? */
2031 for (i = 0; i < 5; i++)
2032 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2033 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2034 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2035 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2036 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2038 /* reenable busmastering */
2039 pci_enable_busmaster(dev);
2040 pci_enable_io(dev, SYS_RES_IOPORT);
2043 /* reinitialize interface if necessary */
2044 if (ifp->if_flags & IFF_UP)
2047 sc->re_flags &= ~RE_F_SUSPENDED;
2049 lwkt_serialize_exit(ifp->if_serializer);
2055 * Stop all chip I/O so that the kernel's probe routines don't
2056 * get confused by errant DMAs when rebooting.
2059 re_shutdown(device_t dev)
2061 struct re_softc *sc = device_get_softc(dev);
2062 struct ifnet *ifp = &sc->arpcom.ac_if;
2064 lwkt_serialize_enter(ifp->if_serializer);
2067 rtl_phy_power_down(sc);
2068 lwkt_serialize_exit(ifp->if_serializer);
2072 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
2074 struct re_softc *sc = arg1;
2076 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
2080 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
2082 struct re_softc *sc = arg1;
2084 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
2088 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
2090 struct re_softc *sc = arg1;
2091 struct ifnet *ifp = &sc->arpcom.ac_if;
2094 lwkt_serialize_enter(ifp->if_serializer);
2097 error = sysctl_handle_int(oidp, &v, 0, req);
2098 if (error || req->newptr == NULL)
2109 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) ==
2110 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
2114 lwkt_serialize_exit(ifp->if_serializer);
2119 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
2121 struct re_softc *sc = arg1;
2122 struct ifnet *ifp = &sc->arpcom.ac_if;
2125 lwkt_serialize_enter(ifp->if_serializer);
2127 v = sc->re_sim_time;
2128 error = sysctl_handle_int(oidp, &v, 0, req);
2129 if (error || req->newptr == NULL)
2137 if (v != sc->re_sim_time) {
2138 sc->re_sim_time = v;
2140 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) ==
2141 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
2144 * Following code causes various strange
2145 * performance problems. Hmm ...
2147 CSR_WRITE_2(sc, RE_IMR, 0);
2148 CSR_WRITE_4(sc, RE_TIMERINT, 0);
2149 CSR_READ_4(sc, RE_TIMERINT); /* flush */
2151 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2152 re_setup_sim_im(sc);
2154 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2156 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2161 lwkt_serialize_exit(ifp->if_serializer);
2166 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
2168 struct re_softc *sc = arg1;
2169 struct ifnet *ifp = &sc->arpcom.ac_if;
2172 lwkt_serialize_enter(ifp->if_serializer);
2175 error = sysctl_handle_int(oidp, &v, 0, req);
2176 if (error || req->newptr == NULL)
2179 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
2183 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
2184 /* Can't do hardware interrupt moderation */
2189 if (v != sc->re_imtype) {
2191 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) ==
2193 re_setup_intr(sc, 1, sc->re_imtype);
2196 lwkt_serialize_exit(ifp->if_serializer);
2201 re_setup_hw_im(struct re_softc *sc)
2203 KKASSERT(sc->re_caps & RE_C_HWIM);
2206 * Interrupt moderation
2209 * A - unknown (maybe TX related)
2210 * B - TX timer (unit: 25us)
2211 * C - unknown (maybe RX related)
2212 * D - RX timer (unit: 25us)
2215 * re(4)'s interrupt moderation is actually controlled by
2216 * two variables, like most other NICs (bge, bce etc.)
2218 * o number of packets [P]
2220 * The logic relationship between these two variables is
2221 * similar to other NICs too:
2222 * if (timer expire || packets > [P])
2223 * Interrupt is delivered
2225 * Currently we only know how to set 'timer', but not
2226 * 'number of packets', which should be ~30, as far as I
2227 * tested (sink ~900Kpps, interrupt rate is 30KHz)
2229 CSR_WRITE_2(sc, RE_IM,
2230 RE_IM_RXTIME(sc->re_rx_time) |
2231 RE_IM_TXTIME(sc->re_tx_time) |
2236 re_disable_hw_im(struct re_softc *sc)
2238 if (sc->re_caps & RE_C_HWIM)
2239 CSR_WRITE_2(sc, RE_IM, 0);
2243 re_setup_sim_im(struct re_softc *sc)
2247 if (sc->re_if_flags & RL_FLAG_PCIE) {
2248 ticks = sc->re_sim_time * sc->re_bus_speed;
2251 * Datasheet says tick decreases at bus speed,
2252 * but it seems the clock runs a little bit
2253 * faster, so we do some compensation here.
2255 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
2257 CSR_WRITE_4(sc, RE_TIMERINT, ticks);
2259 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2260 sc->re_flags |= RE_F_TIMER_INTR;
2264 re_disable_sim_im(struct re_softc *sc)
2266 CSR_WRITE_4(sc, RE_TIMERINT, 0);
2267 sc->re_flags &= ~RE_F_TIMER_INTR;
2271 re_config_imtype(struct re_softc *sc, int imtype)
2275 KKASSERT(sc->re_caps & RE_C_HWIM);
2277 case RE_IMTYPE_NONE:
2278 sc->re_intrs = RE_INTRS;
2279 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
2281 sc->re_tx_ack = RE_ISR_TX_OK;
2285 sc->re_intrs = RE_INTRS_TIMER;
2286 sc->re_rx_ack = RE_ISR_PCS_TIMEOUT;
2287 sc->re_tx_ack = RE_ISR_PCS_TIMEOUT;
2291 panic("%s: unknown imtype %d",
2292 sc->arpcom.ac_if.if_xname, imtype);
2297 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
2299 re_config_imtype(sc, imtype);
2302 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2304 CSR_WRITE_2(sc, RE_IMR, 0);
2306 sc->re_npoll.ifpc_stcount = 0;
2309 case RE_IMTYPE_NONE:
2310 re_disable_sim_im(sc);
2311 re_disable_hw_im(sc);
2315 KKASSERT(sc->re_caps & RE_C_HWIM);
2316 re_disable_sim_im(sc);
2321 re_disable_hw_im(sc);
2322 re_setup_sim_im(sc);
2326 panic("%s: unknown imtype %d",
2327 sc->arpcom.ac_if.if_xname, imtype);
2332 re_jpool_alloc(struct re_softc *sc)
2334 struct re_list_data *ldata = &sc->re_ldata;
2335 struct re_jbuf *jbuf;
2337 bus_size_t jpool_size;
2342 lwkt_serialize_init(&ldata->re_jbuf_serializer);
2344 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
2345 M_DEVBUF, M_WAITOK | M_ZERO);
2347 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
2349 error = bus_dmamem_coherent(sc->re_parent_tag,
2351 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2352 jpool_size, BUS_DMA_WAITOK, &dmem);
2354 device_printf(sc->dev, "could not allocate jumbo memory\n");
2357 ldata->re_jpool_tag = dmem.dmem_tag;
2358 ldata->re_jpool_map = dmem.dmem_map;
2359 ldata->re_jpool = dmem.dmem_addr;
2360 paddr = dmem.dmem_busaddr;
2362 /* ..and split it into 9KB chunks */
2363 SLIST_INIT(&ldata->re_jbuf_free);
2365 buf = ldata->re_jpool;
2366 for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
2367 jbuf = &ldata->re_jbuf[i];
2373 jbuf->re_paddr = paddr;
2375 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
2377 buf += RE_JBUF_SIZE;
2378 paddr += RE_JBUF_SIZE;
2384 re_jpool_free(struct re_softc *sc)
2386 struct re_list_data *ldata = &sc->re_ldata;
2388 if (ldata->re_jpool_tag != NULL) {
2389 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
2390 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
2391 ldata->re_jpool_map);
2392 bus_dma_tag_destroy(ldata->re_jpool_tag);
2393 ldata->re_jpool_tag = NULL;
2396 if (ldata->re_jbuf != NULL) {
2397 kfree(ldata->re_jbuf, M_DEVBUF);
2398 ldata->re_jbuf = NULL;
2403 static struct re_jbuf *
2404 re_jbuf_alloc(struct re_softc *sc)
2406 struct re_list_data *ldata = &sc->re_ldata;
2407 struct re_jbuf *jbuf;
2409 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
2411 jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
2413 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
2417 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
2423 re_jbuf_free(void *arg)
2425 struct re_jbuf *jbuf = arg;
2426 struct re_softc *sc = jbuf->re_sc;
2427 struct re_list_data *ldata = &sc->re_ldata;
2429 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
2430 panic("%s: free wrong jumbo buffer",
2431 sc->arpcom.ac_if.if_xname);
2432 } else if (jbuf->re_inuse == 0) {
2433 panic("%s: jumbo buffer already freed",
2434 sc->arpcom.ac_if.if_xname);
2437 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
2438 atomic_subtract_int(&jbuf->re_inuse, 1);
2439 if (jbuf->re_inuse == 0)
2440 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
2441 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
2445 re_jbuf_ref(void *arg)
2447 struct re_jbuf *jbuf = arg;
2448 struct re_softc *sc = jbuf->re_sc;
2449 struct re_list_data *ldata = &sc->re_ldata;
2451 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
2452 panic("%s: ref wrong jumbo buffer",
2453 sc->arpcom.ac_if.if_xname);
2454 } else if (jbuf->re_inuse == 0) {
2455 panic("%s: jumbo buffer already freed",
2456 sc->arpcom.ac_if.if_xname);
2458 atomic_add_int(&jbuf->re_inuse, 1);
2460 #endif /* RE_JUMBO */
2463 re_disable_aspm(device_t dev)
2465 uint16_t link_cap, link_ctrl;
2466 uint8_t pcie_ptr, reg;
2468 pcie_ptr = pci_get_pciecap_ptr(dev);
2472 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
2473 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
2477 device_printf(dev, "disable ASPM\n");
2479 reg = pcie_ptr + PCIER_LINKCTRL;
2480 link_ctrl = pci_read_config(dev, reg, 2);
2481 link_ctrl &= ~(PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1);
2482 pci_write_config(dev, reg, link_ctrl, 2);