sys/dev/netif/jme/if_jme.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
  28  */
  29
  30 #include "opt_ifpoll.h"
  31 #include "opt_jme.h"
  32
  33 #include <sys/param.h>
  34 #include <sys/endian.h>
  35 #include <sys/kernel.h>
  36 #include <sys/bus.h>
  37 #include <sys/interrupt.h>
  38 #include <sys/malloc.h>
  39 #include <sys/proc.h>
  40 #include <sys/rman.h>
  41 #include <sys/serialize.h>
  42 #include <sys/serialize2.h>
  43 #include <sys/socket.h>
  44 #include <sys/sockio.h>
  45 #include <sys/sysctl.h>
  46
  47 #include <net/ethernet.h>
  48 #include <net/if.h>
  49 #include <net/bpf.h>
  50 #include <net/if_arp.h>
  51 #include <net/if_dl.h>
  52 #include <net/if_media.h>
  53 #include <net/if_poll.h>
  54 #include <net/ifq_var.h>
  55 #include <net/toeplitz.h>
  56 #include <net/toeplitz2.h>
  57 #include <net/vlan/if_vlan_var.h>
  58 #include <net/vlan/if_vlan_ether.h>
  59
  60 #include <netinet/ip.h>
  61 #include <netinet/tcp.h>
  62
  63 #include <dev/netif/mii_layer/miivar.h>
  64 #include <dev/netif/mii_layer/jmphyreg.h>
  65
  66 #include <bus/pci/pcireg.h>
  67 #include <bus/pci/pcivar.h>
  68 #include <bus/pci/pcidevs.h>
  69
  70 #include <dev/netif/jme/if_jmereg.h>
  71 #include <dev/netif/jme/if_jmevar.h>
  72
  73 #include "miibus_if.h"
  74
  75 #define JME_TX_SERIALIZE        1
  76 #define JME_RX_SERIALIZE        2
  77
  78 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  79
  80 #ifdef JME_RSS_DEBUG
  81 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
  82 do { \
  83         if ((sc)->jme_rss_debug >= (lvl)) \
  84                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
  85 } while (0)
  86 #else   /* !JME_RSS_DEBUG */
  87 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  88 #endif  /* JME_RSS_DEBUG */
  89
  90 static int      jme_probe(device_t);
  91 static int      jme_attach(device_t);
  92 static int      jme_detach(device_t);
  93 static int      jme_shutdown(device_t);
  94 static int      jme_suspend(device_t);
  95 static int      jme_resume(device_t);
  96
  97 static int      jme_miibus_readreg(device_t, int, int);
  98 static int      jme_miibus_writereg(device_t, int, int, int);
  99 static void     jme_miibus_statchg(device_t);
 100
 101 static void     jme_init(void *);
 102 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 103 static void     jme_start(struct ifnet *);
 104 static void     jme_watchdog(struct ifnet *);
 105 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
 106 static int      jme_mediachange(struct ifnet *);
 107 #ifdef IFPOLL_ENABLE
 108 static void     jme_npoll(struct ifnet *, struct ifpoll_info *);
 109 static void     jme_npoll_status(struct ifnet *, int);
 110 static void     jme_npoll_rx(struct ifnet *, void *, int);
 111 static void     jme_npoll_tx(struct ifnet *, void *, int);
 112 #endif
 113 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
 114 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
 115 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
 116 #ifdef INVARIANTS
 117 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
 118                     boolean_t);
 119 #endif
 120
 121 static void     jme_intr(void *);
 122 static void     jme_msix_tx(void *);
 123 static void     jme_msix_rx(void *);
 124 static void     jme_msix_status(void *);
 125 static void     jme_txeof(struct jme_txdata *);
 126 static void     jme_rxeof(struct jme_rxdata *, int);
 127 static void     jme_rx_intr(struct jme_softc *, uint32_t);
 128 static void     jme_enable_intr(struct jme_softc *);
 129 static void     jme_disable_intr(struct jme_softc *);
 130 static void     jme_rx_restart(struct jme_softc *, uint32_t);
 131
 132 static int      jme_msix_setup(device_t);
 133 static void     jme_msix_teardown(device_t, int);
 134 static int      jme_intr_setup(device_t);
 135 static void     jme_intr_teardown(device_t);
 136 static void     jme_msix_try_alloc(device_t);
 137 static void     jme_msix_free(device_t);
 138 static int      jme_intr_alloc(device_t);
 139 static void     jme_intr_free(device_t);
 140 static int      jme_dma_alloc(struct jme_softc *);
 141 static void     jme_dma_free(struct jme_softc *);
 142 static int      jme_init_rx_ring(struct jme_rxdata *);
 143 static void     jme_init_tx_ring(struct jme_txdata *);
 144 static void     jme_init_ssb(struct jme_softc *);
 145 static int      jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
 146 static int      jme_encap(struct jme_txdata *, struct mbuf **);
 147 static void     jme_rxpkt(struct jme_rxdata *);
 148 static int      jme_rxring_dma_alloc(struct jme_rxdata *);
 149 static int      jme_rxbuf_dma_alloc(struct jme_rxdata *);
 150 static int      jme_rxbuf_dma_filter(void *, bus_addr_t);
 151
 152 static void     jme_tick(void *);
 153 static void     jme_stop(struct jme_softc *);
 154 static void     jme_reset(struct jme_softc *);
 155 static void     jme_set_msinum(struct jme_softc *);
 156 static void     jme_set_vlan(struct jme_softc *);
 157 static void     jme_set_filter(struct jme_softc *);
 158 static void     jme_stop_tx(struct jme_softc *);
 159 static void     jme_stop_rx(struct jme_softc *);
 160 static void     jme_mac_config(struct jme_softc *);
 161 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
 162 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
 163 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
 164 #ifdef notyet
 165 static void     jme_setwol(struct jme_softc *);
 166 static void     jme_setlinkspeed(struct jme_softc *);
 167 #endif
 168 static void     jme_set_tx_coal(struct jme_softc *);
 169 static void     jme_set_rx_coal(struct jme_softc *);
 170 static void     jme_enable_rss(struct jme_softc *);
 171 static void     jme_disable_rss(struct jme_softc *);
 172 static void     jme_serialize_skipmain(struct jme_softc *);
 173 static void     jme_deserialize_skipmain(struct jme_softc *);
 174
 175 static void     jme_sysctl_node(struct jme_softc *);
 176 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
 177 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
 178 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
 179 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
 180 #ifdef IFPOLL_ENABLE
 181 static int      jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 182 static int      jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 183 #endif
 184
 185 /*
 186  * Devices supported by this driver.
 187  */
 188 static const struct jme_dev {
 189         uint16_t        jme_vendorid;
 190         uint16_t        jme_deviceid;
 191         uint32_t        jme_caps;
 192         const char      *jme_name;
 193 } jme_devs[] = {
 194         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
 195             JME_CAP_JUMBO,
 196             "JMicron Inc, JMC250 Gigabit Ethernet" },
 197         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
 198             JME_CAP_FASTETH,
 199             "JMicron Inc, JMC260 Fast Ethernet" },
 200         { 0, 0, 0, NULL }
 201 };
 202
 203 static device_method_t jme_methods[] = {
 204         /* Device interface. */
 205         DEVMETHOD(device_probe,         jme_probe),
 206         DEVMETHOD(device_attach,        jme_attach),
 207         DEVMETHOD(device_detach,        jme_detach),
 208         DEVMETHOD(device_shutdown,      jme_shutdown),
 209         DEVMETHOD(device_suspend,       jme_suspend),
 210         DEVMETHOD(device_resume,        jme_resume),
 211
 212         /* Bus interface. */
 213         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 214         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 215
 216         /* MII interface. */
 217         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
 218         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
 219         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
 220
 221         { NULL, NULL }
 222 };
 223
 224 static driver_t jme_driver = {
 225         "jme",
 226         jme_methods,
 227         sizeof(struct jme_softc)
 228 };
 229
 230 static devclass_t jme_devclass;
 231
 232 DECLARE_DUMMY_MODULE(if_jme);
 233 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
 234 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
 235 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
 236
 237 static const struct {
 238         uint32_t        jme_coal;
 239         uint32_t        jme_comp;
 240         uint32_t        jme_empty;
 241 } jme_rx_status[JME_NRXRING_MAX] = {
 242         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
 243           INTR_RXQ0_DESC_EMPTY },
 244         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
 245           INTR_RXQ1_DESC_EMPTY },
 246         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
 247           INTR_RXQ2_DESC_EMPTY },
 248         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
 249           INTR_RXQ3_DESC_EMPTY }
 250 };
 251
 252 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
 253 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
 254 static int      jme_rx_ring_count = 0;
 255 static int      jme_msi_enable = 1;
 256 static int      jme_msix_enable = 1;
 257
 258 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
 259 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
 260 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
 261 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
 262 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
 263
 264 static __inline void
 265 jme_setup_rxdesc(struct jme_rxdesc *rxd)
 266 {
 267         struct jme_desc *desc;
 268
 269         desc = rxd->rx_desc;
 270         desc->buflen = htole32(MCLBYTES);
 271         desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
 272         desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
 273         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
 274 }
 275
 276 /*
 277  *      Read a PHY register on the MII of the JMC250.
 278  */
 279 static int
 280 jme_miibus_readreg(device_t dev, int phy, int reg)
 281 {
 282         struct jme_softc *sc = device_get_softc(dev);
 283         uint32_t val;
 284         int i;
 285
 286         /* For FPGA version, PHY address 0 should be ignored. */
 287         if (sc->jme_caps & JME_CAP_FPGA) {
 288                 if (phy == 0)
 289                         return (0);
 290         } else {
 291                 if (sc->jme_phyaddr != phy)
 292                         return (0);
 293         }
 294
 295         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
 296             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 297
 298         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 299                 DELAY(1);
 300                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 301                         break;
 302         }
 303         if (i == 0) {
 304                 device_printf(sc->jme_dev, "phy read timeout: "
 305                               "phy %d, reg %d\n", phy, reg);
 306                 return (0);
 307         }
 308
 309         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
 310 }
 311
 312 /*
 313  *      Write a PHY register on the MII of the JMC250.
 314  */
 315 static int
 316 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
 317 {
 318         struct jme_softc *sc = device_get_softc(dev);
 319         int i;
 320
 321         /* For FPGA version, PHY address 0 should be ignored. */
 322         if (sc->jme_caps & JME_CAP_FPGA) {
 323                 if (phy == 0)
 324                         return (0);
 325         } else {
 326                 if (sc->jme_phyaddr != phy)
 327                         return (0);
 328         }
 329
 330         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
 331             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
 332             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 333
 334         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 335                 DELAY(1);
 336                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 337                         break;
 338         }
 339         if (i == 0) {
 340                 device_printf(sc->jme_dev, "phy write timeout: "
 341                               "phy %d, reg %d\n", phy, reg);
 342         }
 343
 344         return (0);
 345 }
 346
 347 /*
 348  *      Callback from MII layer when media changes.
 349  */
 350 static void
 351 jme_miibus_statchg(device_t dev)
 352 {
 353         struct jme_softc *sc = device_get_softc(dev);
 354         struct ifnet *ifp = &sc->arpcom.ac_if;
 355         struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
 356         struct mii_data *mii;
 357         struct jme_txdesc *txd;
 358         bus_addr_t paddr;
 359         int i, r;
 360
 361         if (sc->jme_in_tick)
 362                 jme_serialize_skipmain(sc);
 363         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 364
 365         if ((ifp->if_flags & IFF_RUNNING) == 0)
 366                 goto done;
 367
 368         mii = device_get_softc(sc->jme_miibus);
 369
 370         sc->jme_has_link = FALSE;
 371         if ((mii->mii_media_status & IFM_AVALID) != 0) {
 372                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 373                 case IFM_10_T:
 374                 case IFM_100_TX:
 375                         sc->jme_has_link = TRUE;
 376                         break;
 377                 case IFM_1000_T:
 378                         if (sc->jme_caps & JME_CAP_FASTETH)
 379                                 break;
 380                         sc->jme_has_link = TRUE;
 381                         break;
 382                 default:
 383                         break;
 384                 }
 385         }
 386
 387         /*
 388          * Disabling Rx/Tx MACs have a side-effect of resetting
 389          * JME_TXNDA/JME_RXNDA register to the first address of
 390          * Tx/Rx descriptor address. So driver should reset its
 391          * internal procucer/consumer pointer and reclaim any
 392          * allocated resources.  Note, just saving the value of
 393          * JME_TXNDA and JME_RXNDA registers before stopping MAC
 394          * and restoring JME_TXNDA/JME_RXNDA register is not
 395          * sufficient to make sure correct MAC state because
 396          * stopping MAC operation can take a while and hardware
 397          * might have updated JME_TXNDA/JME_RXNDA registers
 398          * during the stop operation.
 399          */
 400
 401         /* Disable interrupts */
 402         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
 403
 404         /* Stop driver */
 405         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 406         ifp->if_timer = 0;
 407         callout_stop(&sc->jme_tick_ch);
 408
 409         /* Stop receiver/transmitter. */
 410         jme_stop_rx(sc);
 411         jme_stop_tx(sc);
 412
 413         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 414                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
 415
 416                 jme_rxeof(rdata, -1);
 417                 if (rdata->jme_rxhead != NULL)
 418                         m_freem(rdata->jme_rxhead);
 419                 JME_RXCHAIN_RESET(rdata);
 420
 421                 /*
 422                  * Reuse configured Rx descriptors and reset
 423                  * procuder/consumer index.
 424                  */
 425                 rdata->jme_rx_cons = 0;
 426         }
 427         if (JME_ENABLE_HWRSS(sc))
 428                 jme_enable_rss(sc);
 429         else
 430                 jme_disable_rss(sc);
 431
 432         jme_txeof(tdata);
 433         if (tdata->jme_tx_cnt != 0) {
 434                 /* Remove queued packets for transmit. */
 435                 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
 436                         txd = &tdata->jme_txdesc[i];
 437                         if (txd->tx_m != NULL) {
 438                                 bus_dmamap_unload( tdata->jme_tx_tag,
 439                                     txd->tx_dmamap);
 440                                 m_freem(txd->tx_m);
 441                                 txd->tx_m = NULL;
 442                                 txd->tx_ndesc = 0;
 443                                 ifp->if_oerrors++;
 444                         }
 445                 }
 446         }
 447         jme_init_tx_ring(tdata);
 448
 449         /* Initialize shadow status block. */
 450         jme_init_ssb(sc);
 451
 452         /* Program MAC with resolved speed/duplex/flow-control. */
 453         if (sc->jme_has_link) {
 454                 jme_mac_config(sc);
 455
 456                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
 457
 458                 /* Set Tx ring address to the hardware. */
 459                 paddr = tdata->jme_tx_ring_paddr;
 460                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
 461                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
 462
 463                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 464                         CSR_WRITE_4(sc, JME_RXCSR,
 465                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
 466
 467                         /* Set Rx ring address to the hardware. */
 468                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
 469                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
 470                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
 471                 }
 472
 473                 /* Restart receiver/transmitter. */
 474                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
 475                     RXCSR_RXQ_START);
 476                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
 477         }
 478
 479         ifp->if_flags |= IFF_RUNNING;
 480         ifp->if_flags &= ~IFF_OACTIVE;
 481         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
 482
 483 #ifdef IFPOLL_ENABLE
 484         if (!(ifp->if_flags & IFF_NPOLLING))
 485 #endif
 486         /* Reenable interrupts. */
 487         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
 488
 489 done:
 490         if (sc->jme_in_tick)
 491                 jme_deserialize_skipmain(sc);
 492 }
 493
 494 /*
 495  *      Get the current interface media status.
 496  */
 497 static void
 498 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 499 {
 500         struct jme_softc *sc = ifp->if_softc;
 501         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 502
 503         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 504
 505         mii_pollstat(mii);
 506         ifmr->ifm_status = mii->mii_media_status;
 507         ifmr->ifm_active = mii->mii_media_active;
 508 }
 509
 510 /*
 511  *      Set hardware to newly-selected media.
 512  */
 513 static int
 514 jme_mediachange(struct ifnet *ifp)
 515 {
 516         struct jme_softc *sc = ifp->if_softc;
 517         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 518         int error;
 519
 520         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 521
 522         if (mii->mii_instance != 0) {
 523                 struct mii_softc *miisc;
 524
 525                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 526                         mii_phy_reset(miisc);
 527         }
 528         error = mii_mediachg(mii);
 529
 530         return (error);
 531 }
 532
 533 static int
 534 jme_probe(device_t dev)
 535 {
 536         const struct jme_dev *sp;
 537         uint16_t vid, did;
 538
 539         vid = pci_get_vendor(dev);
 540         did = pci_get_device(dev);
 541         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
 542                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
 543                         struct jme_softc *sc = device_get_softc(dev);
 544
 545                         sc->jme_caps = sp->jme_caps;
 546                         device_set_desc(dev, sp->jme_name);
 547                         return (0);
 548                 }
 549         }
 550         return (ENXIO);
 551 }
 552
 553 static int
 554 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
 555 {
 556         uint32_t reg;
 557         int i;
 558
 559         *val = 0;
 560         for (i = JME_TIMEOUT; i > 0; i--) {
 561                 reg = CSR_READ_4(sc, JME_SMBCSR);
 562                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
 563                         break;
 564                 DELAY(1);
 565         }
 566
 567         if (i == 0) {
 568                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
 569                 return (ETIMEDOUT);
 570         }
 571
 572         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
 573         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
 574         for (i = JME_TIMEOUT; i > 0; i--) {
 575                 DELAY(1);
 576                 reg = CSR_READ_4(sc, JME_SMBINTF);
 577                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
 578                         break;
 579         }
 580
 581         if (i == 0) {
 582                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
 583                 return (ETIMEDOUT);
 584         }
 585
 586         reg = CSR_READ_4(sc, JME_SMBINTF);
 587         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
 588
 589         return (0);
 590 }
 591
 592 static int
 593 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 594 {
 595         uint8_t fup, reg, val;
 596         uint32_t offset;
 597         int match;
 598
 599         offset = 0;
 600         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 601             fup != JME_EEPROM_SIG0)
 602                 return (ENOENT);
 603         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 604             fup != JME_EEPROM_SIG1)
 605                 return (ENOENT);
 606         match = 0;
 607         do {
 608                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
 609                         break;
 610                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
 611                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
 612                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
 613                                 break;
 614                         if (reg >= JME_PAR0 &&
 615                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
 616                                 if (jme_eeprom_read_byte(sc, offset + 2,
 617                                     &val) != 0)
 618                                         break;
 619                                 eaddr[reg - JME_PAR0] = val;
 620                                 match++;
 621                         }
 622                 }
 623                 /* Check for the end of EEPROM descriptor. */
 624                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
 625                         break;
 626                 /* Try next eeprom descriptor. */
 627                 offset += JME_EEPROM_DESC_BYTES;
 628         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
 629
 630         if (match == ETHER_ADDR_LEN)
 631                 return (0);
 632
 633         return (ENOENT);
 634 }
 635
 636 static void
 637 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 638 {
 639         uint32_t par0, par1;
 640
 641         /* Read station address. */
 642         par0 = CSR_READ_4(sc, JME_PAR0);
 643         par1 = CSR_READ_4(sc, JME_PAR1);
 644         par1 &= 0xFFFF;
 645         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
 646                 device_printf(sc->jme_dev,
 647                     "generating fake ethernet address.\n");
 648                 par0 = karc4random();
 649                 /* Set OUI to JMicron. */
 650                 eaddr[0] = 0x00;
 651                 eaddr[1] = 0x1B;
 652                 eaddr[2] = 0x8C;
 653                 eaddr[3] = (par0 >> 16) & 0xff;
 654                 eaddr[4] = (par0 >> 8) & 0xff;
 655                 eaddr[5] = par0 & 0xff;
 656         } else {
 657                 eaddr[0] = (par0 >> 0) & 0xFF;
 658                 eaddr[1] = (par0 >> 8) & 0xFF;
 659                 eaddr[2] = (par0 >> 16) & 0xFF;
 660                 eaddr[3] = (par0 >> 24) & 0xFF;
 661                 eaddr[4] = (par1 >> 0) & 0xFF;
 662                 eaddr[5] = (par1 >> 8) & 0xFF;
 663         }
 664 }
 665
 666 static int
 667 jme_attach(device_t dev)
 668 {
 669         struct jme_softc *sc = device_get_softc(dev);
 670         struct ifnet *ifp = &sc->arpcom.ac_if;
 671         uint32_t reg;
 672         uint16_t did;
 673         uint8_t pcie_ptr, rev;
 674         int error = 0, i, j, rx_desc_cnt, coal_max;
 675         uint8_t eaddr[ETHER_ADDR_LEN];
 676 #ifdef IFPOLL_ENABLE
 677         int offset, offset_def;
 678 #endif
 679
 680         /*
 681          * Initialize serializers
 682          */
 683         lwkt_serialize_init(&sc->jme_serialize);
 684         lwkt_serialize_init(&sc->jme_cdata.jme_tx_data.jme_tx_serialize);
 685         for (i = 0; i < JME_NRXRING_MAX; ++i) {
 686                 lwkt_serialize_init(
 687                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
 688         }
 689
 690         /*
 691          * Get # of RX ring descriptors
 692          */
 693         rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
 694             jme_rx_desc_count);
 695         rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
 696         if (rx_desc_cnt > JME_NDESC_MAX)
 697                 rx_desc_cnt = JME_NDESC_MAX;
 698
 699         /*
 700          * Get # of TX ring descriptors
 701          */
 702         sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt =
 703             device_getenv_int(dev, "tx_desc_count", jme_tx_desc_count);
 704         sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt =
 705             roundup(sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, JME_NDESC_ALIGN);
 706         if (sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt > JME_NDESC_MAX)
 707                 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = JME_NDESC_MAX;
 708
 709         /*
 710          * Get # of RX rings
 711          */
 712         sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
 713             jme_rx_ring_count);
 714         sc->jme_cdata.jme_rx_ring_cnt =
 715             if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
 716
 717         /*
 718          * Initialize serializer array
 719          */
 720         i = 0;
 721         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
 722
 723         KKASSERT(i == JME_TX_SERIALIZE);
 724         sc->jme_serialize_arr[i++] =
 725             &sc->jme_cdata.jme_tx_data.jme_tx_serialize;
 726
 727         KKASSERT(i == JME_RX_SERIALIZE);
 728         for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
 729                 sc->jme_serialize_arr[i++] =
 730                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
 731         }
 732         KKASSERT(i <= JME_NSERIALIZE);
 733         sc->jme_serialize_cnt = i;
 734
 735         /*
 736          * Setup TX ring specific data
 737          */
 738         sc->jme_cdata.jme_tx_data.jme_sc = sc;
 739
 740         /*
 741          * Setup RX rings specific data
 742          */
 743         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
 744                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
 745
 746                 rdata->jme_sc = sc;
 747                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
 748                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
 749                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
 750                 rdata->jme_rx_idx = i;
 751                 rdata->jme_rx_desc_cnt = rx_desc_cnt;
 752         }
 753
 754         sc->jme_dev = dev;
 755         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
 756
 757         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 758
 759         callout_init(&sc->jme_tick_ch);
 760
 761 #ifndef BURN_BRIDGES
 762         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 763                 uint32_t irq, mem;
 764
 765                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 766                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
 767
 768                 device_printf(dev, "chip is in D%d power mode "
 769                     "-- setting to D0\n", pci_get_powerstate(dev));
 770
 771                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 772
 773                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 774                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
 775         }
 776 #endif  /* !BURN_BRIDGE */
 777
 778         /* Enable bus mastering */
 779         pci_enable_busmaster(dev);
 780
 781         /*
 782          * Allocate IO memory
 783          *
 784          * JMC250 supports both memory mapped and I/O register space
 785          * access.  Because I/O register access should use different
 786          * BARs to access registers it's waste of time to use I/O
 787          * register spce access.  JMC250 uses 16K to map entire memory
 788          * space.
 789          */
 790         sc->jme_mem_rid = JME_PCIR_BAR;
 791         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 792                                                  &sc->jme_mem_rid, RF_ACTIVE);
 793         if (sc->jme_mem_res == NULL) {
 794                 device_printf(dev, "can't allocate IO memory\n");
 795                 return ENXIO;
 796         }
 797         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
 798         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
 799
 800         /*
 801          * Allocate IRQ
 802          */
 803         error = jme_intr_alloc(dev);
 804         if (error)
 805                 goto fail;
 806
 807         /*
 808          * Extract revisions
 809          */
 810         reg = CSR_READ_4(sc, JME_CHIPMODE);
 811         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
 812             CHIPMODE_NOT_FPGA) {
 813                 sc->jme_caps |= JME_CAP_FPGA;
 814                 if (bootverbose) {
 815                         device_printf(dev, "FPGA revision: 0x%04x\n",
 816                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
 817                                       CHIPMODE_FPGA_REV_SHIFT);
 818                 }
 819         }
 820
 821         /* NOTE: FM revision is put in the upper 4 bits */
 822         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
 823         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
 824         if (bootverbose)
 825                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
 826
 827         did = pci_get_device(dev);
 828         switch (did) {
 829         case PCI_PRODUCT_JMICRON_JMC250:
 830                 if (rev == JME_REV1_A2)
 831                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
 832                 break;
 833
 834         case PCI_PRODUCT_JMICRON_JMC260:
 835                 if (rev == JME_REV2)
 836                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
 837                 break;
 838
 839         default:
 840                 panic("unknown device id 0x%04x", did);
 841         }
 842         if (rev >= JME_REV2) {
 843                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
 844                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
 845                                       GHC_TXMAC_CLKSRC_1000;
 846         }
 847
 848         /* Reset the ethernet controller. */
 849         jme_reset(sc);
 850
 851         /* Map MSI/MSI-X vectors */
 852         jme_set_msinum(sc);
 853
 854         /* Get station address. */
 855         reg = CSR_READ_4(sc, JME_SMBCSR);
 856         if (reg & SMBCSR_EEPROM_PRESENT)
 857                 error = jme_eeprom_macaddr(sc, eaddr);
 858         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
 859                 if (error != 0 && (bootverbose)) {
 860                         device_printf(dev, "ethernet hardware address "
 861                                       "not found in EEPROM.\n");
 862                 }
 863                 jme_reg_macaddr(sc, eaddr);
 864         }
 865
 866         /*
 867          * Save PHY address.
 868          * Integrated JR0211 has fixed PHY address whereas FPGA version
 869          * requires PHY probing to get correct PHY address.
 870          */
 871         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
 872                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
 873                     GPREG0_PHY_ADDR_MASK;
 874                 if (bootverbose) {
 875                         device_printf(dev, "PHY is at address %d.\n",
 876                             sc->jme_phyaddr);
 877                 }
 878         } else {
 879                 sc->jme_phyaddr = 0;
 880         }
 881
 882         /* Set max allowable DMA size. */
 883         pcie_ptr = pci_get_pciecap_ptr(dev);
 884         if (pcie_ptr != 0) {
 885                 uint16_t ctrl;
 886
 887                 sc->jme_caps |= JME_CAP_PCIE;
 888                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
 889                 if (bootverbose) {
 890                         device_printf(dev, "Read request size : %d bytes.\n",
 891                             128 << ((ctrl >> 12) & 0x07));
 892                         device_printf(dev, "TLP payload size : %d bytes.\n",
 893                             128 << ((ctrl >> 5) & 0x07));
 894                 }
 895                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
 896                 case PCIEM_DEVCTL_MAX_READRQ_128:
 897                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
 898                         break;
 899                 case PCIEM_DEVCTL_MAX_READRQ_256:
 900                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
 901                         break;
 902                 default:
 903                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 904                         break;
 905                 }
 906                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 907         } else {
 908                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 909                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 910         }
 911
 912 #ifdef notyet
 913         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
 914                 sc->jme_caps |= JME_CAP_PMCAP;
 915 #endif
 916
 917 #ifdef IFPOLL_ENABLE
 918         /*
 919          * NPOLLING RX CPU offset
 920          */
 921         if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) {
 922                 offset = 0;
 923         } else {
 924                 offset_def = (sc->jme_cdata.jme_rx_ring_cnt *
 925                     device_get_unit(dev)) % ncpus2;
 926                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 927                 if (offset >= ncpus2 ||
 928                     offset % sc->jme_cdata.jme_rx_ring_cnt != 0) {
 929                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 930                             offset, offset_def);
 931                         offset = offset_def;
 932                 }
 933         }
 934         sc->jme_npoll_rxoff = offset;
 935
 936         /*
 937          * NPOLLING TX CPU offset
 938          */
 939         offset_def = sc->jme_npoll_rxoff;
 940         offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 941         if (offset >= ncpus2) {
 942                 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 943                     offset, offset_def);
 944                 offset = offset_def;
 945         }
 946         sc->jme_npoll_txoff = offset;
 947 #endif
 948
 949         /*
 950          * Set default coalesce valves
 951          */
 952         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
 953         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
 954         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
 955         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
 956
 957         /*
 958          * Adjust coalesce valves, in case that the number of TX/RX
 959          * descs are set to small values by users.
 960          *
 961          * NOTE: coal_max will not be zero, since number of descs
 962          * must aligned by JME_NDESC_ALIGN (16 currently)
 963          */
 964         coal_max = sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt / 2;
 965         if (coal_max < sc->jme_tx_coal_pkt)
 966                 sc->jme_tx_coal_pkt = coal_max;
 967
 968         coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 2;
 969         if (coal_max < sc->jme_rx_coal_pkt)
 970                 sc->jme_rx_coal_pkt = coal_max;
 971
 972         /*
 973          * Create sysctl tree
 974          */
 975         jme_sysctl_node(sc);
 976
 977         /* Allocate DMA stuffs */
 978         error = jme_dma_alloc(sc);
 979         if (error)
 980                 goto fail;
 981
 982         ifp->if_softc = sc;
 983         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 984         ifp->if_init = jme_init;
 985         ifp->if_ioctl = jme_ioctl;
 986         ifp->if_start = jme_start;
 987 #ifdef IFPOLL_ENABLE
 988         ifp->if_npoll = jme_npoll;
 989 #endif
 990         ifp->if_watchdog = jme_watchdog;
 991         ifp->if_serialize = jme_serialize;
 992         ifp->if_deserialize = jme_deserialize;
 993         ifp->if_tryserialize = jme_tryserialize;
 994 #ifdef INVARIANTS
 995         ifp->if_serialize_assert = jme_serialize_assert;
 996 #endif
 997         ifq_set_maxlen(&ifp->if_snd,
 998             sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt - JME_TXD_RSVD);
 999         ifq_set_ready(&ifp->if_snd);
1000
1001         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
1002         ifp->if_capabilities = IFCAP_HWCSUM |
1003                                IFCAP_TSO |
1004                                IFCAP_VLAN_MTU |
1005                                IFCAP_VLAN_HWTAGGING;
1006         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
1007                 ifp->if_capabilities |= IFCAP_RSS;
1008         ifp->if_capenable = ifp->if_capabilities;
1009
1010         /*
1011          * Disable TXCSUM by default to improve bulk data
1012          * transmit performance (+20Mbps improvement).
1013          */
1014         ifp->if_capenable &= ~IFCAP_TXCSUM;
1015
1016         if (ifp->if_capenable & IFCAP_TXCSUM)
1017                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1018         ifp->if_hwassist |= CSUM_TSO;
1019
1020         /* Set up MII bus. */
1021         error = mii_phy_probe(dev, &sc->jme_miibus,
1022                               jme_mediachange, jme_mediastatus);
1023         if (error) {
1024                 device_printf(dev, "no PHY found!\n");
1025                 goto fail;
1026         }
1027
1028         /*
1029          * Save PHYADDR for FPGA mode PHY.
1030          */
1031         if (sc->jme_caps & JME_CAP_FPGA) {
1032                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1033
1034                 if (mii->mii_instance != 0) {
1035                         struct mii_softc *miisc;
1036
1037                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
1038                                 if (miisc->mii_phy != 0) {
1039                                         sc->jme_phyaddr = miisc->mii_phy;
1040                                         break;
1041                                 }
1042                         }
1043                         if (sc->jme_phyaddr != 0) {
1044                                 device_printf(sc->jme_dev,
1045                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
1046                                 /* vendor magic. */
1047                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
1048                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
1049
1050                                 /* XXX should we clear JME_WA_EXTFIFO */
1051                         }
1052                 }
1053         }
1054
1055         ether_ifattach(ifp, eaddr, NULL);
1056
1057         /* Tell the upper layer(s) we support long frames. */
1058         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1059
1060         error = jme_intr_setup(dev);
1061         if (error) {
1062                 ether_ifdetach(ifp);
1063                 goto fail;
1064         }
1065
1066         return 0;
1067 fail:
1068         jme_detach(dev);
1069         return (error);
1070 }
1071
1072 static int
1073 jme_detach(device_t dev)
1074 {
1075         struct jme_softc *sc = device_get_softc(dev);
1076
1077         if (device_is_attached(dev)) {
1078                 struct ifnet *ifp = &sc->arpcom.ac_if;
1079
1080                 ifnet_serialize_all(ifp);
1081                 jme_stop(sc);
1082                 jme_intr_teardown(dev);
1083                 ifnet_deserialize_all(ifp);
1084
1085                 ether_ifdetach(ifp);
1086         }
1087
1088         if (sc->jme_sysctl_tree != NULL)
1089                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1090
1091         if (sc->jme_miibus != NULL)
1092                 device_delete_child(dev, sc->jme_miibus);
1093         bus_generic_detach(dev);
1094
1095         jme_intr_free(dev);
1096
1097         if (sc->jme_mem_res != NULL) {
1098                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1099                                      sc->jme_mem_res);
1100         }
1101
1102         jme_dma_free(sc);
1103
1104         return (0);
1105 }
1106
1107 static void
1108 jme_sysctl_node(struct jme_softc *sc)
1109 {
1110 #ifdef JME_RSS_DEBUG
1111         int r;
1112 #endif
1113
1114         sysctl_ctx_init(&sc->jme_sysctl_ctx);
1115         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1116                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1117                                 device_get_nameunit(sc->jme_dev),
1118                                 CTLFLAG_RD, 0, "");
1119         if (sc->jme_sysctl_tree == NULL) {
1120                 device_printf(sc->jme_dev, "can't add sysctl node\n");
1121                 return;
1122         }
1123
1124         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1125             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1126             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1127             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1128
1129         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1130             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1131             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1132             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1133
1134         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1135             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1136             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1137             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1138
1139         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1140             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1141             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1142             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1143
1144         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1145                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1146                        "rx_desc_count", CTLFLAG_RD,
1147                        &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1148                        0, "RX desc count");
1149         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1150                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1151                        "tx_desc_count", CTLFLAG_RD,
1152                        &sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt,
1153                        0, "TX desc count");
1154         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1155                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1156                        "rx_ring_count", CTLFLAG_RD,
1157                        &sc->jme_cdata.jme_rx_ring_cnt,
1158                        0, "RX ring count");
1159
1160 #ifdef JME_RSS_DEBUG
1161         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1162                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1163                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1164                        0, "RSS debug level");
1165         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1166                 char rx_ring_desc[32];
1167
1168                 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1169                     "rx_ring%d_pkt", r);
1170                 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1171                     SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1172                     rx_ring_desc, CTLFLAG_RW,
1173                     &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1174
1175                 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1176                     "rx_ring%d_emp", r);
1177                 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1178                     SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1179                     rx_ring_desc, CTLFLAG_RW,
1180                     &sc->jme_cdata.jme_rx_data[r].jme_rx_emp,
1181                     "# of time RX ring empty");
1182         }
1183 #endif
1184
1185 #ifdef IFPOLL_ENABLE
1186         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1187             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1188             "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
1189             jme_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1190         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1191             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1192             "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
1193             jme_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1194 #endif
1195 }
1196
1197 static int
1198 jme_dma_alloc(struct jme_softc *sc)
1199 {
1200         struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
1201         struct jme_txdesc *txd;
1202         bus_dmamem_t dmem;
1203         int error, i, asize;
1204
1205         asize = __VM_CACHELINE_ALIGN(
1206             tdata->jme_tx_desc_cnt * sizeof(struct jme_txdesc));
1207         tdata->jme_txdesc = kmalloc_cachealign(asize, M_DEVBUF,
1208             M_WAITOK | M_ZERO);
1209
1210         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1211                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1212
1213                 asize = __VM_CACHELINE_ALIGN(
1214                     rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc));
1215                 rdata->jme_rxdesc = kmalloc_cachealign(asize, M_DEVBUF,
1216                     M_WAITOK | M_ZERO);
1217         }
1218
1219         /* Create parent ring tag. */
1220         error = bus_dma_tag_create(NULL,/* parent */
1221             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1222             sc->jme_lowaddr,            /* lowaddr */
1223             BUS_SPACE_MAXADDR,          /* highaddr */
1224             NULL, NULL,                 /* filter, filterarg */
1225             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1226             0,                          /* nsegments */
1227             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1228             0,                          /* flags */
1229             &sc->jme_cdata.jme_ring_tag);
1230         if (error) {
1231                 device_printf(sc->jme_dev,
1232                     "could not create parent ring DMA tag.\n");
1233                 return error;
1234         }
1235
1236         /*
1237          * Create DMA stuffs for TX ring
1238          */
1239         asize = roundup2(JME_TX_RING_SIZE(tdata), JME_TX_RING_ALIGN);
1240         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1241                         JME_TX_RING_ALIGN, 0,
1242                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1243                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1244         if (error) {
1245                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1246                 return error;
1247         }
1248         tdata->jme_tx_ring_tag = dmem.dmem_tag;
1249         tdata->jme_tx_ring_map = dmem.dmem_map;
1250         tdata->jme_tx_ring = dmem.dmem_addr;
1251         tdata->jme_tx_ring_paddr = dmem.dmem_busaddr;
1252
1253         /*
1254          * Create DMA stuffs for RX rings
1255          */
1256         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1257                 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1258                 if (error)
1259                         return error;
1260         }
1261
1262         /* Create parent buffer tag. */
1263         error = bus_dma_tag_create(NULL,/* parent */
1264             1, 0,                       /* algnmnt, boundary */
1265             sc->jme_lowaddr,            /* lowaddr */
1266             BUS_SPACE_MAXADDR,          /* highaddr */
1267             NULL, NULL,                 /* filter, filterarg */
1268             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1269             0,                          /* nsegments */
1270             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1271             0,                          /* flags */
1272             &sc->jme_cdata.jme_buffer_tag);
1273         if (error) {
1274                 device_printf(sc->jme_dev,
1275                     "could not create parent buffer DMA tag.\n");
1276                 return error;
1277         }
1278
1279         /*
1280          * Create DMA stuffs for shadow status block
1281          */
1282         asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1283         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1284                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1285                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1286         if (error) {
1287                 device_printf(sc->jme_dev,
1288                     "could not create shadow status block.\n");
1289                 return error;
1290         }
1291         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1292         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1293         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1294         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1295
1296         /*
1297          * Create DMA stuffs for TX buffers
1298          */
1299
1300         /* Create tag for Tx buffers. */
1301         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1302             1, 0,                       /* algnmnt, boundary */
1303             BUS_SPACE_MAXADDR,          /* lowaddr */
1304             BUS_SPACE_MAXADDR,          /* highaddr */
1305             NULL, NULL,                 /* filter, filterarg */
1306             JME_TSO_MAXSIZE,            /* maxsize */
1307             JME_MAXTXSEGS,              /* nsegments */
1308             JME_MAXSEGSIZE,             /* maxsegsize */
1309             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1310             &tdata->jme_tx_tag);
1311         if (error != 0) {
1312                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1313                 return error;
1314         }
1315
1316         /* Create DMA maps for Tx buffers. */
1317         for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
1318                 txd = &tdata->jme_txdesc[i];
1319                 error = bus_dmamap_create(tdata->jme_tx_tag,
1320                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1321                                 &txd->tx_dmamap);
1322                 if (error) {
1323                         int j;
1324
1325                         device_printf(sc->jme_dev,
1326                             "could not create %dth Tx dmamap.\n", i);
1327
1328                         for (j = 0; j < i; ++j) {
1329                                 txd = &tdata->jme_txdesc[j];
1330                                 bus_dmamap_destroy(tdata->jme_tx_tag,
1331                                                    txd->tx_dmamap);
1332                         }
1333                         bus_dma_tag_destroy(tdata->jme_tx_tag);
1334                         tdata->jme_tx_tag = NULL;
1335                         return error;
1336                 }
1337         }
1338
1339         /*
1340          * Create DMA stuffs for RX buffers
1341          */
1342         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1343                 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1344                 if (error)
1345                         return error;
1346         }
1347         return 0;
1348 }
1349
1350 static void
1351 jme_dma_free(struct jme_softc *sc)
1352 {
1353         struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
1354         struct jme_txdesc *txd;
1355         struct jme_rxdesc *rxd;
1356         struct jme_rxdata *rdata;
1357         int i, r;
1358
1359         /* Tx ring */
1360         if (tdata->jme_tx_ring_tag != NULL) {
1361                 bus_dmamap_unload(tdata->jme_tx_ring_tag,
1362                     tdata->jme_tx_ring_map);
1363                 bus_dmamem_free(tdata->jme_tx_ring_tag,
1364                     tdata->jme_tx_ring, tdata->jme_tx_ring_map);
1365                 bus_dma_tag_destroy(tdata->jme_tx_ring_tag);
1366                 tdata->jme_tx_ring_tag = NULL;
1367         }
1368
1369         /* Rx ring */
1370         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1371                 rdata = &sc->jme_cdata.jme_rx_data[r];
1372                 if (rdata->jme_rx_ring_tag != NULL) {
1373                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1374                                           rdata->jme_rx_ring_map);
1375                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1376                                         rdata->jme_rx_ring,
1377                                         rdata->jme_rx_ring_map);
1378                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1379                         rdata->jme_rx_ring_tag = NULL;
1380                 }
1381         }
1382
1383         /* Tx buffers */
1384         if (tdata->jme_tx_tag != NULL) {
1385                 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
1386                         txd = &tdata->jme_txdesc[i];
1387                         bus_dmamap_destroy(tdata->jme_tx_tag, txd->tx_dmamap);
1388                 }
1389                 bus_dma_tag_destroy(tdata->jme_tx_tag);
1390                 tdata->jme_tx_tag = NULL;
1391         }
1392
1393         /* Rx buffers */
1394         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1395                 rdata = &sc->jme_cdata.jme_rx_data[r];
1396                 if (rdata->jme_rx_tag != NULL) {
1397                         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1398                                 rxd = &rdata->jme_rxdesc[i];
1399                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1400                                                    rxd->rx_dmamap);
1401                         }
1402                         bus_dmamap_destroy(rdata->jme_rx_tag,
1403                                            rdata->jme_rx_sparemap);
1404                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1405                         rdata->jme_rx_tag = NULL;
1406                 }
1407         }
1408
1409         /* Shadow status block. */
1410         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1411                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1412                     sc->jme_cdata.jme_ssb_map);
1413                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1414                     sc->jme_cdata.jme_ssb_block,
1415                     sc->jme_cdata.jme_ssb_map);
1416                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1417                 sc->jme_cdata.jme_ssb_tag = NULL;
1418         }
1419
1420         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1421                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1422                 sc->jme_cdata.jme_buffer_tag = NULL;
1423         }
1424         if (sc->jme_cdata.jme_ring_tag != NULL) {
1425                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1426                 sc->jme_cdata.jme_ring_tag = NULL;
1427         }
1428
1429         if (tdata->jme_txdesc != NULL) {
1430                 kfree(tdata->jme_txdesc, M_DEVBUF);
1431                 tdata->jme_txdesc = NULL;
1432         }
1433         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1434                 rdata = &sc->jme_cdata.jme_rx_data[r];
1435                 if (rdata->jme_rxdesc != NULL) {
1436                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1437                         rdata->jme_rxdesc = NULL;
1438                 }
1439         }
1440 }
1441
1442 /*
1443  *      Make sure the interface is stopped at reboot time.
1444  */
1445 static int
1446 jme_shutdown(device_t dev)
1447 {
1448         return jme_suspend(dev);
1449 }
1450
1451 #ifdef notyet
1452 /*
1453  * Unlike other ethernet controllers, JMC250 requires
1454  * explicit resetting link speed to 10/100Mbps as gigabit
1455  * link will cunsume more power than 375mA.
1456  * Note, we reset the link speed to 10/100Mbps with
1457  * auto-negotiation but we don't know whether that operation
1458  * would succeed or not as we have no control after powering
1459  * off. If the renegotiation fail WOL may not work. Running
1460  * at 1Gbps draws more power than 375mA at 3.3V which is
1461  * specified in PCI specification and that would result in
1462  * complete shutdowning power to ethernet controller.
1463  *
1464  * TODO
1465  *  Save current negotiated media speed/duplex/flow-control
1466  *  to softc and restore the same link again after resuming.
1467  *  PHY handling such as power down/resetting to 100Mbps
1468  *  may be better handled in suspend method in phy driver.
1469  */
1470 static void
1471 jme_setlinkspeed(struct jme_softc *sc)
1472 {
1473         struct mii_data *mii;
1474         int aneg, i;
1475
1476         JME_LOCK_ASSERT(sc);
1477
1478         mii = device_get_softc(sc->jme_miibus);
1479         mii_pollstat(mii);
1480         aneg = 0;
1481         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1482                 switch IFM_SUBTYPE(mii->mii_media_active) {
1483                 case IFM_10_T:
1484                 case IFM_100_TX:
1485                         return;
1486                 case IFM_1000_T:
1487                         aneg++;
1488                 default:
1489                         break;
1490                 }
1491         }
1492         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1493         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1494             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1495         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1496             BMCR_AUTOEN | BMCR_STARTNEG);
1497         DELAY(1000);
1498         if (aneg != 0) {
1499                 /* Poll link state until jme(4) get a 10/100 link. */
1500                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1501                         mii_pollstat(mii);
1502                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1503                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1504                                 case IFM_10_T:
1505                                 case IFM_100_TX:
1506                                         jme_mac_config(sc);
1507                                         return;
1508                                 default:
1509                                         break;
1510                                 }
1511                         }
1512                         JME_UNLOCK(sc);
1513                         pause("jmelnk", hz);
1514                         JME_LOCK(sc);
1515                 }
1516                 if (i == MII_ANEGTICKS_GIGE)
1517                         device_printf(sc->jme_dev, "establishing link failed, "
1518                             "WOL may not work!");
1519         }
1520         /*
1521          * No link, force MAC to have 100Mbps, full-duplex link.
1522          * This is the last resort and may/may not work.
1523          */
1524         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1525         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1526         jme_mac_config(sc);
1527 }
1528
1529 static void
1530 jme_setwol(struct jme_softc *sc)
1531 {
1532         struct ifnet *ifp = &sc->arpcom.ac_if;
1533         uint32_t gpr, pmcs;
1534         uint16_t pmstat;
1535         int pmc;
1536
1537         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1538                 /* No PME capability, PHY power down. */
1539                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1540                     MII_BMCR, BMCR_PDOWN);
1541                 return;
1542         }
1543
1544         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1545         pmcs = CSR_READ_4(sc, JME_PMCS);
1546         pmcs &= ~PMCS_WOL_ENB_MASK;
1547         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1548                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1549                 /* Enable PME message. */
1550                 gpr |= GPREG0_PME_ENB;
1551                 /* For gigabit controllers, reset link speed to 10/100. */
1552                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1553                         jme_setlinkspeed(sc);
1554         }
1555
1556         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1557         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1558
1559         /* Request PME. */
1560         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1561         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1562         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1563                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1564         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1565         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1566                 /* No WOL, PHY power down. */
1567                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1568                     MII_BMCR, BMCR_PDOWN);
1569         }
1570 }
1571 #endif
1572
1573 static int
1574 jme_suspend(device_t dev)
1575 {
1576         struct jme_softc *sc = device_get_softc(dev);
1577         struct ifnet *ifp = &sc->arpcom.ac_if;
1578
1579         ifnet_serialize_all(ifp);
1580         jme_stop(sc);
1581 #ifdef notyet
1582         jme_setwol(sc);
1583 #endif
1584         ifnet_deserialize_all(ifp);
1585
1586         return (0);
1587 }
1588
1589 static int
1590 jme_resume(device_t dev)
1591 {
1592         struct jme_softc *sc = device_get_softc(dev);
1593         struct ifnet *ifp = &sc->arpcom.ac_if;
1594 #ifdef notyet
1595         int pmc;
1596 #endif
1597
1598         ifnet_serialize_all(ifp);
1599
1600 #ifdef notyet
1601         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1602                 uint16_t pmstat;
1603
1604                 pmstat = pci_read_config(sc->jme_dev,
1605                     pmc + PCIR_POWER_STATUS, 2);
1606                 /* Disable PME clear PME status. */
1607                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1608                 pci_write_config(sc->jme_dev,
1609                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1610         }
1611 #endif
1612
1613         if (ifp->if_flags & IFF_UP)
1614                 jme_init(sc);
1615
1616         ifnet_deserialize_all(ifp);
1617
1618         return (0);
1619 }
1620
1621 static __inline int
1622 jme_tso_pullup(struct mbuf **mp)
1623 {
1624         int hoff, iphlen, thoff;
1625         struct mbuf *m;
1626
1627         m = *mp;
1628         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
1629
1630         iphlen = m->m_pkthdr.csum_iphlen;
1631         thoff = m->m_pkthdr.csum_thlen;
1632         hoff = m->m_pkthdr.csum_lhlen;
1633
1634         KASSERT(iphlen > 0, ("invalid ip hlen"));
1635         KASSERT(thoff > 0, ("invalid tcp hlen"));
1636         KASSERT(hoff > 0, ("invalid ether hlen"));
1637
1638         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
1639                 m = m_pullup(m, hoff + iphlen + thoff);
1640                 if (m == NULL) {
1641                         *mp = NULL;
1642                         return ENOBUFS;
1643                 }
1644                 *mp = m;
1645         }
1646         return 0;
1647 }
1648
1649 static int
1650 jme_encap(struct jme_txdata *tdata, struct mbuf **m_head)
1651 {
1652         struct jme_txdesc *txd;
1653         struct jme_desc *desc;
1654         struct mbuf *m;
1655         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1656         int maxsegs, nsegs;
1657         int error, i, prod, symbol_desc;
1658         uint32_t cflags, flag64, mss;
1659
1660         M_ASSERTPKTHDR((*m_head));
1661
1662         if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) {
1663                 /* XXX Is this necessary? */
1664                 error = jme_tso_pullup(m_head);
1665                 if (error)
1666                         return error;
1667         }
1668
1669         prod = tdata->jme_tx_prod;
1670         txd = &tdata->jme_txdesc[prod];
1671
1672         if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1673                 symbol_desc = 1;
1674         else
1675                 symbol_desc = 0;
1676
1677         maxsegs = (tdata->jme_tx_desc_cnt - tdata->jme_tx_cnt) -
1678                   (JME_TXD_RSVD + symbol_desc);
1679         if (maxsegs > JME_MAXTXSEGS)
1680                 maxsegs = JME_MAXTXSEGS;
1681         KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc),
1682                 ("not enough segments %d", maxsegs));
1683
1684         error = bus_dmamap_load_mbuf_defrag(tdata->jme_tx_tag,
1685                         txd->tx_dmamap, m_head,
1686                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1687         if (error)
1688                 goto fail;
1689
1690         bus_dmamap_sync(tdata->jme_tx_tag, txd->tx_dmamap,
1691                         BUS_DMASYNC_PREWRITE);
1692
1693         m = *m_head;
1694         cflags = 0;
1695         mss = 0;
1696
1697         /* Configure checksum offload. */
1698         if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1699                 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT;
1700                 cflags |= JME_TD_TSO;
1701         } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) {
1702                 if (m->m_pkthdr.csum_flags & CSUM_IP)
1703                         cflags |= JME_TD_IPCSUM;
1704                 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1705                         cflags |= JME_TD_TCPCSUM;
1706                 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1707                         cflags |= JME_TD_UDPCSUM;
1708         }
1709
1710         /* Configure VLAN. */
1711         if (m->m_flags & M_VLANTAG) {
1712                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1713                 cflags |= JME_TD_VLAN_TAG;
1714         }
1715
1716         desc = &tdata->jme_tx_ring[prod];
1717         desc->flags = htole32(cflags);
1718         desc->addr_hi = htole32(m->m_pkthdr.len);
1719         if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1720                 /*
1721                  * Use 64bits TX desc chain format.
1722                  *
1723                  * The first TX desc of the chain, which is setup here,
1724                  * is just a symbol TX desc carrying no payload.
1725                  */
1726                 flag64 = JME_TD_64BIT;
1727                 desc->buflen = htole32(mss);
1728                 desc->addr_lo = 0;
1729
1730                 /* No effective TX desc is consumed */
1731                 i = 0;
1732         } else {
1733                 /*
1734                  * Use 32bits TX desc chain format.
1735                  *
1736                  * The first TX desc of the chain, which is setup here,
1737                  * is an effective TX desc carrying the first segment of
1738                  * the mbuf chain.
1739                  */
1740                 flag64 = 0;
1741                 desc->buflen = htole32(mss | txsegs[0].ds_len);
1742                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1743
1744                 /* One effective TX desc is consumed */
1745                 i = 1;
1746         }
1747         tdata->jme_tx_cnt++;
1748         KKASSERT(tdata->jme_tx_cnt - i < tdata->jme_tx_desc_cnt - JME_TXD_RSVD);
1749         JME_DESC_INC(prod, tdata->jme_tx_desc_cnt);
1750
1751         txd->tx_ndesc = 1 - i;
1752         for (; i < nsegs; i++) {
1753                 desc = &tdata->jme_tx_ring[prod];
1754                 desc->buflen = htole32(txsegs[i].ds_len);
1755                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1756                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1757                 desc->flags = htole32(JME_TD_OWN | flag64);
1758
1759                 tdata->jme_tx_cnt++;
1760                 KKASSERT(tdata->jme_tx_cnt <=
1761                          tdata->jme_tx_desc_cnt - JME_TXD_RSVD);
1762                 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt);
1763         }
1764
1765         /* Update producer index. */
1766         tdata->jme_tx_prod = prod;
1767         /*
1768          * Finally request interrupt and give the first descriptor
1769          * owenership to hardware.
1770          */
1771         desc = txd->tx_desc;
1772         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1773
1774         txd->tx_m = m;
1775         txd->tx_ndesc += nsegs;
1776
1777         return 0;
1778 fail:
1779         m_freem(*m_head);
1780         *m_head = NULL;
1781         return error;
1782 }
1783
1784 static void
1785 jme_start(struct ifnet *ifp)
1786 {
1787         struct jme_softc *sc = ifp->if_softc;
1788         struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
1789         struct mbuf *m_head;
1790         int enq = 0;
1791
1792         ASSERT_SERIALIZED(&tdata->jme_tx_serialize);
1793
1794         if (!sc->jme_has_link) {
1795                 ifq_purge(&ifp->if_snd);
1796                 return;
1797         }
1798
1799         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1800                 return;
1801
1802         if (tdata->jme_tx_cnt >= JME_TX_DESC_HIWAT(tdata))
1803                 jme_txeof(tdata);
1804
1805         while (!ifq_is_empty(&ifp->if_snd)) {
1806                 /*
1807                  * Check number of available TX descs, always
1808                  * leave JME_TXD_RSVD free TX descs.
1809                  */
1810                 if (tdata->jme_tx_cnt + JME_TXD_SPARE >
1811                     tdata->jme_tx_desc_cnt - JME_TXD_RSVD) {
1812                         ifp->if_flags |= IFF_OACTIVE;
1813                         break;
1814                 }
1815
1816                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1817                 if (m_head == NULL)
1818                         break;
1819
1820                 /*
1821                  * Pack the data into the transmit ring. If we
1822                  * don't have room, set the OACTIVE flag and wait
1823                  * for the NIC to drain the ring.
1824                  */
1825                 if (jme_encap(tdata, &m_head)) {
1826                         KKASSERT(m_head == NULL);
1827                         ifp->if_oerrors++;
1828                         ifp->if_flags |= IFF_OACTIVE;
1829                         break;
1830                 }
1831                 enq++;
1832
1833                 /*
1834                  * If there's a BPF listener, bounce a copy of this frame
1835                  * to him.
1836                  */
1837                 ETHER_BPF_MTAP(ifp, m_head);
1838         }
1839
1840         if (enq > 0) {
1841                 /*
1842                  * Reading TXCSR takes very long time under heavy load
1843                  * so cache TXCSR value and writes the ORed value with
1844                  * the kick command to the TXCSR. This saves one register
1845                  * access cycle.
1846                  */
1847                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1848                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1849                 /* Set a timeout in case the chip goes out to lunch. */
1850                 ifp->if_timer = JME_TX_TIMEOUT;
1851         }
1852 }
1853
1854 static void
1855 jme_watchdog(struct ifnet *ifp)
1856 {
1857         struct jme_softc *sc = ifp->if_softc;
1858         struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
1859
1860         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1861
1862         if (!sc->jme_has_link) {
1863                 if_printf(ifp, "watchdog timeout (missed link)\n");
1864                 ifp->if_oerrors++;
1865                 jme_init(sc);
1866                 return;
1867         }
1868
1869         jme_txeof(tdata);
1870         if (tdata->jme_tx_cnt == 0) {
1871                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1872                           "-- recovering\n");
1873                 if (!ifq_is_empty(&ifp->if_snd))
1874                         if_devstart(ifp);
1875                 return;
1876         }
1877
1878         if_printf(ifp, "watchdog timeout\n");
1879         ifp->if_oerrors++;
1880         jme_init(sc);
1881         if (!ifq_is_empty(&ifp->if_snd))
1882                 if_devstart(ifp);
1883 }
1884
1885 static int
1886 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1887 {
1888         struct jme_softc *sc = ifp->if_softc;
1889         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1890         struct ifreq *ifr = (struct ifreq *)data;
1891         int error = 0, mask;
1892
1893         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1894
1895         switch (cmd) {
1896         case SIOCSIFMTU:
1897                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1898                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1899                      ifr->ifr_mtu > JME_MAX_MTU)) {
1900                         error = EINVAL;
1901                         break;
1902                 }
1903
1904                 if (ifp->if_mtu != ifr->ifr_mtu) {
1905                         /*
1906                          * No special configuration is required when interface
1907                          * MTU is changed but availability of Tx checksum
1908                          * offload should be chcked against new MTU size as
1909                          * FIFO size is just 2K.
1910                          */
1911                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1912                                 ifp->if_capenable &=
1913                                     ~(IFCAP_TXCSUM | IFCAP_TSO);
1914                                 ifp->if_hwassist &=
1915                                     ~(JME_CSUM_FEATURES | CSUM_TSO);
1916                         }
1917                         ifp->if_mtu = ifr->ifr_mtu;
1918                         if (ifp->if_flags & IFF_RUNNING)
1919                                 jme_init(sc);
1920                 }
1921                 break;
1922
1923         case SIOCSIFFLAGS:
1924                 if (ifp->if_flags & IFF_UP) {
1925                         if (ifp->if_flags & IFF_RUNNING) {
1926                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1927                                     (IFF_PROMISC | IFF_ALLMULTI))
1928                                         jme_set_filter(sc);
1929                         } else {
1930                                 jme_init(sc);
1931                         }
1932                 } else {
1933                         if (ifp->if_flags & IFF_RUNNING)
1934                                 jme_stop(sc);
1935                 }
1936                 sc->jme_if_flags = ifp->if_flags;
1937                 break;
1938
1939         case SIOCADDMULTI:
1940         case SIOCDELMULTI:
1941                 if (ifp->if_flags & IFF_RUNNING)
1942                         jme_set_filter(sc);
1943                 break;
1944
1945         case SIOCSIFMEDIA:
1946         case SIOCGIFMEDIA:
1947                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1948                 break;
1949
1950         case SIOCSIFCAP:
1951                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1952
1953                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1954                         ifp->if_capenable ^= IFCAP_TXCSUM;
1955                         if (ifp->if_capenable & IFCAP_TXCSUM)
1956                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1957                         else
1958                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1959                 }
1960                 if (mask & IFCAP_RXCSUM) {
1961                         uint32_t reg;
1962
1963                         ifp->if_capenable ^= IFCAP_RXCSUM;
1964                         reg = CSR_READ_4(sc, JME_RXMAC);
1965                         reg &= ~RXMAC_CSUM_ENB;
1966                         if (ifp->if_capenable & IFCAP_RXCSUM)
1967                                 reg |= RXMAC_CSUM_ENB;
1968                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1969                 }
1970
1971                 if (mask & IFCAP_VLAN_HWTAGGING) {
1972                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1973                         jme_set_vlan(sc);
1974                 }
1975
1976                 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1977                         ifp->if_capenable ^= IFCAP_TSO;
1978                         if (ifp->if_capenable & IFCAP_TSO)
1979                                 ifp->if_hwassist |= CSUM_TSO;
1980                         else
1981                                 ifp->if_hwassist &= ~CSUM_TSO;
1982                 }
1983
1984                 if (mask & IFCAP_RSS)
1985                         ifp->if_capenable ^= IFCAP_RSS;
1986                 break;
1987
1988         default:
1989                 error = ether_ioctl(ifp, cmd, data);
1990                 break;
1991         }
1992         return (error);
1993 }
1994
1995 static void
1996 jme_mac_config(struct jme_softc *sc)
1997 {
1998         struct mii_data *mii;
1999         uint32_t ghc, rxmac, txmac, txpause, gp1;
2000         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
2001
2002         mii = device_get_softc(sc->jme_miibus);
2003
2004         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2005         DELAY(10);
2006         CSR_WRITE_4(sc, JME_GHC, 0);
2007         ghc = 0;
2008         rxmac = CSR_READ_4(sc, JME_RXMAC);
2009         rxmac &= ~RXMAC_FC_ENB;
2010         txmac = CSR_READ_4(sc, JME_TXMAC);
2011         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2012         txpause = CSR_READ_4(sc, JME_TXPFC);
2013         txpause &= ~TXPFC_PAUSE_ENB;
2014         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2015                 ghc |= GHC_FULL_DUPLEX;
2016                 rxmac &= ~RXMAC_COLL_DET_ENB;
2017                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2018                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2019                     TXMAC_FRAME_BURST);
2020 #ifdef notyet
2021                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2022                         txpause |= TXPFC_PAUSE_ENB;
2023                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2024                         rxmac |= RXMAC_FC_ENB;
2025 #endif
2026                 /* Disable retry transmit timer/retry limit. */
2027                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2028                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2029         } else {
2030                 rxmac |= RXMAC_COLL_DET_ENB;
2031                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2032                 /* Enable retry transmit timer/retry limit. */
2033                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2034                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2035         }
2036
2037         /*
2038          * Reprogram Tx/Rx MACs with resolved speed/duplex.
2039          */
2040         gp1 = CSR_READ_4(sc, JME_GPREG1);
2041         gp1 &= ~GPREG1_WA_HDX;
2042
2043         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2044                 hdx = 1;
2045
2046         switch (IFM_SUBTYPE(mii->mii_media_active)) {
2047         case IFM_10_T:
2048                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
2049                 if (hdx)
2050                         gp1 |= GPREG1_WA_HDX;
2051                 break;
2052
2053         case IFM_100_TX:
2054                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
2055                 if (hdx)
2056                         gp1 |= GPREG1_WA_HDX;
2057
2058                 /*
2059                  * Use extended FIFO depth to workaround CRC errors
2060                  * emitted by chips before JMC250B
2061                  */
2062                 phyconf = JMPHY_CONF_EXTFIFO;
2063                 break;
2064
2065         case IFM_1000_T:
2066                 if (sc->jme_caps & JME_CAP_FASTETH)
2067                         break;
2068
2069                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
2070                 if (hdx)
2071                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2072                 break;
2073
2074         default:
2075                 break;
2076         }
2077         CSR_WRITE_4(sc, JME_GHC, ghc);
2078         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2079         CSR_WRITE_4(sc, JME_TXMAC, txmac);
2080         CSR_WRITE_4(sc, JME_TXPFC, txpause);
2081
2082         if (sc->jme_workaround & JME_WA_EXTFIFO) {
2083                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2084                                     JMPHY_CONF, phyconf);
2085         }
2086         if (sc->jme_workaround & JME_WA_HDX)
2087                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
2088 }
2089
2090 static void
2091 jme_intr(void *xsc)
2092 {
2093         struct jme_softc *sc = xsc;
2094         struct ifnet *ifp = &sc->arpcom.ac_if;
2095         uint32_t status;
2096         int r;
2097
2098         ASSERT_SERIALIZED(&sc->jme_serialize);
2099
2100         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2101         if (status == 0 || status == 0xFFFFFFFF)
2102                 return;
2103
2104         /* Disable interrupts. */
2105         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2106
2107         status = CSR_READ_4(sc, JME_INTR_STATUS);
2108         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2109                 goto back;
2110
2111         /* Reset PCC counter/timer and Ack interrupts. */
2112         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2113
2114         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
2115                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2116
2117         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2118                 if (status & jme_rx_status[r].jme_coal) {
2119                         status |= jme_rx_status[r].jme_coal |
2120                                   jme_rx_status[r].jme_comp;
2121                 }
2122         }
2123
2124         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2125
2126         if (ifp->if_flags & IFF_RUNNING) {
2127                 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
2128
2129                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
2130                         jme_rx_intr(sc, status);
2131
2132                 if (status & INTR_RXQ_DESC_EMPTY) {
2133                         /*
2134                          * Notify hardware availability of new Rx buffers.
2135                          * Reading RXCSR takes very long time under heavy
2136                          * load so cache RXCSR value and writes the ORed
2137                          * value with the kick command to the RXCSR. This
2138                          * saves one register access cycle.
2139                          */
2140                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2141                             RXCSR_RX_ENB | RXCSR_RXQ_START);
2142                 }
2143
2144                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
2145                         lwkt_serialize_enter(&tdata->jme_tx_serialize);
2146                         jme_txeof(tdata);
2147                         if (!ifq_is_empty(&ifp->if_snd))
2148                                 if_devstart(ifp);
2149                         lwkt_serialize_exit(&tdata->jme_tx_serialize);
2150                 }
2151         }
2152 back:
2153         /* Reenable interrupts. */
2154         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2155 }
2156
2157 static void
2158 jme_txeof(struct jme_txdata *tdata)
2159 {
2160         struct ifnet *ifp = &tdata->jme_sc->arpcom.ac_if;
2161         int cons;
2162
2163         cons = tdata->jme_tx_cons;
2164         if (cons == tdata->jme_tx_prod)
2165                 return;
2166
2167         /*
2168          * Go through our Tx list and free mbufs for those
2169          * frames which have been transmitted.
2170          */
2171         while (cons != tdata->jme_tx_prod) {
2172                 struct jme_txdesc *txd, *next_txd;
2173                 uint32_t status, next_status;
2174                 int next_cons, nsegs;
2175
2176                 txd = &tdata->jme_txdesc[cons];
2177                 KASSERT(txd->tx_m != NULL,
2178                         ("%s: freeing NULL mbuf!", __func__));
2179
2180                 status = le32toh(txd->tx_desc->flags);
2181                 if ((status & JME_TD_OWN) == JME_TD_OWN)
2182                         break;
2183
2184                 /*
2185                  * NOTE:
2186                  * This chip will always update the TX descriptor's
2187                  * buflen field and this updating always happens
2188                  * after clearing the OWN bit, so even if the OWN
2189                  * bit is cleared by the chip, we still don't sure
2190                  * about whether the buflen field has been updated
2191                  * by the chip or not.  To avoid this race, we wait
2192                  * for the next TX descriptor's OWN bit to be cleared
2193                  * by the chip before reusing this TX descriptor.
2194                  */
2195                 next_cons = cons;
2196                 JME_DESC_ADD(next_cons, txd->tx_ndesc, tdata->jme_tx_desc_cnt);
2197                 next_txd = &tdata->jme_txdesc[next_cons];
2198                 if (next_txd->tx_m == NULL)
2199                         break;
2200                 next_status = le32toh(next_txd->tx_desc->flags);
2201                 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2202                         break;
2203
2204                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2205                         ifp->if_oerrors++;
2206                 } else {
2207                         ifp->if_opackets++;
2208                         if (status & JME_TD_COLLISION) {
2209                                 ifp->if_collisions +=
2210                                     le32toh(txd->tx_desc->buflen) &
2211                                     JME_TD_BUF_LEN_MASK;
2212                         }
2213                 }
2214
2215                 /*
2216                  * Only the first descriptor of multi-descriptor
2217                  * transmission is updated so driver have to skip entire
2218                  * chained buffers for the transmiited frame. In other
2219                  * words, JME_TD_OWN bit is valid only at the first
2220                  * descriptor of a multi-descriptor transmission.
2221                  */
2222                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2223                         tdata->jme_tx_ring[cons].flags = 0;
2224                         JME_DESC_INC(cons, tdata->jme_tx_desc_cnt);
2225                 }
2226
2227                 /* Reclaim transferred mbufs. */
2228                 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap);
2229                 m_freem(txd->tx_m);
2230                 txd->tx_m = NULL;
2231                 tdata->jme_tx_cnt -= txd->tx_ndesc;
2232                 KASSERT(tdata->jme_tx_cnt >= 0,
2233                         ("%s: Active Tx desc counter was garbled", __func__));
2234                 txd->tx_ndesc = 0;
2235         }
2236         tdata->jme_tx_cons = cons;
2237
2238         /* 1 for symbol TX descriptor */
2239         if (tdata->jme_tx_cnt <= JME_MAXTXSEGS + 1)
2240                 ifp->if_timer = 0;
2241
2242         if (tdata->jme_tx_cnt + JME_TXD_SPARE <=
2243             tdata->jme_tx_desc_cnt - JME_TXD_RSVD)
2244                 ifp->if_flags &= ~IFF_OACTIVE;
2245 }
2246
2247 static __inline void
2248 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2249 {
2250         int i;
2251
2252         for (i = 0; i < count; ++i) {
2253                 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2254                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2255         }
2256 }
2257
2258 static __inline struct pktinfo *
2259 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2260 {
2261         if (flags & JME_RD_IPV4)
2262                 pi->pi_netisr = NETISR_IP;
2263         else if (flags & JME_RD_IPV6)
2264                 pi->pi_netisr = NETISR_IPV6;
2265         else
2266                 return NULL;
2267
2268         pi->pi_flags = 0;
2269         pi->pi_l3proto = IPPROTO_UNKNOWN;
2270
2271         if (flags & JME_RD_MORE_FRAG)
2272                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2273         else if (flags & JME_RD_TCP)
2274                 pi->pi_l3proto = IPPROTO_TCP;
2275         else if (flags & JME_RD_UDP)
2276                 pi->pi_l3proto = IPPROTO_UDP;
2277         else
2278                 pi = NULL;
2279         return pi;
2280 }
2281
2282 /* Receive a frame. */
2283 static void
2284 jme_rxpkt(struct jme_rxdata *rdata)
2285 {
2286         struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2287         struct jme_desc *desc;
2288         struct jme_rxdesc *rxd;
2289         struct mbuf *mp, *m;
2290         uint32_t flags, status, hash, hashinfo;
2291         int cons, count, nsegs;
2292
2293         cons = rdata->jme_rx_cons;
2294         desc = &rdata->jme_rx_ring[cons];
2295
2296         flags = le32toh(desc->flags);
2297         status = le32toh(desc->buflen);
2298         hash = le32toh(desc->addr_hi);
2299         hashinfo = le32toh(desc->addr_lo);
2300         nsegs = JME_RX_NSEGS(status);
2301
2302         if (nsegs > 1) {
2303                 /* Skip the first descriptor. */
2304                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2305
2306                 /*
2307                  * Clear the OWN bit of the following RX descriptors;
2308                  * hardware will not clear the OWN bit except the first
2309                  * RX descriptor.
2310                  *
2311                  * Since the first RX descriptor is setup, i.e. OWN bit
2312                  * on, before its followins RX descriptors, leaving the
2313                  * OWN bit on the following RX descriptors will trick
2314                  * the hardware into thinking that the following RX
2315                  * descriptors are ready to be used too.
2316                  */
2317                 for (count = 1; count < nsegs; count++,
2318                      JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2319                         rdata->jme_rx_ring[cons].flags = 0;
2320
2321                 cons = rdata->jme_rx_cons;
2322         }
2323
2324         JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2325                         "hash 0x%08x, hash info 0x%08x\n",
2326                         rdata->jme_rx_idx, flags, hash, hashinfo);
2327
2328         if (status & JME_RX_ERR_STAT) {
2329                 ifp->if_ierrors++;
2330                 jme_discard_rxbufs(rdata, cons, nsegs);
2331 #ifdef JME_SHOW_ERRORS
2332                 if_printf(ifp, "%s : receive error = 0x%b\n",
2333                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2334 #endif
2335                 rdata->jme_rx_cons += nsegs;
2336                 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2337                 return;
2338         }
2339
2340         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2341         for (count = 0; count < nsegs; count++,
2342              JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2343                 rxd = &rdata->jme_rxdesc[cons];
2344                 mp = rxd->rx_m;
2345
2346                 /* Add a new receive buffer to the ring. */
2347                 if (jme_newbuf(rdata, rxd, 0) != 0) {
2348                         ifp->if_iqdrops++;
2349                         /* Reuse buffer. */
2350                         jme_discard_rxbufs(rdata, cons, nsegs - count);
2351                         if (rdata->jme_rxhead != NULL) {
2352                                 m_freem(rdata->jme_rxhead);
2353                                 JME_RXCHAIN_RESET(rdata);
2354                         }
2355                         break;
2356                 }
2357
2358                 /*
2359                  * Assume we've received a full sized frame.
2360                  * Actual size is fixed when we encounter the end of
2361                  * multi-segmented frame.
2362                  */
2363                 mp->m_len = MCLBYTES;
2364
2365                 /* Chain received mbufs. */
2366                 if (rdata->jme_rxhead == NULL) {
2367                         rdata->jme_rxhead = mp;
2368                         rdata->jme_rxtail = mp;
2369                 } else {
2370                         /*
2371                          * Receive processor can receive a maximum frame
2372                          * size of 65535 bytes.
2373                          */
2374                         rdata->jme_rxtail->m_next = mp;
2375                         rdata->jme_rxtail = mp;
2376                 }
2377
2378                 if (count == nsegs - 1) {
2379                         struct pktinfo pi0, *pi;
2380
2381                         /* Last desc. for this frame. */
2382                         m = rdata->jme_rxhead;
2383                         m->m_pkthdr.len = rdata->jme_rxlen;
2384                         if (nsegs > 1) {
2385                                 /* Set first mbuf size. */
2386                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2387                                 /* Set last mbuf size. */
2388                                 mp->m_len = rdata->jme_rxlen -
2389                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2390                                     (MCLBYTES * (nsegs - 2)));
2391                         } else {
2392                                 m->m_len = rdata->jme_rxlen;
2393                         }
2394                         m->m_pkthdr.rcvif = ifp;
2395
2396                         /*
2397                          * Account for 10bytes auto padding which is used
2398                          * to align IP header on 32bit boundary. Also note,
2399                          * CRC bytes is automatically removed by the
2400                          * hardware.
2401                          */
2402                         m->m_data += JME_RX_PAD_BYTES;
2403
2404                         /* Set checksum information. */
2405                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2406                             (flags & JME_RD_IPV4)) {
2407                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2408                                 if (flags & JME_RD_IPCSUM)
2409                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2410                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2411                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2412                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2413                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2414                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2415                                         m->m_pkthdr.csum_flags |=
2416                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2417                                         m->m_pkthdr.csum_data = 0xffff;
2418                                 }
2419                         }
2420
2421                         /* Check for VLAN tagged packets. */
2422                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2423                             (flags & JME_RD_VLAN_TAG)) {
2424                                 m->m_pkthdr.ether_vlantag =
2425                                     flags & JME_RD_VLAN_MASK;
2426                                 m->m_flags |= M_VLANTAG;
2427                         }
2428
2429                         ifp->if_ipackets++;
2430
2431                         if (ifp->if_capenable & IFCAP_RSS)
2432                                 pi = jme_pktinfo(&pi0, flags);
2433                         else
2434                                 pi = NULL;
2435
2436                         if (pi != NULL &&
2437                             (hashinfo & JME_RD_HASH_FN_MASK) ==
2438                             JME_RD_HASH_FN_TOEPLITZ) {
2439                                 m->m_flags |= (M_HASH | M_CKHASH);
2440                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2441                         }
2442
2443 #ifdef JME_RSS_DEBUG
2444                         if (pi != NULL) {
2445                                 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2446                                     "isr %d flags %08x, l3 %d %s\n",
2447                                     pi->pi_netisr, pi->pi_flags,
2448                                     pi->pi_l3proto,
2449                                     (m->m_flags & M_HASH) ? "hash" : "");
2450                         }
2451 #endif
2452
2453                         /* Pass it on. */
2454                         ether_input_pkt(ifp, m, pi);
2455
2456                         /* Reset mbuf chains. */
2457                         JME_RXCHAIN_RESET(rdata);
2458 #ifdef JME_RSS_DEBUG
2459                         rdata->jme_rx_pkt++;
2460 #endif
2461                 }
2462         }
2463
2464         rdata->jme_rx_cons += nsegs;
2465         rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2466 }
2467
2468 static void
2469 jme_rxeof(struct jme_rxdata *rdata, int count)
2470 {
2471         struct jme_desc *desc;
2472         int nsegs, pktlen;
2473
2474         for (;;) {
2475 #ifdef IFPOLL_ENABLE
2476                 if (count >= 0 && count-- == 0)
2477                         break;
2478 #endif
2479                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2480                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2481                         break;
2482                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2483                         break;
2484
2485                 /*
2486                  * Check number of segments against received bytes.
2487                  * Non-matching value would indicate that hardware
2488                  * is still trying to update Rx descriptors. I'm not
2489                  * sure whether this check is needed.
2490                  */
2491                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2492                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2493                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2494                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2495                             "RX fragment count(%d) and "
2496                             "packet size(%d) mismach\n", nsegs, pktlen);
2497                         break;
2498                 }
2499
2500                 /*
2501                  * NOTE:
2502                  * RSS hash and hash information may _not_ be set by the
2503                  * hardware even if the OWN bit is cleared and VALID bit
2504                  * is set.
2505                  *
2506                  * If the RSS information is not delivered by the hardware
2507                  * yet, we MUST NOT accept this packet, let alone reusing
2508                  * its RX descriptor.  If this packet was accepted and its
2509                  * RX descriptor was reused before hardware delivering the
2510                  * RSS information, the RX buffer's address would be trashed
2511                  * by the RSS information delivered by the hardware.
2512                  */
2513                 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2514                         struct jme_rxdesc *rxd;
2515                         uint32_t hashinfo;
2516
2517                         hashinfo = le32toh(desc->addr_lo);
2518                         rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2519
2520                         /*
2521                          * This test should be enough to detect the pending
2522                          * RSS information delivery, given:
2523                          * - If RSS hash is not calculated, the hashinfo
2524                          *   will be 0.  Howvever, the lower 32bits of RX
2525                          *   buffers' physical address will never be 0.
2526                          *   (see jme_rxbuf_dma_filter)
2527                          * - If RSS hash is calculated, the lowest 4 bits
2528                          *   of hashinfo will be set, while the RX buffers
2529                          *   are at least 2K aligned.
2530                          */
2531                         if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2532 #ifdef JME_SHOW_RSSWB
2533                                 if_printf(&rdata->jme_sc->arpcom.ac_if,
2534                                     "RSS is not written back yet\n");
2535 #endif
2536                                 break;
2537                         }
2538                 }
2539
2540                 /* Received a frame. */
2541                 jme_rxpkt(rdata);
2542         }
2543 }
2544
2545 static void
2546 jme_tick(void *xsc)
2547 {
2548         struct jme_softc *sc = xsc;
2549         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2550
2551         lwkt_serialize_enter(&sc->jme_serialize);
2552
2553         sc->jme_in_tick = TRUE;
2554         mii_tick(mii);
2555         sc->jme_in_tick = FALSE;
2556
2557         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2558
2559         lwkt_serialize_exit(&sc->jme_serialize);
2560 }
2561
2562 static void
2563 jme_reset(struct jme_softc *sc)
2564 {
2565         uint32_t val;
2566
2567         /* Make sure that TX and RX are stopped */
2568         jme_stop_tx(sc);
2569         jme_stop_rx(sc);
2570
2571         /* Start reset */
2572         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2573         DELAY(20);
2574
2575         /*
2576          * Hold reset bit before stop reset
2577          */
2578
2579         /* Disable TXMAC and TXOFL clock sources */
2580         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2581         /* Disable RXMAC clock source */
2582         val = CSR_READ_4(sc, JME_GPREG1);
2583         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2584         /* Flush */
2585         CSR_READ_4(sc, JME_GHC);
2586
2587         /* Stop reset */
2588         CSR_WRITE_4(sc, JME_GHC, 0);
2589         /* Flush */
2590         CSR_READ_4(sc, JME_GHC);
2591
2592         /*
2593          * Clear reset bit after stop reset
2594          */
2595
2596         /* Enable TXMAC and TXOFL clock sources */
2597         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2598         /* Enable RXMAC clock source */
2599         val = CSR_READ_4(sc, JME_GPREG1);
2600         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2601         /* Flush */
2602         CSR_READ_4(sc, JME_GHC);
2603
2604         /* Disable TXMAC and TXOFL clock sources */
2605         CSR_WRITE_4(sc, JME_GHC, 0);
2606         /* Disable RXMAC clock source */
2607         val = CSR_READ_4(sc, JME_GPREG1);
2608         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2609         /* Flush */
2610         CSR_READ_4(sc, JME_GHC);
2611
2612         /* Enable TX and RX */
2613         val = CSR_READ_4(sc, JME_TXCSR);
2614         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2615         val = CSR_READ_4(sc, JME_RXCSR);
2616         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2617         /* Flush */
2618         CSR_READ_4(sc, JME_TXCSR);
2619         CSR_READ_4(sc, JME_RXCSR);
2620
2621         /* Enable TXMAC and TXOFL clock sources */
2622         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2623         /* Eisable RXMAC clock source */
2624         val = CSR_READ_4(sc, JME_GPREG1);
2625         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2626         /* Flush */
2627         CSR_READ_4(sc, JME_GHC);
2628
2629         /* Stop TX and RX */
2630         jme_stop_tx(sc);
2631         jme_stop_rx(sc);
2632 }
2633
2634 static void
2635 jme_init(void *xsc)
2636 {
2637         struct jme_softc *sc = xsc;
2638         struct ifnet *ifp = &sc->arpcom.ac_if;
2639         struct mii_data *mii;
2640         uint8_t eaddr[ETHER_ADDR_LEN];
2641         bus_addr_t paddr;
2642         uint32_t reg;
2643         int error, r;
2644
2645         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2646
2647         /*
2648          * Cancel any pending I/O.
2649          */
2650         jme_stop(sc);
2651
2652         /*
2653          * Reset the chip to a known state.
2654          */
2655         jme_reset(sc);
2656
2657         /*
2658          * Setup MSI/MSI-X vectors to interrupts mapping
2659          */
2660         jme_set_msinum(sc);
2661
2662         if (JME_ENABLE_HWRSS(sc))
2663                 jme_enable_rss(sc);
2664         else
2665                 jme_disable_rss(sc);
2666
2667         /* Init RX descriptors */
2668         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2669                 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2670                 if (error) {
2671                         if_printf(ifp, "initialization failed: "
2672                                   "no memory for %dth RX ring.\n", r);
2673                         jme_stop(sc);
2674                         return;
2675                 }
2676         }
2677
2678         /* Init TX descriptors */
2679         jme_init_tx_ring(&sc->jme_cdata.jme_tx_data);
2680
2681         /* Initialize shadow status block. */
2682         jme_init_ssb(sc);
2683
2684         /* Reprogram the station address. */
2685         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2686         CSR_WRITE_4(sc, JME_PAR0,
2687             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2688         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2689
2690         /*
2691          * Configure Tx queue.
2692          *  Tx priority queue weight value : 0
2693          *  Tx FIFO threshold for processing next packet : 16QW
2694          *  Maximum Tx DMA length : 512
2695          *  Allow Tx DMA burst.
2696          */
2697         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2698         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2699         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2700         sc->jme_txcsr |= sc->jme_tx_dma_size;
2701         sc->jme_txcsr |= TXCSR_DMA_BURST;
2702         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2703
2704         /* Set Tx descriptor counter. */
2705         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt);
2706
2707         /* Set Tx ring address to the hardware. */
2708         paddr = sc->jme_cdata.jme_tx_data.jme_tx_ring_paddr;
2709         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2710         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2711
2712         /* Configure TxMAC parameters. */
2713         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2714         reg |= TXMAC_THRESH_1_PKT;
2715         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2716         CSR_WRITE_4(sc, JME_TXMAC, reg);
2717
2718         /*
2719          * Configure Rx queue.
2720          *  FIFO full threshold for transmitting Tx pause packet : 128T
2721          *  FIFO threshold for processing next packet : 128QW
2722          *  Rx queue 0 select
2723          *  Max Rx DMA length : 128
2724          *  Rx descriptor retry : 32
2725          *  Rx descriptor retry time gap : 256ns
2726          *  Don't receive runt/bad frame.
2727          */
2728         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2729 #if 0
2730         /*
2731          * Since Rx FIFO size is 4K bytes, receiving frames larger
2732          * than 4K bytes will suffer from Rx FIFO overruns. So
2733          * decrease FIFO threshold to reduce the FIFO overruns for
2734          * frames larger than 4000 bytes.
2735          * For best performance of standard MTU sized frames use
2736          * maximum allowable FIFO threshold, 128QW.
2737          */
2738         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2739             JME_RX_FIFO_SIZE)
2740                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2741         else
2742                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2743 #else
2744         /* Improve PCI Express compatibility */
2745         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2746 #endif
2747         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2748         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2749         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2750         /* XXX TODO DROP_BAD */
2751
2752         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2753                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2754
2755                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2756
2757                 /* Set Rx descriptor counter. */
2758                 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2759
2760                 /* Set Rx ring address to the hardware. */
2761                 paddr = rdata->jme_rx_ring_paddr;
2762                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2763                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2764         }
2765
2766         /* Clear receive filter. */
2767         CSR_WRITE_4(sc, JME_RXMAC, 0);
2768
2769         /* Set up the receive filter. */
2770         jme_set_filter(sc);
2771         jme_set_vlan(sc);
2772
2773         /*
2774          * Disable all WOL bits as WOL can interfere normal Rx
2775          * operation. Also clear WOL detection status bits.
2776          */
2777         reg = CSR_READ_4(sc, JME_PMCS);
2778         reg &= ~PMCS_WOL_ENB_MASK;
2779         CSR_WRITE_4(sc, JME_PMCS, reg);
2780
2781         /*
2782          * Pad 10bytes right before received frame. This will greatly
2783          * help Rx performance on strict-alignment architectures as
2784          * it does not need to copy the frame to align the payload.
2785          */
2786         reg = CSR_READ_4(sc, JME_RXMAC);
2787         reg |= RXMAC_PAD_10BYTES;
2788
2789         if (ifp->if_capenable & IFCAP_RXCSUM)
2790                 reg |= RXMAC_CSUM_ENB;
2791         CSR_WRITE_4(sc, JME_RXMAC, reg);
2792
2793         /* Configure general purpose reg0 */
2794         reg = CSR_READ_4(sc, JME_GPREG0);
2795         reg &= ~GPREG0_PCC_UNIT_MASK;
2796         /* Set PCC timer resolution to micro-seconds unit. */
2797         reg |= GPREG0_PCC_UNIT_US;
2798         /*
2799          * Disable all shadow register posting as we have to read
2800          * JME_INTR_STATUS register in jme_intr. Also it seems
2801          * that it's hard to synchronize interrupt status between
2802          * hardware and software with shadow posting due to
2803          * requirements of bus_dmamap_sync(9).
2804          */
2805         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2806             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2807             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2808             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2809         /* Disable posting of DW0. */
2810         reg &= ~GPREG0_POST_DW0_ENB;
2811         /* Clear PME message. */
2812         reg &= ~GPREG0_PME_ENB;
2813         /* Set PHY address. */
2814         reg &= ~GPREG0_PHY_ADDR_MASK;
2815         reg |= sc->jme_phyaddr;
2816         CSR_WRITE_4(sc, JME_GPREG0, reg);
2817
2818         /* Configure Tx queue 0 packet completion coalescing. */
2819         jme_set_tx_coal(sc);
2820
2821         /* Configure Rx queues packet completion coalescing. */
2822         jme_set_rx_coal(sc);
2823
2824         /* Configure shadow status block but don't enable posting. */
2825         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2826         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2827         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2828
2829         /* Disable Timer 1 and Timer 2. */
2830         CSR_WRITE_4(sc, JME_TIMER1, 0);
2831         CSR_WRITE_4(sc, JME_TIMER2, 0);
2832
2833         /* Configure retry transmit period, retry limit value. */
2834         CSR_WRITE_4(sc, JME_TXTRHD,
2835             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2836             TXTRHD_RT_PERIOD_MASK) |
2837             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2838             TXTRHD_RT_LIMIT_SHIFT));
2839
2840 #ifdef IFPOLL_ENABLE
2841         if (!(ifp->if_flags & IFF_NPOLLING))
2842 #endif
2843         /* Initialize the interrupt mask. */
2844         jme_enable_intr(sc);
2845         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2846
2847         /*
2848          * Enabling Tx/Rx DMA engines and Rx queue processing is
2849          * done after detection of valid link in jme_miibus_statchg.
2850          */
2851         sc->jme_has_link = FALSE;
2852
2853         /* Set the current media. */
2854         mii = device_get_softc(sc->jme_miibus);
2855         mii_mediachg(mii);
2856
2857         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2858
2859         ifp->if_flags |= IFF_RUNNING;
2860         ifp->if_flags &= ~IFF_OACTIVE;
2861 }
2862
2863 static void
2864 jme_stop(struct jme_softc *sc)
2865 {
2866         struct ifnet *ifp = &sc->arpcom.ac_if;
2867         struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
2868         struct jme_txdesc *txd;
2869         struct jme_rxdesc *rxd;
2870         struct jme_rxdata *rdata;
2871         int i, r;
2872
2873         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2874
2875         /*
2876          * Mark the interface down and cancel the watchdog timer.
2877          */
2878         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2879         ifp->if_timer = 0;
2880
2881         callout_stop(&sc->jme_tick_ch);
2882         sc->jme_has_link = FALSE;
2883
2884         /*
2885          * Disable interrupts.
2886          */
2887         jme_disable_intr(sc);
2888         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2889
2890         /* Disable updating shadow status block. */
2891         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2892             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2893
2894         /* Stop receiver, transmitter. */
2895         jme_stop_rx(sc);
2896         jme_stop_tx(sc);
2897
2898         /*
2899          * Free partial finished RX segments
2900          */
2901         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2902                 rdata = &sc->jme_cdata.jme_rx_data[r];
2903                 if (rdata->jme_rxhead != NULL)
2904                         m_freem(rdata->jme_rxhead);
2905                 JME_RXCHAIN_RESET(rdata);
2906         }
2907
2908         /*
2909          * Free RX and TX mbufs still in the queues.
2910          */
2911         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2912                 rdata = &sc->jme_cdata.jme_rx_data[r];
2913                 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2914                         rxd = &rdata->jme_rxdesc[i];
2915                         if (rxd->rx_m != NULL) {
2916                                 bus_dmamap_unload(rdata->jme_rx_tag,
2917                                                   rxd->rx_dmamap);
2918                                 m_freem(rxd->rx_m);
2919                                 rxd->rx_m = NULL;
2920                         }
2921                 }
2922         }
2923         for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
2924                 txd = &tdata->jme_txdesc[i];
2925                 if (txd->tx_m != NULL) {
2926                         bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap);
2927                         m_freem(txd->tx_m);
2928                         txd->tx_m = NULL;
2929                         txd->tx_ndesc = 0;
2930                 }
2931         }
2932 }
2933
2934 static void
2935 jme_stop_tx(struct jme_softc *sc)
2936 {
2937         uint32_t reg;
2938         int i;
2939
2940         reg = CSR_READ_4(sc, JME_TXCSR);
2941         if ((reg & TXCSR_TX_ENB) == 0)
2942                 return;
2943         reg &= ~TXCSR_TX_ENB;
2944         CSR_WRITE_4(sc, JME_TXCSR, reg);
2945         for (i = JME_TIMEOUT; i > 0; i--) {
2946                 DELAY(1);
2947                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2948                         break;
2949         }
2950         if (i == 0)
2951                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2952 }
2953
2954 static void
2955 jme_stop_rx(struct jme_softc *sc)
2956 {
2957         uint32_t reg;
2958         int i;
2959
2960         reg = CSR_READ_4(sc, JME_RXCSR);
2961         if ((reg & RXCSR_RX_ENB) == 0)
2962                 return;
2963         reg &= ~RXCSR_RX_ENB;
2964         CSR_WRITE_4(sc, JME_RXCSR, reg);
2965         for (i = JME_TIMEOUT; i > 0; i--) {
2966                 DELAY(1);
2967                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2968                         break;
2969         }
2970         if (i == 0)
2971                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2972 }
2973
2974 static void
2975 jme_init_tx_ring(struct jme_txdata *tdata)
2976 {
2977         struct jme_txdesc *txd;
2978         int i;
2979
2980         tdata->jme_tx_prod = 0;
2981         tdata->jme_tx_cons = 0;
2982         tdata->jme_tx_cnt = 0;
2983
2984         bzero(tdata->jme_tx_ring, JME_TX_RING_SIZE(tdata));
2985         for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
2986                 txd = &tdata->jme_txdesc[i];
2987                 txd->tx_m = NULL;
2988                 txd->tx_desc = &tdata->jme_tx_ring[i];
2989                 txd->tx_ndesc = 0;
2990         }
2991 }
2992
2993 static void
2994 jme_init_ssb(struct jme_softc *sc)
2995 {
2996         struct jme_chain_data *cd;
2997
2998         cd = &sc->jme_cdata;
2999         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
3000 }
3001
3002 static int
3003 jme_init_rx_ring(struct jme_rxdata *rdata)
3004 {
3005         struct jme_rxdesc *rxd;
3006         int i;
3007
3008         KKASSERT(rdata->jme_rxhead == NULL &&
3009                  rdata->jme_rxtail == NULL &&
3010                  rdata->jme_rxlen == 0);
3011         rdata->jme_rx_cons = 0;
3012
3013         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
3014         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3015                 int error;
3016
3017                 rxd = &rdata->jme_rxdesc[i];
3018                 rxd->rx_m = NULL;
3019                 rxd->rx_desc = &rdata->jme_rx_ring[i];
3020                 error = jme_newbuf(rdata, rxd, 1);
3021                 if (error)
3022                         return error;
3023         }
3024         return 0;
3025 }
3026
3027 static int
3028 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
3029 {
3030         struct mbuf *m;
3031         bus_dma_segment_t segs;
3032         bus_dmamap_t map;
3033         int error, nsegs;
3034
3035         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3036         if (m == NULL)
3037                 return ENOBUFS;
3038         /*
3039          * JMC250 has 64bit boundary alignment limitation so jme(4)
3040          * takes advantage of 10 bytes padding feature of hardware
3041          * in order not to copy entire frame to align IP header on
3042          * 32bit boundary.
3043          */
3044         m->m_len = m->m_pkthdr.len = MCLBYTES;
3045
3046         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
3047                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
3048                         BUS_DMA_NOWAIT);
3049         if (error) {
3050                 m_freem(m);
3051                 if (init) {
3052                         if_printf(&rdata->jme_sc->arpcom.ac_if,
3053                             "can't load RX mbuf\n");
3054                 }
3055                 return error;
3056         }
3057
3058         if (rxd->rx_m != NULL) {
3059                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
3060                                 BUS_DMASYNC_POSTREAD);
3061                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
3062         }
3063         map = rxd->rx_dmamap;
3064         rxd->rx_dmamap = rdata->jme_rx_sparemap;
3065         rdata->jme_rx_sparemap = map;
3066         rxd->rx_m = m;
3067         rxd->rx_paddr = segs.ds_addr;
3068
3069         jme_setup_rxdesc(rxd);
3070         return 0;
3071 }
3072
3073 static void
3074 jme_set_vlan(struct jme_softc *sc)
3075 {
3076         struct ifnet *ifp = &sc->arpcom.ac_if;
3077         uint32_t reg;
3078
3079         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3080
3081         reg = CSR_READ_4(sc, JME_RXMAC);
3082         reg &= ~RXMAC_VLAN_ENB;
3083         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
3084                 reg |= RXMAC_VLAN_ENB;
3085         CSR_WRITE_4(sc, JME_RXMAC, reg);
3086 }
3087
3088 static void
3089 jme_set_filter(struct jme_softc *sc)
3090 {
3091         struct ifnet *ifp = &sc->arpcom.ac_if;
3092         struct ifmultiaddr *ifma;
3093         uint32_t crc;
3094         uint32_t mchash[2];
3095         uint32_t rxcfg;
3096
3097         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3098
3099         rxcfg = CSR_READ_4(sc, JME_RXMAC);
3100         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3101             RXMAC_ALLMULTI);
3102
3103         /*
3104          * Always accept frames destined to our station address.
3105          * Always accept broadcast frames.
3106          */
3107         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
3108
3109         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
3110                 if (ifp->if_flags & IFF_PROMISC)
3111                         rxcfg |= RXMAC_PROMISC;
3112                 if (ifp->if_flags & IFF_ALLMULTI)
3113                         rxcfg |= RXMAC_ALLMULTI;
3114                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3115                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3116                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3117                 return;
3118         }
3119
3120         /*
3121          * Set up the multicast address filter by passing all multicast
3122          * addresses through a CRC generator, and then using the low-order
3123          * 6 bits as an index into the 64 bit multicast hash table.  The
3124          * high order bits select the register, while the rest of the bits
3125          * select the bit within the register.
3126          */
3127         rxcfg |= RXMAC_MULTICAST;
3128         bzero(mchash, sizeof(mchash));
3129
3130         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3131                 if (ifma->ifma_addr->sa_family != AF_LINK)
3132                         continue;
3133                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3134                     ifma->ifma_addr), ETHER_ADDR_LEN);
3135
3136                 /* Just want the 6 least significant bits. */
3137                 crc &= 0x3f;
3138
3139                 /* Set the corresponding bit in the hash table. */
3140                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3141         }
3142
3143         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3144         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3145         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3146 }
3147
3148 static int
3149 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
3150 {
3151         struct jme_softc *sc = arg1;
3152         struct ifnet *ifp = &sc->arpcom.ac_if;
3153         int error, v;
3154
3155         ifnet_serialize_all(ifp);
3156
3157         v = sc->jme_tx_coal_to;
3158         error = sysctl_handle_int(oidp, &v, 0, req);
3159         if (error || req->newptr == NULL)
3160                 goto back;
3161
3162         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3163                 error = EINVAL;
3164                 goto back;
3165         }
3166
3167         if (v != sc->jme_tx_coal_to) {
3168                 sc->jme_tx_coal_to = v;
3169                 if (ifp->if_flags & IFF_RUNNING)
3170                         jme_set_tx_coal(sc);
3171         }
3172 back:
3173         ifnet_deserialize_all(ifp);
3174         return error;
3175 }
3176
3177 static int
3178 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3179 {
3180         struct jme_softc *sc = arg1;
3181         struct ifnet *ifp = &sc->arpcom.ac_if;
3182         int error, v;
3183
3184         ifnet_serialize_all(ifp);
3185
3186         v = sc->jme_tx_coal_pkt;
3187         error = sysctl_handle_int(oidp, &v, 0, req);
3188         if (error || req->newptr == NULL)
3189                 goto back;
3190
3191         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3192                 error = EINVAL;
3193                 goto back;
3194         }
3195
3196         if (v != sc->jme_tx_coal_pkt) {
3197                 sc->jme_tx_coal_pkt = v;
3198                 if (ifp->if_flags & IFF_RUNNING)
3199                         jme_set_tx_coal(sc);
3200         }
3201 back:
3202         ifnet_deserialize_all(ifp);
3203         return error;
3204 }
3205
3206 static int
3207 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3208 {
3209         struct jme_softc *sc = arg1;
3210         struct ifnet *ifp = &sc->arpcom.ac_if;
3211         int error, v;
3212
3213         ifnet_serialize_all(ifp);
3214
3215         v = sc->jme_rx_coal_to;
3216         error = sysctl_handle_int(oidp, &v, 0, req);
3217         if (error || req->newptr == NULL)
3218                 goto back;
3219
3220         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3221                 error = EINVAL;
3222                 goto back;
3223         }
3224
3225         if (v != sc->jme_rx_coal_to) {
3226                 sc->jme_rx_coal_to = v;
3227                 if (ifp->if_flags & IFF_RUNNING)
3228                         jme_set_rx_coal(sc);
3229         }
3230 back:
3231         ifnet_deserialize_all(ifp);
3232         return error;
3233 }
3234
3235 static int
3236 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3237 {
3238         struct jme_softc *sc = arg1;
3239         struct ifnet *ifp = &sc->arpcom.ac_if;
3240         int error, v;
3241
3242         ifnet_serialize_all(ifp);
3243
3244         v = sc->jme_rx_coal_pkt;
3245         error = sysctl_handle_int(oidp, &v, 0, req);
3246         if (error || req->newptr == NULL)
3247                 goto back;
3248
3249         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3250                 error = EINVAL;
3251                 goto back;
3252         }
3253
3254         if (v != sc->jme_rx_coal_pkt) {
3255                 sc->jme_rx_coal_pkt = v;
3256                 if (ifp->if_flags & IFF_RUNNING)
3257                         jme_set_rx_coal(sc);
3258         }
3259 back:
3260         ifnet_deserialize_all(ifp);
3261         return error;
3262 }
3263
3264 static void
3265 jme_set_tx_coal(struct jme_softc *sc)
3266 {
3267         uint32_t reg;
3268
3269         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3270             PCCTX_COAL_TO_MASK;
3271         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3272             PCCTX_COAL_PKT_MASK;
3273         reg |= PCCTX_COAL_TXQ0;
3274         CSR_WRITE_4(sc, JME_PCCTX, reg);
3275 }
3276
3277 static void
3278 jme_set_rx_coal(struct jme_softc *sc)
3279 {
3280         uint32_t reg;
3281         int r;
3282
3283         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3284             PCCRX_COAL_TO_MASK;
3285         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3286             PCCRX_COAL_PKT_MASK;
3287         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3288                 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3289 }
3290
3291 #ifdef IFPOLL_ENABLE
3292
3293 static void
3294 jme_npoll_status(struct ifnet *ifp, int pollhz __unused)
3295 {
3296         struct jme_softc *sc = ifp->if_softc;
3297         uint32_t status;
3298
3299         ASSERT_SERIALIZED(&sc->jme_serialize);
3300
3301         status = CSR_READ_4(sc, JME_INTR_STATUS);
3302         if (status & INTR_RXQ_DESC_EMPTY) {
3303                 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY);
3304                 jme_rx_restart(sc, status);
3305         }
3306 }
3307
3308 static void
3309 jme_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3310 {
3311         struct jme_rxdata *rdata = arg;
3312
3313         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3314
3315         jme_rxeof(rdata, cycle);
3316 }
3317
3318 static void
3319 jme_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3320 {
3321         struct jme_txdata *tdata = arg;
3322
3323         ASSERT_SERIALIZED(&tdata->jme_tx_serialize);
3324
3325         jme_txeof(tdata);
3326         if (!ifq_is_empty(&ifp->if_snd))
3327                 if_devstart(ifp);
3328 }
3329
3330 static void
3331 jme_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3332 {
3333         struct jme_softc *sc = ifp->if_softc;
3334
3335         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3336
3337         if (info) {
3338                 int i, off;
3339
3340                 info->ifpi_status.status_func = jme_npoll_status;
3341                 info->ifpi_status.serializer = &sc->jme_serialize;
3342
3343                 off = sc->jme_npoll_txoff;
3344                 KKASSERT(off <= ncpus2);
3345                 info->ifpi_tx[off].poll_func = jme_npoll_tx;
3346                 info->ifpi_tx[off].arg = &sc->jme_cdata.jme_tx_data;
3347                 info->ifpi_tx[off].serializer =
3348                     &sc->jme_cdata.jme_tx_data.jme_tx_serialize;
3349
3350                 off = sc->jme_npoll_rxoff;
3351                 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
3352                         struct jme_rxdata *rdata =
3353                             &sc->jme_cdata.jme_rx_data[i];
3354                         int idx = i + off;
3355
3356                         info->ifpi_rx[idx].poll_func = jme_npoll_rx;
3357                         info->ifpi_rx[idx].arg = rdata;
3358                         info->ifpi_rx[idx].serializer =
3359                             &rdata->jme_rx_serialize;
3360                 }
3361
3362                 if (ifp->if_flags & IFF_RUNNING)
3363                         jme_disable_intr(sc);
3364                 ifp->if_npoll_cpuid = sc->jme_npoll_txoff;
3365         } else {
3366                 if (ifp->if_flags & IFF_RUNNING)
3367                         jme_enable_intr(sc);
3368                 ifp->if_npoll_cpuid = -1;
3369         }
3370 }
3371
3372 static int
3373 jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3374 {
3375         struct jme_softc *sc = (void *)arg1;
3376         struct ifnet *ifp = &sc->arpcom.ac_if;
3377         int error, off;
3378
3379         off = sc->jme_npoll_rxoff;
3380         error = sysctl_handle_int(oidp, &off, 0, req);
3381         if (error || req->newptr == NULL)
3382                 return error;
3383         if (off < 0)
3384                 return EINVAL;
3385
3386         ifnet_serialize_all(ifp);
3387         if (off >= ncpus2 || off % sc->jme_cdata.jme_rx_ring_cnt != 0) {
3388                 error = EINVAL;
3389         } else {
3390                 error = 0;
3391                 sc->jme_npoll_rxoff = off;
3392         }
3393         ifnet_deserialize_all(ifp);
3394
3395         return error;
3396 }
3397
3398 static int
3399 jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3400 {
3401         struct jme_softc *sc = (void *)arg1;
3402         struct ifnet *ifp = &sc->arpcom.ac_if;
3403         int error, off;
3404
3405         off = sc->jme_npoll_txoff;
3406         error = sysctl_handle_int(oidp, &off, 0, req);
3407         if (error || req->newptr == NULL)
3408                 return error;
3409         if (off < 0)
3410                 return EINVAL;
3411
3412         ifnet_serialize_all(ifp);
3413         if (off >= ncpus2) {
3414                 error = EINVAL;
3415         } else {
3416                 error = 0;
3417                 sc->jme_npoll_txoff = off;
3418         }
3419         ifnet_deserialize_all(ifp);
3420
3421         return error;
3422 }
3423
3424 #endif  /* IFPOLL_ENABLE */
3425
3426 static int
3427 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3428 {
3429         bus_dmamem_t dmem;
3430         int error, asize;
3431
3432         asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3433         error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3434                         JME_RX_RING_ALIGN, 0,
3435                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3436                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3437         if (error) {
3438                 device_printf(rdata->jme_sc->jme_dev,
3439                     "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3440                 return error;
3441         }
3442         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3443         rdata->jme_rx_ring_map = dmem.dmem_map;
3444         rdata->jme_rx_ring = dmem.dmem_addr;
3445         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3446
3447         return 0;
3448 }
3449
3450 static int
3451 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3452 {
3453         if ((paddr & 0xffffffff) == 0) {
3454                 /*
3455                  * Don't allow lower 32bits of the RX buffer's
3456                  * physical address to be 0, else it will break
3457                  * hardware pending RSS information delivery
3458                  * detection on RX path.
3459                  */
3460                 return 1;
3461         }
3462         return 0;
3463 }
3464
3465 static int
3466 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3467 {
3468         bus_addr_t lowaddr;
3469         int i, error;
3470
3471         lowaddr = BUS_SPACE_MAXADDR;
3472         if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3473                 /* jme_rxbuf_dma_filter will be called */
3474                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3475         }
3476
3477         /* Create tag for Rx buffers. */
3478         error = bus_dma_tag_create(
3479             rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3480             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3481             lowaddr,                    /* lowaddr */
3482             BUS_SPACE_MAXADDR,          /* highaddr */
3483             jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
3484             MCLBYTES,                   /* maxsize */
3485             1,                          /* nsegments */
3486             MCLBYTES,                   /* maxsegsize */
3487             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3488             &rdata->jme_rx_tag);
3489         if (error) {
3490                 device_printf(rdata->jme_sc->jme_dev,
3491                     "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3492                 return error;
3493         }
3494
3495         /* Create DMA maps for Rx buffers. */
3496         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3497                                   &rdata->jme_rx_sparemap);
3498         if (error) {
3499                 device_printf(rdata->jme_sc->jme_dev,
3500                     "could not create %dth spare Rx dmamap.\n",
3501                     rdata->jme_rx_idx);
3502                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3503                 rdata->jme_rx_tag = NULL;
3504                 return error;
3505         }
3506         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3507                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3508
3509                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3510                                           &rxd->rx_dmamap);
3511                 if (error) {
3512                         int j;
3513
3514                         device_printf(rdata->jme_sc->jme_dev,
3515                             "could not create %dth Rx dmamap "
3516                             "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3517
3518                         for (j = 0; j < i; ++j) {
3519                                 rxd = &rdata->jme_rxdesc[j];
3520                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3521                                                    rxd->rx_dmamap);
3522                         }
3523                         bus_dmamap_destroy(rdata->jme_rx_tag,
3524                                            rdata->jme_rx_sparemap);
3525                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3526                         rdata->jme_rx_tag = NULL;
3527                         return error;
3528                 }
3529         }
3530         return 0;
3531 }
3532
3533 static void
3534 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3535 {
3536         int r;
3537
3538         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3539                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3540
3541                 if (status & rdata->jme_rx_coal) {
3542                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3543                         jme_rxeof(rdata, -1);
3544                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3545                 }
3546         }
3547 }
3548
3549 static void
3550 jme_enable_rss(struct jme_softc *sc)
3551 {
3552         uint32_t rssc, ind;
3553         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3554         int i;
3555
3556         KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3557                 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3558                 ("%s: invalid # of RX rings (%d)",
3559                  sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3560
3561         rssc = RSSC_HASH_64_ENTRY;
3562         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3563         rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3564         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3565         CSR_WRITE_4(sc, JME_RSSC, rssc);
3566
3567         toeplitz_get_key(key, sizeof(key));
3568         for (i = 0; i < RSSKEY_NREGS; ++i) {
3569                 uint32_t keyreg;
3570
3571                 keyreg = RSSKEY_REGVAL(key, i);
3572                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3573
3574                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3575         }
3576
3577         /*
3578          * Create redirect table in following fashion:
3579          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3580          */
3581         ind = 0;
3582         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3583                 int q;
3584
3585                 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3586                 ind |= q << (i * 8);
3587         }
3588         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3589
3590         for (i = 0; i < RSSTBL_NREGS; ++i)
3591                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3592 }
3593
3594 static void
3595 jme_disable_rss(struct jme_softc *sc)
3596 {
3597         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3598 }
3599
3600 static void
3601 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3602 {
3603         struct jme_softc *sc = ifp->if_softc;
3604
3605         ifnet_serialize_array_enter(sc->jme_serialize_arr,
3606             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3607 }
3608
3609 static void
3610 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3611 {
3612         struct jme_softc *sc = ifp->if_softc;
3613
3614         ifnet_serialize_array_exit(sc->jme_serialize_arr,
3615             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3616 }
3617
3618 static int
3619 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3620 {
3621         struct jme_softc *sc = ifp->if_softc;
3622
3623         return ifnet_serialize_array_try(sc->jme_serialize_arr,
3624             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3625 }
3626
3627 #ifdef INVARIANTS
3628
3629 static void
3630 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3631     boolean_t serialized)
3632 {
3633         struct jme_softc *sc = ifp->if_softc;
3634
3635         ifnet_serialize_array_assert(sc->jme_serialize_arr,
3636             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3637             slz, serialized);
3638 }
3639
3640 #endif  /* INVARIANTS */
3641
3642 static void
3643 jme_msix_try_alloc(device_t dev)
3644 {
3645         struct jme_softc *sc = device_get_softc(dev);
3646         struct jme_msix_data *msix;
3647         int error, i, r, msix_enable, msix_count;
3648         int offset, offset_def;
3649
3650         msix_count = JME_MSIXCNT(sc->jme_cdata.jme_rx_ring_cnt);
3651         KKASSERT(msix_count <= JME_NMSIX);
3652
3653         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3654
3655         /*
3656          * We leave the 1st MSI-X vector unused, so we
3657          * actually need msix_count + 1 MSI-X vectors.
3658          */
3659         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3660                 return;
3661
3662         for (i = 0; i < msix_count; ++i)
3663                 sc->jme_msix[i].jme_msix_rid = -1;
3664
3665         i = 0;
3666
3667         /*
3668          * Setup status MSI-X
3669          */
3670
3671         msix = &sc->jme_msix[i++];
3672         msix->jme_msix_cpuid = 0;
3673         msix->jme_msix_arg = sc;
3674         msix->jme_msix_func = jme_msix_status;
3675         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3676                 msix->jme_msix_intrs |=
3677                     sc->jme_cdata.jme_rx_data[r].jme_rx_empty;
3678         }
3679         msix->jme_msix_serialize = &sc->jme_serialize;
3680         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s sts",
3681             device_get_nameunit(dev));
3682
3683         /*
3684          * Setup TX MSI-X
3685          */
3686
3687         offset_def = device_get_unit(dev) % ncpus2;
3688         offset = device_getenv_int(dev, "msix.txoff", offset_def);
3689         if (offset >= ncpus2) {
3690                 device_printf(dev, "invalid msix.txoff %d, use %d\n",
3691                     offset, offset_def);
3692                 offset = offset_def;
3693         }
3694
3695         msix = &sc->jme_msix[i++];
3696         msix->jme_msix_cpuid = offset;
3697         sc->jme_tx_cpuid = msix->jme_msix_cpuid;
3698         msix->jme_msix_arg = &sc->jme_cdata.jme_tx_data;
3699         msix->jme_msix_func = jme_msix_tx;
3700         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3701         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_data.jme_tx_serialize;
3702         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3703             device_get_nameunit(dev));
3704
3705         /*
3706          * Setup RX MSI-X
3707          */
3708
3709         if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) {
3710                 offset = 0;
3711         } else {
3712                 offset_def = (sc->jme_cdata.jme_rx_ring_cnt *
3713                     device_get_unit(dev)) % ncpus2;
3714
3715                 offset = device_getenv_int(dev, "msix.rxoff", offset_def);
3716                 if (offset >= ncpus2 ||
3717                     offset % sc->jme_cdata.jme_rx_ring_cnt != 0) {
3718                         device_printf(dev, "invalid msix.rxoff %d, use %d\n",
3719                             offset, offset_def);
3720                         offset = offset_def;
3721                 }
3722         }
3723
3724         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3725                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3726
3727                 msix = &sc->jme_msix[i++];
3728                 msix->jme_msix_cpuid = r + offset;
3729                 KKASSERT(msix->jme_msix_cpuid < ncpus2);
3730                 msix->jme_msix_arg = rdata;
3731                 msix->jme_msix_func = jme_msix_rx;
3732                 msix->jme_msix_intrs = rdata->jme_rx_coal;
3733                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3734                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3735                     "%s rx%d", device_get_nameunit(dev), r);
3736         }
3737
3738         KKASSERT(i == msix_count);
3739
3740         error = pci_setup_msix(dev);
3741         if (error)
3742                 return;
3743
3744         /* Setup jme_msix_cnt early, so we could cleanup */
3745         sc->jme_msix_cnt = msix_count;
3746
3747         for (i = 0; i < msix_count; ++i) {
3748                 msix = &sc->jme_msix[i];
3749
3750                 msix->jme_msix_vector = i + 1;
3751                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3752                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3753                 if (error)
3754                         goto back;
3755
3756                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3757                     &msix->jme_msix_rid, RF_ACTIVE);
3758                 if (msix->jme_msix_res == NULL) {
3759                         error = ENOMEM;
3760                         goto back;
3761                 }
3762         }
3763
3764         for (i = 0; i < JME_INTR_CNT; ++i) {
3765                 uint32_t intr_mask = (1 << i);
3766                 int x;
3767
3768                 if ((JME_INTRS & intr_mask) == 0)
3769                         continue;
3770
3771                 for (x = 0; x < msix_count; ++x) {
3772                         msix = &sc->jme_msix[x];
3773                         if (msix->jme_msix_intrs & intr_mask) {
3774                                 int reg, shift;
3775
3776                                 reg = i / JME_MSINUM_FACTOR;
3777                                 KKASSERT(reg < JME_MSINUM_CNT);
3778
3779                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3780
3781                                 sc->jme_msinum[reg] |=
3782                                     (msix->jme_msix_vector << shift);
3783
3784                                 break;
3785                         }
3786                 }
3787         }
3788
3789         if (bootverbose) {
3790                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3791                         device_printf(dev, "MSINUM%d: %#x\n", i,
3792                             sc->jme_msinum[i]);
3793                 }
3794         }
3795
3796         pci_enable_msix(dev);
3797         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3798
3799 back:
3800         if (error)
3801                 jme_msix_free(dev);
3802 }
3803
3804 static int
3805 jme_intr_alloc(device_t dev)
3806 {
3807         struct jme_softc *sc = device_get_softc(dev);
3808         u_int irq_flags;
3809
3810         jme_msix_try_alloc(dev);
3811
3812         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3813                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3814                     &sc->jme_irq_rid, &irq_flags);
3815
3816                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3817                     &sc->jme_irq_rid, irq_flags);
3818                 if (sc->jme_irq_res == NULL) {
3819                         device_printf(dev, "can't allocate irq\n");
3820                         return ENXIO;
3821                 }
3822         }
3823         return 0;
3824 }
3825
3826 static void
3827 jme_msix_free(device_t dev)
3828 {
3829         struct jme_softc *sc = device_get_softc(dev);
3830         int i;
3831
3832         KKASSERT(sc->jme_msix_cnt > 1);
3833
3834         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3835                 struct jme_msix_data *msix = &sc->jme_msix[i];
3836
3837                 if (msix->jme_msix_res != NULL) {
3838                         bus_release_resource(dev, SYS_RES_IRQ,
3839                             msix->jme_msix_rid, msix->jme_msix_res);
3840                         msix->jme_msix_res = NULL;
3841                 }
3842                 if (msix->jme_msix_rid >= 0) {
3843                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3844                         msix->jme_msix_rid = -1;
3845                 }
3846         }
3847         pci_teardown_msix(dev);
3848 }
3849
3850 static void
3851 jme_intr_free(device_t dev)
3852 {
3853         struct jme_softc *sc = device_get_softc(dev);
3854
3855         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3856                 if (sc->jme_irq_res != NULL) {
3857                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3858                                              sc->jme_irq_res);
3859                 }
3860                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3861                         pci_release_msi(dev);
3862         } else {
3863                 jme_msix_free(dev);
3864         }
3865 }
3866
3867 static void
3868 jme_msix_tx(void *xtdata)
3869 {
3870         struct jme_txdata *tdata = xtdata;
3871         struct jme_softc *sc = tdata->jme_sc;
3872         struct ifnet *ifp = &sc->arpcom.ac_if;
3873
3874         ASSERT_SERIALIZED(&tdata->jme_tx_serialize);
3875
3876         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3877
3878         CSR_WRITE_4(sc, JME_INTR_STATUS,
3879             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3880
3881         if (ifp->if_flags & IFF_RUNNING) {
3882                 jme_txeof(tdata);
3883                 if (!ifq_is_empty(&ifp->if_snd))
3884                         if_devstart(ifp);
3885         }
3886
3887         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3888 }
3889
3890 static void
3891 jme_msix_rx(void *xrdata)
3892 {
3893         struct jme_rxdata *rdata = xrdata;
3894         struct jme_softc *sc = rdata->jme_sc;
3895         struct ifnet *ifp = &sc->arpcom.ac_if;
3896
3897         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3898
3899         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, rdata->jme_rx_coal);
3900
3901         CSR_WRITE_4(sc, JME_INTR_STATUS,
3902             rdata->jme_rx_coal | rdata->jme_rx_comp);
3903
3904         if (ifp->if_flags & IFF_RUNNING)
3905                 jme_rxeof(rdata, -1);
3906
3907         CSR_WRITE_4(sc, JME_INTR_MASK_SET, rdata->jme_rx_coal);
3908 }
3909
3910 static void
3911 jme_msix_status(void *xsc)
3912 {
3913         struct jme_softc *sc = xsc;
3914         struct ifnet *ifp = &sc->arpcom.ac_if;
3915         uint32_t status;
3916
3917         ASSERT_SERIALIZED(&sc->jme_serialize);
3918
3919         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_RXQ_DESC_EMPTY);
3920
3921         status = CSR_READ_4(sc, JME_INTR_STATUS);
3922
3923         if (status & INTR_RXQ_DESC_EMPTY) {
3924                 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY);
3925                 if (ifp->if_flags & IFF_RUNNING)
3926                         jme_rx_restart(sc, status);
3927         }
3928
3929         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_RXQ_DESC_EMPTY);
3930 }
3931
3932 static void
3933 jme_rx_restart(struct jme_softc *sc, uint32_t status)
3934 {
3935         int i;
3936
3937         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
3938                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
3939
3940                 if (status & rdata->jme_rx_empty) {
3941                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3942                         jme_rxeof(rdata, -1);
3943 #ifdef JME_RSS_DEBUG
3944                         rdata->jme_rx_emp++;
3945 #endif
3946                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3947                 }
3948         }
3949         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
3950             RXCSR_RXQ_START);
3951 }
3952
3953 static void
3954 jme_set_msinum(struct jme_softc *sc)
3955 {
3956         int i;
3957
3958         for (i = 0; i < JME_MSINUM_CNT; ++i)
3959                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3960 }
3961
3962 static int
3963 jme_intr_setup(device_t dev)
3964 {
3965         struct jme_softc *sc = device_get_softc(dev);
3966         struct ifnet *ifp = &sc->arpcom.ac_if;
3967         int error;
3968
3969         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3970                 return jme_msix_setup(dev);
3971
3972         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3973             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3974         if (error) {
3975                 device_printf(dev, "could not set up interrupt handler.\n");
3976                 return error;
3977         }
3978
3979         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3980         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3981         return 0;
3982 }
3983
3984 static void
3985 jme_intr_teardown(device_t dev)
3986 {
3987         struct jme_softc *sc = device_get_softc(dev);
3988
3989         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3990                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3991         else
3992                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3993 }
3994
3995 static int
3996 jme_msix_setup(device_t dev)
3997 {
3998         struct jme_softc *sc = device_get_softc(dev);
3999         struct ifnet *ifp = &sc->arpcom.ac_if;
4000         int x;
4001
4002         for (x = 0; x < sc->jme_msix_cnt; ++x) {
4003                 struct jme_msix_data *msix = &sc->jme_msix[x];
4004                 int error;
4005
4006                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
4007                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
4008                     &msix->jme_msix_handle, msix->jme_msix_serialize,
4009                     msix->jme_msix_desc);
4010                 if (error) {
4011                         device_printf(dev, "could not set up %s "
4012                             "interrupt handler.\n", msix->jme_msix_desc);
4013                         jme_msix_teardown(dev, x);
4014                         return error;
4015                 }
4016         }
4017         ifp->if_cpuid = sc->jme_tx_cpuid;
4018         return 0;
4019 }
4020
4021 static void
4022 jme_msix_teardown(device_t dev, int msix_count)
4023 {
4024         struct jme_softc *sc = device_get_softc(dev);
4025         int x;
4026
4027         for (x = 0; x < msix_count; ++x) {
4028                 struct jme_msix_data *msix = &sc->jme_msix[x];
4029
4030                 bus_teardown_intr(dev, msix->jme_msix_res,
4031                     msix->jme_msix_handle);
4032         }
4033 }
4034
4035 static void
4036 jme_serialize_skipmain(struct jme_softc *sc)
4037 {
4038         lwkt_serialize_array_enter(sc->jme_serialize_arr,
4039             sc->jme_serialize_cnt, 1);
4040 }
4041
4042 static void
4043 jme_deserialize_skipmain(struct jme_softc *sc)
4044 {
4045         lwkt_serialize_array_exit(sc->jme_serialize_arr,
4046             sc->jme_serialize_cnt, 1);
4047 }
4048
4049 static void
4050 jme_enable_intr(struct jme_softc *sc)
4051 {
4052         int i;
4053
4054         for (i = 0; i < sc->jme_serialize_cnt; ++i)
4055                 lwkt_serialize_handler_enable(sc->jme_serialize_arr[i]);
4056
4057         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
4058 }
4059
4060 static void
4061 jme_disable_intr(struct jme_softc *sc)
4062 {
4063         int i;
4064
4065         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
4066
4067         for (i = 0; i < sc->jme_serialize_cnt; ++i)
4068                 lwkt_serialize_handler_disable(sc->jme_serialize_arr[i]);
4069 }