2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
26 * $FreeBSD: src/sys/dev/drm2/i915/intel_display.c,v 1.2 2012/05/24 19:13:54 dim Exp $
30 #include <sys/limits.h>
33 #include <drm/drm_edid.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
37 #include <drm/drm_dp_helper.h>
38 #include <drm/drm_crtc_helper.h>
40 #include <linux/err.h>
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
83 int target, int refclk, intel_clock_t *match_clock,
84 intel_clock_t *best_clock);
86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *match_clock,
88 intel_clock_t *best_clock);
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *match_clock,
93 intel_clock_t *best_clock);
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *match_clock,
97 intel_clock_t *best_clock);
99 static inline u32 /* units of 100MHz */
100 intel_fdi_link_freq(struct drm_device *dev)
103 struct drm_i915_private *dev_priv = dev->dev_private;
104 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
109 static const intel_limit_t intel_limits_i8xx_dvo = {
110 .dot = { .min = 25000, .max = 350000 },
111 .vco = { .min = 930000, .max = 1400000 },
112 .n = { .min = 3, .max = 16 },
113 .m = { .min = 96, .max = 140 },
114 .m1 = { .min = 18, .max = 26 },
115 .m2 = { .min = 6, .max = 16 },
116 .p = { .min = 4, .max = 128 },
117 .p1 = { .min = 2, .max = 33 },
118 .p2 = { .dot_limit = 165000,
119 .p2_slow = 4, .p2_fast = 2 },
120 .find_pll = intel_find_best_PLL,
123 static const intel_limit_t intel_limits_i8xx_lvds = {
124 .dot = { .min = 25000, .max = 350000 },
125 .vco = { .min = 930000, .max = 1400000 },
126 .n = { .min = 3, .max = 16 },
127 .m = { .min = 96, .max = 140 },
128 .m1 = { .min = 18, .max = 26 },
129 .m2 = { .min = 6, .max = 16 },
130 .p = { .min = 4, .max = 128 },
131 .p1 = { .min = 1, .max = 6 },
132 .p2 = { .dot_limit = 165000,
133 .p2_slow = 14, .p2_fast = 7 },
134 .find_pll = intel_find_best_PLL,
137 static const intel_limit_t intel_limits_i9xx_sdvo = {
138 .dot = { .min = 20000, .max = 400000 },
139 .vco = { .min = 1400000, .max = 2800000 },
140 .n = { .min = 1, .max = 6 },
141 .m = { .min = 70, .max = 120 },
142 .m1 = { .min = 10, .max = 22 },
143 .m2 = { .min = 5, .max = 9 },
144 .p = { .min = 5, .max = 80 },
145 .p1 = { .min = 1, .max = 8 },
146 .p2 = { .dot_limit = 200000,
147 .p2_slow = 10, .p2_fast = 5 },
148 .find_pll = intel_find_best_PLL,
151 static const intel_limit_t intel_limits_i9xx_lvds = {
152 .dot = { .min = 20000, .max = 400000 },
153 .vco = { .min = 1400000, .max = 2800000 },
154 .n = { .min = 1, .max = 6 },
155 .m = { .min = 70, .max = 120 },
156 .m1 = { .min = 10, .max = 22 },
157 .m2 = { .min = 5, .max = 9 },
158 .p = { .min = 7, .max = 98 },
159 .p1 = { .min = 1, .max = 8 },
160 .p2 = { .dot_limit = 112000,
161 .p2_slow = 14, .p2_fast = 7 },
162 .find_pll = intel_find_best_PLL,
166 static const intel_limit_t intel_limits_g4x_sdvo = {
167 .dot = { .min = 25000, .max = 270000 },
168 .vco = { .min = 1750000, .max = 3500000},
169 .n = { .min = 1, .max = 4 },
170 .m = { .min = 104, .max = 138 },
171 .m1 = { .min = 17, .max = 23 },
172 .m2 = { .min = 5, .max = 11 },
173 .p = { .min = 10, .max = 30 },
174 .p1 = { .min = 1, .max = 3},
175 .p2 = { .dot_limit = 270000,
179 .find_pll = intel_g4x_find_best_PLL,
182 static const intel_limit_t intel_limits_g4x_hdmi = {
183 .dot = { .min = 22000, .max = 400000 },
184 .vco = { .min = 1750000, .max = 3500000},
185 .n = { .min = 1, .max = 4 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 16, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 5, .max = 80 },
190 .p1 = { .min = 1, .max = 8},
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 10, .p2_fast = 5 },
193 .find_pll = intel_g4x_find_best_PLL,
196 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
197 .dot = { .min = 20000, .max = 115000 },
198 .vco = { .min = 1750000, .max = 3500000 },
199 .n = { .min = 1, .max = 3 },
200 .m = { .min = 104, .max = 138 },
201 .m1 = { .min = 17, .max = 23 },
202 .m2 = { .min = 5, .max = 11 },
203 .p = { .min = 28, .max = 112 },
204 .p1 = { .min = 2, .max = 8 },
205 .p2 = { .dot_limit = 0,
206 .p2_slow = 14, .p2_fast = 14
208 .find_pll = intel_g4x_find_best_PLL,
211 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
212 .dot = { .min = 80000, .max = 224000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 14, .max = 42 },
219 .p1 = { .min = 2, .max = 6 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 7, .p2_fast = 7
223 .find_pll = intel_g4x_find_best_PLL,
226 static const intel_limit_t intel_limits_g4x_display_port = {
227 .dot = { .min = 161670, .max = 227000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 2 },
230 .m = { .min = 97, .max = 108 },
231 .m1 = { .min = 0x10, .max = 0x12 },
232 .m2 = { .min = 0x05, .max = 0x06 },
233 .p = { .min = 10, .max = 20 },
234 .p1 = { .min = 1, .max = 2},
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 10, .p2_fast = 10 },
237 .find_pll = intel_find_pll_g4x_dp,
240 static const intel_limit_t intel_limits_pineview_sdvo = {
241 .dot = { .min = 20000, .max = 400000},
242 .vco = { .min = 1700000, .max = 3500000 },
243 /* Pineview's Ncounter is a ring counter */
244 .n = { .min = 3, .max = 6 },
245 .m = { .min = 2, .max = 256 },
246 /* Pineview only has one combined m divider, which we treat as m2. */
247 .m1 = { .min = 0, .max = 0 },
248 .m2 = { .min = 0, .max = 254 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
253 .find_pll = intel_find_best_PLL,
256 static const intel_limit_t intel_limits_pineview_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1700000, .max = 3500000 },
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 .m1 = { .min = 0, .max = 0 },
262 .m2 = { .min = 0, .max = 254 },
263 .p = { .min = 7, .max = 112 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 14 },
267 .find_pll = intel_find_best_PLL,
270 /* Ironlake / Sandybridge
272 * We calculate clock using (register_value + 2) for N/M1/M2, so here
273 * the range value for them is (actual_value - 2).
275 static const intel_limit_t intel_limits_ironlake_dac = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 5 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 10, .p2_fast = 5 },
286 .find_pll = intel_g4x_find_best_PLL,
289 static const intel_limit_t intel_limits_ironlake_single_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 3 },
293 .m = { .min = 79, .max = 118 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
300 .find_pll = intel_g4x_find_best_PLL,
303 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 56 },
311 .p1 = { .min = 2, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
314 .find_pll = intel_g4x_find_best_PLL,
317 /* LVDS 100mhz refclk limits. */
318 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 2 },
322 .m = { .min = 79, .max = 126 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 .find_pll = intel_g4x_find_best_PLL,
332 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
333 .dot = { .min = 25000, .max = 350000 },
334 .vco = { .min = 1760000, .max = 3510000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 79, .max = 126 },
337 .m1 = { .min = 12, .max = 22 },
338 .m2 = { .min = 5, .max = 9 },
339 .p = { .min = 14, .max = 42 },
340 .p1 = { .min = 2, .max = 6 },
341 .p2 = { .dot_limit = 225000,
342 .p2_slow = 7, .p2_fast = 7 },
343 .find_pll = intel_g4x_find_best_PLL,
346 static const intel_limit_t intel_limits_ironlake_display_port = {
347 .dot = { .min = 25000, .max = 350000 },
348 .vco = { .min = 1760000, .max = 3510000},
349 .n = { .min = 1, .max = 2 },
350 .m = { .min = 81, .max = 90 },
351 .m1 = { .min = 12, .max = 22 },
352 .m2 = { .min = 5, .max = 9 },
353 .p = { .min = 10, .max = 20 },
354 .p1 = { .min = 1, .max = 2},
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 10, .p2_fast = 10 },
357 .find_pll = intel_find_pll_ironlake_dp,
360 static void vlv_init_dpio(struct drm_device *dev)
362 struct drm_i915_private *dev_priv = dev->dev_private;
364 /* Reset the DPIO config */
365 I915_WRITE(DPIO_CTL, 0);
366 POSTING_READ(DPIO_CTL);
367 I915_WRITE(DPIO_CTL, 1);
368 POSTING_READ(DPIO_CTL);
371 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 const intel_limit_t *limit;
378 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
379 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
380 LVDS_CLKB_POWER_UP) {
381 /* LVDS dual channel */
382 if (refclk == 100000)
383 limit = &intel_limits_ironlake_dual_lvds_100m;
385 limit = &intel_limits_ironlake_dual_lvds;
387 if (refclk == 100000)
388 limit = &intel_limits_ironlake_single_lvds_100m;
390 limit = &intel_limits_ironlake_single_lvds;
392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
394 limit = &intel_limits_ironlake_display_port;
396 limit = &intel_limits_ironlake_dac;
401 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
403 struct drm_device *dev = crtc->dev;
404 struct drm_i915_private *dev_priv = dev->dev_private;
405 const intel_limit_t *limit;
407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
408 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
410 /* LVDS with dual channel */
411 limit = &intel_limits_g4x_dual_channel_lvds;
413 /* LVDS with dual channel */
414 limit = &intel_limits_g4x_single_channel_lvds;
415 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
416 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
417 limit = &intel_limits_g4x_hdmi;
418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
419 limit = &intel_limits_g4x_sdvo;
420 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
421 limit = &intel_limits_g4x_display_port;
422 } else /* The option is for other outputs */
423 limit = &intel_limits_i9xx_sdvo;
428 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
430 struct drm_device *dev = crtc->dev;
431 const intel_limit_t *limit;
433 if (HAS_PCH_SPLIT(dev))
434 limit = intel_ironlake_limit(crtc, refclk);
435 else if (IS_G4X(dev)) {
436 limit = intel_g4x_limit(crtc);
437 } else if (IS_PINEVIEW(dev)) {
438 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
439 limit = &intel_limits_pineview_lvds;
441 limit = &intel_limits_pineview_sdvo;
442 } else if (!IS_GEN2(dev)) {
443 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
444 limit = &intel_limits_i9xx_lvds;
446 limit = &intel_limits_i9xx_sdvo;
448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449 limit = &intel_limits_i8xx_lvds;
451 limit = &intel_limits_i8xx_dvo;
456 /* m1 is reserved as 0 in Pineview, n is a ring counter */
457 static void pineview_clock(int refclk, intel_clock_t *clock)
459 clock->m = clock->m2 + 2;
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / clock->n;
462 clock->dot = clock->vco / clock->p;
465 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
467 if (IS_PINEVIEW(dev)) {
468 pineview_clock(refclk, clock);
471 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
472 clock->p = clock->p1 * clock->p2;
473 clock->vco = refclk * clock->m / (clock->n + 2);
474 clock->dot = clock->vco / clock->p;
478 * Returns whether any output on the specified pipe is of the specified type
480 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
482 struct drm_device *dev = crtc->dev;
483 struct drm_mode_config *mode_config = &dev->mode_config;
484 struct intel_encoder *encoder;
486 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
487 if (encoder->base.crtc == crtc && encoder->type == type)
493 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
495 * Returns whether the given set of divisors are valid for a given refclk with
496 * the given connectors.
499 static bool intel_PLL_is_valid(struct drm_device *dev,
500 const intel_limit_t *limit,
501 const intel_clock_t *clock)
503 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
504 INTELPllInvalid("p1 out of range\n");
505 if (clock->p < limit->p.min || limit->p.max < clock->p)
506 INTELPllInvalid("p out of range\n");
507 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
508 INTELPllInvalid("m2 out of range\n");
509 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
510 INTELPllInvalid("m1 out of range\n");
511 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
512 INTELPllInvalid("m1 <= m2\n");
513 if (clock->m < limit->m.min || limit->m.max < clock->m)
514 INTELPllInvalid("m out of range\n");
515 if (clock->n < limit->n.min || limit->n.max < clock->n)
516 INTELPllInvalid("n out of range\n");
517 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
518 INTELPllInvalid("vco out of range\n");
519 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
520 * connector, etc., rather than just a single range.
522 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
523 INTELPllInvalid("dot out of range\n");
529 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
530 int target, int refclk, intel_clock_t *match_clock,
531 intel_clock_t *best_clock)
534 struct drm_device *dev = crtc->dev;
535 struct drm_i915_private *dev_priv = dev->dev_private;
539 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
540 (I915_READ(LVDS)) != 0) {
542 * For LVDS, if the panel is on, just rely on its current
543 * settings for dual-channel. We haven't figured out how to
544 * reliably set up different single/dual channel state, if we
547 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
549 clock.p2 = limit->p2.p2_fast;
551 clock.p2 = limit->p2.p2_slow;
553 if (target < limit->p2.dot_limit)
554 clock.p2 = limit->p2.p2_slow;
556 clock.p2 = limit->p2.p2_fast;
559 memset(best_clock, 0, sizeof(*best_clock));
561 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
563 for (clock.m2 = limit->m2.min;
564 clock.m2 <= limit->m2.max; clock.m2++) {
565 /* m1 is always 0 in Pineview */
566 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
568 for (clock.n = limit->n.min;
569 clock.n <= limit->n.max; clock.n++) {
570 for (clock.p1 = limit->p1.min;
571 clock.p1 <= limit->p1.max; clock.p1++) {
574 intel_clock(dev, refclk, &clock);
575 if (!intel_PLL_is_valid(dev, limit,
579 clock.p != match_clock->p)
582 this_err = abs(clock.dot - target);
583 if (this_err < err) {
592 return (err != target);
596 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
597 int target, int refclk, intel_clock_t *match_clock,
598 intel_clock_t *best_clock)
600 struct drm_device *dev = crtc->dev;
601 struct drm_i915_private *dev_priv = dev->dev_private;
605 /* approximately equals target * 0.00585 */
606 int err_most = (target >> 8) + (target >> 9);
609 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612 if (HAS_PCH_SPLIT(dev))
616 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
618 clock.p2 = limit->p2.p2_fast;
620 clock.p2 = limit->p2.p2_slow;
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
625 clock.p2 = limit->p2.p2_fast;
628 memset(best_clock, 0, sizeof(*best_clock));
629 max_n = limit->n.max;
630 /* based on hardware requirement, prefer smaller n to precision */
631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
632 /* based on hardware requirement, prefere larger m1,m2 */
633 for (clock.m1 = limit->m1.max;
634 clock.m1 >= limit->m1.min; clock.m1--) {
635 for (clock.m2 = limit->m2.max;
636 clock.m2 >= limit->m2.min; clock.m2--) {
637 for (clock.p1 = limit->p1.max;
638 clock.p1 >= limit->p1.min; clock.p1--) {
641 intel_clock(dev, refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
646 clock.p != match_clock->p)
649 this_err = abs(clock.dot - target);
650 if (this_err < err_most) {
664 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
668 struct drm_device *dev = crtc->dev;
671 if (target < 200000) {
684 intel_clock(dev, refclk, &clock);
685 memcpy(best_clock, &clock, sizeof(intel_clock_t));
689 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
691 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
692 int target, int refclk, intel_clock_t *match_clock,
693 intel_clock_t *best_clock)
696 if (target < 200000) {
709 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
710 clock.p = (clock.p1 * clock.p2);
711 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
713 memcpy(best_clock, &clock, sizeof(intel_clock_t));
717 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
720 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
723 return intel_crtc->cpu_transcoder;
727 * intel_wait_for_vblank - wait for vblank on a given pipe
729 * @pipe: pipe to wait for
731 * Wait for vblank to occur on a given pipe. Needed for various bits of
734 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
736 struct drm_i915_private *dev_priv = dev->dev_private;
737 int pipestat_reg = PIPESTAT(pipe);
739 /* Clear existing vblank status. Note this will clear any other
740 * sticky status fields as well.
742 * This races with i915_driver_irq_handler() with the result
743 * that either function could miss a vblank event. Here it is not
744 * fatal, as we will either wait upon the next vblank interrupt or
745 * timeout. Generally speaking intel_wait_for_vblank() is only
746 * called during modeset at which time the GPU should be idle and
747 * should *not* be performing page flips and thus not waiting on
749 * Currently, the result of us stealing a vblank from the irq
750 * handler is that a single frame will be skipped during swapbuffers.
752 I915_WRITE(pipestat_reg,
753 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
755 /* Wait for vblank interrupt bit to set */
756 if (_intel_wait_for(dev,
757 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS,
759 DRM_DEBUG_KMS("vblank wait timed out\n");
763 * intel_wait_for_pipe_off - wait for pipe to turn off
765 * @pipe: pipe to wait for
767 * After disabling a pipe, we can't wait for vblank in the usual way,
768 * spinning on the vblank interrupt status bit, since we won't actually
769 * see an interrupt when the pipe is disabled.
772 * wait for the pipe register state bit to turn off
775 * wait for the display line value to settle (it usually
776 * ends up stopping at the start of the next frame).
779 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
781 struct drm_i915_private *dev_priv = dev->dev_private;
783 if (INTEL_INFO(dev)->gen >= 4) {
784 int reg = PIPECONF(pipe);
786 /* Wait for the Pipe State to go off */
787 if (_intel_wait_for(dev,
788 (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100,
790 DRM_DEBUG_KMS("pipe_off wait timed out\n");
792 u32 last_line, line_mask;
793 int reg = PIPEDSL(pipe);
794 unsigned long timeout = jiffies + msecs_to_jiffies(100);
797 line_mask = DSL_LINEMASK_GEN2;
799 line_mask = DSL_LINEMASK_GEN3;
801 /* Wait for the display line to settle */
803 last_line = I915_READ(reg) & line_mask;
805 } while (((I915_READ(reg) & line_mask) != last_line) &&
806 time_after(timeout, jiffies));
807 if (time_after(jiffies, timeout))
808 DRM_DEBUG_KMS("pipe_off wait timed out\n");
812 static const char *state_string(bool enabled)
814 return enabled ? "on" : "off";
817 /* Only for pre-ILK configs */
818 static void assert_pll(struct drm_i915_private *dev_priv,
819 enum i915_pipe pipe, bool state)
826 val = I915_READ(reg);
827 cur_state = !!(val & DPLL_VCO_ENABLE);
828 if (cur_state != state)
829 kprintf("PLL state assertion failure (expected %s, current %s)\n",
830 state_string(state), state_string(cur_state));
832 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
833 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
836 static void assert_pch_pll(struct drm_i915_private *dev_priv,
837 enum i915_pipe pipe, bool state)
843 if (HAS_PCH_CPT(dev_priv->dev)) {
846 pch_dpll = I915_READ(PCH_DPLL_SEL);
848 /* Make sure the selected PLL is enabled to the transcoder */
849 KASSERT(((pch_dpll >> (4 * pipe)) & 8) != 0,
850 ("transcoder %d PLL not enabled\n", pipe));
852 /* Convert the transcoder pipe number to a pll pipe number */
853 pipe = (pch_dpll >> (4 * pipe)) & 1;
856 reg = _PCH_DPLL(pipe);
857 val = I915_READ(reg);
858 cur_state = !!(val & DPLL_VCO_ENABLE);
859 if (cur_state != state)
860 kprintf("PCH PLL state assertion failure (expected %s, current %s)\n",
861 state_string(state), state_string(cur_state));
863 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
864 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
866 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
867 enum i915_pipe pipe, bool state)
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 cur_state = !!(val & FDI_TX_ENABLE);
876 if (cur_state != state)
877 kprintf("FDI TX state assertion failure (expected %s, current %s)\n",
878 state_string(state), state_string(cur_state));
880 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
881 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
883 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
884 enum i915_pipe pipe, bool state)
890 reg = FDI_RX_CTL(pipe);
891 val = I915_READ(reg);
892 cur_state = !!(val & FDI_RX_ENABLE);
893 if (cur_state != state)
894 kprintf("FDI RX state assertion failure (expected %s, current %s)\n",
895 state_string(state), state_string(cur_state));
897 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
898 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
900 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
906 /* ILK FDI PLL is always enabled */
907 if (dev_priv->info->gen == 5)
910 reg = FDI_TX_CTL(pipe);
911 val = I915_READ(reg);
912 if (!(val & FDI_TX_PLL_ENABLE))
913 kprintf("FDI TX PLL assertion failure, should be active but is disabled\n");
916 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
922 reg = FDI_RX_CTL(pipe);
923 val = I915_READ(reg);
924 if (!(val & FDI_RX_PLL_ENABLE))
925 kprintf("FDI RX PLL assertion failure, should be active but is disabled\n");
928 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
931 int pp_reg, lvds_reg;
933 enum i915_pipe panel_pipe = PIPE_A;
936 if (HAS_PCH_SPLIT(dev_priv->dev)) {
937 pp_reg = PCH_PP_CONTROL;
944 val = I915_READ(pp_reg);
945 if (!(val & PANEL_POWER_ON) ||
946 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
949 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
952 if (panel_pipe == pipe && locked)
953 kprintf("panel assertion failure, pipe %c regs locked\n",
957 void assert_pipe(struct drm_i915_private *dev_priv,
958 enum i915_pipe pipe, bool state)
964 /* if we need the pipe A quirk it must be always on */
965 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
968 reg = PIPECONF(pipe);
969 val = I915_READ(reg);
970 cur_state = !!(val & PIPECONF_ENABLE);
971 if (cur_state != state)
972 kprintf("pipe %c assertion failure (expected %s, current %s)\n",
973 pipe_name(pipe), state_string(state), state_string(cur_state));
976 static void assert_plane(struct drm_i915_private *dev_priv,
977 enum plane plane, bool state)
983 reg = DSPCNTR(plane);
984 val = I915_READ(reg);
985 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
986 if (cur_state != state)
987 kprintf("plane %c assertion failure, (expected %s, current %s)\n",
988 plane_name(plane), state_string(state), state_string(cur_state));
991 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
992 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
994 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1001 /* Planes are fixed to pipes on ILK+ */
1002 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1003 reg = DSPCNTR(pipe);
1004 val = I915_READ(reg);
1005 if ((val & DISPLAY_PLANE_ENABLE) != 0)
1006 kprintf("plane %c assertion failure, should be disabled but not\n",
1011 /* Need to check both planes against the pipe */
1012 for (i = 0; i < 2; i++) {
1014 val = I915_READ(reg);
1015 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1016 DISPPLANE_SEL_PIPE_SHIFT;
1017 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
1018 kprintf("plane %c assertion failure, should be off on pipe %c but is still active\n",
1019 plane_name(i), pipe_name(pipe));
1023 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1028 val = I915_READ(PCH_DREF_CONTROL);
1029 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1030 DREF_SUPERSPREAD_SOURCE_MASK));
1032 kprintf("PCH refclk assertion failure, should be active but is disabled\n");
1035 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1036 enum i915_pipe pipe)
1042 reg = TRANSCONF(pipe);
1043 val = I915_READ(reg);
1044 enabled = !!(val & TRANS_ENABLE);
1046 kprintf("transcoder assertion failed, should be off on pipe %c but is still active\n",
1050 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1051 enum i915_pipe pipe, u32 val)
1053 if ((val & PORT_ENABLE) == 0)
1056 if (HAS_PCH_CPT(dev_priv->dev)) {
1057 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1060 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1066 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1067 enum i915_pipe pipe, u32 val)
1069 if ((val & LVDS_PORT_EN) == 0)
1072 if (HAS_PCH_CPT(dev_priv->dev)) {
1073 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1076 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1082 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1083 enum i915_pipe pipe, u32 val)
1085 if ((val & ADPA_DAC_ENABLE) == 0)
1087 if (HAS_PCH_CPT(dev_priv->dev)) {
1088 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1091 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1097 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1098 enum i915_pipe pipe, u32 port_sel, u32 val)
1100 if ((val & DP_PORT_EN) == 0)
1103 if (HAS_PCH_CPT(dev_priv->dev)) {
1104 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1105 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1106 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1109 if ((val & DP_PIPE_MASK) != (pipe << 30))
1115 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1116 enum i915_pipe pipe, int reg, u32 port_sel)
1118 u32 val = I915_READ(reg);
1119 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1120 kprintf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1121 reg, pipe_name(pipe));
1124 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1125 enum i915_pipe pipe, int reg)
1127 u32 val = I915_READ(reg);
1128 if (hdmi_pipe_enabled(dev_priv, val, pipe))
1129 kprintf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1130 reg, pipe_name(pipe));
1133 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1134 enum i915_pipe pipe)
1139 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1140 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1141 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1144 val = I915_READ(reg);
1145 if (adpa_pipe_enabled(dev_priv, val, pipe))
1146 kprintf("PCH VGA enabled on transcoder %c, should be disabled\n",
1150 val = I915_READ(reg);
1151 if (lvds_pipe_enabled(dev_priv, val, pipe))
1152 kprintf("PCH LVDS enabled on transcoder %c, should be disabled\n",
1155 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1156 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1157 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1161 * intel_enable_pll - enable a PLL
1162 * @dev_priv: i915 private structure
1163 * @pipe: pipe PLL to enable
1165 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1166 * make sure the PLL reg is writable first though, since the panel write
1167 * protect mechanism may be enabled.
1169 * Note! This is for pre-ILK only.
1171 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1176 /* No really, not for ILK+ */
1177 KASSERT(dev_priv->info->gen < 5, ("Wrong device gen"));
1179 /* PLL is protected by panel, make sure we can write it */
1180 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1181 assert_panel_unlocked(dev_priv, pipe);
1184 val = I915_READ(reg);
1185 val |= DPLL_VCO_ENABLE;
1187 /* We do this three times for luck */
1188 I915_WRITE(reg, val);
1190 DELAY(150); /* wait for warmup */
1191 I915_WRITE(reg, val);
1193 DELAY(150); /* wait for warmup */
1194 I915_WRITE(reg, val);
1196 DELAY(150); /* wait for warmup */
1200 * intel_disable_pll - disable a PLL
1201 * @dev_priv: i915 private structure
1202 * @pipe: pipe PLL to disable
1204 * Disable the PLL for @pipe, making sure the pipe is off first.
1206 * Note! This is for pre-ILK only.
1208 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1213 /* Don't disable pipe A or pipe A PLLs if needed */
1214 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1217 /* Make sure the pipe isn't still relying on us */
1218 assert_pipe_disabled(dev_priv, pipe);
1221 val = I915_READ(reg);
1222 val &= ~DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1228 * intel_enable_pch_pll - enable PCH PLL
1229 * @dev_priv: i915 private structure
1230 * @pipe: pipe PLL to enable
1232 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1233 * drives the transcoder clock.
1235 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1236 enum i915_pipe pipe)
1244 /* PCH only available on ILK+ */
1245 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1247 /* PCH refclock must be enabled first */
1248 assert_pch_refclk_enabled(dev_priv);
1250 reg = _PCH_DPLL(pipe);
1251 val = I915_READ(reg);
1252 val |= DPLL_VCO_ENABLE;
1253 I915_WRITE(reg, val);
1258 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1259 enum i915_pipe pipe)
1262 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1263 pll_sel = TRANSC_DPLL_ENABLE;
1268 /* PCH only available on ILK+ */
1269 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1271 /* Make sure transcoder isn't still depending on us */
1272 assert_transcoder_disabled(dev_priv, pipe);
1275 pll_sel |= TRANSC_DPLLA_SEL;
1277 pll_sel |= TRANSC_DPLLB_SEL;
1280 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1283 reg = _PCH_DPLL(pipe);
1284 val = I915_READ(reg);
1285 val &= ~DPLL_VCO_ENABLE;
1286 I915_WRITE(reg, val);
1291 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1292 enum i915_pipe pipe)
1295 u32 val, pipeconf_val;
1296 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1298 /* PCH only available on ILK+ */
1299 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1301 /* Make sure PCH DPLL is enabled */
1302 assert_pch_pll_enabled(dev_priv, pipe);
1304 /* FDI must be feeding us bits for PCH ports */
1305 assert_fdi_tx_enabled(dev_priv, pipe);
1306 assert_fdi_rx_enabled(dev_priv, pipe);
1309 reg = TRANSCONF(pipe);
1310 val = I915_READ(reg);
1311 pipeconf_val = I915_READ(PIPECONF(pipe));
1313 if (HAS_PCH_IBX(dev_priv->dev)) {
1315 * make the BPC in transcoder be consistent with
1316 * that in pipeconf reg.
1318 val &= ~PIPE_BPC_MASK;
1319 val |= pipeconf_val & PIPE_BPC_MASK;
1322 val &= ~TRANS_INTERLACE_MASK;
1323 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1324 if (HAS_PCH_IBX(dev_priv->dev) &&
1325 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1326 val |= TRANS_LEGACY_INTERLACED_ILK;
1328 val |= TRANS_INTERLACED;
1330 val |= TRANS_PROGRESSIVE;
1332 I915_WRITE(reg, val | TRANS_ENABLE);
1333 if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE,
1335 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1338 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1339 enum i915_pipe pipe)
1344 /* FDI relies on the transcoder */
1345 assert_fdi_tx_disabled(dev_priv, pipe);
1346 assert_fdi_rx_disabled(dev_priv, pipe);
1348 /* Ports must be off as well */
1349 assert_pch_ports_disabled(dev_priv, pipe);
1351 reg = TRANSCONF(pipe);
1352 val = I915_READ(reg);
1353 val &= ~TRANS_ENABLE;
1354 I915_WRITE(reg, val);
1355 /* wait for PCH transcoder off, transcoder state */
1356 if (_intel_wait_for(dev_priv->dev,
1357 (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50,
1359 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1363 * intel_enable_pipe - enable a pipe, asserting requirements
1364 * @dev_priv: i915 private structure
1365 * @pipe: pipe to enable
1366 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1368 * Enable @pipe, making sure that various hardware specific requirements
1369 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1371 * @pipe should be %PIPE_A or %PIPE_B.
1373 * Will wait until the pipe is actually running (i.e. first vblank) before
1376 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
1383 * A pipe without a PLL won't actually be able to drive bits from
1384 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1387 if (!HAS_PCH_SPLIT(dev_priv->dev))
1388 assert_pll_enabled(dev_priv, pipe);
1391 /* if driving the PCH, we need FDI enabled */
1392 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1393 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1395 /* FIXME: assert CPU port conditions for SNB+ */
1398 reg = PIPECONF(pipe);
1399 val = I915_READ(reg);
1400 if (val & PIPECONF_ENABLE)
1403 I915_WRITE(reg, val | PIPECONF_ENABLE);
1404 intel_wait_for_vblank(dev_priv->dev, pipe);
1408 * intel_disable_pipe - disable a pipe, asserting requirements
1409 * @dev_priv: i915 private structure
1410 * @pipe: pipe to disable
1412 * Disable @pipe, making sure that various hardware specific requirements
1413 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1415 * @pipe should be %PIPE_A or %PIPE_B.
1417 * Will wait until the pipe has shut down before returning.
1419 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1420 enum i915_pipe pipe)
1426 * Make sure planes won't keep trying to pump pixels to us,
1427 * or we might hang the display.
1429 assert_planes_disabled(dev_priv, pipe);
1431 /* Don't disable pipe A or pipe A PLLs if needed */
1432 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1435 reg = PIPECONF(pipe);
1436 val = I915_READ(reg);
1437 if ((val & PIPECONF_ENABLE) == 0)
1440 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1441 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1445 * Plane regs are double buffered, going from enabled->disabled needs a
1446 * trigger in order to latch. The display address reg provides this.
1448 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1451 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1452 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1456 * intel_enable_plane - enable a display plane on a given pipe
1457 * @dev_priv: i915 private structure
1458 * @plane: plane to enable
1459 * @pipe: pipe being fed
1461 * Enable @plane on @pipe, making sure that @pipe is running first.
1463 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1464 enum plane plane, enum i915_pipe pipe)
1469 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1470 assert_pipe_enabled(dev_priv, pipe);
1472 reg = DSPCNTR(plane);
1473 val = I915_READ(reg);
1474 if (val & DISPLAY_PLANE_ENABLE)
1477 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1478 intel_flush_display_plane(dev_priv, plane);
1479 intel_wait_for_vblank(dev_priv->dev, pipe);
1483 * intel_disable_plane - disable a display plane
1484 * @dev_priv: i915 private structure
1485 * @plane: plane to disable
1486 * @pipe: pipe consuming the data
1488 * Disable @plane; should be an independent operation.
1490 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1491 enum plane plane, enum i915_pipe pipe)
1496 reg = DSPCNTR(plane);
1497 val = I915_READ(reg);
1498 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1501 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1502 intel_flush_display_plane(dev_priv, plane);
1503 intel_wait_for_vblank(dev_priv->dev, pipe);
1506 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1507 enum i915_pipe pipe, int reg, u32 port_sel)
1509 u32 val = I915_READ(reg);
1510 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1511 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1512 I915_WRITE(reg, val & ~DP_PORT_EN);
1516 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1517 enum i915_pipe pipe, int reg)
1519 u32 val = I915_READ(reg);
1520 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1521 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1523 I915_WRITE(reg, val & ~PORT_ENABLE);
1527 /* Disable any ports connected to this transcoder */
1528 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1529 enum i915_pipe pipe)
1533 val = I915_READ(PCH_PP_CONTROL);
1534 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1536 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1537 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1538 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1541 val = I915_READ(reg);
1542 if (adpa_pipe_enabled(dev_priv, val, pipe))
1543 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1546 val = I915_READ(reg);
1547 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1548 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1549 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1554 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1555 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1556 disable_pch_hdmi(dev_priv, pipe, HDMID);
1560 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1561 struct drm_i915_gem_object *obj,
1562 struct intel_ring_buffer *pipelined)
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1568 alignment = 0; /* shut gcc */
1569 switch (obj->tiling_mode) {
1570 case I915_TILING_NONE:
1571 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1572 alignment = 128 * 1024;
1573 else if (INTEL_INFO(dev)->gen >= 4)
1574 alignment = 4 * 1024;
1576 alignment = 64 * 1024;
1579 /* pin() will align the object as required by fence */
1583 /* FIXME: Is this true? */
1584 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1587 KASSERT(0, ("Wrong tiling for fb obj"));
1590 dev_priv->mm.interruptible = false;
1591 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1593 goto err_interruptible;
1595 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1596 * fence, whereas 965+ only requires a fence if using
1597 * framebuffer compression. For simplicity, we always install
1598 * a fence as the cost is not that onerous.
1600 if (obj->tiling_mode != I915_TILING_NONE) {
1601 ret = i915_gem_object_get_fence(obj);
1605 i915_gem_object_pin_fence(obj);
1608 dev_priv->mm.interruptible = true;
1612 i915_gem_object_unpin(obj);
1614 dev_priv->mm.interruptible = true;
1618 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1620 i915_gem_object_unpin_fence(obj);
1621 i915_gem_object_unpin(obj);
1624 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1625 * is assumed to be a power-of-two. */
1626 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1627 unsigned int tiling_mode,
1631 if (tiling_mode != I915_TILING_NONE) {
1632 unsigned int tile_rows, tiles;
1637 tiles = *x / (512/cpp);
1640 return tile_rows * pitch * 8 + tiles * 4096;
1642 unsigned int offset;
1644 offset = *y * pitch + *x * cpp;
1646 *x = (offset & 4095) / cpp;
1647 return offset & -4096;
1651 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1654 struct drm_device *dev = crtc->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1657 struct intel_framebuffer *intel_fb;
1658 struct drm_i915_gem_object *obj;
1659 int plane = intel_crtc->plane;
1660 unsigned long Start, Offset;
1669 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1673 intel_fb = to_intel_framebuffer(fb);
1674 obj = intel_fb->obj;
1676 reg = DSPCNTR(plane);
1677 dspcntr = I915_READ(reg);
1678 /* Mask out pixel format bits in case we change it */
1679 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1680 switch (fb->bits_per_pixel) {
1682 dspcntr |= DISPPLANE_8BPP;
1685 if (fb->depth == 15)
1686 dspcntr |= DISPPLANE_BGRX555;
1688 dspcntr |= DISPPLANE_BGRX565;
1692 dspcntr |= DISPPLANE_BGRX888;
1695 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1698 if (INTEL_INFO(dev)->gen >= 4) {
1699 if (obj->tiling_mode != I915_TILING_NONE)
1700 dspcntr |= DISPPLANE_TILED;
1702 dspcntr &= ~DISPPLANE_TILED;
1705 I915_WRITE(reg, dspcntr);
1707 Start = obj->gtt_offset;
1708 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1710 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1711 Start, Offset, x, y, fb->pitches[0]);
1712 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1713 if (INTEL_INFO(dev)->gen >= 4) {
1714 I915_WRITE(DSPSURF(plane), Start);
1715 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1716 I915_WRITE(DSPADDR(plane), Offset);
1718 I915_WRITE(DSPADDR(plane), Start + Offset);
1724 static int ironlake_update_plane(struct drm_crtc *crtc,
1725 struct drm_framebuffer *fb, int x, int y)
1727 struct drm_device *dev = crtc->dev;
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1730 struct intel_framebuffer *intel_fb;
1731 struct drm_i915_gem_object *obj;
1732 int plane = intel_crtc->plane;
1733 unsigned long Start, Offset;
1743 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1747 intel_fb = to_intel_framebuffer(fb);
1748 obj = intel_fb->obj;
1750 reg = DSPCNTR(plane);
1751 dspcntr = I915_READ(reg);
1752 /* Mask out pixel format bits in case we change it */
1753 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1754 switch (fb->bits_per_pixel) {
1756 dspcntr |= DISPPLANE_8BPP;
1759 if (fb->depth != 16) {
1760 DRM_ERROR("bpp 16, depth %d\n", fb->depth);
1764 dspcntr |= DISPPLANE_BGRX565;
1768 if (fb->depth == 24)
1769 dspcntr |= DISPPLANE_BGRX888;
1770 else if (fb->depth == 30)
1771 dspcntr |= DISPPLANE_BGRX101010;
1773 DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
1779 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1783 if (obj->tiling_mode != I915_TILING_NONE)
1784 dspcntr |= DISPPLANE_TILED;
1786 dspcntr &= ~DISPPLANE_TILED;
1789 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1791 I915_WRITE(reg, dspcntr);
1793 Start = obj->gtt_offset;
1794 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1796 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1797 Start, Offset, x, y, fb->pitches[0]);
1798 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1799 I915_WRITE(DSPSURF(plane), Start);
1800 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1801 I915_WRITE(DSPADDR(plane), Offset);
1807 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1809 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1810 int x, int y, enum mode_set_atomic state)
1812 struct drm_device *dev = crtc->dev;
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1815 if (dev_priv->display.disable_fbc)
1816 dev_priv->display.disable_fbc(dev);
1817 intel_increase_pllclock(crtc);
1819 return dev_priv->display.update_plane(crtc, fb, x, y);
1823 intel_finish_fb(struct drm_framebuffer *old_fb)
1825 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1826 struct drm_device *dev = obj->base.dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828 bool was_interruptible = dev_priv->mm.interruptible;
1831 /* XXX */ lockmgr(&dev->event_lock, LK_EXCLUSIVE);
1832 while (!atomic_read(&dev_priv->mm.wedged) &&
1833 atomic_read(&obj->pending_flip) != 0) {
1834 lksleep(&obj->pending_flip, &dev->event_lock,
1837 /* XXX */ lockmgr(&dev->event_lock, LK_RELEASE);
1839 /* Big Hammer, we also need to ensure that any pending
1840 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1841 * current scanout is retired before unpinning the old
1844 * This should only fail upon a hung GPU, in which case we
1845 * can safely continue.
1847 dev_priv->mm.interruptible = false;
1848 ret = i915_gem_object_finish_gpu(obj);
1849 dev_priv->mm.interruptible = was_interruptible;
1854 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1855 struct drm_framebuffer *old_fb)
1857 struct drm_device *dev = crtc->dev;
1859 struct drm_i915_master_private *master_priv;
1861 drm_i915_private_t *dev_priv = dev->dev_private;
1863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868 DRM_ERROR("No FB bound\n");
1872 switch (intel_crtc->plane) {
1877 if (IS_IVYBRIDGE(dev))
1879 /* fall through otherwise */
1881 DRM_ERROR("no plane for crtc\n");
1886 ret = intel_pin_and_fence_fb_obj(dev,
1887 to_intel_framebuffer(crtc->fb)->obj,
1891 DRM_ERROR("pin & fence failed\n");
1896 intel_finish_fb(old_fb);
1898 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1899 LEAVE_ATOMIC_MODE_SET);
1901 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1903 DRM_ERROR("failed to update base address\n");
1908 intel_wait_for_vblank(dev, intel_crtc->pipe);
1909 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1915 if (!dev->primary->master)
1918 master_priv = dev->primary->master->driver_priv;
1919 if (!master_priv->sarea_priv)
1922 if (intel_crtc->pipe) {
1923 master_priv->sarea_priv->pipeB_x = x;
1924 master_priv->sarea_priv->pipeB_y = y;
1926 master_priv->sarea_priv->pipeA_x = x;
1927 master_priv->sarea_priv->pipeA_y = y;
1931 if (!dev_priv->sarea_priv)
1934 if (intel_crtc->pipe) {
1935 dev_priv->sarea_priv->planeB_x = x;
1936 dev_priv->sarea_priv->planeB_y = y;
1938 dev_priv->sarea_priv->planeA_x = x;
1939 dev_priv->sarea_priv->planeA_y = y;
1946 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1948 struct drm_device *dev = crtc->dev;
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1952 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1953 dpa_ctl = I915_READ(DP_A);
1954 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1956 if (clock < 200000) {
1958 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1959 /* workaround for 160Mhz:
1960 1) program 0x4600c bits 15:0 = 0x8124
1961 2) program 0x46010 bit 0 = 1
1962 3) program 0x46034 bit 24 = 1
1963 4) program 0x64000 bit 14 = 1
1965 temp = I915_READ(0x4600c);
1967 I915_WRITE(0x4600c, temp | 0x8124);
1969 temp = I915_READ(0x46010);
1970 I915_WRITE(0x46010, temp | 1);
1972 temp = I915_READ(0x46034);
1973 I915_WRITE(0x46034, temp | (1 << 24));
1975 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1977 I915_WRITE(DP_A, dpa_ctl);
1983 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1985 struct drm_device *dev = crtc->dev;
1986 struct drm_i915_private *dev_priv = dev->dev_private;
1987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1988 int pipe = intel_crtc->pipe;
1991 /* enable normal train */
1992 reg = FDI_TX_CTL(pipe);
1993 temp = I915_READ(reg);
1994 if (IS_IVYBRIDGE(dev)) {
1995 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
1996 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
1998 temp &= ~FDI_LINK_TRAIN_NONE;
1999 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2001 I915_WRITE(reg, temp);
2003 reg = FDI_RX_CTL(pipe);
2004 temp = I915_READ(reg);
2005 if (HAS_PCH_CPT(dev)) {
2006 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2007 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2009 temp &= ~FDI_LINK_TRAIN_NONE;
2010 temp |= FDI_LINK_TRAIN_NONE;
2012 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2014 /* wait one idle pattern time */
2018 /* IVB wants error correction enabled */
2019 if (IS_IVYBRIDGE(dev))
2020 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2021 FDI_FE_ERRC_ENABLE);
2024 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2027 u32 flags = I915_READ(SOUTH_CHICKEN1);
2029 flags |= FDI_PHASE_SYNC_OVR(pipe);
2030 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2031 flags |= FDI_PHASE_SYNC_EN(pipe);
2032 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2033 POSTING_READ(SOUTH_CHICKEN1);
2036 /* The FDI link training functions for ILK/Ibexpeak. */
2037 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2039 struct drm_device *dev = crtc->dev;
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2042 int pipe = intel_crtc->pipe;
2043 int plane = intel_crtc->plane;
2044 u32 reg, temp, tries;
2046 /* FDI needs bits from pipe & plane first */
2047 assert_pipe_enabled(dev_priv, pipe);
2048 assert_plane_enabled(dev_priv, plane);
2050 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2052 reg = FDI_RX_IMR(pipe);
2053 temp = I915_READ(reg);
2054 temp &= ~FDI_RX_SYMBOL_LOCK;
2055 temp &= ~FDI_RX_BIT_LOCK;
2056 I915_WRITE(reg, temp);
2060 /* enable CPU FDI TX and PCH FDI RX */
2061 reg = FDI_TX_CTL(pipe);
2062 temp = I915_READ(reg);
2064 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2065 temp &= ~FDI_LINK_TRAIN_NONE;
2066 temp |= FDI_LINK_TRAIN_PATTERN_1;
2067 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2069 reg = FDI_RX_CTL(pipe);
2070 temp = I915_READ(reg);
2071 temp &= ~FDI_LINK_TRAIN_NONE;
2072 temp |= FDI_LINK_TRAIN_PATTERN_1;
2073 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2078 /* Ironlake workaround, enable clock pointer after FDI enable*/
2079 if (HAS_PCH_IBX(dev)) {
2080 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2081 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2082 FDI_RX_PHASE_SYNC_POINTER_EN);
2085 reg = FDI_RX_IIR(pipe);
2086 for (tries = 0; tries < 5; tries++) {
2087 temp = I915_READ(reg);
2088 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2090 if ((temp & FDI_RX_BIT_LOCK)) {
2091 DRM_DEBUG_KMS("FDI train 1 done.\n");
2092 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2097 DRM_ERROR("FDI train 1 fail!\n");
2100 reg = FDI_TX_CTL(pipe);
2101 temp = I915_READ(reg);
2102 temp &= ~FDI_LINK_TRAIN_NONE;
2103 temp |= FDI_LINK_TRAIN_PATTERN_2;
2104 I915_WRITE(reg, temp);
2106 reg = FDI_RX_CTL(pipe);
2107 temp = I915_READ(reg);
2108 temp &= ~FDI_LINK_TRAIN_NONE;
2109 temp |= FDI_LINK_TRAIN_PATTERN_2;
2110 I915_WRITE(reg, temp);
2115 reg = FDI_RX_IIR(pipe);
2116 for (tries = 0; tries < 5; tries++) {
2117 temp = I915_READ(reg);
2118 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2120 if (temp & FDI_RX_SYMBOL_LOCK) {
2121 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2122 DRM_DEBUG_KMS("FDI train 2 done.\n");
2127 DRM_ERROR("FDI train 2 fail!\n");
2129 DRM_DEBUG_KMS("FDI train done\n");
2133 static const int snb_b_fdi_train_param[] = {
2134 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2135 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2136 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2137 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2140 /* The FDI link training functions for SNB/Cougarpoint. */
2141 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146 int pipe = intel_crtc->pipe;
2149 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2151 reg = FDI_RX_IMR(pipe);
2152 temp = I915_READ(reg);
2153 temp &= ~FDI_RX_SYMBOL_LOCK;
2154 temp &= ~FDI_RX_BIT_LOCK;
2155 I915_WRITE(reg, temp);
2160 /* enable CPU FDI TX and PCH FDI RX */
2161 reg = FDI_TX_CTL(pipe);
2162 temp = I915_READ(reg);
2164 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2165 temp &= ~FDI_LINK_TRAIN_NONE;
2166 temp |= FDI_LINK_TRAIN_PATTERN_1;
2167 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2169 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2170 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2172 reg = FDI_RX_CTL(pipe);
2173 temp = I915_READ(reg);
2174 if (HAS_PCH_CPT(dev)) {
2175 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2176 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2178 temp &= ~FDI_LINK_TRAIN_NONE;
2179 temp |= FDI_LINK_TRAIN_PATTERN_1;
2181 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2186 if (HAS_PCH_CPT(dev))
2187 cpt_phase_pointer_enable(dev, pipe);
2189 for (i = 0; i < 4; i++) {
2190 reg = FDI_TX_CTL(pipe);
2191 temp = I915_READ(reg);
2192 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2193 temp |= snb_b_fdi_train_param[i];
2194 I915_WRITE(reg, temp);
2199 reg = FDI_RX_IIR(pipe);
2200 temp = I915_READ(reg);
2201 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2203 if (temp & FDI_RX_BIT_LOCK) {
2204 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2205 DRM_DEBUG_KMS("FDI train 1 done.\n");
2210 DRM_ERROR("FDI train 1 fail!\n");
2213 reg = FDI_TX_CTL(pipe);
2214 temp = I915_READ(reg);
2215 temp &= ~FDI_LINK_TRAIN_NONE;
2216 temp |= FDI_LINK_TRAIN_PATTERN_2;
2218 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2220 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2222 I915_WRITE(reg, temp);
2224 reg = FDI_RX_CTL(pipe);
2225 temp = I915_READ(reg);
2226 if (HAS_PCH_CPT(dev)) {
2227 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2228 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2230 temp &= ~FDI_LINK_TRAIN_NONE;
2231 temp |= FDI_LINK_TRAIN_PATTERN_2;
2233 I915_WRITE(reg, temp);
2238 for (i = 0; i < 4; i++) {
2239 reg = FDI_TX_CTL(pipe);
2240 temp = I915_READ(reg);
2241 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2242 temp |= snb_b_fdi_train_param[i];
2243 I915_WRITE(reg, temp);
2248 reg = FDI_RX_IIR(pipe);
2249 temp = I915_READ(reg);
2250 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2252 if (temp & FDI_RX_SYMBOL_LOCK) {
2253 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2254 DRM_DEBUG_KMS("FDI train 2 done.\n");
2259 DRM_ERROR("FDI train 2 fail!\n");
2261 DRM_DEBUG_KMS("FDI train done.\n");
2264 /* Manual link training for Ivy Bridge A0 parts */
2265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2267 struct drm_device *dev = crtc->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270 int pipe = intel_crtc->pipe;
2273 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2275 reg = FDI_RX_IMR(pipe);
2276 temp = I915_READ(reg);
2277 temp &= ~FDI_RX_SYMBOL_LOCK;
2278 temp &= ~FDI_RX_BIT_LOCK;
2279 I915_WRITE(reg, temp);
2284 /* enable CPU FDI TX and PCH FDI RX */
2285 reg = FDI_TX_CTL(pipe);
2286 temp = I915_READ(reg);
2288 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2289 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2290 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2293 temp |= FDI_COMPOSITE_SYNC;
2294 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2296 reg = FDI_RX_CTL(pipe);
2297 temp = I915_READ(reg);
2298 temp &= ~FDI_LINK_TRAIN_AUTO;
2299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2300 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2301 temp |= FDI_COMPOSITE_SYNC;
2302 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2307 for (i = 0; i < 4; i++) {
2308 reg = FDI_TX_CTL(pipe);
2309 temp = I915_READ(reg);
2310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2311 temp |= snb_b_fdi_train_param[i];
2312 I915_WRITE(reg, temp);
2317 reg = FDI_RX_IIR(pipe);
2318 temp = I915_READ(reg);
2319 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2321 if (temp & FDI_RX_BIT_LOCK ||
2322 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2323 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2324 DRM_DEBUG_KMS("FDI train 1 done.\n");
2329 DRM_ERROR("FDI train 1 fail!\n");
2332 reg = FDI_TX_CTL(pipe);
2333 temp = I915_READ(reg);
2334 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2335 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2336 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2338 I915_WRITE(reg, temp);
2340 reg = FDI_RX_CTL(pipe);
2341 temp = I915_READ(reg);
2342 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2343 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2344 I915_WRITE(reg, temp);
2349 for (i = 0; i < 4; i++ ) {
2350 reg = FDI_TX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2353 temp |= snb_b_fdi_train_param[i];
2354 I915_WRITE(reg, temp);
2359 reg = FDI_RX_IIR(pipe);
2360 temp = I915_READ(reg);
2361 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2363 if (temp & FDI_RX_SYMBOL_LOCK) {
2364 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2365 DRM_DEBUG_KMS("FDI train 2 done.\n");
2370 DRM_ERROR("FDI train 2 fail!\n");
2372 DRM_DEBUG_KMS("FDI train done.\n");
2375 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2377 struct drm_device *dev = crtc->dev;
2378 struct drm_i915_private *dev_priv = dev->dev_private;
2379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2380 int pipe = intel_crtc->pipe;
2383 /* Write the TU size bits so error detection works */
2384 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2385 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2387 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 temp &= ~((0x7 << 19) | (0x7 << 16));
2391 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2392 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2393 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2398 /* Switch from Rawclk to PCDclk */
2399 temp = I915_READ(reg);
2400 I915_WRITE(reg, temp | FDI_PCDCLK);
2405 /* Enable CPU FDI TX PLL, always on for Ironlake */
2406 reg = FDI_TX_CTL(pipe);
2407 temp = I915_READ(reg);
2408 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2409 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2416 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 u32 flags = I915_READ(SOUTH_CHICKEN1);
2421 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2422 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2423 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2424 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2425 POSTING_READ(SOUTH_CHICKEN1);
2428 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2430 struct drm_device *dev = crtc->dev;
2431 struct drm_i915_private *dev_priv = dev->dev_private;
2432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2433 int pipe = intel_crtc->pipe;
2436 /* disable CPU FDI tx and PCH FDI rx */
2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2442 reg = FDI_RX_CTL(pipe);
2443 temp = I915_READ(reg);
2444 temp &= ~(0x7 << 16);
2445 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2446 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2451 /* Ironlake workaround, disable clock pointer after downing FDI */
2452 if (HAS_PCH_IBX(dev)) {
2453 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2454 I915_WRITE(FDI_RX_CHICKEN(pipe),
2455 I915_READ(FDI_RX_CHICKEN(pipe) &
2456 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2457 } else if (HAS_PCH_CPT(dev)) {
2458 cpt_phase_pointer_disable(dev, pipe);
2461 /* still set train pattern 1 */
2462 reg = FDI_TX_CTL(pipe);
2463 temp = I915_READ(reg);
2464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_1;
2466 I915_WRITE(reg, temp);
2468 reg = FDI_RX_CTL(pipe);
2469 temp = I915_READ(reg);
2470 if (HAS_PCH_CPT(dev)) {
2471 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2472 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2474 temp &= ~FDI_LINK_TRAIN_NONE;
2475 temp |= FDI_LINK_TRAIN_PATTERN_1;
2477 /* BPC in FDI rx is consistent with that in PIPECONF */
2478 temp &= ~(0x07 << 16);
2479 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2480 I915_WRITE(reg, temp);
2487 * When we disable a pipe, we need to clear any pending scanline wait events
2488 * to avoid hanging the ring, which we assume we are waiting on.
2490 static void intel_clear_scanline_wait(struct drm_device *dev)
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_ring_buffer *ring;
2497 /* Can't break the hang on i8xx */
2500 ring = LP_RING(dev_priv);
2501 tmp = I915_READ_CTL(ring);
2502 if (tmp & RING_WAIT)
2503 I915_WRITE_CTL(ring, tmp);
2506 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2508 struct drm_i915_gem_object *obj;
2509 struct drm_i915_private *dev_priv;
2510 struct drm_device *dev;
2512 if (crtc->fb == NULL)
2515 obj = to_intel_framebuffer(crtc->fb)->obj;
2517 dev_priv = dev->dev_private;
2518 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
2519 while (atomic_read(&obj->pending_flip) != 0)
2520 lksleep(&obj->pending_flip, &dev->event_lock, 0, "915wfl", 0);
2521 lockmgr(&dev->event_lock, LK_RELEASE);
2524 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2526 struct drm_device *dev = crtc->dev;
2527 struct drm_mode_config *mode_config = &dev->mode_config;
2528 struct intel_encoder *encoder;
2531 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2532 * must be driven by its own crtc; no sharing is possible.
2534 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2535 if (encoder->base.crtc != crtc)
2538 switch (encoder->type) {
2539 case INTEL_OUTPUT_EDP:
2540 if (!intel_encoder_is_pch_edp(&encoder->base))
2550 * Enable PCH resources required for PCH ports:
2552 * - FDI training & RX/TX
2553 * - update transcoder timings
2554 * - DP transcoding bits
2557 static void ironlake_pch_enable(struct drm_crtc *crtc)
2559 struct drm_device *dev = crtc->dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562 int pipe = intel_crtc->pipe;
2563 u32 reg, temp, transc_sel;
2565 /* For PCH output, training FDI link */
2566 dev_priv->display.fdi_link_train(crtc);
2568 intel_enable_pch_pll(dev_priv, pipe);
2570 if (HAS_PCH_CPT(dev)) {
2571 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2574 /* Be sure PCH DPLL SEL is set */
2575 temp = I915_READ(PCH_DPLL_SEL);
2577 temp &= ~(TRANSA_DPLLB_SEL);
2578 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2579 } else if (pipe == 1) {
2580 temp &= ~(TRANSB_DPLLB_SEL);
2581 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2582 } else if (pipe == 2) {
2583 temp &= ~(TRANSC_DPLLB_SEL);
2584 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2586 I915_WRITE(PCH_DPLL_SEL, temp);
2589 /* set transcoder timing, panel must allow it */
2590 assert_panel_unlocked(dev_priv, pipe);
2591 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2592 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2593 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2595 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2596 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2597 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2598 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2600 intel_fdi_normal_train(crtc);
2602 /* For PCH DP, enable TRANS_DP_CTL */
2603 if (HAS_PCH_CPT(dev) &&
2604 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2605 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2606 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2607 reg = TRANS_DP_CTL(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2610 TRANS_DP_SYNC_MASK |
2612 temp |= (TRANS_DP_OUTPUT_ENABLE |
2613 TRANS_DP_ENH_FRAMING);
2614 temp |= bpc << 9; /* same format but at 11:9 */
2616 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2617 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2618 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2619 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2621 switch (intel_trans_dp_port_sel(crtc)) {
2623 temp |= TRANS_DP_PORT_SEL_B;
2626 temp |= TRANS_DP_PORT_SEL_C;
2629 temp |= TRANS_DP_PORT_SEL_D;
2632 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2633 temp |= TRANS_DP_PORT_SEL_B;
2637 I915_WRITE(reg, temp);
2640 intel_enable_transcoder(dev_priv, pipe);
2643 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 int dslreg = PIPEDSL(pipe);
2649 temp = I915_READ(dslreg);
2651 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2652 if (wait_for(I915_READ(dslreg) != temp, 5))
2653 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2657 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2659 struct drm_device *dev = crtc->dev;
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662 int pipe = intel_crtc->pipe;
2663 int plane = intel_crtc->plane;
2667 if (intel_crtc->active)
2670 intel_crtc->active = true;
2671 intel_update_watermarks(dev);
2673 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2674 temp = I915_READ(PCH_LVDS);
2675 if ((temp & LVDS_PORT_EN) == 0)
2676 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2679 is_pch_port = intel_crtc_driving_pch(crtc);
2682 ironlake_fdi_pll_enable(crtc);
2684 ironlake_fdi_disable(crtc);
2686 /* Enable panel fitting for LVDS */
2687 if (dev_priv->pch_pf_size &&
2688 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2689 /* Force use of hard-coded filter coefficients
2690 * as some pre-programmed values are broken,
2693 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2694 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2695 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2698 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2699 intel_enable_plane(dev_priv, plane, pipe);
2702 ironlake_pch_enable(crtc);
2704 intel_crtc_load_lut(crtc);
2707 intel_update_fbc(dev);
2710 intel_crtc_update_cursor(crtc, true);
2713 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2715 struct drm_device *dev = crtc->dev;
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718 int pipe = intel_crtc->pipe;
2719 int plane = intel_crtc->plane;
2722 if (!intel_crtc->active)
2725 intel_crtc_wait_for_pending_flips(crtc);
2726 drm_vblank_off(dev, pipe);
2727 intel_crtc_update_cursor(crtc, false);
2729 intel_disable_plane(dev_priv, plane, pipe);
2731 if (dev_priv->cfb_plane == plane)
2732 intel_disable_fbc(dev);
2734 intel_disable_pipe(dev_priv, pipe);
2737 I915_WRITE(PF_CTL(pipe), 0);
2738 I915_WRITE(PF_WIN_SZ(pipe), 0);
2740 ironlake_fdi_disable(crtc);
2742 /* This is a horrible layering violation; we should be doing this in
2743 * the connector/encoder ->prepare instead, but we don't always have
2744 * enough information there about the config to know whether it will
2745 * actually be necessary or just cause undesired flicker.
2747 intel_disable_pch_ports(dev_priv, pipe);
2749 intel_disable_transcoder(dev_priv, pipe);
2751 if (HAS_PCH_CPT(dev)) {
2752 /* disable TRANS_DP_CTL */
2753 reg = TRANS_DP_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2756 temp |= TRANS_DP_PORT_SEL_NONE;
2757 I915_WRITE(reg, temp);
2759 /* disable DPLL_SEL */
2760 temp = I915_READ(PCH_DPLL_SEL);
2763 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2766 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2769 /* C shares PLL A or B */
2770 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2773 KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */
2775 I915_WRITE(PCH_DPLL_SEL, temp);
2778 /* disable PCH DPLL */
2779 if (!intel_crtc->no_pll)
2780 intel_disable_pch_pll(dev_priv, pipe);
2782 /* Switch from PCDclk to Rawclk */
2783 reg = FDI_RX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2787 /* Disable CPU FDI TX PLL */
2788 reg = FDI_TX_CTL(pipe);
2789 temp = I915_READ(reg);
2790 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2795 reg = FDI_RX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2799 /* Wait for the clocks to turn off. */
2803 intel_crtc->active = false;
2804 intel_update_watermarks(dev);
2807 intel_update_fbc(dev);
2808 intel_clear_scanline_wait(dev);
2812 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 int pipe = intel_crtc->pipe;
2816 int plane = intel_crtc->plane;
2818 /* XXX: When our outputs are all unaware of DPMS modes other than off
2819 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2822 case DRM_MODE_DPMS_ON:
2823 case DRM_MODE_DPMS_STANDBY:
2824 case DRM_MODE_DPMS_SUSPEND:
2825 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2826 ironlake_crtc_enable(crtc);
2829 case DRM_MODE_DPMS_OFF:
2830 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2831 ironlake_crtc_disable(crtc);
2836 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2838 if (!enable && intel_crtc->overlay) {
2839 struct drm_device *dev = intel_crtc->base.dev;
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2843 dev_priv->mm.interruptible = false;
2844 (void) intel_overlay_switch_off(intel_crtc->overlay);
2845 dev_priv->mm.interruptible = true;
2849 /* Let userspace switch the overlay on again. In most cases userspace
2850 * has to recompute where to put it anyway.
2854 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2856 struct drm_device *dev = crtc->dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2859 int pipe = intel_crtc->pipe;
2860 int plane = intel_crtc->plane;
2862 if (intel_crtc->active)
2865 intel_crtc->active = true;
2866 intel_update_watermarks(dev);
2868 intel_enable_pll(dev_priv, pipe);
2869 intel_enable_pipe(dev_priv, pipe, false);
2870 intel_enable_plane(dev_priv, plane, pipe);
2872 intel_crtc_load_lut(crtc);
2873 intel_update_fbc(dev);
2875 /* Give the overlay scaler a chance to enable if it's on this pipe */
2876 intel_crtc_dpms_overlay(intel_crtc, true);
2877 intel_crtc_update_cursor(crtc, true);
2880 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2882 struct drm_device *dev = crtc->dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 int pipe = intel_crtc->pipe;
2886 int plane = intel_crtc->plane;
2888 if (!intel_crtc->active)
2891 /* Give the overlay scaler a chance to disable if it's on this pipe */
2892 intel_crtc_wait_for_pending_flips(crtc);
2893 drm_vblank_off(dev, pipe);
2894 intel_crtc_dpms_overlay(intel_crtc, false);
2895 intel_crtc_update_cursor(crtc, false);
2897 if (dev_priv->cfb_plane == plane)
2898 intel_disable_fbc(dev);
2900 intel_disable_plane(dev_priv, plane, pipe);
2901 intel_disable_pipe(dev_priv, pipe);
2902 intel_disable_pll(dev_priv, pipe);
2904 intel_crtc->active = false;
2905 intel_update_fbc(dev);
2906 intel_update_watermarks(dev);
2907 intel_clear_scanline_wait(dev);
2910 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2912 /* XXX: When our outputs are all unaware of DPMS modes other than off
2913 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2916 case DRM_MODE_DPMS_ON:
2917 case DRM_MODE_DPMS_STANDBY:
2918 case DRM_MODE_DPMS_SUSPEND:
2919 i9xx_crtc_enable(crtc);
2921 case DRM_MODE_DPMS_OFF:
2922 i9xx_crtc_disable(crtc);
2928 * Sets the power management mode of the pipe and plane.
2930 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2935 struct drm_i915_master_private *master_priv;
2937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2938 int pipe = intel_crtc->pipe;
2941 if (intel_crtc->dpms_mode == mode)
2944 intel_crtc->dpms_mode = mode;
2946 dev_priv->display.dpms(crtc, mode);
2949 if (!dev->primary->master)
2952 master_priv = dev->primary->master->driver_priv;
2953 if (!master_priv->sarea_priv)
2956 if (!dev_priv->sarea_priv)
2960 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2965 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2966 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2968 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0;
2969 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0;
2974 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2975 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2977 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0;
2978 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0;
2982 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2987 static void intel_crtc_disable(struct drm_crtc *crtc)
2989 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2990 struct drm_device *dev = crtc->dev;
2992 /* Flush any pending WAITs before we disable the pipe. Note that
2993 * we need to drop the struct_mutex in order to acquire it again
2994 * during the lowlevel dpms routines around a couple of the
2995 * operations. It does not look trivial nor desirable to move
2996 * that locking higher. So instead we leave a window for the
2997 * submission of further commands on the fb before we can actually
2998 * disable it. This race with userspace exists anyway, and we can
2999 * only rely on the pipe being disabled by userspace after it
3000 * receives the hotplug notification and has flushed any pending
3005 intel_finish_fb(crtc->fb);
3009 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3010 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3011 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3015 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3020 /* Prepare for a mode set.
3022 * Note we could be a lot smarter here. We need to figure out which outputs
3023 * will be enabled, which disabled (in short, how the config will changes)
3024 * and perform the minimum necessary steps to accomplish that, e.g. updating
3025 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3026 * panel fitting is in the proper state, etc.
3028 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3030 i9xx_crtc_disable(crtc);
3033 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3035 i9xx_crtc_enable(crtc);
3038 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3040 ironlake_crtc_disable(crtc);
3043 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3045 ironlake_crtc_enable(crtc);
3048 void intel_encoder_prepare(struct drm_encoder *encoder)
3050 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3051 /* lvds has its own version of prepare see intel_lvds_prepare */
3052 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3055 void intel_encoder_commit(struct drm_encoder *encoder)
3057 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3058 struct drm_device *dev = encoder->dev;
3059 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3060 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3062 /* lvds has its own version of commit see intel_lvds_commit */
3063 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3065 if (HAS_PCH_CPT(dev))
3066 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3069 void intel_encoder_destroy(struct drm_encoder *encoder)
3071 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3073 drm_encoder_cleanup(encoder);
3074 drm_free(intel_encoder, DRM_MEM_KMS);
3077 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3078 const struct drm_display_mode *mode,
3079 struct drm_display_mode *adjusted_mode)
3081 struct drm_device *dev = crtc->dev;
3083 if (HAS_PCH_SPLIT(dev)) {
3084 /* FDI link clock is fixed at 2.7G */
3085 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3089 /* All interlaced capable intel hw wants timings in frames. Note though
3090 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3091 * timings, so we need to be careful not to clobber these.*/
3092 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3093 drm_mode_set_crtcinfo(adjusted_mode, 0);
3098 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3100 return 400000; /* FIXME */
3103 static int i945_get_display_clock_speed(struct drm_device *dev)
3108 static int i915_get_display_clock_speed(struct drm_device *dev)
3113 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3118 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3122 gcfgc = pci_read_config(dev->dev, GCFGC, 2);
3124 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3127 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3128 case GC_DISPLAY_CLOCK_333_MHZ:
3131 case GC_DISPLAY_CLOCK_190_200_MHZ:
3137 static int i865_get_display_clock_speed(struct drm_device *dev)
3142 static int i855_get_display_clock_speed(struct drm_device *dev)
3145 /* Assume that the hardware is in the high speed state. This
3146 * should be the default.
3148 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3149 case GC_CLOCK_133_200:
3150 case GC_CLOCK_100_200:
3152 case GC_CLOCK_166_250:
3154 case GC_CLOCK_100_133:
3158 /* Shouldn't happen */
3162 static int i830_get_display_clock_speed(struct drm_device *dev)
3176 fdi_reduce_ratio(u32 *num, u32 *den)
3178 while (*num > 0xffffff || *den > 0xffffff) {
3185 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3186 int link_clock, struct fdi_m_n *m_n)
3188 m_n->tu = 64; /* default size */
3190 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3191 m_n->gmch_m = bits_per_pixel * pixel_clock;
3192 m_n->gmch_n = link_clock * nlanes * 8;
3193 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3195 m_n->link_m = pixel_clock;
3196 m_n->link_n = link_clock;
3197 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3200 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3202 if (i915_panel_use_ssc >= 0)
3203 return i915_panel_use_ssc != 0;
3204 return dev_priv->lvds_use_ssc
3205 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3209 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3210 * @crtc: CRTC structure
3211 * @mode: requested mode
3213 * A pipe may be connected to one or more outputs. Based on the depth of the
3214 * attached framebuffer, choose a good color depth to use on the pipe.
3216 * If possible, match the pipe depth to the fb depth. In some cases, this
3217 * isn't ideal, because the connected output supports a lesser or restricted
3218 * set of depths. Resolve that here:
3219 * LVDS typically supports only 6bpc, so clamp down in that case
3220 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3221 * Displays may support a restricted set as well, check EDID and clamp as
3223 * DP may want to dither down to 6bpc to fit larger modes
3226 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3227 * true if they don't match).
3229 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3230 unsigned int *pipe_bpp,
3231 struct drm_display_mode *mode)
3233 struct drm_device *dev = crtc->dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct drm_encoder *encoder;
3236 struct drm_connector *connector;
3237 unsigned int display_bpc = UINT_MAX, bpc;
3239 /* Walk the encoders & connectors on this crtc, get min bpc */
3240 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3241 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3243 if (encoder->crtc != crtc)
3246 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3247 unsigned int lvds_bpc;
3249 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3255 if (lvds_bpc < display_bpc) {
3256 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3257 display_bpc = lvds_bpc;
3262 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3263 /* Use VBT settings if we have an eDP panel */
3264 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3266 if (edp_bpc < display_bpc) {
3267 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3268 display_bpc = edp_bpc;
3273 /* Not one of the known troublemakers, check the EDID */
3274 list_for_each_entry(connector, &dev->mode_config.connector_list,
3276 if (connector->encoder != encoder)
3279 /* Don't use an invalid EDID bpc value */
3280 if (connector->display_info.bpc &&
3281 connector->display_info.bpc < display_bpc) {
3282 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3283 display_bpc = connector->display_info.bpc;
3288 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3289 * through, clamp it down. (Note: >12bpc will be caught below.)
3291 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3292 if (display_bpc > 8 && display_bpc < 12) {
3293 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3296 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3302 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3303 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3308 * We could just drive the pipe at the highest bpc all the time and
3309 * enable dithering as needed, but that costs bandwidth. So choose
3310 * the minimum value that expresses the full color range of the fb but
3311 * also stays within the max display bpc discovered above.
3314 switch (crtc->fb->depth) {
3316 bpc = 8; /* since we go through a colormap */
3320 bpc = 6; /* min is 18bpp */
3332 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3333 bpc = min((unsigned int)8, display_bpc);
3337 display_bpc = min(display_bpc, bpc);
3339 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3342 *pipe_bpp = display_bpc * 3;
3344 return display_bpc != bpc;
3347 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3349 struct drm_device *dev = crtc->dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3353 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3354 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3355 refclk = dev_priv->lvds_ssc_freq * 1000;
3356 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3358 } else if (!IS_GEN2(dev)) {
3367 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3368 intel_clock_t *clock)
3370 /* SDVO TV has fixed PLL values depend on its clock range,
3371 this mirrors vbios setting. */
3372 if (adjusted_mode->clock >= 100000
3373 && adjusted_mode->clock < 140500) {
3379 } else if (adjusted_mode->clock >= 140500
3380 && adjusted_mode->clock <= 200000) {
3389 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3390 intel_clock_t *clock,
3391 intel_clock_t *reduced_clock)
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 int pipe = intel_crtc->pipe;
3399 if (IS_PINEVIEW(dev)) {
3400 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3402 fp2 = (1 << reduced_clock->n) << 16 |
3403 reduced_clock->m1 << 8 | reduced_clock->m2;
3405 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3407 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3411 I915_WRITE(FP0(pipe), fp);
3413 intel_crtc->lowfreq_avail = false;
3414 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3415 reduced_clock && i915_powersave) {
3416 I915_WRITE(FP1(pipe), fp2);
3417 intel_crtc->lowfreq_avail = true;
3419 I915_WRITE(FP1(pipe), fp);
3423 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3424 struct drm_display_mode *mode,
3425 struct drm_display_mode *adjusted_mode,
3427 struct drm_framebuffer *old_fb)
3429 struct drm_device *dev = crtc->dev;
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3432 int pipe = intel_crtc->pipe;
3433 int plane = intel_crtc->plane;
3434 int refclk, num_connectors = 0;
3435 intel_clock_t clock, reduced_clock;
3436 u32 dpll, dspcntr, pipeconf, vsyncshift;
3437 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3438 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3439 struct drm_mode_config *mode_config = &dev->mode_config;
3440 struct intel_encoder *encoder;
3441 const intel_limit_t *limit;
3446 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3447 if (encoder->base.crtc != crtc)
3450 switch (encoder->type) {
3451 case INTEL_OUTPUT_LVDS:
3454 case INTEL_OUTPUT_SDVO:
3455 case INTEL_OUTPUT_HDMI:
3457 if (encoder->needs_tv_clock)
3460 case INTEL_OUTPUT_DVO:
3463 case INTEL_OUTPUT_TVOUT:
3466 case INTEL_OUTPUT_ANALOG:
3469 case INTEL_OUTPUT_DISPLAYPORT:
3477 refclk = i9xx_get_refclk(crtc, num_connectors);
3480 * Returns a set of divisors for the desired target clock with the given
3481 * refclk, or false. The returned values represent the clock equation:
3482 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3484 limit = intel_limit(crtc, refclk);
3485 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3488 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3492 /* Ensure that the cursor is valid for the new mode before changing... */
3493 intel_crtc_update_cursor(crtc, true);
3495 if (is_lvds && dev_priv->lvds_downclock_avail) {
3497 * Ensure we match the reduced clock's P to the target clock.
3498 * If the clocks don't match, we can't switch the display clock
3499 * by using the FP0/FP1. In such case we will disable the LVDS
3500 * downclock feature.
3502 has_reduced_clock = limit->find_pll(limit, crtc,
3503 dev_priv->lvds_downclock,
3509 if (is_sdvo && is_tv)
3510 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3512 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3513 &reduced_clock : NULL);
3515 dpll = DPLL_VGA_MODE_DIS;
3517 if (!IS_GEN2(dev)) {
3519 dpll |= DPLLB_MODE_LVDS;
3521 dpll |= DPLLB_MODE_DAC_SERIAL;
3523 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3524 if (pixel_multiplier > 1) {
3525 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3526 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3528 dpll |= DPLL_DVO_HIGH_SPEED;
3531 dpll |= DPLL_DVO_HIGH_SPEED;
3533 /* compute bitmask from p1 value */
3534 if (IS_PINEVIEW(dev))
3535 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3537 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3538 if (IS_G4X(dev) && has_reduced_clock)
3539 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3543 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3546 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3549 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3552 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3555 if (INTEL_INFO(dev)->gen >= 4)
3556 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3559 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3562 dpll |= PLL_P1_DIVIDE_BY_TWO;
3564 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3566 dpll |= PLL_P2_DIVIDE_BY_4;
3570 if (is_sdvo && is_tv)
3571 dpll |= PLL_REF_INPUT_TVCLKINBC;
3573 /* XXX: just matching BIOS for now */
3574 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3576 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3577 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3579 dpll |= PLL_REF_INPUT_DREFCLK;
3581 /* setup pipeconf */
3582 pipeconf = I915_READ(PIPECONF(pipe));
3584 /* Set up the display plane register */
3585 dspcntr = DISPPLANE_GAMMA_ENABLE;
3588 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3590 dspcntr |= DISPPLANE_SEL_PIPE_B;
3592 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3593 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3596 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3600 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3601 pipeconf |= PIPECONF_DOUBLE_WIDE;
3603 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3606 /* default to 8bpc */
3607 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3609 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3610 pipeconf |= PIPECONF_BPP_6 |
3611 PIPECONF_DITHER_EN |
3612 PIPECONF_DITHER_TYPE_SP;
3616 dpll |= DPLL_VCO_ENABLE;
3618 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3619 drm_mode_debug_printmodeline(mode);
3621 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3623 POSTING_READ(DPLL(pipe));
3626 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3627 * This is an exception to the general rule that mode_set doesn't turn
3631 temp = I915_READ(LVDS);
3632 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3634 temp |= LVDS_PIPEB_SELECT;
3636 temp &= ~LVDS_PIPEB_SELECT;
3638 /* set the corresponsding LVDS_BORDER bit */
3639 temp |= dev_priv->lvds_border_bits;
3640 /* Set the B0-B3 data pairs corresponding to whether we're going to
3641 * set the DPLLs for dual-channel mode or not.
3644 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3646 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3648 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3649 * appropriately here, but we need to look more thoroughly into how
3650 * panels behave in the two modes.
3652 /* set the dithering flag on LVDS as needed */
3653 if (INTEL_INFO(dev)->gen >= 4) {
3654 if (dev_priv->lvds_dither)
3655 temp |= LVDS_ENABLE_DITHER;
3657 temp &= ~LVDS_ENABLE_DITHER;
3659 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3660 lvds_sync |= LVDS_HSYNC_POLARITY;
3661 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3662 lvds_sync |= LVDS_VSYNC_POLARITY;
3663 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
3665 char flags[2] = "-+";
3666 DRM_INFO("Changing LVDS panel from "
3667 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
3668 flags[!(temp & LVDS_HSYNC_POLARITY)],
3669 flags[!(temp & LVDS_VSYNC_POLARITY)],
3670 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
3671 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
3672 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3675 I915_WRITE(LVDS, temp);
3679 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3682 I915_WRITE(DPLL(pipe), dpll);
3684 /* Wait for the clocks to stabilize. */
3685 POSTING_READ(DPLL(pipe));
3688 if (INTEL_INFO(dev)->gen >= 4) {
3691 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3693 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3697 I915_WRITE(DPLL_MD(pipe), temp);
3699 /* The pixel multiplier can only be updated once the
3700 * DPLL is enabled and the clocks are stable.
3702 * So write it again.
3704 I915_WRITE(DPLL(pipe), dpll);
3707 if (HAS_PIPE_CXSR(dev)) {
3708 if (intel_crtc->lowfreq_avail) {
3709 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3710 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3712 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3713 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3717 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3718 if (!IS_GEN2(dev) &&
3719 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3720 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3721 /* the chip adds 2 halflines automatically */
3722 adjusted_mode->crtc_vtotal -= 1;
3723 adjusted_mode->crtc_vblank_end -= 1;
3724 vsyncshift = adjusted_mode->crtc_hsync_start
3725 - adjusted_mode->crtc_htotal/2;
3727 pipeconf |= PIPECONF_PROGRESSIVE;
3732 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3734 I915_WRITE(HTOTAL(pipe),
3735 (adjusted_mode->crtc_hdisplay - 1) |
3736 ((adjusted_mode->crtc_htotal - 1) << 16));
3737 I915_WRITE(HBLANK(pipe),
3738 (adjusted_mode->crtc_hblank_start - 1) |
3739 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3740 I915_WRITE(HSYNC(pipe),
3741 (adjusted_mode->crtc_hsync_start - 1) |
3742 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3744 I915_WRITE(VTOTAL(pipe),
3745 (adjusted_mode->crtc_vdisplay - 1) |
3746 ((adjusted_mode->crtc_vtotal - 1) << 16));
3747 I915_WRITE(VBLANK(pipe),
3748 (adjusted_mode->crtc_vblank_start - 1) |
3749 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3750 I915_WRITE(VSYNC(pipe),
3751 (adjusted_mode->crtc_vsync_start - 1) |
3752 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3754 /* pipesrc and dspsize control the size that is scaled from,
3755 * which should always be the user's requested size.
3757 I915_WRITE(DSPSIZE(plane),
3758 ((mode->vdisplay - 1) << 16) |
3759 (mode->hdisplay - 1));
3760 I915_WRITE(DSPPOS(plane), 0);
3761 I915_WRITE(PIPESRC(pipe),
3762 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3764 I915_WRITE(PIPECONF(pipe), pipeconf);
3765 POSTING_READ(PIPECONF(pipe));
3766 intel_enable_pipe(dev_priv, pipe, false);
3768 intel_wait_for_vblank(dev, pipe);
3770 I915_WRITE(DSPCNTR(plane), dspcntr);
3771 POSTING_READ(DSPCNTR(plane));
3772 intel_enable_plane(dev_priv, plane, pipe);
3774 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3776 intel_update_watermarks(dev);
3782 * Initialize reference clocks when the driver loads
3784 void ironlake_init_pch_refclk(struct drm_device *dev)
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct drm_mode_config *mode_config = &dev->mode_config;
3788 struct intel_encoder *encoder;
3790 bool has_lvds = false;
3791 bool has_cpu_edp = false;
3792 bool has_pch_edp = false;
3793 bool has_panel = false;
3794 bool has_ck505 = false;
3795 bool can_ssc = false;
3797 /* We need to take the global config into account */
3798 list_for_each_entry(encoder, &mode_config->encoder_list,
3800 switch (encoder->type) {
3801 case INTEL_OUTPUT_LVDS:
3805 case INTEL_OUTPUT_EDP:
3807 if (intel_encoder_is_pch_edp(&encoder->base))
3815 if (HAS_PCH_IBX(dev)) {
3816 has_ck505 = dev_priv->display_clock_mode;
3817 can_ssc = has_ck505;
3823 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3824 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3827 /* Ironlake: try to setup display ref clock before DPLL
3828 * enabling. This is only under driver's control after
3829 * PCH B stepping, previous chipset stepping should be
3830 * ignoring this setting.
3832 temp = I915_READ(PCH_DREF_CONTROL);
3833 /* Always enable nonspread source */
3834 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3837 temp |= DREF_NONSPREAD_CK505_ENABLE;
3839 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3842 temp &= ~DREF_SSC_SOURCE_MASK;
3843 temp |= DREF_SSC_SOURCE_ENABLE;
3845 /* SSC must be turned on before enabling the CPU output */
3846 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3847 DRM_DEBUG_KMS("Using SSC on panel\n");
3848 temp |= DREF_SSC1_ENABLE;
3850 temp &= ~DREF_SSC1_ENABLE;
3852 /* Get SSC going before enabling the outputs */
3853 I915_WRITE(PCH_DREF_CONTROL, temp);
3854 POSTING_READ(PCH_DREF_CONTROL);
3857 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3859 /* Enable CPU source on CPU attached eDP */
3861 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3862 DRM_DEBUG_KMS("Using SSC on eDP\n");
3863 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3866 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3868 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3870 I915_WRITE(PCH_DREF_CONTROL, temp);
3871 POSTING_READ(PCH_DREF_CONTROL);
3874 DRM_DEBUG_KMS("Disabling SSC entirely\n");
3876 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3878 /* Turn off CPU output */
3879 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3881 I915_WRITE(PCH_DREF_CONTROL, temp);
3882 POSTING_READ(PCH_DREF_CONTROL);
3885 /* Turn off the SSC source */
3886 temp &= ~DREF_SSC_SOURCE_MASK;
3887 temp |= DREF_SSC_SOURCE_DISABLE;
3890 temp &= ~ DREF_SSC1_ENABLE;
3892 I915_WRITE(PCH_DREF_CONTROL, temp);
3893 POSTING_READ(PCH_DREF_CONTROL);
3898 static int ironlake_get_refclk(struct drm_crtc *crtc)
3900 struct drm_device *dev = crtc->dev;
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902 struct intel_encoder *encoder;
3903 struct drm_mode_config *mode_config = &dev->mode_config;
3904 struct intel_encoder *edp_encoder = NULL;
3905 int num_connectors = 0;
3906 bool is_lvds = false;
3908 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3909 if (encoder->base.crtc != crtc)
3912 switch (encoder->type) {
3913 case INTEL_OUTPUT_LVDS:
3916 case INTEL_OUTPUT_EDP:
3917 edp_encoder = encoder;
3923 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3924 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3925 dev_priv->lvds_ssc_freq);
3926 return dev_priv->lvds_ssc_freq * 1000;
3932 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
3933 struct drm_display_mode *mode,
3934 struct drm_display_mode *adjusted_mode,
3936 struct drm_framebuffer *old_fb)
3938 struct drm_device *dev = crtc->dev;
3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3941 int pipe = intel_crtc->pipe;
3942 int plane = intel_crtc->plane;
3943 int refclk, num_connectors = 0;
3944 intel_clock_t clock, reduced_clock;
3945 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3946 bool ok, has_reduced_clock = false, is_sdvo = false;
3947 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3948 struct intel_encoder *has_edp_encoder = NULL;
3949 struct drm_mode_config *mode_config = &dev->mode_config;
3950 struct intel_encoder *encoder;
3951 const intel_limit_t *limit;
3953 struct fdi_m_n m_n = {0};
3956 int target_clock, pixel_multiplier, lane, link_bw, factor;
3957 unsigned int pipe_bpp;
3960 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3961 if (encoder->base.crtc != crtc)
3964 switch (encoder->type) {
3965 case INTEL_OUTPUT_LVDS:
3968 case INTEL_OUTPUT_SDVO:
3969 case INTEL_OUTPUT_HDMI:
3971 if (encoder->needs_tv_clock)
3974 case INTEL_OUTPUT_TVOUT:
3977 case INTEL_OUTPUT_ANALOG:
3980 case INTEL_OUTPUT_DISPLAYPORT:
3983 case INTEL_OUTPUT_EDP:
3984 has_edp_encoder = encoder;
3991 refclk = ironlake_get_refclk(crtc);
3994 * Returns a set of divisors for the desired target clock with the given
3995 * refclk, or false. The returned values represent the clock equation:
3996 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3998 limit = intel_limit(crtc, refclk);
3999 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4002 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4006 /* Ensure that the cursor is valid for the new mode before changing... */
4007 intel_crtc_update_cursor(crtc, true);
4009 if (is_lvds && dev_priv->lvds_downclock_avail) {
4011 * Ensure we match the reduced clock's P to the target clock.
4012 * If the clocks don't match, we can't switch the display clock
4013 * by using the FP0/FP1. In such case we will disable the LVDS
4014 * downclock feature.
4016 has_reduced_clock = limit->find_pll(limit, crtc,
4017 dev_priv->lvds_downclock,
4022 /* SDVO TV has fixed PLL values depend on its clock range,
4023 this mirrors vbios setting. */
4024 if (is_sdvo && is_tv) {
4025 if (adjusted_mode->clock >= 100000
4026 && adjusted_mode->clock < 140500) {
4032 } else if (adjusted_mode->clock >= 140500
4033 && adjusted_mode->clock <= 200000) {
4043 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4045 /* CPU eDP doesn't require FDI link, so just set DP M/N
4046 according to current link config */
4047 if (has_edp_encoder &&
4048 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4049 target_clock = mode->clock;
4050 intel_edp_link_config(has_edp_encoder,
4053 /* [e]DP over FDI requires target mode clock
4054 instead of link clock */
4055 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4056 target_clock = mode->clock;
4058 target_clock = adjusted_mode->clock;
4060 /* FDI is a binary signal running at ~2.7GHz, encoding
4061 * each output octet as 10 bits. The actual frequency
4062 * is stored as a divider into a 100MHz clock, and the
4063 * mode pixel clock is stored in units of 1KHz.
4064 * Hence the bw of each lane in terms of the mode signal
4067 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4070 /* determine panel color depth */
4071 temp = I915_READ(PIPECONF(pipe));
4072 temp &= ~PIPE_BPC_MASK;
4073 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4088 kprintf("intel_choose_pipe_bpp returned invalid value %d\n",
4095 intel_crtc->bpp = pipe_bpp;
4096 I915_WRITE(PIPECONF(pipe), temp);
4100 * Account for spread spectrum to avoid
4101 * oversubscribing the link. Max center spread
4102 * is 2.5%; use 5% for safety's sake.
4104 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4105 lane = bps / (link_bw * 8) + 1;
4108 intel_crtc->fdi_lanes = lane;
4110 if (pixel_multiplier > 1)
4111 link_bw *= pixel_multiplier;
4112 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4115 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4116 if (has_reduced_clock)
4117 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4120 /* Enable autotuning of the PLL clock (if permissible) */
4123 if ((intel_panel_use_ssc(dev_priv) &&
4124 dev_priv->lvds_ssc_freq == 100) ||
4125 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4127 } else if (is_sdvo && is_tv)
4130 if (clock.m < factor * clock.n)
4136 dpll |= DPLLB_MODE_LVDS;
4138 dpll |= DPLLB_MODE_DAC_SERIAL;
4140 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4141 if (pixel_multiplier > 1) {
4142 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4144 dpll |= DPLL_DVO_HIGH_SPEED;
4146 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4147 dpll |= DPLL_DVO_HIGH_SPEED;
4149 /* compute bitmask from p1 value */
4150 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4152 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4156 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4159 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4162 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4165 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4169 if (is_sdvo && is_tv)
4170 dpll |= PLL_REF_INPUT_TVCLKINBC;
4172 /* XXX: just matching BIOS for now */
4173 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4175 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4176 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4178 dpll |= PLL_REF_INPUT_DREFCLK;
4180 /* setup pipeconf */
4181 pipeconf = I915_READ(PIPECONF(pipe));
4183 /* Set up the display plane register */
4184 dspcntr = DISPPLANE_GAMMA_ENABLE;
4186 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4187 drm_mode_debug_printmodeline(mode);
4189 /* PCH eDP needs FDI, but CPU eDP does not */
4190 if (!intel_crtc->no_pll) {
4191 if (!has_edp_encoder ||
4192 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4193 I915_WRITE(_PCH_FP0(pipe), fp);
4194 I915_WRITE(_PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4196 POSTING_READ(_PCH_DPLL(pipe));
4200 if (dpll == (I915_READ(_PCH_DPLL(0)) & 0x7fffffff) &&
4201 fp == I915_READ(_PCH_FP0(0))) {
4202 intel_crtc->use_pll_a = true;
4203 DRM_DEBUG_KMS("using pipe a dpll\n");
4204 } else if (dpll == (I915_READ(_PCH_DPLL(1)) & 0x7fffffff) &&
4205 fp == I915_READ(_PCH_FP0(1))) {
4206 intel_crtc->use_pll_a = false;
4207 DRM_DEBUG_KMS("using pipe b dpll\n");
4209 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
4214 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4215 * This is an exception to the general rule that mode_set doesn't turn
4219 temp = I915_READ(PCH_LVDS);
4220 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4221 if (HAS_PCH_CPT(dev)) {
4222 temp &= ~PORT_TRANS_SEL_MASK;
4223 temp |= PORT_TRANS_SEL_CPT(pipe);
4226 temp |= LVDS_PIPEB_SELECT;
4228 temp &= ~LVDS_PIPEB_SELECT;
4231 /* set the corresponsding LVDS_BORDER bit */
4232 temp |= dev_priv->lvds_border_bits;
4233 /* Set the B0-B3 data pairs corresponding to whether we're going to
4234 * set the DPLLs for dual-channel mode or not.
4237 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4239 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4241 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4242 * appropriately here, but we need to look more thoroughly into how
4243 * panels behave in the two modes.
4245 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4246 lvds_sync |= LVDS_HSYNC_POLARITY;
4247 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4248 lvds_sync |= LVDS_VSYNC_POLARITY;
4249 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4251 char flags[2] = "-+";
4252 DRM_INFO("Changing LVDS panel from "
4253 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4254 flags[!(temp & LVDS_HSYNC_POLARITY)],
4255 flags[!(temp & LVDS_VSYNC_POLARITY)],
4256 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4257 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4258 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4261 I915_WRITE(PCH_LVDS, temp);
4264 pipeconf &= ~PIPECONF_DITHER_EN;
4265 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4266 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4267 pipeconf |= PIPECONF_DITHER_EN;
4268 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4270 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4271 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4273 /* For non-DP output, clear any trans DP clock recovery setting.*/
4274 I915_WRITE(TRANSDATA_M1(pipe), 0);
4275 I915_WRITE(TRANSDATA_N1(pipe), 0);
4276 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4277 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4280 if (!intel_crtc->no_pll &&
4281 (!has_edp_encoder ||
4282 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
4283 I915_WRITE(_PCH_DPLL(pipe), dpll);
4285 /* Wait for the clocks to stabilize. */
4286 POSTING_READ(_PCH_DPLL(pipe));
4289 /* The pixel multiplier can only be updated once the
4290 * DPLL is enabled and the clocks are stable.
4292 * So write it again.
4294 I915_WRITE(_PCH_DPLL(pipe), dpll);
4297 intel_crtc->lowfreq_avail = false;
4298 if (!intel_crtc->no_pll) {
4299 if (is_lvds && has_reduced_clock && i915_powersave) {
4300 I915_WRITE(_PCH_FP1(pipe), fp2);
4301 intel_crtc->lowfreq_avail = true;
4302 if (HAS_PIPE_CXSR(dev)) {
4303 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4304 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4307 I915_WRITE(_PCH_FP1(pipe), fp);
4308 if (HAS_PIPE_CXSR(dev)) {
4309 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4310 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4315 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4316 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4317 pipeconf |= PIPECONF_INTERLACED_ILK;
4318 /* the chip adds 2 halflines automatically */
4319 adjusted_mode->crtc_vtotal -= 1;
4320 adjusted_mode->crtc_vblank_end -= 1;
4321 I915_WRITE(VSYNCSHIFT(pipe),
4322 adjusted_mode->crtc_hsync_start
4323 - adjusted_mode->crtc_htotal/2);
4325 pipeconf |= PIPECONF_PROGRESSIVE;
4326 I915_WRITE(VSYNCSHIFT(pipe), 0);
4329 I915_WRITE(HTOTAL(pipe),
4330 (adjusted_mode->crtc_hdisplay - 1) |
4331 ((adjusted_mode->crtc_htotal - 1) << 16));
4332 I915_WRITE(HBLANK(pipe),
4333 (adjusted_mode->crtc_hblank_start - 1) |
4334 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4335 I915_WRITE(HSYNC(pipe),
4336 (adjusted_mode->crtc_hsync_start - 1) |
4337 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4339 I915_WRITE(VTOTAL(pipe),
4340 (adjusted_mode->crtc_vdisplay - 1) |
4341 ((adjusted_mode->crtc_vtotal - 1) << 16));
4342 I915_WRITE(VBLANK(pipe),
4343 (adjusted_mode->crtc_vblank_start - 1) |
4344 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4345 I915_WRITE(VSYNC(pipe),
4346 (adjusted_mode->crtc_vsync_start - 1) |
4347 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4349 /* pipesrc controls the size that is scaled from, which should
4350 * always be the user's requested size.
4352 I915_WRITE(PIPESRC(pipe),
4353 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4355 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4356 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4357 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4358 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4360 if (has_edp_encoder &&
4361 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4362 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4365 I915_WRITE(PIPECONF(pipe), pipeconf);
4366 POSTING_READ(PIPECONF(pipe));
4368 intel_wait_for_vblank(dev, pipe);
4370 I915_WRITE(DSPCNTR(plane), dspcntr);
4371 POSTING_READ(DSPCNTR(plane));
4373 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4375 intel_update_watermarks(dev);
4380 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4381 struct drm_display_mode *mode,
4382 struct drm_display_mode *adjusted_mode,
4384 struct drm_framebuffer *old_fb)
4386 struct drm_device *dev = crtc->dev;
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4389 int pipe = intel_crtc->pipe;
4392 drm_vblank_pre_modeset(dev, pipe);
4394 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4396 drm_vblank_post_modeset(dev, pipe);
4399 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4401 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4406 static bool intel_eld_uptodate(struct drm_connector *connector,
4407 int reg_eldv, uint32_t bits_eldv,
4408 int reg_elda, uint32_t bits_elda,
4411 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4412 uint8_t *eld = connector->eld;
4415 i = I915_READ(reg_eldv);
4424 i = I915_READ(reg_elda);
4426 I915_WRITE(reg_elda, i);
4428 for (i = 0; i < eld[2]; i++)
4429 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4435 static void g4x_write_eld(struct drm_connector *connector,
4436 struct drm_crtc *crtc)
4438 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4439 uint8_t *eld = connector->eld;
4444 i = I915_READ(G4X_AUD_VID_DID);
4446 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4447 eldv = G4X_ELDV_DEVCL_DEVBLC;
4449 eldv = G4X_ELDV_DEVCTG;
4451 if (intel_eld_uptodate(connector,
4452 G4X_AUD_CNTL_ST, eldv,
4453 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4454 G4X_HDMIW_HDMIEDID))
4457 i = I915_READ(G4X_AUD_CNTL_ST);
4458 i &= ~(eldv | G4X_ELD_ADDR);
4459 len = (i >> 9) & 0x1f; /* ELD buffer size */
4460 I915_WRITE(G4X_AUD_CNTL_ST, i);
4465 if (eld[2] < (uint8_t)len)
4467 DRM_DEBUG_KMS("ELD size %d\n", len);
4468 for (i = 0; i < len; i++)
4469 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4471 i = I915_READ(G4X_AUD_CNTL_ST);
4473 I915_WRITE(G4X_AUD_CNTL_ST, i);
4476 static void ironlake_write_eld(struct drm_connector *connector,
4477 struct drm_crtc *crtc)
4479 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4480 uint8_t *eld = connector->eld;
4489 if (HAS_PCH_IBX(connector->dev)) {
4490 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4491 aud_config = IBX_AUD_CONFIG_A;
4492 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4493 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4495 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4496 aud_config = CPT_AUD_CONFIG_A;
4497 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4498 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4501 i = to_intel_crtc(crtc)->pipe;
4502 hdmiw_hdmiedid += i * 0x100;
4503 aud_cntl_st += i * 0x100;
4504 aud_config += i * 0x100;
4506 DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i));
4508 i = I915_READ(aud_cntl_st);
4509 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4511 DRM_DEBUG_KMS("Audio directed to unknown port\n");
4512 /* operate blindly on all ports */
4513 eldv = IBX_ELD_VALIDB;
4514 eldv |= IBX_ELD_VALIDB << 4;
4515 eldv |= IBX_ELD_VALIDB << 8;
4517 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i);
4518 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4521 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4522 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4523 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4524 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4526 I915_WRITE(aud_config, 0);
4528 if (intel_eld_uptodate(connector,
4529 aud_cntrl_st2, eldv,
4530 aud_cntl_st, IBX_ELD_ADDRESS,
4534 i = I915_READ(aud_cntrl_st2);
4536 I915_WRITE(aud_cntrl_st2, i);
4541 i = I915_READ(aud_cntl_st);
4542 i &= ~IBX_ELD_ADDRESS;
4543 I915_WRITE(aud_cntl_st, i);
4545 /* 84 bytes of hw ELD buffer */
4547 if (eld[2] < (uint8_t)len)
4549 DRM_DEBUG_KMS("ELD size %d\n", len);
4550 for (i = 0; i < len; i++)
4551 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4553 i = I915_READ(aud_cntrl_st2);
4555 I915_WRITE(aud_cntrl_st2, i);
4558 void intel_write_eld(struct drm_encoder *encoder,
4559 struct drm_display_mode *mode)
4561 struct drm_crtc *crtc = encoder->crtc;
4562 struct drm_connector *connector;
4563 struct drm_device *dev = encoder->dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4566 connector = drm_select_eld(encoder, mode);
4570 DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4572 drm_get_connector_name(connector),
4573 connector->encoder->base.id,
4574 drm_get_encoder_name(connector->encoder));
4576 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4578 if (dev_priv->display.write_eld)
4579 dev_priv->display.write_eld(connector, crtc);
4582 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4583 void intel_crtc_load_lut(struct drm_crtc *crtc)
4585 struct drm_device *dev = crtc->dev;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
4587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4588 int palreg = PALETTE(intel_crtc->pipe);
4591 /* The clocks have to be on to load the palette. */
4592 if (!crtc->enabled || !intel_crtc->active)
4595 /* use legacy palette for Ironlake */
4596 if (HAS_PCH_SPLIT(dev))
4597 palreg = LGC_PALETTE(intel_crtc->pipe);
4599 for (i = 0; i < 256; i++) {
4600 I915_WRITE(palreg + 4 * i,
4601 (intel_crtc->lut_r[i] << 16) |
4602 (intel_crtc->lut_g[i] << 8) |
4603 intel_crtc->lut_b[i]);
4607 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4609 struct drm_device *dev = crtc->dev;
4610 struct drm_i915_private *dev_priv = dev->dev_private;
4611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4612 bool visible = base != 0;
4615 if (intel_crtc->cursor_visible == visible)
4618 cntl = I915_READ(_CURACNTR);
4620 /* On these chipsets we can only modify the base whilst
4621 * the cursor is disabled.
4623 I915_WRITE(_CURABASE, base);
4625 cntl &= ~(CURSOR_FORMAT_MASK);
4626 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4627 cntl |= CURSOR_ENABLE |
4628 CURSOR_GAMMA_ENABLE |
4631 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4632 I915_WRITE(_CURACNTR, cntl);
4634 intel_crtc->cursor_visible = visible;
4637 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4639 struct drm_device *dev = crtc->dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642 int pipe = intel_crtc->pipe;
4643 bool visible = base != 0;
4645 if (intel_crtc->cursor_visible != visible) {
4646 uint32_t cntl = I915_READ(CURCNTR(pipe));
4648 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4649 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4650 cntl |= pipe << 28; /* Connect to correct pipe */
4652 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4653 cntl |= CURSOR_MODE_DISABLE;
4655 I915_WRITE(CURCNTR(pipe), cntl);
4657 intel_crtc->cursor_visible = visible;
4659 /* and commit changes on next vblank */
4660 I915_WRITE(CURBASE(pipe), base);
4663 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4665 struct drm_device *dev = crtc->dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4668 int pipe = intel_crtc->pipe;
4669 bool visible = base != 0;
4671 if (intel_crtc->cursor_visible != visible) {
4672 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4674 cntl &= ~CURSOR_MODE;
4675 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4677 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4678 cntl |= CURSOR_MODE_DISABLE;
4680 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4682 intel_crtc->cursor_visible = visible;
4684 /* and commit changes on next vblank */
4685 I915_WRITE(CURBASE_IVB(pipe), base);
4688 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4689 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4692 struct drm_device *dev = crtc->dev;
4693 struct drm_i915_private *dev_priv = dev->dev_private;
4694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4695 int pipe = intel_crtc->pipe;
4696 int x = intel_crtc->cursor_x;
4697 int y = intel_crtc->cursor_y;
4703 if (on && crtc->enabled && crtc->fb) {
4704 base = intel_crtc->cursor_addr;
4705 if (x > (int) crtc->fb->width)
4708 if (y > (int) crtc->fb->height)
4714 if (x + intel_crtc->cursor_width < 0)
4717 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4720 pos |= x << CURSOR_X_SHIFT;
4723 if (y + intel_crtc->cursor_height < 0)
4726 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4729 pos |= y << CURSOR_Y_SHIFT;
4731 visible = base != 0;
4732 if (!visible && !intel_crtc->cursor_visible)
4735 if (IS_IVYBRIDGE(dev)) {
4736 I915_WRITE(CURPOS_IVB(pipe), pos);
4737 ivb_update_cursor(crtc, base);
4739 I915_WRITE(CURPOS(pipe), pos);
4740 if (IS_845G(dev) || IS_I865G(dev))
4741 i845_update_cursor(crtc, base);
4743 i9xx_update_cursor(crtc, base);
4747 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4748 struct drm_file *file,
4750 uint32_t width, uint32_t height)
4752 struct drm_device *dev = crtc->dev;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4755 struct drm_i915_gem_object *obj;
4759 DRM_DEBUG_KMS("\n");
4761 /* if we want to turn off the cursor ignore width and height */
4763 DRM_DEBUG_KMS("cursor off\n");
4770 /* Currently we only support 64x64 cursors */
4771 if (width != 64 || height != 64) {
4772 DRM_ERROR("we currently only support 64x64 cursors\n");
4776 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4777 if (&obj->base == NULL)
4780 if (obj->base.size < width * height * 4) {
4781 DRM_ERROR("buffer is to small\n");
4786 /* we only need to pin inside GTT if cursor is non-phy */
4788 if (!dev_priv->info->cursor_needs_physical) {
4789 if (obj->tiling_mode) {
4790 DRM_ERROR("cursor cannot be tiled\n");
4795 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4797 DRM_ERROR("failed to move cursor bo into the GTT\n");
4801 ret = i915_gem_object_put_fence(obj);
4803 DRM_ERROR("failed to release fence for cursor\n");
4807 addr = obj->gtt_offset;
4809 int align = IS_I830(dev) ? 16 * 1024 : 256;
4810 ret = i915_gem_attach_phys_object(dev, obj,
4811 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4814 DRM_ERROR("failed to attach phys object\n");
4817 addr = obj->phys_obj->handle->busaddr;
4821 I915_WRITE(CURSIZE, (height << 12) | width);
4824 if (intel_crtc->cursor_bo) {
4825 if (dev_priv->info->cursor_needs_physical) {
4826 if (intel_crtc->cursor_bo != obj)
4827 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4829 i915_gem_object_unpin(intel_crtc->cursor_bo);
4830 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4835 intel_crtc->cursor_addr = addr;
4836 intel_crtc->cursor_bo = obj;
4837 intel_crtc->cursor_width = width;
4838 intel_crtc->cursor_height = height;
4840 intel_crtc_update_cursor(crtc, true);
4844 i915_gem_object_unpin(obj);
4848 drm_gem_object_unreference_unlocked(&obj->base);
4852 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4856 intel_crtc->cursor_x = x;
4857 intel_crtc->cursor_y = y;
4859 intel_crtc_update_cursor(crtc, true);
4864 /** Sets the color ramps on behalf of RandR */
4865 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4866 u16 blue, int regno)
4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4870 intel_crtc->lut_r[regno] = red >> 8;
4871 intel_crtc->lut_g[regno] = green >> 8;
4872 intel_crtc->lut_b[regno] = blue >> 8;
4875 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4876 u16 *blue, int regno)
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4880 *red = intel_crtc->lut_r[regno] << 8;
4881 *green = intel_crtc->lut_g[regno] << 8;
4882 *blue = intel_crtc->lut_b[regno] << 8;
4885 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4886 u16 *blue, uint32_t start, uint32_t size)
4888 int end = (start + size > 256) ? 256 : start + size, i;
4889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891 for (i = start; i < end; i++) {
4892 intel_crtc->lut_r[i] = red[i] >> 8;
4893 intel_crtc->lut_g[i] = green[i] >> 8;
4894 intel_crtc->lut_b[i] = blue[i] >> 8;
4897 intel_crtc_load_lut(crtc);
4901 * Get a pipe with a simple mode set on it for doing load-based monitor
4904 * It will be up to the load-detect code to adjust the pipe as appropriate for
4905 * its requirements. The pipe will be connected to no other encoders.
4907 * Currently this code will only succeed if there is a pipe with no encoders
4908 * configured for it. In the future, it could choose to temporarily disable
4909 * some outputs to free up a pipe for its use.
4911 * \return crtc, or NULL if no pipes are available.
4914 /* VESA 640x480x72Hz mode to set on the pipe */
4915 static struct drm_display_mode load_detect_mode = {
4916 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4917 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4920 static struct drm_framebuffer *
4921 intel_framebuffer_create(struct drm_device *dev,
4922 struct drm_mode_fb_cmd2 *mode_cmd,
4923 struct drm_i915_gem_object *obj)
4925 struct intel_framebuffer *intel_fb;
4928 intel_fb = kmalloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO);
4930 drm_gem_object_unreference_unlocked(&obj->base);
4931 return ERR_PTR(-ENOMEM);
4934 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
4936 drm_gem_object_unreference_unlocked(&obj->base);
4937 kfree(intel_fb, DRM_MEM_KMS);
4938 return ERR_PTR(ret);
4941 return &intel_fb->base;
4945 intel_framebuffer_pitch_for_width(int width, int bpp)
4947 u32 pitch = howmany(width * bpp, 8);
4948 return roundup2(pitch, 64);
4952 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
4954 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
4955 return roundup2(pitch * mode->vdisplay, PAGE_SIZE);
4958 static struct drm_framebuffer *
4959 intel_framebuffer_create_for_mode(struct drm_device *dev,
4960 struct drm_display_mode *mode,
4963 struct drm_i915_gem_object *obj;
4964 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
4966 obj = i915_gem_alloc_object(dev,
4967 intel_framebuffer_size_for_mode(mode, bpp));
4969 return ERR_PTR(-ENOMEM);
4971 mode_cmd.width = mode->hdisplay;
4972 mode_cmd.height = mode->vdisplay;
4973 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
4975 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
4977 return intel_framebuffer_create(dev, &mode_cmd, obj);
4981 mode_fits_in_fbdev(struct drm_device *dev,
4982 struct drm_display_mode *mode, struct drm_framebuffer **res)
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 struct drm_i915_gem_object *obj;
4986 struct drm_framebuffer *fb;
4988 if (dev_priv->fbdev == NULL) {
4993 obj = dev_priv->fbdev->ifb.obj;
4999 fb = &dev_priv->fbdev->ifb.base;
5000 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5001 fb->bits_per_pixel)) {
5006 if (obj->base.size < mode->vdisplay * fb->pitches[0]) {
5015 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5016 struct drm_connector *connector,
5017 struct drm_display_mode *mode,
5018 struct intel_load_detect_pipe *old)
5020 struct intel_crtc *intel_crtc;
5021 struct drm_crtc *possible_crtc;
5022 struct drm_encoder *encoder = &intel_encoder->base;
5023 struct drm_crtc *crtc = NULL;
5024 struct drm_device *dev = encoder->dev;
5025 struct drm_framebuffer *old_fb;
5028 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5029 connector->base.id, drm_get_connector_name(connector),
5030 encoder->base.id, drm_get_encoder_name(encoder));
5033 * Algorithm gets a little messy:
5035 * - if the connector already has an assigned crtc, use it (but make
5036 * sure it's on first)
5038 * - try to find the first unused crtc that can drive this connector,
5039 * and use that if we find one
5042 /* See if we already have a CRTC for this connector */
5043 if (encoder->crtc) {
5044 crtc = encoder->crtc;
5046 intel_crtc = to_intel_crtc(crtc);
5047 old->dpms_mode = intel_crtc->dpms_mode;
5048 old->load_detect_temp = false;
5050 /* Make sure the crtc and connector are running */
5051 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5052 struct drm_encoder_helper_funcs *encoder_funcs;
5053 struct drm_crtc_helper_funcs *crtc_funcs;
5055 crtc_funcs = crtc->helper_private;
5056 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5058 encoder_funcs = encoder->helper_private;
5059 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5065 /* Find an unused one (if possible) */
5066 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5068 if (!(encoder->possible_crtcs & (1 << i)))
5070 if (!possible_crtc->enabled) {
5071 crtc = possible_crtc;
5077 * If we didn't find an unused CRTC, don't use any.
5080 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5084 encoder->crtc = crtc;
5085 connector->encoder = encoder;
5087 intel_crtc = to_intel_crtc(crtc);
5088 old->dpms_mode = intel_crtc->dpms_mode;
5089 old->load_detect_temp = true;
5090 old->release_fb = NULL;
5093 mode = &load_detect_mode;
5097 /* We need a framebuffer large enough to accommodate all accesses
5098 * that the plane may generate whilst we perform load detection.
5099 * We can not rely on the fbcon either being present (we get called
5100 * during its initialisation to detect all boot displays, or it may
5101 * not even exist) or that it is large enough to satisfy the
5104 r = mode_fits_in_fbdev(dev, mode, &crtc->fb);
5105 if (crtc->fb == NULL) {
5106 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5107 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5108 old->release_fb = crtc->fb;
5110 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5111 if (IS_ERR(crtc->fb)) {
5112 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5116 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5117 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5118 if (old->release_fb)
5119 old->release_fb->funcs->destroy(old->release_fb);
5124 /* let the connector get through one full cycle before testing */
5125 intel_wait_for_vblank(dev, intel_crtc->pipe);
5130 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5131 struct drm_connector *connector,
5132 struct intel_load_detect_pipe *old)
5134 struct drm_encoder *encoder = &intel_encoder->base;
5135 struct drm_device *dev = encoder->dev;
5136 struct drm_crtc *crtc = encoder->crtc;
5137 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5138 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5141 connector->base.id, drm_get_connector_name(connector),
5142 encoder->base.id, drm_get_encoder_name(encoder));
5144 if (old->load_detect_temp) {
5145 connector->encoder = NULL;
5146 drm_helper_disable_unused_functions(dev);
5148 if (old->release_fb)
5149 old->release_fb->funcs->destroy(old->release_fb);
5154 /* Switch crtc and encoder back off if necessary */
5155 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5156 encoder_funcs->dpms(encoder, old->dpms_mode);
5157 crtc_funcs->dpms(crtc, old->dpms_mode);
5161 /* Returns the clock of the currently programmed mode of the given pipe. */
5162 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5164 struct drm_i915_private *dev_priv = dev->dev_private;
5165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5166 int pipe = intel_crtc->pipe;
5167 u32 dpll = I915_READ(DPLL(pipe));
5169 intel_clock_t clock;
5171 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5172 fp = I915_READ(FP0(pipe));
5174 fp = I915_READ(FP1(pipe));
5176 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5177 if (IS_PINEVIEW(dev)) {
5178 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5179 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5181 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5182 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5185 if (!IS_GEN2(dev)) {
5186 if (IS_PINEVIEW(dev))
5187 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5188 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5190 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5191 DPLL_FPA01_P1_POST_DIV_SHIFT);
5193 switch (dpll & DPLL_MODE_MASK) {
5194 case DPLLB_MODE_DAC_SERIAL:
5195 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5198 case DPLLB_MODE_LVDS:
5199 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5203 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5204 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5208 /* XXX: Handle the 100Mhz refclk */
5209 intel_clock(dev, 96000, &clock);
5211 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5214 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5215 DPLL_FPA01_P1_POST_DIV_SHIFT);
5218 if ((dpll & PLL_REF_INPUT_MASK) ==
5219 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5220 /* XXX: might not be 66MHz */
5221 intel_clock(dev, 66000, &clock);
5223 intel_clock(dev, 48000, &clock);
5225 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5228 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5229 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5231 if (dpll & PLL_P2_DIVIDE_BY_4)
5236 intel_clock(dev, 48000, &clock);
5240 /* XXX: It would be nice to validate the clocks, but we can't reuse
5241 * i830PllIsValid() because it relies on the xf86_config connector
5242 * configuration being accurate, which it isn't necessarily.
5248 /** Returns the currently programmed mode of the given pipe. */
5249 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5250 struct drm_crtc *crtc)
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254 int pipe = intel_crtc->pipe;
5255 struct drm_display_mode *mode;
5256 int htot = I915_READ(HTOTAL(pipe));
5257 int hsync = I915_READ(HSYNC(pipe));
5258 int vtot = I915_READ(VTOTAL(pipe));
5259 int vsync = I915_READ(VSYNC(pipe));
5261 mode = kmalloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO);
5263 mode->clock = intel_crtc_clock_get(dev, crtc);
5264 mode->hdisplay = (htot & 0xffff) + 1;
5265 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5266 mode->hsync_start = (hsync & 0xffff) + 1;
5267 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5268 mode->vdisplay = (vtot & 0xffff) + 1;
5269 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5270 mode->vsync_start = (vsync & 0xffff) + 1;
5271 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5273 drm_mode_set_name(mode);
5274 drm_mode_set_crtcinfo(mode, 0);
5279 static void intel_increase_pllclock(struct drm_crtc *crtc)
5281 struct drm_device *dev = crtc->dev;
5282 drm_i915_private_t *dev_priv = dev->dev_private;
5283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5284 int pipe = intel_crtc->pipe;
5285 int dpll_reg = DPLL(pipe);
5288 if (HAS_PCH_SPLIT(dev))
5291 if (!dev_priv->lvds_downclock_avail)
5294 dpll = I915_READ(dpll_reg);
5295 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5296 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5298 assert_panel_unlocked(dev_priv, pipe);
5300 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5301 I915_WRITE(dpll_reg, dpll);
5302 intel_wait_for_vblank(dev, pipe);
5304 dpll = I915_READ(dpll_reg);
5305 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5306 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5310 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5312 struct drm_device *dev = crtc->dev;
5313 drm_i915_private_t *dev_priv = dev->dev_private;
5314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5316 if (HAS_PCH_SPLIT(dev))
5319 if (!dev_priv->lvds_downclock_avail)
5323 * Since this is called by a timer, we should never get here in
5326 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5327 int pipe = intel_crtc->pipe;
5328 int dpll_reg = DPLL(pipe);
5331 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5333 assert_panel_unlocked(dev_priv, pipe);
5335 dpll = I915_READ(dpll_reg);
5336 dpll |= DISPLAY_RATE_SELECT_FPA1;
5337 I915_WRITE(dpll_reg, dpll);
5338 intel_wait_for_vblank(dev, pipe);
5339 dpll = I915_READ(dpll_reg);
5340 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5341 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5345 void intel_mark_busy(struct drm_device *dev)
5347 i915_update_gfx_val(dev->dev_private);
5350 void intel_mark_idle(struct drm_device *dev)
5352 struct drm_crtc *crtc;
5354 if (!i915_powersave)
5357 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5361 intel_decrease_pllclock(crtc);
5365 static void intel_crtc_destroy(struct drm_crtc *crtc)
5367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5368 struct drm_device *dev = crtc->dev;
5369 struct intel_unpin_work *work;
5371 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5372 work = intel_crtc->unpin_work;
5373 intel_crtc->unpin_work = NULL;
5374 lockmgr(&dev->event_lock, LK_RELEASE);
5377 cancel_work_sync(&work->work);
5378 kfree(work, DRM_MEM_KMS);
5381 drm_crtc_cleanup(crtc);
5383 drm_free(intel_crtc, DRM_MEM_KMS);
5386 static void intel_unpin_work_fn(struct work_struct *__work)
5388 struct intel_unpin_work *work =
5389 container_of(__work, struct intel_unpin_work, work);
5390 struct drm_device *dev;
5394 intel_unpin_fb_obj(work->old_fb_obj);
5395 drm_gem_object_unreference(&work->pending_flip_obj->base);
5396 drm_gem_object_unreference(&work->old_fb_obj->base);
5398 intel_update_fbc(work->dev);
5400 drm_free(work, DRM_MEM_KMS);
5403 static void do_intel_finish_page_flip(struct drm_device *dev,
5404 struct drm_crtc *crtc)
5406 drm_i915_private_t *dev_priv = dev->dev_private;
5407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5408 struct intel_unpin_work *work;
5409 struct drm_i915_gem_object *obj;
5411 /* Ignore early vblank irqs */
5412 if (intel_crtc == NULL)
5415 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5416 work = intel_crtc->unpin_work;
5417 if (work == NULL || !atomic_read(&work->pending)) {
5418 lockmgr(&dev->event_lock, LK_RELEASE);
5422 intel_crtc->unpin_work = NULL;
5425 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
5427 drm_vblank_put(dev, intel_crtc->pipe);
5429 lockmgr(&dev->event_lock, LK_RELEASE);
5431 obj = work->old_fb_obj;
5433 atomic_clear_mask(1 << intel_crtc->plane,
5434 &obj->pending_flip.counter);
5435 wakeup(&obj->pending_flip);
5437 queue_work(dev_priv->wq, &work->work);
5440 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5442 drm_i915_private_t *dev_priv = dev->dev_private;
5443 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5445 do_intel_finish_page_flip(dev, crtc);
5448 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5450 drm_i915_private_t *dev_priv = dev->dev_private;
5451 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5453 do_intel_finish_page_flip(dev, crtc);
5456 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5458 drm_i915_private_t *dev_priv = dev->dev_private;
5459 struct intel_crtc *intel_crtc =
5460 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5462 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5463 if (intel_crtc->unpin_work)
5464 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
5465 lockmgr(&dev->event_lock, LK_RELEASE);
5468 static int intel_gen2_queue_flip(struct drm_device *dev,
5469 struct drm_crtc *crtc,
5470 struct drm_framebuffer *fb,
5471 struct drm_i915_gem_object *obj)
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5475 unsigned long offset;
5479 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5483 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5484 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5486 ret = BEGIN_LP_RING(6);
5490 /* Can't queue multiple flips, so wait for the previous
5491 * one to finish before executing the next.
5493 if (intel_crtc->plane)
5494 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5496 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5497 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5499 OUT_RING(MI_DISPLAY_FLIP |
5500 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5501 OUT_RING(fb->pitches[0]);
5502 OUT_RING(obj->gtt_offset + offset);
5503 OUT_RING(0); /* aux display base address, unused */
5509 static int intel_gen3_queue_flip(struct drm_device *dev,
5510 struct drm_crtc *crtc,
5511 struct drm_framebuffer *fb,
5512 struct drm_i915_gem_object *obj)
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5516 unsigned long offset;
5520 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5524 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5525 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5527 ret = BEGIN_LP_RING(6);
5531 if (intel_crtc->plane)
5532 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5534 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5535 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5537 OUT_RING(MI_DISPLAY_FLIP_I915 |
5538 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5539 OUT_RING(fb->pitches[0]);
5540 OUT_RING(obj->gtt_offset + offset);
5548 static int intel_gen4_queue_flip(struct drm_device *dev,
5549 struct drm_crtc *crtc,
5550 struct drm_framebuffer *fb,
5551 struct drm_i915_gem_object *obj)
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5555 uint32_t pf, pipesrc;
5558 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5562 ret = BEGIN_LP_RING(4);
5566 /* i965+ uses the linear or tiled offsets from the
5567 * Display Registers (which do not change across a page-flip)
5568 * so we need only reprogram the base address.
5570 OUT_RING(MI_DISPLAY_FLIP |
5571 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5572 OUT_RING(fb->pitches[0]);
5573 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5575 /* XXX Enabling the panel-fitter across page-flip is so far
5576 * untested on non-native modes, so ignore it for now.
5577 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5580 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5581 OUT_RING(pf | pipesrc);
5587 static int intel_gen6_queue_flip(struct drm_device *dev,
5588 struct drm_crtc *crtc,
5589 struct drm_framebuffer *fb,
5590 struct drm_i915_gem_object *obj)
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5594 uint32_t pf, pipesrc;
5597 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5601 ret = BEGIN_LP_RING(4);
5605 OUT_RING(MI_DISPLAY_FLIP |
5606 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5607 OUT_RING(fb->pitches[0] | obj->tiling_mode);
5608 OUT_RING(obj->gtt_offset);
5610 /* Contrary to the suggestions in the documentation,
5611 * "Enable Panel Fitter" does not seem to be required when page
5612 * flipping with a non-native mode, and worse causes a normal
5614 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5617 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5618 OUT_RING(pf | pipesrc);
5625 * On gen7 we currently use the blit ring because (in early silicon at least)
5626 * the render ring doesn't give us interrpts for page flip completion, which
5627 * means clients will hang after the first flip is queued. Fortunately the
5628 * blit ring generates interrupts properly, so use it instead.
5630 static int intel_gen7_queue_flip(struct drm_device *dev,
5631 struct drm_crtc *crtc,
5632 struct drm_framebuffer *fb,
5633 struct drm_i915_gem_object *obj)
5635 struct drm_i915_private *dev_priv = dev->dev_private;
5636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5637 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5640 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5644 ret = intel_ring_begin(ring, 4);
5648 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5649 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5650 intel_ring_emit(ring, (obj->gtt_offset));
5651 intel_ring_emit(ring, (MI_NOOP));
5652 intel_ring_advance(ring);
5657 static int intel_default_queue_flip(struct drm_device *dev,
5658 struct drm_crtc *crtc,
5659 struct drm_framebuffer *fb,
5660 struct drm_i915_gem_object *obj)
5665 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5666 struct drm_framebuffer *fb,
5667 struct drm_pending_vblank_event *event)
5669 struct drm_device *dev = crtc->dev;
5670 struct drm_i915_private *dev_priv = dev->dev_private;
5671 struct intel_framebuffer *intel_fb;
5672 struct drm_i915_gem_object *obj;
5673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5674 struct intel_unpin_work *work;
5677 work = kmalloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
5679 work->event = event;
5680 work->dev = crtc->dev;
5681 intel_fb = to_intel_framebuffer(crtc->fb);
5682 work->old_fb_obj = intel_fb->obj;
5683 INIT_WORK(&work->work, intel_unpin_work_fn);
5685 ret = drm_vblank_get(dev, intel_crtc->pipe);
5689 /* We borrow the event spin lock for protecting unpin_work */
5690 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5691 if (intel_crtc->unpin_work) {
5692 lockmgr(&dev->event_lock, LK_RELEASE);
5693 drm_free(work, DRM_MEM_KMS);
5694 drm_vblank_put(dev, intel_crtc->pipe);
5696 DRM_DEBUG("flip queue: crtc already busy\n");
5699 intel_crtc->unpin_work = work;
5700 lockmgr(&dev->event_lock, LK_RELEASE);
5702 intel_fb = to_intel_framebuffer(fb);
5703 obj = intel_fb->obj;
5707 /* Reference the objects for the scheduled work. */
5708 drm_gem_object_reference(&work->old_fb_obj->base);
5709 drm_gem_object_reference(&obj->base);
5713 work->pending_flip_obj = obj;
5715 work->enable_stall_check = true;
5717 /* Block clients from rendering to the new back buffer until
5718 * the flip occurs and the object is no longer visible.
5720 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5722 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5724 goto cleanup_pending;
5725 intel_disable_fbc(dev);
5731 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5732 drm_gem_object_unreference(&work->old_fb_obj->base);
5733 drm_gem_object_unreference(&obj->base);
5736 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5737 intel_crtc->unpin_work = NULL;
5738 lockmgr(&dev->event_lock, LK_RELEASE);
5740 drm_vblank_put(dev, intel_crtc->pipe);
5742 drm_free(work, DRM_MEM_KMS);
5747 static void intel_sanitize_modesetting(struct drm_device *dev,
5748 int pipe, int plane)
5750 struct drm_i915_private *dev_priv = dev->dev_private;
5753 /* Clear any frame start delays used for debugging left by the BIOS */
5754 for_each_pipe(pipe) {
5755 reg = PIPECONF(pipe);
5756 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
5759 if (HAS_PCH_SPLIT(dev))
5762 /* Who knows what state these registers were left in by the BIOS or
5765 * If we leave the registers in a conflicting state (e.g. with the
5766 * display plane reading from the other pipe than the one we intend
5767 * to use) then when we attempt to teardown the active mode, we will
5768 * not disable the pipes and planes in the correct order -- leaving
5769 * a plane reading from a disabled pipe and possibly leading to
5770 * undefined behaviour.
5773 reg = DSPCNTR(plane);
5774 val = I915_READ(reg);
5776 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5778 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5781 /* This display plane is active and attached to the other CPU pipe. */
5784 /* Disable the plane and wait for it to stop reading from the pipe. */
5785 intel_disable_plane(dev_priv, plane, pipe);
5786 intel_disable_pipe(dev_priv, pipe);
5789 static void intel_crtc_reset(struct drm_crtc *crtc)
5791 struct drm_device *dev = crtc->dev;
5792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5794 /* Reset flags back to the 'unknown' status so that they
5795 * will be correctly set on the initial modeset.
5797 intel_crtc->dpms_mode = -1;
5799 /* We need to fix up any BIOS configuration that conflicts with
5802 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5805 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5806 .dpms = intel_crtc_dpms,
5807 .mode_fixup = intel_crtc_mode_fixup,
5808 .mode_set = intel_crtc_mode_set,
5809 .mode_set_base = intel_pipe_set_base,
5810 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5811 .load_lut = intel_crtc_load_lut,
5812 .disable = intel_crtc_disable,
5815 static const struct drm_crtc_funcs intel_crtc_funcs = {
5816 .reset = intel_crtc_reset,
5817 .cursor_set = intel_crtc_cursor_set,
5818 .cursor_move = intel_crtc_cursor_move,
5819 .gamma_set = intel_crtc_gamma_set,
5820 .set_config = drm_crtc_helper_set_config,
5821 .destroy = intel_crtc_destroy,
5822 .page_flip = intel_crtc_page_flip,
5825 static void intel_cpu_pll_init(struct drm_device *dev)
5828 if (IS_HASWELL(dev))
5829 intel_ddi_pll_init(dev);
5833 static void intel_pch_pll_init(struct drm_device *dev)
5835 drm_i915_private_t *dev_priv = dev->dev_private;
5838 if (dev_priv->num_pch_pll == 0) {
5839 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
5843 for (i = 0; i < dev_priv->num_pch_pll; i++) {
5844 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
5845 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
5846 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
5850 static void intel_crtc_init(struct drm_device *dev, int pipe)
5852 drm_i915_private_t *dev_priv = dev->dev_private;
5853 struct intel_crtc *intel_crtc;
5856 intel_crtc = kmalloc(sizeof(struct intel_crtc) +
5857 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
5858 DRM_MEM_KMS, M_WAITOK | M_ZERO);
5860 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5862 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5863 for (i = 0; i < 256; i++) {
5864 intel_crtc->lut_r[i] = i;
5865 intel_crtc->lut_g[i] = i;
5866 intel_crtc->lut_b[i] = i;
5869 /* Swap pipes & planes for FBC on pre-965 */
5870 intel_crtc->pipe = pipe;
5871 intel_crtc->plane = pipe;
5872 intel_crtc->cpu_transcoder = pipe;
5873 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5874 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5875 intel_crtc->plane = !pipe;
5878 KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) &&
5879 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL,
5880 ("plane_to_crtc is already initialized"));
5881 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5882 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5884 intel_crtc_reset(&intel_crtc->base);
5885 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5886 intel_crtc->bpp = 24; /* default for pre-Ironlake */
5888 if (HAS_PCH_SPLIT(dev)) {
5889 if (pipe == 2 && IS_IVYBRIDGE(dev))
5890 intel_crtc->no_pll = true;
5891 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5892 intel_helper_funcs.commit = ironlake_crtc_commit;
5894 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5895 intel_helper_funcs.commit = i9xx_crtc_commit;
5898 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5900 intel_crtc->busy = false;
5902 callout_init_mp(&intel_crtc->idle_callout);
5905 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5906 struct drm_file *file)
5908 drm_i915_private_t *dev_priv = dev->dev_private;
5909 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5910 struct drm_mode_object *drmmode_obj;
5911 struct intel_crtc *crtc;
5914 DRM_ERROR("called with no initialization\n");
5918 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5919 DRM_MODE_OBJECT_CRTC);
5922 DRM_ERROR("no such CRTC id\n");
5926 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5927 pipe_from_crtc_id->pipe = crtc->pipe;
5932 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5934 struct intel_encoder *encoder;
5938 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5939 if (type_mask & encoder->clone_mask)
5940 index_mask |= (1 << entry);
5947 static bool has_edp_a(struct drm_device *dev)
5949 struct drm_i915_private *dev_priv = dev->dev_private;
5951 if (!IS_MOBILE(dev))
5954 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5958 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5964 static void intel_setup_outputs(struct drm_device *dev)
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 struct intel_encoder *encoder;
5968 bool dpd_is_edp = false;
5971 has_lvds = intel_lvds_init(dev);
5972 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5973 /* disable the panel fitter on everything but LVDS */
5974 I915_WRITE(PFIT_CONTROL, 0);
5977 if (HAS_PCH_SPLIT(dev)) {
5978 dpd_is_edp = intel_dpd_is_edp(dev);
5981 intel_dp_init(dev, DP_A);
5983 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5984 intel_dp_init(dev, PCH_DP_D);
5987 intel_crt_init(dev);
5989 if (HAS_PCH_SPLIT(dev)) {
5993 "HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n",
5994 (I915_READ(HDMIB) & PORT_DETECTED) != 0,
5995 (I915_READ(PCH_DP_B) & DP_DETECTED) != 0,
5996 (I915_READ(HDMIC) & PORT_DETECTED) != 0,
5997 (I915_READ(HDMID) & PORT_DETECTED) != 0,
5998 (I915_READ(PCH_DP_C) & DP_DETECTED) != 0,
5999 (I915_READ(PCH_DP_D) & DP_DETECTED) != 0,
6000 (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0);
6002 if (I915_READ(HDMIB) & PORT_DETECTED) {
6003 /* PCH SDVOB multiplex with HDMIB */
6004 found = intel_sdvo_init(dev, PCH_SDVOB);
6006 intel_hdmi_init(dev, HDMIB);
6007 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6008 intel_dp_init(dev, PCH_DP_B);
6011 if (I915_READ(HDMIC) & PORT_DETECTED)
6012 intel_hdmi_init(dev, HDMIC);
6014 if (I915_READ(HDMID) & PORT_DETECTED)
6015 intel_hdmi_init(dev, HDMID);
6017 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6018 intel_dp_init(dev, PCH_DP_C);
6020 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6021 intel_dp_init(dev, PCH_DP_D);
6023 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6026 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6027 DRM_DEBUG_KMS("probing SDVOB\n");
6028 found = intel_sdvo_init(dev, SDVOB);
6029 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6030 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6031 intel_hdmi_init(dev, SDVOB);
6034 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6035 DRM_DEBUG_KMS("probing DP_B\n");
6036 intel_dp_init(dev, DP_B);
6040 /* Before G4X SDVOC doesn't have its own detect register */
6042 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6043 DRM_DEBUG_KMS("probing SDVOC\n");
6044 found = intel_sdvo_init(dev, SDVOC);
6047 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6049 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6050 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6051 intel_hdmi_init(dev, SDVOC);
6053 if (SUPPORTS_INTEGRATED_DP(dev)) {
6054 DRM_DEBUG_KMS("probing DP_C\n");
6055 intel_dp_init(dev, DP_C);
6059 if (SUPPORTS_INTEGRATED_DP(dev) &&
6060 (I915_READ(DP_D) & DP_DETECTED)) {
6061 DRM_DEBUG_KMS("probing DP_D\n");
6062 intel_dp_init(dev, DP_D);
6064 } else if (IS_GEN2(dev)) {
6068 intel_dvo_init(dev);
6072 if (SUPPORTS_TV(dev))
6075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6076 encoder->base.possible_crtcs = encoder->crtc_mask;
6077 encoder->base.possible_clones =
6078 intel_encoder_clones(dev, encoder->clone_mask);
6081 /* disable all the possible outputs/crtcs before entering KMS mode */
6082 drm_helper_disable_unused_functions(dev);
6084 if (HAS_PCH_SPLIT(dev))
6085 ironlake_init_pch_refclk(dev);
6088 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6090 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6092 drm_framebuffer_cleanup(fb);
6093 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6095 drm_free(intel_fb, DRM_MEM_KMS);
6098 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6099 struct drm_file *file,
6100 unsigned int *handle)
6102 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6103 struct drm_i915_gem_object *obj = intel_fb->obj;
6105 return drm_gem_handle_create(file, &obj->base, handle);
6108 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6109 .destroy = intel_user_framebuffer_destroy,
6110 .create_handle = intel_user_framebuffer_create_handle,
6113 int intel_framebuffer_init(struct drm_device *dev,
6114 struct intel_framebuffer *intel_fb,
6115 struct drm_mode_fb_cmd2 *mode_cmd,
6116 struct drm_i915_gem_object *obj)
6120 if (obj->tiling_mode == I915_TILING_Y)
6123 if (mode_cmd->pitches[0] & 63)
6126 switch (mode_cmd->pixel_format) {
6127 case DRM_FORMAT_RGB332:
6128 case DRM_FORMAT_RGB565:
6129 case DRM_FORMAT_XRGB8888:
6130 case DRM_FORMAT_XBGR8888:
6131 case DRM_FORMAT_ARGB8888:
6132 case DRM_FORMAT_XRGB2101010:
6133 case DRM_FORMAT_ARGB2101010:
6134 /* RGB formats are common across chipsets */
6136 case DRM_FORMAT_YUYV:
6137 case DRM_FORMAT_UYVY:
6138 case DRM_FORMAT_YVYU:
6139 case DRM_FORMAT_VYUY:
6142 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6143 mode_cmd->pixel_format);
6147 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6149 DRM_ERROR("framebuffer init failed %d\n", ret);
6153 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6154 intel_fb->obj = obj;
6158 static struct drm_framebuffer *
6159 intel_user_framebuffer_create(struct drm_device *dev,
6160 struct drm_file *filp,
6161 struct drm_mode_fb_cmd2 *mode_cmd)
6163 struct drm_i915_gem_object *obj;
6165 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6166 mode_cmd->handles[0]));
6167 if (&obj->base == NULL)
6168 return ERR_PTR(-ENOENT);
6170 return intel_framebuffer_create(dev, mode_cmd, obj);
6173 static const struct drm_mode_config_funcs intel_mode_funcs = {
6174 .fb_create = intel_user_framebuffer_create,
6175 .output_poll_changed = intel_fb_output_poll_changed,
6178 /* Set up chip specific display functions */
6179 static void intel_init_display(struct drm_device *dev)
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6183 /* We always want a DPMS function */
6184 if (HAS_PCH_SPLIT(dev)) {
6185 dev_priv->display.dpms = ironlake_crtc_dpms;
6186 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6187 dev_priv->display.update_plane = ironlake_update_plane;
6189 dev_priv->display.dpms = i9xx_crtc_dpms;
6190 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6191 dev_priv->display.update_plane = i9xx_update_plane;
6194 /* Returns the core display clock speed */
6195 if (IS_VALLEYVIEW(dev))
6196 dev_priv->display.get_display_clock_speed =
6197 valleyview_get_display_clock_speed;
6198 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6199 dev_priv->display.get_display_clock_speed =
6200 i945_get_display_clock_speed;
6201 else if (IS_I915G(dev))
6202 dev_priv->display.get_display_clock_speed =
6203 i915_get_display_clock_speed;
6204 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6205 dev_priv->display.get_display_clock_speed =
6206 i9xx_misc_get_display_clock_speed;
6207 else if (IS_I915GM(dev))
6208 dev_priv->display.get_display_clock_speed =
6209 i915gm_get_display_clock_speed;
6210 else if (IS_I865G(dev))
6211 dev_priv->display.get_display_clock_speed =
6212 i865_get_display_clock_speed;
6213 else if (IS_I85X(dev))
6214 dev_priv->display.get_display_clock_speed =
6215 i855_get_display_clock_speed;
6217 dev_priv->display.get_display_clock_speed =
6218 i830_get_display_clock_speed;
6220 if (HAS_PCH_SPLIT(dev)) {
6222 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6223 dev_priv->display.write_eld = ironlake_write_eld;
6224 } else if (IS_GEN6(dev)) {
6225 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6226 dev_priv->display.write_eld = ironlake_write_eld;
6227 } else if (IS_IVYBRIDGE(dev)) {
6228 /* FIXME: detect B0+ stepping and use auto training */
6229 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6230 dev_priv->display.write_eld = ironlake_write_eld;
6232 dev_priv->display.update_wm = NULL;
6233 } else if (IS_G4X(dev)) {
6234 dev_priv->display.write_eld = g4x_write_eld;
6237 /* Default just returns -ENODEV to indicate unsupported */
6238 dev_priv->display.queue_flip = intel_default_queue_flip;
6240 switch (INTEL_INFO(dev)->gen) {
6242 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6246 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6251 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6255 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6258 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6264 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6265 * resume, or other times. This quirk makes sure that's the case for
6268 static void quirk_pipea_force(struct drm_device *dev)
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6272 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6273 DRM_DEBUG("applying pipe a force quirk\n");
6277 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6279 static void quirk_ssc_force_disable(struct drm_device *dev)
6281 struct drm_i915_private *dev_priv = dev->dev_private;
6282 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6285 struct intel_quirk {
6287 int subsystem_vendor;
6288 int subsystem_device;
6289 void (*hook)(struct drm_device *dev);
6292 #define PCI_ANY_ID (~0u)
6294 struct intel_quirk intel_quirks[] = {
6295 /* HP Mini needs pipe A force quirk (LP: #322104) */
6296 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6298 /* Thinkpad R31 needs pipe A force quirk */
6299 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6300 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6301 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6303 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6304 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6305 /* ThinkPad X40 needs pipe A force quirk */
6307 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6308 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6310 /* 855 & before need to leave pipe A & dpll A up */
6311 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6312 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6314 /* Lenovo U160 cannot use SSC on LVDS */
6315 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6317 /* Sony Vaio Y cannot use SSC on LVDS */
6318 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6321 static void intel_init_quirks(struct drm_device *dev)
6323 struct intel_quirk *q;
6328 for (i = 0; i < DRM_ARRAY_SIZE(intel_quirks); i++) {
6329 q = &intel_quirks[i];
6330 if (pci_get_device(d) == q->device &&
6331 (pci_get_subvendor(d) == q->subsystem_vendor ||
6332 q->subsystem_vendor == PCI_ANY_ID) &&
6333 (pci_get_subdevice(d) == q->subsystem_device ||
6334 q->subsystem_device == PCI_ANY_ID))
6339 /* Disable the VGA plane that we never use */
6340 static void i915_disable_vga(struct drm_device *dev)
6342 struct drm_i915_private *dev_priv = dev->dev_private;
6346 if (HAS_PCH_SPLIT(dev))
6347 vga_reg = CPU_VGACNTRL;
6352 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6354 outb(VGA_SR_INDEX, 1);
6355 sr1 = inb(VGA_SR_DATA);
6356 outb(VGA_SR_DATA, sr1 | 1 << 5);
6358 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6362 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6363 POSTING_READ(vga_reg);
6366 void intel_modeset_init_hw(struct drm_device *dev)
6368 /* We attempt to init the necessary power wells early in the initialization
6369 * time, so the subsystems that expect power to be enabled can work.
6371 intel_init_power_wells(dev);
6374 intel_prepare_ddi(dev);
6377 intel_init_clock_gating(dev);
6380 intel_enable_gt_powersave(dev);
6384 void intel_modeset_init(struct drm_device *dev)
6386 struct drm_i915_private *dev_priv = dev->dev_private;
6389 drm_mode_config_init(dev);
6391 dev->mode_config.min_width = 0;
6392 dev->mode_config.min_height = 0;
6394 dev->mode_config.preferred_depth = 24;
6395 dev->mode_config.prefer_shadow = 1;
6397 dev->mode_config.funcs = &intel_mode_funcs;
6399 intel_init_quirks(dev);
6403 intel_init_display(dev);
6406 dev->mode_config.max_width = 2048;
6407 dev->mode_config.max_height = 2048;
6408 } else if (IS_GEN3(dev)) {
6409 dev->mode_config.max_width = 4096;
6410 dev->mode_config.max_height = 4096;
6412 dev->mode_config.max_width = 8192;
6413 dev->mode_config.max_height = 8192;
6415 dev->mode_config.fb_base = dev->agp->base;
6417 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6418 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6420 for (i = 0; i < dev_priv->num_pipe; i++) {
6421 intel_crtc_init(dev, i);
6422 ret = intel_plane_init(dev, i);
6424 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6427 intel_cpu_pll_init(dev);
6428 intel_pch_pll_init(dev);
6430 /* Just disable it once at startup */
6431 i915_disable_vga(dev);
6432 intel_setup_outputs(dev);
6435 void intel_modeset_gem_init(struct drm_device *dev)
6437 intel_modeset_init_hw(dev);
6439 intel_setup_overlay(dev);
6442 void intel_modeset_cleanup(struct drm_device *dev)
6444 struct drm_i915_private *dev_priv = dev->dev_private;
6445 struct drm_crtc *crtc;
6446 struct intel_crtc *intel_crtc;
6448 drm_kms_helper_poll_fini(dev);
6452 intel_unregister_dsm_handler();
6455 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6456 /* Skip inactive CRTCs */
6460 intel_crtc = to_intel_crtc(crtc);
6461 intel_increase_pllclock(crtc);
6464 intel_disable_fbc(dev);
6466 intel_disable_gt_powersave(dev);
6468 ironlake_teardown_rc6(dev);
6470 if (IS_VALLEYVIEW(dev))
6475 /* Disable the irq before mode object teardown, for the irq might
6476 * enqueue unpin/hotplug work. */
6477 drm_irq_uninstall(dev);
6478 cancel_work_sync(&dev_priv->hotplug_work);
6479 cancel_work_sync(&dev_priv->rps.work);
6481 /* flush any delayed tasks or pending work */
6482 flush_scheduled_work();
6484 /* destroy backlight, if any, before the connectors */
6485 intel_panel_destroy_backlight(dev);
6487 drm_mode_config_cleanup(dev);
6491 * Return which encoder is currently attached for connector.
6493 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6495 return &intel_attached_encoder(connector)->base;
6498 void intel_connector_attach_encoder(struct intel_connector *connector,
6499 struct intel_encoder *encoder)
6501 connector->encoder = encoder;
6502 drm_mode_connector_attach_encoder(&connector->base,
6507 * set vga decode state - true == enable VGA decode
6509 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6511 struct drm_i915_private *dev_priv;
6512 device_t bridge_dev;
6515 dev_priv = dev->dev_private;
6516 bridge_dev = intel_gtt_get_bridge_device();
6517 gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2);
6519 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6521 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6522 pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2);
6526 struct intel_display_error_state {
6527 struct intel_cursor_error_state {
6534 struct intel_pipe_error_state {
6546 struct intel_plane_error_state {
6557 struct intel_display_error_state *
6558 intel_display_capture_error_state(struct drm_device *dev)
6560 drm_i915_private_t *dev_priv = dev->dev_private;
6561 struct intel_display_error_state *error;
6564 error = kmalloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT);
6568 for (i = 0; i < 2; i++) {
6569 error->cursor[i].control = I915_READ(CURCNTR(i));
6570 error->cursor[i].position = I915_READ(CURPOS(i));
6571 error->cursor[i].base = I915_READ(CURBASE(i));
6573 error->plane[i].control = I915_READ(DSPCNTR(i));
6574 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6575 error->plane[i].size = I915_READ(DSPSIZE(i));
6576 error->plane[i].pos = I915_READ(DSPPOS(i));
6577 error->plane[i].addr = I915_READ(DSPADDR(i));
6578 if (INTEL_INFO(dev)->gen >= 4) {
6579 error->plane[i].surface = I915_READ(DSPSURF(i));
6580 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6583 error->pipe[i].conf = I915_READ(PIPECONF(i));
6584 error->pipe[i].source = I915_READ(PIPESRC(i));
6585 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6586 error->pipe[i].hblank = I915_READ(HBLANK(i));
6587 error->pipe[i].hsync = I915_READ(HSYNC(i));
6588 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6589 error->pipe[i].vblank = I915_READ(VBLANK(i));
6590 error->pipe[i].vsync = I915_READ(VSYNC(i));
6597 intel_display_print_error_state(struct sbuf *m,
6598 struct drm_device *dev,
6599 struct intel_display_error_state *error)
6603 for (i = 0; i < 2; i++) {
6604 sbuf_printf(m, "Pipe [%d]:\n", i);
6605 sbuf_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6606 sbuf_printf(m, " SRC: %08x\n", error->pipe[i].source);
6607 sbuf_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6608 sbuf_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6609 sbuf_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6610 sbuf_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6611 sbuf_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6612 sbuf_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6614 sbuf_printf(m, "Plane [%d]:\n", i);
6615 sbuf_printf(m, " CNTR: %08x\n", error->plane[i].control);
6616 sbuf_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6617 sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size);
6618 sbuf_printf(m, " POS: %08x\n", error->plane[i].pos);
6619 sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6620 if (INTEL_INFO(dev)->gen >= 4) {
6621 sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface);
6622 sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6625 sbuf_printf(m, "Cursor [%d]:\n", i);
6626 sbuf_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6627 sbuf_printf(m, " POS: %08x\n", error->cursor[i].position);
6628 sbuf_printf(m, " BASE: %08x\n", error->cursor[i].base);