2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
35 * Functions to provide access to special i386 instructions.
36 * This in included in sys/systm.h, and that file should be
37 * used in preference to this.
40 #ifndef _CPU_CPUFUNC_H_
41 #define _CPU_CPUFUNC_H_
43 #include <sys/cdefs.h>
44 #include <sys/thread.h>
45 #include <machine/clock.h>
46 #include <machine/psl.h>
47 #include <machine/smp.h>
50 struct region_descriptor;
54 #define readb(va) (*(volatile u_int8_t *) (va))
55 #define readw(va) (*(volatile u_int16_t *) (va))
56 #define readl(va) (*(volatile u_int32_t *) (va))
57 #define readq(va) (*(volatile u_int64_t *) (va))
59 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
60 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
61 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
66 #include <machine/lock.h> /* XXX */
71 __asm __volatile("int $3");
77 __asm __volatile("pause":::"memory");
85 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
89 static __inline u_long
94 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
98 static __inline u_long
103 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
107 static __inline u_int
112 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
116 static __inline u_long
121 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
128 __asm __volatile("clflush %0" : : "m" (*(char *) addr));
132 do_cpuid(u_int ax, u_int *p)
134 __asm __volatile("cpuid"
135 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
140 cpuid_count(u_int ax, u_int cx, u_int *p)
142 __asm __volatile("cpuid"
143 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
144 : "0" (ax), "c" (cx));
147 #ifndef _CPU_DISABLE_INTR_DEFINED
150 cpu_disable_intr(void)
152 __asm __volatile("cli" : : : "memory");
157 #ifndef _CPU_ENABLE_INTR_DEFINED
160 cpu_enable_intr(void)
162 __asm __volatile("sti");
168 * Cpu and compiler memory ordering fence. mfence ensures strong read and
171 * A serializing or fence instruction is required here. A locked bus
172 * cycle on data for which we already own cache mastership is the most
178 __asm __volatile("mfence" : : : "memory");
182 * cpu_lfence() ensures strong read ordering for reads issued prior
183 * to the instruction verses reads issued afterwords.
185 * A serializing or fence instruction is required here. A locked bus
186 * cycle on data for which we already own cache mastership is the most
192 __asm __volatile("lfence" : : : "memory");
196 * cpu_sfence() ensures strong write ordering for writes issued prior
197 * to the instruction verses writes issued afterwords. Writes are
198 * ordered on intel cpus so we do not actually have to do anything.
205 * Don't use 'sfence' here, as it will create a lot of
206 * unnecessary stalls.
208 __asm __volatile("" : : : "memory");
212 * cpu_ccfence() prevents the compiler from reordering instructions, in
213 * particular stores, relative to the current cpu. Use cpu_sfence() if
214 * you need to guarentee ordering by both the compiler and by the cpu.
216 * This also prevents the compiler from caching memory loads into local
217 * variables across the routine.
222 __asm __volatile("" : : : "memory");
226 * This is a horrible, horrible hack that might have to be put at the
227 * end of certain procedures (on a case by case basis), just before it
228 * returns to avoid what we believe to be an unreported AMD cpu bug.
229 * Found to occur on both a Phenom II X4 820 (two of them), as well
230 * as a 48-core built around an Opteron 6168 (Id = 0x100f91 Stepping = 1).
231 * The problem does not appear to occur w/Intel cpus.
233 * The bug is likely related to either a write combining issue or the
234 * Return Address Stack (RAS) hardware cache.
236 * In particular, we had to do this for GCC's fill_sons_in_loop() routine
237 * which due to its deep recursion and stack flow appears to be able to
238 * tickle the amd cpu bug (w/ gcc-4.4.7). Adding a single 'nop' to the
239 * end of the routine just before it returns works around the bug.
241 * The bug appears to be extremely sensitive to %rip and %rsp values, to
242 * the point where even just inserting an instruction in an unrelated
243 * procedure (shifting the entire code base being run) effects the outcome.
244 * DragonFly is probably able to more readily reproduce the bug due to
245 * the stackgap randomization code. We would expect OpenBSD (where we got
246 * the stackgap randomization code from) to also be able to reproduce the
247 * issue. To date we have only reproduced the issue in DragonFly.
249 #define __AMDCPUBUG_DFLY01_AVAILABLE__
252 cpu_amdcpubug_dfly01(void)
254 __asm __volatile("nop" : : : "memory");
259 #define HAVE_INLINE_FFS
266 * Note that gcc-2's builtin ffs would be used if we didn't declare
267 * this inline or turn off the builtin. The builtin is faster but
268 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
271 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
273 /* Actually, the above is way out of date. The builtins use cmov etc */
274 return (__builtin_ffs(mask));
278 #define HAVE_INLINE_FFSL
283 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
286 #define HAVE_INLINE_FLS
291 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
294 #define HAVE_INLINE_FLSL
299 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
302 #define HAVE_INLINE_FLSLL
305 flsll(long long mask)
307 return (flsl((long)mask));
315 __asm __volatile("hlt");
319 * The following complications are to get around gcc not having a
320 * constraint letter for the range 0..255. We still put "d" in the
321 * constraint because "i" isn't a valid constraint when the port
322 * isn't constant. This only matters for -O0 because otherwise
323 * the non-working version gets optimized away.
325 * Use an expression-statement instead of a conditional expression
326 * because gcc-2.6.0 would promote the operands of the conditional
327 * and produce poor code for "if ((inb(var) & const1) == const2)".
329 * The unnecessary test `(port) < 0x10000' is to generate a warning if
330 * the `port' has type u_short or smaller. Such types are pessimal.
331 * This actually only works for signed types. The range check is
332 * careful to avoid generating warnings.
334 #define inb(port) __extension__ ({ \
336 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
337 && (port) < 0x10000) \
338 _data = inbc(port); \
340 _data = inbv(port); \
343 #define outb(port, data) ( \
344 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
345 && (port) < 0x10000 \
346 ? outbc(port, data) : outbv(port, data))
348 static __inline u_char
353 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
358 outbc(u_int port, u_char data)
360 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
363 static __inline u_char
368 * We use %%dx and not %1 here because i/o is done at %dx and not at
369 * %edx, while gcc generates inferior code (movw instead of movl)
370 * if we tell it to load (u_short) port.
372 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
376 static __inline u_int
381 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
386 insb(u_int port, void *addr, size_t cnt)
388 __asm __volatile("cld; rep; insb"
389 : "+D" (addr), "+c" (cnt)
395 insw(u_int port, void *addr, size_t cnt)
397 __asm __volatile("cld; rep; insw"
398 : "+D" (addr), "+c" (cnt)
404 insl(u_int port, void *addr, size_t cnt)
406 __asm __volatile("cld; rep; insl"
407 : "+D" (addr), "+c" (cnt)
415 __asm __volatile("invd");
420 #ifndef _CPU_INVLPG_DEFINED
423 * Invalidate a particular VA on this cpu only
425 * TLB flush for an individual page (even if it has PG_G).
426 * Only works on 486+ CPUs (i386 does not have PG_G).
429 cpu_invlpg(void *addr)
431 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
439 __asm __volatile("rep; nop");
444 static __inline u_short
449 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
453 static __inline u_int
454 loadandclear(volatile u_int *addr)
458 __asm __volatile("xorl %0,%0; xchgl %1,%0"
459 : "=&r" (result) : "m" (*addr));
464 outbv(u_int port, u_char data)
468 * Use an unnecessary assignment to help gcc's register allocator.
469 * This make a large difference for gcc-1.40 and a tiny difference
470 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
471 * best results. gcc-2.6.0 can't handle this.
474 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
478 outl(u_int port, u_int data)
481 * outl() and outw() aren't used much so we haven't looked at
482 * possible micro-optimizations such as the unnecessary
483 * assignment for them.
485 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
489 outsb(u_int port, const void *addr, size_t cnt)
491 __asm __volatile("cld; rep; outsb"
492 : "+S" (addr), "+c" (cnt)
497 outsw(u_int port, const void *addr, size_t cnt)
499 __asm __volatile("cld; rep; outsw"
500 : "+S" (addr), "+c" (cnt)
505 outsl(u_int port, const void *addr, size_t cnt)
507 __asm __volatile("cld; rep; outsl"
508 : "+S" (addr), "+c" (cnt)
513 outw(u_int port, u_short data)
515 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
521 __asm __volatile("pause");
524 static __inline u_long
529 __asm __volatile("pushfq; popq %0" : "=r" (rf));
533 static __inline u_int64_t
538 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
539 return (low | ((u_int64_t)high << 32));
542 static __inline u_int64_t
547 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
548 return (low | ((u_int64_t)high << 32));
551 #define _RDTSC_SUPPORTED_
553 static __inline tsc_uclock_t
558 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
559 return (low | ((tsc_uclock_t)high << 32));
563 #include <machine/cputypes.h>
564 #include <machine/md_var.h>
566 static __inline tsc_uclock_t
569 if (cpu_vendor_id == CPU_VENDOR_INTEL)
580 __asm __volatile("wbinvd");
584 void cpu_wbinvd_on_all_cpus_callback(void *arg);
587 cpu_wbinvd_on_all_cpus(void)
589 lwkt_cpusync_simple(smp_active_mask, cpu_wbinvd_on_all_cpus_callback, NULL);
594 write_rflags(u_long rf)
596 __asm __volatile("pushq %0; popfq" : : "r" (rf));
600 wrmsr(u_int msr, u_int64_t newval)
606 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
610 xsetbv(u_int ecx, u_int eax, u_int edx)
612 __asm __volatile(".byte 0x0f,0x01,0xd1"
614 : "a" (eax), "c" (ecx), "d" (edx));
618 load_cr0(u_long data)
621 __asm __volatile("movq %0,%%cr0" : : "r" (data));
624 static __inline u_long
629 __asm __volatile("movq %%cr0,%0" : "=r" (data));
633 static __inline u_long
638 __asm __volatile("movq %%cr2,%0" : "=r" (data));
643 load_cr3(u_long data)
646 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
649 static __inline u_long
654 __asm __volatile("movq %%cr3,%0" : "=r" (data));
659 load_cr4(u_long data)
661 __asm __volatile("movq %0,%%cr4" : : "r" (data));
664 static __inline u_long
669 __asm __volatile("movq %%cr4,%0" : "=r" (data));
673 #ifndef _CPU_INVLTLB_DEFINED
676 * Invalidate the TLB on this cpu only
682 #if defined(SWTCH_OPTIM_STATS)
689 extern void smp_invltlb(void);
690 extern void smp_sniff(void);
691 extern void cpu_sniff(int dcpu);
693 static __inline u_short
697 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
701 static __inline u_short
705 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
712 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
718 __asm __volatile("movw %0,%%es" : : "rm" (sel));
722 /* This is defined in <machine/specialreg.h> but is too painful to get to */
724 #define MSR_FSBASE 0xc0000100
729 /* Preserve the fsbase value across the selector load */
730 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
731 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
735 #define MSR_GSBASE 0xc0000101
741 * Preserve the gsbase value across the selector load.
742 * Note that we have to disable interrupts because the gsbase
743 * being trashed happens to be the kernel gsbase at the time.
745 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
746 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
749 /* Usable by userland */
753 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
759 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
763 /* void lidt(struct region_descriptor *addr); */
765 lidt(struct region_descriptor *addr)
767 __asm __volatile("lidt (%0)" : : "r" (addr));
770 /* void lldt(u_short sel); */
774 __asm __volatile("lldt %0" : : "r" (sel));
777 /* void ltr(u_short sel); */
781 __asm __volatile("ltr %0" : : "r" (sel));
784 static __inline u_int64_t
788 __asm __volatile("movq %%dr0,%0" : "=r" (data));
793 load_dr0(u_int64_t dr0)
795 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
798 static __inline u_int64_t
802 __asm __volatile("movq %%dr1,%0" : "=r" (data));
807 load_dr1(u_int64_t dr1)
809 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
812 static __inline u_int64_t
816 __asm __volatile("movq %%dr2,%0" : "=r" (data));
821 load_dr2(u_int64_t dr2)
823 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
826 static __inline u_int64_t
830 __asm __volatile("movq %%dr3,%0" : "=r" (data));
835 load_dr3(u_int64_t dr3)
837 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
840 static __inline u_int64_t
844 __asm __volatile("movq %%dr4,%0" : "=r" (data));
849 load_dr4(u_int64_t dr4)
851 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
854 static __inline u_int64_t
858 __asm __volatile("movq %%dr5,%0" : "=r" (data));
863 load_dr5(u_int64_t dr5)
865 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
868 static __inline u_int64_t
872 __asm __volatile("movq %%dr6,%0" : "=r" (data));
877 load_dr6(u_int64_t dr6)
879 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
882 static __inline u_int64_t
886 __asm __volatile("movq %%dr7,%0" : "=r" (data));
891 load_dr7(u_int64_t dr7)
893 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
896 static __inline register_t
901 rflags = read_rflags();
907 intr_restore(register_t rflags)
909 write_rflags(rflags);
912 #else /* !__GNUC__ */
914 int breakpoint(void);
915 void cpu_pause(void);
916 u_int bsfl(u_int mask);
917 u_int bsrl(u_int mask);
918 void cpu_disable_intr(void);
919 void cpu_enable_intr(void);
920 void cpu_invlpg(u_long addr);
921 void cpu_invlpg_range(u_long start, u_long end);
922 void do_cpuid(u_int ax, u_int *p);
924 u_char inb(u_int port);
925 u_int inl(u_int port);
926 void insb(u_int port, void *addr, size_t cnt);
927 void insl(u_int port, void *addr, size_t cnt);
928 void insw(u_int port, void *addr, size_t cnt);
930 void invlpg_range(u_int start, u_int end);
931 void cpu_invltlb(void);
932 u_short inw(u_int port);
933 void load_cr0(u_int cr0);
934 void load_cr3(u_int cr3);
935 void load_cr4(u_int cr4);
936 void load_fs(u_int sel);
937 void load_gs(u_int sel);
938 struct region_descriptor;
939 void lidt(struct region_descriptor *addr);
940 void lldt(u_short sel);
941 void ltr(u_short sel);
942 void outb(u_int port, u_char data);
943 void outl(u_int port, u_int data);
944 void outsb(u_int port, void *addr, size_t cnt);
945 void outsl(u_int port, void *addr, size_t cnt);
946 void outsw(u_int port, void *addr, size_t cnt);
947 void outw(u_int port, u_short data);
948 void ia32_pause(void);
955 u_int64_t rdmsr(u_int msr);
956 u_int64_t rdpmc(u_int pmc);
957 tsc_uclock_t rdtsc(void);
958 u_int read_rflags(void);
960 void write_rflags(u_int rf);
961 void wrmsr(u_int msr, u_int64_t newval);
962 u_int64_t rdr0(void);
963 void load_dr0(u_int64_t dr0);
964 u_int64_t rdr1(void);
965 void load_dr1(u_int64_t dr1);
966 u_int64_t rdr2(void);
967 void load_dr2(u_int64_t dr2);
968 u_int64_t rdr3(void);
969 void load_dr3(u_int64_t dr3);
970 u_int64_t rdr4(void);
971 void load_dr4(u_int64_t dr4);
972 u_int64_t rdr5(void);
973 void load_dr5(u_int64_t dr5);
974 u_int64_t rdr6(void);
975 void load_dr6(u_int64_t dr6);
976 u_int64_t rdr7(void);
977 void load_dr7(u_int64_t dr7);
978 register_t intr_disable(void);
979 void intr_restore(register_t rf);
981 #endif /* __GNUC__ */
983 int rdmsr_safe(u_int msr, uint64_t *val);
984 int wrmsr_safe(u_int msr, uint64_t newval);
985 void reset_dbregs(void);
989 #endif /* !_CPU_CPUFUNC_H_ */