2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
33 * Driver for the Atheros Wireless LAN controller.
35 * This software is derived from work of Atsushi Onoe; his contribution
36 * is greatly appreciated.
42 * This is needed for register operations which are performed
43 * by the driver - eg, calls to ath_hal_gettsf32().
45 * It's also required for any AH_DEBUG checks in here, eg the
46 * module dependencies.
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/sysctl.h>
55 #include <sys/malloc.h>
57 #include <sys/mutex.h>
58 #include <sys/kernel.h>
59 #include <sys/socket.h>
60 #include <sys/sockio.h>
61 #include <sys/errno.h>
62 #include <sys/callout.h>
64 #include <sys/endian.h>
65 #include <sys/kthread.h>
66 #include <sys/taskqueue.h>
68 #include <sys/module.h>
72 #include <net/if_var.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
75 #include <net/if_types.h>
76 #include <net/if_arp.h>
77 #include <net/ethernet.h>
78 #include <net/if_llc.h>
80 #include <netproto/802_11/ieee80211_var.h>
81 #include <netproto/802_11/ieee80211_regdomain.h>
82 #ifdef IEEE80211_SUPPORT_SUPERG
83 #include <netproto/802_11/ieee80211_superg.h>
85 #ifdef IEEE80211_SUPPORT_TDMA
86 #include <netproto/802_11/ieee80211_tdma.h>
92 #include <netinet/in.h>
93 #include <netinet/if_ether.h>
96 #include <dev/netif/ath/ath/if_athvar.h>
97 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */
98 #include <dev/netif/ath/ath_hal/ah_diagcodes.h>
100 #include <dev/netif/ath/ath/if_ath_debug.h>
101 #include <dev/netif/ath/ath/if_ath_misc.h>
102 #include <dev/netif/ath/ath/if_ath_tsf.h>
103 #include <dev/netif/ath/ath/if_ath_tx.h>
104 #include <dev/netif/ath/ath/if_ath_sysctl.h>
105 #include <dev/netif/ath/ath/if_ath_led.h>
106 #include <dev/netif/ath/ath/if_ath_keycache.h>
107 #include <dev/netif/ath/ath/if_ath_rx.h>
108 #include <dev/netif/ath/ath/if_ath_beacon.h>
109 #include <dev/netif/ath/ath/if_athdfs.h>
112 #include <dev/netif/ath/ath_tx99/ath_tx99.h>
115 #include <dev/netif/ath/ath/if_ath_tx_edma.h>
118 #include <dev/netif/ath/ath/if_ath_alq.h>
122 * some general macros
124 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
125 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
128 * XXX doesn't belong here, and should be tunable
130 #define ATH_TXSTATUS_RING_SIZE 512
132 MALLOC_DECLARE(M_ATHDEV);
134 static void ath_edma_tx_processq(struct ath_softc *sc, int dosched);
137 * Push some frames into the TX FIFO if we have space.
140 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
142 struct ath_buf *bf, *bf_last;
145 ATH_TXQ_LOCK_ASSERT(txq);
147 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: called\n",
151 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
152 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
156 * We have space in the FIFO - so let's push a frame
161 * Remove it from the normal list
163 ATH_TXQ_REMOVE(txq, bf, bf_list);
166 * XXX for now, we only dequeue a frame at a time, so
167 * that's only one buffer. Later on when we just
168 * push this staging _list_ into the queue, we'll
169 * set bf_last to the end pointer in the list.
172 DPRINTF(sc, ATH_DEBUG_TX_PROC,
173 "%s: Q%d: depth=%d; pushing %p->%p\n",
181 * Append it to the FIFO staging list
183 ATH_TXQ_INSERT_TAIL(&txq->fifo, bf, bf_list);
186 * Set fifo start / fifo end flags appropriately
189 bf->bf_flags |= ATH_BUF_FIFOPTR;
190 bf_last->bf_flags |= ATH_BUF_FIFOEND;
193 * Push _into_ the FIFO.
195 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
197 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
198 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
199 #endif/* ATH_DEBUG */
201 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
202 ath_tx_alq_post(sc, bf);
203 #endif /* ATH_DEBUG_ALQ */
204 txq->axq_fifo_depth++;
208 ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
212 * Re-initialise the DMA FIFO with the current contents of
215 * This should only be called as part of the chip reset path, as it
216 * assumes the FIFO is currently empty.
219 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
226 DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: called\n",
230 ATH_TXQ_LOCK_ASSERT(txq);
233 * Let's log if the tracked FIFO depth doesn't match
234 * what we actually push in.
236 old_fifo_depth = txq->axq_fifo_depth;
237 txq->axq_fifo_depth = 0;
240 * Walk the FIFO staging list, looking for "head" entries.
241 * Since we may have a partially completed list of frames,
242 * we push the first frame we see into the FIFO and re-mark
243 * it as the head entry. We then skip entries until we see
244 * FIFO end, at which point we get ready to push another
245 * entry into the FIFO.
247 TAILQ_FOREACH(bf, &txq->fifo.axq_q, bf_list) {
249 * If we're looking for FIFOEND and we haven't found
252 * If we're looking for FIFOEND and we've found it,
253 * reset for another descriptor.
256 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
257 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
258 #endif/* ATH_DEBUG */
260 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
261 ath_tx_alq_post(sc, bf);
262 #endif /* ATH_DEBUG_ALQ */
264 if (fifostart == 0) {
265 if (bf->bf_flags & ATH_BUF_FIFOEND)
270 /* Make sure we're not overflowing the FIFO! */
271 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) {
272 device_printf(sc->sc_dev,
273 "%s: Q%d: more frames in the queue; FIFO depth=%d?!\n",
276 txq->axq_fifo_depth);
280 DPRINTF(sc, ATH_DEBUG_RESET,
281 "%s: Q%d: depth=%d: pushing bf=%p; start=%d, end=%d\n",
286 !! (bf->bf_flags & ATH_BUF_FIFOPTR),
287 !! (bf->bf_flags & ATH_BUF_FIFOEND));
291 * Set this to be the first buffer in the FIFO
292 * list - even if it's also the last buffer in
295 bf->bf_flags |= ATH_BUF_FIFOPTR;
297 /* Push it into the FIFO and bump the FIFO count */
298 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
299 txq->axq_fifo_depth++;
302 * If this isn't the last entry either, let's
303 * clear fifostart so we continue looking for
306 if (! (bf->bf_flags & ATH_BUF_FIFOEND))
311 /* Only bother starting the queue if there's something in it */
313 ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
315 DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: FIFO depth was %d, is %d\n",
319 txq->axq_fifo_depth);
321 /* And now, let's check! */
322 if (txq->axq_fifo_depth != old_fifo_depth) {
323 device_printf(sc->sc_dev,
324 "%s: Q%d: FIFO depth should be %d, is %d\n",
328 txq->axq_fifo_depth);
333 * Hand off this frame to a hardware queue.
335 * Things are a bit hairy in the EDMA world. The TX FIFO is only
336 * 8 entries deep, so we need to keep track of exactly what we've
337 * pushed into the FIFO and what's just sitting in the TX queue,
340 * So this is split into two halves - frames get appended to the
341 * TXQ; then a scheduler is called to push some frames into the
345 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
351 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
352 ("%s: busy status 0x%x", __func__, bf->bf_flags));
355 * XXX TODO: write a hard-coded check to ensure that
356 * the queue id in the TX descriptor matches txq->axq_qnum.
359 /* Update aggr stats */
360 if (bf->bf_state.bfs_aggr)
361 txq->axq_aggr_depth++;
363 /* Push and update frame stats */
364 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
366 /* For now, set the link pointer in the last descriptor
369 * Later on, when it comes time to handling multiple descriptors
370 * in one FIFO push, we can link descriptors together this way.
374 * Finally, call the FIFO schedule routine to schedule some
375 * frames to the FIFO.
377 ath_edma_tx_fifo_fill(sc, txq);
382 * Hand off this frame to a multicast software queue.
384 * The EDMA TX CABQ will get a list of chained frames, chained
385 * together using the next pointer. The single head of that
386 * particular queue is pushed to the hardware CABQ.
389 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
393 ATH_TX_LOCK_ASSERT(sc);
394 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
395 ("%s: busy status 0x%x", __func__, bf->bf_flags));
399 * XXX this is mostly duplicated in ath_tx_handoff_mcast().
401 if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) {
402 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s);
403 struct ieee80211_frame *wh;
405 /* mark previous frame */
406 wh = mtod(bf_last->bf_m, struct ieee80211_frame *);
407 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
409 /* re-sync buffer to memory */
410 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap,
411 BUS_DMASYNC_PREWRITE);
413 /* link descriptor */
414 ath_hal_settxdesclink(sc->sc_ah,
419 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
420 ath_tx_alq_post(sc, bf);
421 #endif /* ATH_DEBUG_ALQ */
422 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
427 * Handoff this frame to the hardware.
429 * For the multicast queue, this will treat it as a software queue
430 * and append it to the list, after updating the MORE_DATA flag
431 * in the previous frame. The cabq processing code will ensure
432 * that the queue contents gets transferred over.
434 * For the hardware queues, this will queue a frame to the queue
435 * like before, then populate the FIFO from that. Since the
436 * EDMA hardware has 8 FIFO slots per TXQ, this ensures that
437 * frames such as management frames don't get prematurely dropped.
439 * This does imply that a similar flush-hwq-to-fifoq method will
440 * need to be called from the processq function, before the
441 * per-node software scheduler is called.
444 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
448 DPRINTF(sc, ATH_DEBUG_XMIT_DESC,
449 "%s: called; bf=%p, txq=%p, qnum=%d\n",
455 if (txq->axq_qnum == ATH_TXQ_SWQ)
456 ath_edma_xmit_handoff_mcast(sc, txq, bf);
458 ath_edma_xmit_handoff_hw(sc, txq, bf);
462 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum)
464 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
466 te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH,
469 if (te->m_fifo == NULL) {
470 device_printf(sc->sc_dev, "%s: malloc failed\n",
476 * Set initial "empty" state.
478 te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0;
484 ath_edma_free_txfifo(struct ath_softc *sc, int qnum)
486 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
488 /* XXX TODO: actually deref the ath_buf entries? */
489 free(te->m_fifo, M_ATHDEV);
494 ath_edma_dma_txsetup(struct ath_softc *sc)
499 error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma,
500 NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE);
504 ath_hal_setuptxstatusring(sc->sc_ah,
505 (void *) sc->sc_txsdma.dd_desc,
506 sc->sc_txsdma.dd_desc_paddr,
507 ATH_TXSTATUS_RING_SIZE);
509 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
510 ath_edma_setup_txfifo(sc, i);
517 ath_edma_dma_txteardown(struct ath_softc *sc)
521 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
522 ath_edma_free_txfifo(sc, i);
525 ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL);
530 * Drain all TXQs, potentially after completing the existing completed
534 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
536 struct ifnet *ifp = sc->sc_ifp;
539 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
541 (void) ath_stoptxdma(sc);
544 * If reset type is noloss, the TX FIFO needs to be serviced
545 * and those frames need to be handled.
547 * Otherwise, just toss everything in each TX queue.
549 if (reset_type == ATH_RESET_NOLOSS) {
550 ath_edma_tx_processq(sc, 0);
551 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
552 if (ATH_TXQ_SETUP(sc, i)) {
553 ATH_TXQ_LOCK(&sc->sc_txq[i]);
555 * Free the holding buffer; DMA is now
558 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
560 * Reset the link pointer to NULL; there's
561 * no frames to chain DMA to.
563 sc->sc_txq[i].axq_link = NULL;
564 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
568 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
569 if (ATH_TXQ_SETUP(sc, i))
570 ath_tx_draintxq(sc, &sc->sc_txq[i]);
574 /* XXX dump out the TX completion FIFO contents */
576 /* XXX dump out the frames */
578 IF_LOCK(&ifp->if_snd);
579 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
580 IF_UNLOCK(&ifp->if_snd);
585 * TX completion tasklet.
589 ath_edma_tx_proc(void *arg, int npending)
591 struct ath_softc *sc = (struct ath_softc *) arg;
594 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n",
597 ath_edma_tx_processq(sc, 1);
601 * Process the TX status queue.
604 ath_edma_tx_processq(struct ath_softc *sc, int dosched)
606 struct ath_hal *ah = sc->sc_ah;
608 struct ath_tx_status ts;
611 struct ieee80211_node *ni;
617 uint32_t txstatus[32];
620 for (idx = 0; ; idx++) {
621 bzero(&ts, sizeof(ts));
623 ATH_TXSTATUS_LOCK(sc);
625 ath_hal_gettxrawtxdesc(ah, txstatus);
627 status = ath_hal_txprocdesc(ah, NULL, (void *) &ts);
628 ATH_TXSTATUS_UNLOCK(sc);
630 if (status == HAL_EINPROGRESS)
634 if (sc->sc_debug & ATH_DEBUG_TX_PROC)
635 if (ts.ts_queue_id != sc->sc_bhalq)
636 ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id,
637 idx, (status == HAL_OK));
641 * If there is an error with this descriptor, continue
644 * XXX TBD: log some statistics?
646 if (status == HAL_EIO) {
647 device_printf(sc->sc_dev, "%s: invalid TX status?\n",
652 #if defined(ATH_DEBUG_ALQ) && defined(ATH_DEBUG)
653 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS))
654 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
657 #endif /* ATH_DEBUG_ALQ */
660 * At this point we have a valid status descriptor.
661 * The QID and descriptor ID (which currently isn't set)
662 * is part of the status.
664 * We then assume that the descriptor in question is the
665 * -head- of the given QID. Eventually we should verify
666 * this by using the descriptor ID.
670 * The beacon queue is not currently a "real" queue.
671 * Frames aren't pushed onto it and the lock isn't setup.
672 * So skip it for now; the beacon handling code will
673 * free and alloc more beacon buffers as appropriate.
675 if (ts.ts_queue_id == sc->sc_bhalq)
678 txq = &sc->sc_txq[ts.ts_queue_id];
681 bf = ATH_TXQ_FIRST(&txq->fifo);
684 * Work around the situation where I'm seeing notifications
685 * for Q1 when no frames are available. That needs to be
686 * debugged but not by crashing _here_.
689 device_printf(sc->sc_dev, "%s: Q%d: empty?\n",
696 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d, bf=%p, start=%d, end=%d\n",
699 !! (bf->bf_flags & ATH_BUF_FIFOPTR),
700 !! (bf->bf_flags & ATH_BUF_FIFOEND));
702 /* XXX TODO: actually output debugging info about this */
705 /* XXX assert the buffer/descriptor matches the status descid */
706 if (ts.ts_desc_id != bf->bf_descid) {
707 device_printf(sc->sc_dev,
708 "%s: mismatched descid (qid=%d, tsdescid=%d, "
717 /* This removes the buffer and decrements the queue depth */
718 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
719 if (bf->bf_state.bfs_aggr)
720 txq->axq_aggr_depth--;
723 * If this was the end of a FIFO set, decrement FIFO depth
725 if (bf->bf_flags & ATH_BUF_FIFOEND)
726 txq->axq_fifo_depth--;
729 * If this isn't the final buffer in a FIFO set, mark
730 * the buffer as busy so it goes onto the holding queue.
732 if (! (bf->bf_flags & ATH_BUF_FIFOEND))
733 bf->bf_flags |= ATH_BUF_BUSY;
735 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: FIFO depth is now %d (%d)\n",
739 txq->fifo.axq_depth);
741 /* XXX assert FIFO depth >= 0 */
745 * Outside of the TX lock - if the buffer is end
746 * end buffer in this FIFO, we don't need a holding
749 if (bf->bf_flags & ATH_BUF_FIFOEND) {
751 ath_txq_freeholdingbuf(sc, txq);
756 * First we need to make sure ts_rate is valid.
758 * Pre-EDMA chips pass the whole TX descriptor to
759 * the proctxdesc function which will then fill out
760 * ts_rate based on the ts_finaltsi (final TX index)
761 * in the TX descriptor. However the TX completion
762 * FIFO doesn't have this information. So here we
763 * do a separate HAL call to populate that information.
765 * The same problem exists with ts_longretry.
766 * The FreeBSD HAL corrects ts_longretry in the HAL layer;
767 * the AR9380 HAL currently doesn't. So until the HAL
768 * is imported and this can be added, we correct for it
772 /* XXX faked for now. Ew. */
773 if (ts.ts_finaltsi < 4) {
775 bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode;
776 switch (ts.ts_finaltsi) {
777 case 3: ts.ts_longretry +=
778 bf->bf_state.bfs_rc[2].tries;
779 case 2: ts.ts_longretry +=
780 bf->bf_state.bfs_rc[1].tries;
781 case 1: ts.ts_longretry +=
782 bf->bf_state.bfs_rc[0].tries;
785 device_printf(sc->sc_dev, "%s: finaltsi=%d\n",
788 ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode;
792 * XXX This is terrible.
794 * Right now, some code uses the TX status that is
795 * passed in here, but the completion handlers in the
796 * software TX path also use bf_status.ds_txstat.
797 * Ew. That should all go away.
799 * XXX It's also possible the rate control completion
800 * routine is called twice.
802 memcpy(&bf->bf_status, &ts, sizeof(ts));
807 /* XXX duplicate from ath_tx_processq */
808 if (ni != NULL && ts.ts_status == 0 &&
809 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
811 sc->sc_stats.ast_tx_rssi = ts.ts_rssi;
812 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
816 /* Handle frame completion and rate control update */
817 ath_tx_process_buf_completion(sc, txq, &ts, bf);
819 /* bf is invalid at this point */
822 * Now that there's space in the FIFO, let's push some
823 * more frames into it.
827 ath_edma_tx_fifo_fill(sc, txq);
834 IF_LOCK(&sc->sc_ifp->if_snd);
835 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
836 IF_UNLOCK(&sc->sc_ifp->if_snd);
839 /* Kick software scheduler */
841 * XXX It's inefficient to do this if the FIFO queue is full,
842 * but there's no easy way right now to only populate
843 * the txq task for _one_ TXQ. This should be fixed.
850 ath_edma_attach_comp_func(struct ath_softc *sc)
853 TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc);
857 ath_xmit_setup_edma(struct ath_softc *sc)
860 /* Fetch EDMA field and buffer sizes */
861 (void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen);
862 (void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen);
863 (void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps);
865 device_printf(sc->sc_dev, "TX descriptor length: %d\n",
867 device_printf(sc->sc_dev, "TX status length: %d\n",
868 sc->sc_tx_statuslen);
869 device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n",
872 sc->sc_tx.xmit_setup = ath_edma_dma_txsetup;
873 sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown;
874 sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func;
876 sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart;
877 sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff;
878 sc->sc_tx.xmit_drain = ath_edma_tx_drain;