2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.30 2006/11/14 10:54:21 joerg Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
40 #include <sys/devicestat.h>
46 #include <bus/pci/pcivar.h>
50 static void cyrix_timing(struct ata_device *, int, int);
51 static void promise_timing(struct ata_device *, int, int);
52 static void hpt_timing(struct ata_device *, int, int);
53 static int hpt_cable80(struct ata_device *);
56 #define ATAPI_DEVICE(atadev) \
57 ((atadev->unit == ATA_MASTER && \
58 atadev->channel->devices & ATA_ATAPI_MASTER) || \
59 (atadev->unit == ATA_SLAVE && \
60 atadev->channel->devices & ATA_ATAPI_SLAVE))
62 int ata_dma_debug = 0;
65 ata_dmaalloc(struct ata_device *atadev, int flags)
67 struct ata_channel *ch = atadev->channel;
69 if (atadev->dmastate.dmatab != NULL)
72 KKASSERT(ch->dma_mpipe.max_count != 0);
73 if (flags & M_RNOWAIT)
74 atadev->dmastate.dmatab = mpipe_alloc_nowait(&ch->dma_mpipe);
76 atadev->dmastate.dmatab = mpipe_alloc_waitok(&ch->dma_mpipe);
78 if (atadev->dmastate.dmatab != NULL) {
79 KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
86 ata_dmafree(struct ata_device *atadev)
88 struct ata_channel *ch = atadev->channel;
90 if (atadev->dmastate.dmatab) {
91 mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
92 atadev->dmastate.dmatab = NULL;
97 ata_dmafreetags(struct ata_channel *ch)
102 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
108 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
110 device_t parent = device_get_parent(atadev->channel->dev);
111 int chiptype = atadev->channel->chiptype;
112 int chiprev = pci_get_revid(parent);
113 int channel = atadev->channel->unit;
114 int device = ATA_DEV(atadev->unit);
115 int devno = (channel << 1) + device;
118 /* set our most pessimistic default mode */
119 atadev->mode = ATA_PIO;
121 if (!atadev->channel->r_bmio)
124 /* if simplex controller, only allow DMA on primary channel */
126 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
127 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
128 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
129 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
130 ATA_BMSTAT_DMA_SIMPLEX) {
131 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
136 /* DMA engine address alignment is usually 1 word (2 bytes) */
137 atadev->channel->alignment = 0x1;
140 if (udmamode > 2 && !atadev->param->hwres_cblid) {
141 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
147 case 0x27df8086: /* Intel ICH7 ATA */
148 case 0x27c48086: /* Intel ICH7M SATA */
149 case 0x269e8086: /* Intel ICH6 SATA */
150 case 0x26808086: /* Intel ICH6 SATA */
151 case 0x266f8086: /* Intel ICH6 ATA */
152 case 0x26528086: /* Intel ICH6R/RW SATA */
153 case 0x26518086: /* Intel ICH6/W SATA */
154 case 0x24db8086: /* Intel ICH5 */
155 case 0x24d18086: /* Intel ICH5 SATA */
156 case 0x24ca8086: /* Intel ICH4 mobile */
157 case 0x24cb8086: /* Intel ICH4 */
158 case 0x248a8086: /* Intel ICH3 mobile */
159 case 0x248b8086: /* Intel ICH3 */
160 case 0x244a8086: /* Intel ICH2 mobile */
161 case 0x244b8086: /* Intel ICH2 */
163 int32_t mask48, new48;
166 word54 = pci_read_config(parent, 0x54, 2);
167 if (word54 & (0x10 << devno)) {
168 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
169 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
171 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
172 (error) ? "failed" : "success");
174 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
175 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
176 pci_write_config(parent, 0x48,
177 (pci_read_config(parent, 0x48, 4) &
178 ~mask48) | new48, 4);
179 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
180 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
185 /* make sure eventual ATA100 mode from the BIOS is disabled */
186 pci_write_config(parent, 0x54,
187 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
190 case 0x24118086: /* Intel ICH */
191 case 0x76018086: /* Intel ICH */
193 int32_t mask48, new48;
196 word54 = pci_read_config(parent, 0x54, 2);
197 if (word54 & (0x10 << devno)) {
198 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
199 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
201 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
202 (error) ? "failed" : "success");
204 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
205 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
206 pci_write_config(parent, 0x48,
207 (pci_read_config(parent, 0x48, 4) &
208 ~mask48) | new48, 4);
209 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
210 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
215 /* make sure eventual ATA66 mode from the BIOS is disabled */
216 pci_write_config(parent, 0x54,
217 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
220 case 0x71118086: /* Intel PIIX4 */
221 case 0x84CA8086: /* Intel PIIX4 */
222 case 0x71998086: /* Intel PIIX4e */
223 case 0x24218086: /* Intel ICH0 */
225 int32_t mask48, new48;
227 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
228 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
230 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
231 (error) ? "failed" : "success");
233 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
234 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
235 pci_write_config(parent, 0x48,
236 (pci_read_config(parent, 0x48, 4) &
237 ~mask48) | new48, 4);
238 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
242 /* make sure eventual ATA33 mode from the BIOS is disabled */
243 pci_write_config(parent, 0x48,
244 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
247 case 0x70108086: /* Intel PIIX3 */
248 if (wdmamode >= 2 && apiomode >= 4) {
249 int32_t mask40, new40, mask44, new44;
251 /* if SITRE not set doit for both channels */
252 if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
253 new40 = pci_read_config(parent, 0x40, 4);
254 new44 = pci_read_config(parent, 0x44, 4);
255 if (!(new40 & 0x00004000)) {
256 new44 &= ~0x0000000f;
257 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
259 if (!(new40 & 0x40000000)) {
260 new44 &= ~0x000000f0;
261 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
264 pci_write_config(parent, 0x40, new40, 4);
265 pci_write_config(parent, 0x44, new44, 4);
267 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
268 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
270 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
271 (error) ? "failed" : "success");
273 if (device == ATA_MASTER) {
291 pci_write_config(parent, 0x40,
292 (pci_read_config(parent, 0x40, 4) & ~mask40)|
294 pci_write_config(parent, 0x44,
295 (pci_read_config(parent, 0x44, 4) & ~mask44)|
297 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
301 /* we could set PIO mode timings, but we assume the BIOS did that */
304 case 0x12308086: /* Intel PIIX */
305 if (wdmamode >= 2 && apiomode >= 4) {
308 word40 = pci_read_config(parent, 0x40, 4);
309 word40 >>= channel * 16;
311 /* Check for timing config usable for DMA on controller */
312 if (!((word40 & 0x3300) == 0x2300 &&
313 ((word40 >> (device ? 4 : 0)) & 1) == 1))
316 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
317 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
319 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
320 (error) ? "failed" : "success");
322 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
328 case 0x522910b9: /* AcerLabs Aladdin IV/V */
329 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
330 if (chiprev < 0xc2 &&
331 atadev->channel->devices & ATA_ATAPI_MASTER &&
332 atadev->channel->devices & ATA_ATAPI_SLAVE) {
333 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
336 #if !defined(NO_ATANG)
337 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
339 if (udmamode >= 5 && chiprev >= 0xc4) {
340 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
341 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
343 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
344 (error) ? "failed" : "success");
346 int32_t word54 = pci_read_config(parent, 0x54, 4);
348 pci_write_config(parent, 0x4b,
349 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
350 word54 &= ~(0x000f000f << (devno << 2));
351 word54 |= (0x000f0005 << (devno << 2));
352 pci_write_config(parent, 0x54, word54, 4);
353 pci_write_config(parent, 0x53,
354 pci_read_config(parent, 0x53, 1) | 0x03, 1);
355 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
359 if (udmamode >= 4 && chiprev >= 0xc2) {
360 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
361 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
363 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
364 (error) ? "failed" : "success");
366 int32_t word54 = pci_read_config(parent, 0x54, 4);
368 pci_write_config(parent, 0x4b,
369 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
370 word54 &= ~(0x000f000f << (devno << 2));
371 word54 |= (0x00080005 << (devno << 2));
372 pci_write_config(parent, 0x54, word54, 4);
373 pci_write_config(parent, 0x53,
374 pci_read_config(parent, 0x53, 1) | 0x03, 1);
375 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
379 if (udmamode >= 2 && chiprev >= 0x20) {
380 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
381 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
383 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
384 (error) ? "failed" : "success");
386 int32_t word54 = pci_read_config(parent, 0x54, 4);
388 word54 &= ~(0x000f000f << (devno << 2));
389 word54 |= (0x000a0005 << (devno << 2));
390 pci_write_config(parent, 0x54, word54, 4);
391 pci_write_config(parent, 0x53,
392 pci_read_config(parent, 0x53, 1) | 0x03, 1);
393 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
394 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
399 /* make sure eventual UDMA mode from the BIOS is disabled */
400 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
401 ~(0x0008 << (devno << 2)), 2);
403 if (wdmamode >= 2 && apiomode >= 4) {
404 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
405 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
407 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
408 (error) ? "failed" : "success");
410 pci_write_config(parent, 0x53,
411 pci_read_config(parent, 0x53, 1) | 0x03, 1);
412 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
413 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
417 pci_write_config(parent, 0x53,
418 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
419 #if !defined(NO_ATANG)
420 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
422 ATA_C_F_SETXFER, ATA_WAIT_READY);
424 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
425 (error) ? "failed" : "success",
426 (apiomode >= 0) ? apiomode : 0);
428 int32_t word54 = pci_read_config(parent, 0x54, 4);
431 switch(ATA_PIO0 + apiomode) {
432 case ATA_PIO0: timing = 0x006d0003; break;
433 case ATA_PIO1: timing = 0x00580002; break;
434 case ATA_PIO2: timing = 0x00440001; break;
435 case ATA_PIO3: timing = 0x00330001; break;
436 case ATA_PIO4: timing = 0x00310001; break;
437 default: timing = 0x006d0003; break;
439 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
440 word54 &= ~(0x000f000f << (devno << 2));
441 word54 |= (0x00000004 << (devno << 2));
442 pci_write_config(parent, 0x54, word54, 4);
443 atadev->mode = ATA_PIO0 + apiomode;
449 case 0x31491106: /* VIA 8237 SATA part */
451 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
453 ATA_C_F_SETXFER, ATA_WAIT_READY);
455 ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
456 (error) ? "failed" : "success", udmamode);
458 ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
462 /* we could set PIO mode timings, but we assume the BIOS did that */
465 case 0x01bc10de: /* NVIDIA nForce1 */
466 case 0x006510de: /* NVIDIA nForce2 */
467 case 0x00d510de: /* NVIDIA nForce3 */
468 case 0x00e310de: /* NVIDIA nForce3 PRO S1 */
469 case 0x00e510de: /* NVIDIA nForce3 PRO */
470 case 0x74691022: /* AMD 8111 */
471 case 0x74411022: /* AMD 768 */
472 case 0x74111022: /* AMD 766 */
473 case 0x74091022: /* AMD 756 */
474 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
476 int via_modes[][7] = {
477 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
478 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
479 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
480 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
481 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
486 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
487 ata_find_dev(parent, 0x31771106, 0) || /* 8235 */
488 ata_find_dev(parent, 0x31491106, 0)) { /* 8237 */
489 udmamode = imin(udmamode, 6);
490 reg_val = via_modes[3];
492 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
493 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
494 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
495 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
496 udmamode = imin(udmamode, 5);
497 reg_val = via_modes[2];
499 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
500 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
501 udmamode = imin(udmamode, 4);
502 reg_val = via_modes[1];
504 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
505 udmamode = imin(udmamode, 2);
506 reg_val = via_modes[1];
508 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
509 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
510 udmamode = imin(udmamode, 2);
511 reg_val = via_modes[0];
513 else if (chiptype == 0x74691022 || /* AMD 8111 */
514 chiptype == 0x74411022 || /* AMD 768 */
515 chiptype == 0x74111022) { /* AMD 766 */
516 udmamode = imin(udmamode, 5);
517 reg_val = via_modes[4];
520 else if (chiptype == 0x74091022) { /* AMD 756 */
521 udmamode = imin(udmamode, 4);
522 reg_val = via_modes[4];
525 else if (chiptype == 0x01bc10de) { /* nForce1 */
526 udmamode = imin(udmamode, 5);
527 reg_val = via_modes[4];
528 #if !defined(NO_ATANG)
533 else if (chiptype == 0x006510de || /* nForce2 */
534 chiptype == 0x00d510de || /* nForce3 */
535 chiptype == 0x00e310de || /* nForce3 PRO S1 */
536 chiptype == 0x00e510de) { /* nForce3 PRO */
537 udmamode = imin(udmamode, 6);
538 reg_val = via_modes[4];
539 #if !defined(NO_ATANG)
550 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
551 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
553 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
554 (error) ? "failed" : "success", chip);
556 pci_write_config(parent, reg_off, reg_val[6], 1);
557 pci_write_config(parent, reg_off - 8, 0x20, 1);
558 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
563 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
564 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
566 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
567 (error) ? "failed" : "success", chip);
569 pci_write_config(parent, reg_off, reg_val[5], 1);
570 pci_write_config(parent, reg_off - 8, 0x20, 1);
571 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
576 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
577 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
579 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
580 (error) ? "failed" : "success", chip);
582 pci_write_config(parent, reg_off, reg_val[4], 1);
583 pci_write_config(parent, reg_off - 8, 0x20, 1);
584 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
589 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
590 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
592 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
593 (error) ? "failed" : "success", chip);
595 pci_write_config(parent, reg_off, reg_val[2], 1);
596 pci_write_config(parent, reg_off - 8, 0x20, 1);
597 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
601 if (wdmamode >= 2 && apiomode >= 4) {
602 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
603 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
605 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
606 (error) ? "failed" : "success", chip);
608 pci_write_config(parent, reg_off, 0x0b, 1);
609 pci_write_config(parent, reg_off - 8, 0x20, 1);
610 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
614 pci_write_config(parent, reg_off, 0x8b, 1);
617 pci_write_config(parent, reg_off - 8, 0xa8, 1);
620 pci_write_config(parent, reg_off - 8, 0x65, 1);
623 pci_write_config(parent, reg_off - 8, 0x42, 1);
626 pci_write_config(parent, reg_off - 8, 0x22, 1);
629 pci_write_config(parent, reg_off - 8, 0x20, 1);
635 case 0x55131039: /* SiS 5591 */
636 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
637 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
638 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
639 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
640 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
641 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
642 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
643 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
644 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
645 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
646 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
647 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
648 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
649 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
650 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
651 int8_t reg = 0x40 + (devno << 1);
652 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
655 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
656 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
658 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
659 (error) ? "failed" : "success");
661 pci_write_config(parent, reg, val | 0x8000, 2);
662 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
667 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
668 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
670 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
671 (error) ? "failed" : "success");
673 pci_write_config(parent, reg, val | 0x9000, 2);
674 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
679 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
680 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
682 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
683 (error) ? "failed" : "success");
685 pci_write_config(parent, reg, val | 0xb000, 2);
686 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
690 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
691 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
692 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
693 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
694 int8_t reg = 0x40 + (devno << 1);
695 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
698 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
699 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
701 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
702 (error) ? "failed" : "success");
704 pci_write_config(parent, reg, val | 0x9000, 2);
705 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
710 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
711 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
713 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
714 (error) ? "failed" : "success");
716 pci_write_config(parent, reg, val | 0xa000, 2);
717 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
721 } else if (udmamode >= 2 && chiprev > 0xc1) {
722 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
723 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
725 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
726 (error) ? "failed" : "success");
728 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
729 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
733 if (wdmamode >=2 && apiomode >= 4) {
734 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
735 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
737 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
738 (error) ? "failed" : "success");
740 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
741 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
745 /* we could set PIO mode timings, but we assume the BIOS did that */
748 case 0x35121095: /* SiI 3512 SATA controller */
749 /* EXPERIMENTAL! Works with FN85 AMD 64 3200+ motherboard */
751 case 0x31241095: /* SiI 3124 SATA controller */
752 case 0x31141095: /* SiI 3114 SATA controller */
753 case 0x31121095: /* SiI 3112 SATA controller */
754 case 0x06801095: /* SiI 0680 ATA133 controller */
756 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
757 u_int8_t uval = pci_read_config(parent, ureg, 1);
758 u_int8_t mreg = channel ? 0x84 : 0x80;
759 u_int8_t mask = device ? 0x30 : 0x03;
760 u_int8_t mode = pci_read_config(parent, mreg, 1);
762 /* enable UDMA mode */
763 pci_write_config(parent, mreg,
764 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
766 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
767 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
769 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
770 (error) ? "failed" : "success");
772 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
773 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
778 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
779 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
781 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
782 (error) ? "failed" : "success");
784 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
785 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
790 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
791 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
793 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
794 (error) ? "failed" : "success");
796 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
797 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
802 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
803 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
805 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
806 (error) ? "failed" : "success");
808 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
809 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
814 /* disable UDMA mode and enable WDMA mode */
815 pci_write_config(parent, mreg,
816 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
817 if (wdmamode >= 2 && apiomode >= 4) {
818 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
819 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
821 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
822 (error) ? "failed" : "success");
824 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
825 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
830 /* restore PIO mode */
831 pci_write_config(parent, mreg, mode, 1);
833 /* we could set PIO mode timings, but we assume the BIOS did that */
836 case 0x06491095: /* CMD 649 ATA100 controller */
840 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
841 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
843 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
844 (error) ? "failed" : "success");
846 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
847 umode &= ~(device ? 0xca : 0x35);
848 umode |= (device ? 0x0a : 0x05);
849 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
850 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
856 case 0x06481095: /* CMD 648 ATA66 controller */
860 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
861 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
863 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
864 (error) ? "failed" : "success");
866 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
867 umode &= ~(device ? 0xca : 0x35);
868 umode |= (device ? 0x4a : 0x15);
869 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
870 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
877 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
878 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
880 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
881 (error) ? "failed" : "success");
883 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
884 umode &= ~(device ? 0xca : 0x35);
885 umode |= (device ? 0x42 : 0x11);
886 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
887 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
891 /* make sure eventual UDMA mode from the BIOS is disabled */
892 pci_write_config(parent, channel ? 0x7b : 0x73,
893 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
894 #if !defined(NO_ATANG)
895 ~(device ? 0xca : 0x53), 1);
897 ~(device ? 0xca : 0x35), 1);
901 case 0x06461095: /* CMD 646 ATA controller */
902 if (wdmamode >= 2 && apiomode >= 4) {
903 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
904 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
906 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
907 error ? "failed" : "success");
909 int32_t offset = (devno < 3) ? (devno << 1) : 7;
911 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
912 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
916 /* we could set PIO mode timings, but we assume the BIOS did that */
919 case 0xc6931080: /* Cypress 82c693 ATA controller */
920 if (wdmamode >= 2 && apiomode >= 4) {
921 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
922 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
924 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
925 error ? "failed" : "success");
927 pci_write_config(atadev->channel->dev,
928 channel ? 0x4e:0x4c, 0x2020, 2);
929 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
933 /* we could set PIO mode timings, but we assume the BIOS did that */
936 case 0x01021078: /* Cyrix 5530 ATA33 controller */
937 atadev->channel->alignment = 0xf; /* DMA engine requires 16 byte alignment */
939 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
940 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
942 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
943 (error) ? "failed" : "success");
945 cyrix_timing(atadev, devno, ATA_UDMA2);
946 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
950 if (wdmamode >= 2 && apiomode >= 4) {
951 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
952 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
954 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
955 (error) ? "failed" : "success");
957 cyrix_timing(atadev, devno, ATA_WDMA2);
958 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
962 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
963 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
966 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
967 (error) ? "failed" : "success",
968 ata_mode2str(ATA_PIO0 + apiomode));
969 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
970 atadev->mode = ATA_PIO0 + apiomode;
973 #if !defined(NO_ATANG)
974 case 0x02131166: /* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
976 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
977 #if !defined(NO_ATANG)
978 if (udmamode >= 5 && (chiptype == 0x02131166 ||
979 (chiptype == 0x02121166 &&
982 if (udmamode >= 5 && chiprev >= 0x92) {
984 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
985 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
987 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
988 (error) ? "failed" : "success");
992 pci_write_config(parent, 0x54,
993 pci_read_config(parent, 0x54, 1) |
995 reg56 = pci_read_config(parent, 0x56, 2);
996 reg56 &= ~(0xf << (devno * 4));
997 reg56 |= (0x5 << (devno * 4));
998 pci_write_config(parent, 0x56, reg56, 2);
999 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1003 #if !defined(NO_ATANG)
1005 case 0x02171166: /* Server Works CSB6 ATA 66 controller chan 2 */
1007 if (udmamode >= 4) {
1008 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1009 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1011 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
1012 (error) ? "failed" : "success");
1016 pci_write_config(parent, 0x54,
1017 pci_read_config(parent, 0x54, 1) |
1018 (0x01 << devno), 1);
1019 reg56 = pci_read_config(parent, 0x56, 2);
1020 reg56 &= ~(0xf << (devno * 4));
1021 reg56 |= (0x4 << (devno * 4));
1022 pci_write_config(parent, 0x56, reg56, 2);
1023 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1029 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
1030 if (udmamode >= 2) {
1031 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1032 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1034 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
1035 (error) ? "failed" : "success");
1039 pci_write_config(parent, 0x54,
1040 pci_read_config(parent, 0x54, 1) |
1041 (0x01 << devno), 1);
1042 reg56 = pci_read_config(parent, 0x56, 2);
1043 reg56 &= ~(0xf << (devno * 4));
1044 reg56 |= (0x2 << (devno * 4));
1045 pci_write_config(parent, 0x56, reg56, 2);
1046 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1050 if (wdmamode >= 2 && apiomode >= 4) {
1051 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1052 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1054 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1055 (error) ? "failed" : "success");
1057 int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
1058 int word44 = pci_read_config(parent, 0x44, 4);
1060 pci_write_config(parent, 0x54,
1061 pci_read_config(parent, 0x54, 1) &
1062 ~(0x01 << devno), 1);
1063 word44 &= ~(0xff << (offset << 8));
1064 word44 |= (0x20 << (offset << 8));
1065 pci_write_config(parent, 0x44, 0x20, 4);
1066 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1070 /* we could set PIO mode timings, but we assume the BIOS did that */
1073 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1074 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1075 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1076 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1077 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1078 if (udmamode >= 6 &&
1079 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1080 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1081 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1083 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1084 (error) ? "failed" : "success");
1086 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1092 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1093 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1094 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1095 if (udmamode >= 5 &&
1096 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1097 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1098 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1100 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1101 (error) ? "failed" : "success");
1103 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1107 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1108 if (udmamode >= 4 &&
1109 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1110 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1111 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1113 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1114 (error) ? "failed" : "success");
1116 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1120 if (udmamode >= 2) {
1121 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1122 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1124 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1125 (error) ? "failed" : "success");
1127 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1131 if (wdmamode >= 2 && apiomode >= 4) {
1132 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1133 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1135 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1136 (error) ? "failed" : "success");
1138 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1144 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1145 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1146 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1147 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1148 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1149 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1151 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1152 (error) ? "failed" : "success");
1154 promise_timing(atadev, devno, ATA_UDMA5);
1155 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1161 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1162 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1163 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1164 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1165 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1166 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1168 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1169 (error) ? "failed" : "success");
1171 promise_timing(atadev, devno, ATA_UDMA4);
1172 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1178 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1179 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1180 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1181 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1183 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1184 (error) ? "failed" : "success");
1186 promise_timing(atadev, devno, ATA_UDMA2);
1187 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1191 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1192 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1193 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1195 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1196 (error) ? "failed" : "success");
1198 promise_timing(atadev, devno, ATA_WDMA2);
1199 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1203 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1204 ATA_PIO0 + apiomode,
1205 ATA_C_F_SETXFER, ATA_WAIT_READY);
1207 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1208 (error) ? "failed" : "success",
1209 (apiomode >= 0) ? apiomode : 0);
1210 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1211 atadev->mode = ATA_PIO0 + apiomode;
1214 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1215 case 0x00051103: /* HighPoint HPT372 controllers */
1216 case 0x00081103: /* HighPoint HPT374 controllers */
1217 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1218 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1219 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1220 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1221 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1222 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1224 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1225 (error) ? "failed" : "success");
1227 hpt_timing(atadev, devno, ATA_UDMA6);
1228 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1232 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1233 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1234 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1235 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1236 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1237 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1239 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1240 (error) ? "failed" : "success");
1242 hpt_timing(atadev, devno, ATA_UDMA5);
1243 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1247 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1248 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1249 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1251 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1252 (error) ? "failed" : "success");
1254 hpt_timing(atadev, devno, ATA_UDMA4);
1255 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1259 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1260 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1261 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1263 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1264 (error) ? "failed" : "success");
1266 hpt_timing(atadev, devno, ATA_UDMA2);
1267 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1271 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1272 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1273 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1275 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1276 (error) ? "failed" : "success");
1278 hpt_timing(atadev, devno, ATA_WDMA2);
1279 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1283 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1284 ATA_PIO0 + apiomode,
1285 ATA_C_F_SETXFER, ATA_WAIT_READY);
1287 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1288 (error) ? "failed" : "success",
1289 (apiomode >= 0) ? apiomode : 0);
1290 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1291 atadev->mode = ATA_PIO0 + apiomode;
1294 case 0x000116ca: /* Cenatek Rocket Drive controller */
1295 if (wdmamode >= 0 &&
1296 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1297 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1298 ata_dmacreate(atadev, apiomode, ATA_DMA);
1300 atadev->mode = ATA_PIO;
1303 default: /* unknown controller chip */
1304 /* better not try generic DMA on ATAPI devices it almost never works */
1305 if (ATAPI_DEVICE(atadev))
1308 /* if controller says its setup for DMA take the easy way out */
1309 /* the downside is we dont know what DMA mode we are in */
1310 if ((udmamode >= 0 || wdmamode >= 2) &&
1311 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1312 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1313 ata_dmacreate(atadev, apiomode, ATA_DMA);
1317 /* well, we have no support for this, but try anyways */
1318 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1319 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1320 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1322 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1323 (error) ? "failed" : "success");
1325 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1330 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1331 ATA_C_F_SETXFER, ATA_WAIT_READY);
1333 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1334 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1336 atadev->mode = ATA_PIO0 + apiomode;
1339 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1340 atadev->mode = ATA_PIO;
1345 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1347 struct ata_channel *ch = atadev->channel;
1348 struct ata_dmastate *ds = &atadev->dmastate;
1349 u_int32_t dma_count, dma_base;
1352 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1353 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1358 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1362 dma_base = vtophys(data);
1363 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1368 ds->dmatab[i].base = dma_base;
1369 ds->dmatab[i].count = (dma_count & 0xffff);
1371 if (i >= ATA_DMA_ENTRIES) {
1372 ata_prtdev(atadev, "too many segments in DMA table\n");
1375 dma_base = vtophys(data);
1376 dma_count = imin(count, PAGE_SIZE);
1377 data += imin(count, PAGE_SIZE);
1378 count -= imin(count, PAGE_SIZE);
1380 ds->dmatab[i].base = dma_base;
1381 ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1386 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1388 struct ata_channel *ch = atadev->channel;
1389 struct ata_dmastate *ds = &atadev->dmastate;
1391 ch->flags |= ATA_DMA_ACTIVE;
1392 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
1393 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1394 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1395 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1396 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1397 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1398 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1403 ata_dmadone(struct ata_device *atadev)
1405 struct ata_channel *ch;
1406 struct ata_dmastate *ds;
1409 ch = atadev->channel;
1410 ds = &atadev->dmastate;
1412 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1413 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1414 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1415 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1416 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1417 ch->flags &= ~ATA_DMA_ACTIVE;
1419 return error & ATA_BMSTAT_MASK;
1423 ata_dmastatus(struct ata_channel *ch)
1425 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1429 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1431 u_int32_t reg20 = 0x0000e132;
1432 u_int32_t reg24 = 0x00017771;
1435 case ATA_PIO0: reg20 = 0x0000e132; break;
1436 case ATA_PIO1: reg20 = 0x00018121; break;
1437 case ATA_PIO2: reg20 = 0x00024020; break;
1438 case ATA_PIO3: reg20 = 0x00032010; break;
1439 case ATA_PIO4: reg20 = 0x00040010; break;
1440 case ATA_WDMA2: reg24 = 0x00002020; break;
1441 case ATA_UDMA2: reg24 = 0x00911030; break;
1443 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1444 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1448 promise_timing(struct ata_device *atadev, int devno, int mode)
1450 u_int32_t timing = 0;
1451 /* XXX: Endianess */
1452 struct promise_timing {
1454 u_int8_t prefetch:1;
1465 u_int8_t reserved:8;
1466 } *t = (struct promise_timing*)&timing;
1468 t->iordy = 1; t->iordyp = 1;
1469 if (mode >= ATA_DMA) {
1470 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1473 switch (atadev->channel->chiptype) {
1474 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1477 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1478 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1479 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1480 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1481 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1482 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1483 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1487 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1488 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1489 case 0x0d30105a: /* Promise OEM ATA 100 */
1492 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1493 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1494 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1495 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1496 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1497 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1498 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1499 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1500 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1504 pci_write_config(device_get_parent(atadev->channel->dev),
1505 0x60 + (devno<<2), timing, 4);
1509 hpt_timing(struct ata_device *atadev, int devno, int mode)
1511 device_t parent = device_get_parent(atadev->channel->dev);
1512 u_int32_t chiptype = atadev->channel->chiptype;
1513 int chiprev = pci_get_revid(parent);
1516 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1517 switch (mode) { /* HPT374 */
1518 case ATA_PIO0: timing = 0x0ac1f48a; break;
1519 case ATA_PIO1: timing = 0x0ac1f465; break;
1520 case ATA_PIO2: timing = 0x0a81f454; break;
1521 case ATA_PIO3: timing = 0x0a81f443; break;
1522 case ATA_PIO4: timing = 0x0a81f442; break;
1523 case ATA_WDMA2: timing = 0x22808242; break;
1524 case ATA_UDMA2: timing = 0x120c8242; break;
1525 case ATA_UDMA4: timing = 0x12ac8242; break;
1526 case ATA_UDMA5: timing = 0x12848242; break;
1527 case ATA_UDMA6: timing = 0x12808242; break;
1528 default: timing = 0x0d029d5e;
1531 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1532 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1533 switch (mode) { /* HPT372 */
1534 case ATA_PIO0: timing = 0x0d029d5e; break;
1535 case ATA_PIO1: timing = 0x0d029d26; break;
1536 case ATA_PIO2: timing = 0x0c829ca6; break;
1537 case ATA_PIO3: timing = 0x0c829c84; break;
1538 case ATA_PIO4: timing = 0x0c829c62; break;
1539 case ATA_WDMA2: timing = 0x2c829262; break;
1540 case ATA_UDMA2: timing = 0x1c91dc62; break;
1541 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1542 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1543 case ATA_UDMA6: timing = 0x1c81dc62; break;
1544 default: timing = 0x0d029d5e;
1547 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1548 switch (mode) { /* HPT370 */
1549 case ATA_PIO0: timing = 0x06914e57; break;
1550 case ATA_PIO1: timing = 0x06914e43; break;
1551 case ATA_PIO2: timing = 0x06514e33; break;
1552 case ATA_PIO3: timing = 0x06514e22; break;
1553 case ATA_PIO4: timing = 0x06514e21; break;
1554 case ATA_WDMA2: timing = 0x26514e21; break;
1555 case ATA_UDMA2: timing = 0x16494e31; break;
1556 case ATA_UDMA4: timing = 0x16454e31; break;
1557 case ATA_UDMA5: timing = 0x16454e31; break;
1558 default: timing = 0x06514e57;
1560 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1562 else { /* HPT36[68] */
1563 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1564 case 0x85: /* 25Mhz */
1566 case ATA_PIO0: timing = 0x40d08585; break;
1567 case ATA_PIO1: timing = 0x40d08572; break;
1568 case ATA_PIO2: timing = 0x40ca8542; break;
1569 case ATA_PIO3: timing = 0x40ca8532; break;
1570 case ATA_PIO4: timing = 0x40ca8521; break;
1571 case ATA_WDMA2: timing = 0x20ca8521; break;
1572 case ATA_UDMA2: timing = 0x10cf8521; break;
1573 case ATA_UDMA4: timing = 0x10c98521; break;
1574 default: timing = 0x01208585;
1578 case 0xa7: /* 33MHz */
1580 case ATA_PIO0: timing = 0x40d0a7aa; break;
1581 case ATA_PIO1: timing = 0x40d0a7a3; break;
1582 case ATA_PIO2: timing = 0x40d0a753; break;
1583 case ATA_PIO3: timing = 0x40c8a742; break;
1584 case ATA_PIO4: timing = 0x40c8a731; break;
1585 case ATA_WDMA2: timing = 0x20c8a731; break;
1586 case ATA_UDMA2: timing = 0x10caa731; break;
1587 case ATA_UDMA4: timing = 0x10c9a731; break;
1588 default: timing = 0x0120a7a7;
1591 case 0xd9: /* 40Mhz */
1593 case ATA_PIO0: timing = 0x4018d9d9; break;
1594 case ATA_PIO1: timing = 0x4010d9c7; break;
1595 case ATA_PIO2: timing = 0x4010d997; break;
1596 case ATA_PIO3: timing = 0x4010d974; break;
1597 case ATA_PIO4: timing = 0x4008d963; break;
1598 case ATA_WDMA2: timing = 0x2008d943; break;
1599 case ATA_UDMA2: timing = 0x100bd943; break;
1600 case ATA_UDMA4: timing = 0x100fd943; break;
1601 default: timing = 0x0120d9d9;
1605 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1609 hpt_cable80(struct ata_device *atadev)
1611 device_t parent = device_get_parent(atadev->channel->dev);
1612 u_int8_t reg, val, res;
1614 if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1615 reg = atadev->channel->unit ? 0x57 : 0x53;
1616 val = pci_read_config(parent, reg, 1);
1617 pci_write_config(parent, reg, val | 0x80, 1);
1621 val = pci_read_config(parent, reg, 1);
1622 pci_write_config(parent, reg, val & 0xfe, 1);
1624 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
1625 pci_write_config(parent, reg, val, 1);