sys/dev/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/export.h>
  30 #include <drm/drmP.h>
  31 #include <linux/slab.h>
  32 #include <linux/string.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  41
  42 /**
  43  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  44  * @intel_dp: DP struct
  45  *
  46  * If a CPU or PCH DP output is attached to an eDP panel, this function
  47  * will return true, and false otherwise.
  48  */
  49 static bool is_edp(struct intel_dp *intel_dp)
  50 {
  51         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  52
  53         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  54 }
  55
  56 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  57 {
  58         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  59
  60         return intel_dig_port->base.base.dev;
  61 }
  62
  63 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  64 {
  65         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  66 }
  67
  68 static void intel_dp_link_down(struct intel_dp *intel_dp);
  69
  70 static int
  71 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  72 {
  73         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  74
  75         switch (max_link_bw) {
  76         case DP_LINK_BW_1_62:
  77         case DP_LINK_BW_2_7:
  78                 break;
  79         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
  80                 max_link_bw = DP_LINK_BW_2_7;
  81                 break;
  82         default:
  83                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
  84                      max_link_bw);
  85                 max_link_bw = DP_LINK_BW_1_62;
  86                 break;
  87         }
  88         return max_link_bw;
  89 }
  90
  91 /*
  92  * The units on the numbers in the next two are... bizarre.  Examples will
  93  * make it clearer; this one parallels an example in the eDP spec.
  94  *
  95  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  96  *
  97  *     270000 * 1 * 8 / 10 == 216000
  98  *
  99  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 100  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 101  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 102  * 119000.  At 18bpp that's 2142000 kilobits per second.
 103  *
 104  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 105  * get the result in decakilobits instead of kilobits.
 106  */
 107
 108 static int
 109 intel_dp_link_required(int pixel_clock, int bpp)
 110 {
 111         return (pixel_clock * bpp + 9) / 10;
 112 }
 113
 114 static int
 115 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 116 {
 117         return (max_link_clock * max_lanes * 8) / 10;
 118 }
 119
 120 static int
 121 intel_dp_mode_valid(struct drm_connector *connector,
 122                     struct drm_display_mode *mode)
 123 {
 124         struct intel_dp *intel_dp = intel_attached_dp(connector);
 125         struct intel_connector *intel_connector = to_intel_connector(connector);
 126         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 127         int target_clock = mode->clock;
 128         int max_rate, mode_rate, max_lanes, max_link_clock;
 129
 130         if (is_edp(intel_dp) && fixed_mode) {
 131                 if (mode->hdisplay > fixed_mode->hdisplay)
 132                         return MODE_PANEL;
 133
 134                 if (mode->vdisplay > fixed_mode->vdisplay)
 135                         return MODE_PANEL;
 136
 137                 target_clock = fixed_mode->clock;
 138         }
 139
 140         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 141         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 142
 143         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 144         mode_rate = intel_dp_link_required(target_clock, 18);
 145
 146         if (mode_rate > max_rate)
 147                 return MODE_CLOCK_HIGH;
 148
 149         if (mode->clock < 10000)
 150                 return MODE_CLOCK_LOW;
 151
 152         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 153                 return MODE_H_ILLEGAL;
 154
 155         return MODE_OK;
 156 }
 157
 158 static uint32_t
 159 pack_aux(uint8_t *src, int src_bytes)
 160 {
 161         int     i;
 162         uint32_t v = 0;
 163
 164         if (src_bytes > 4)
 165                 src_bytes = 4;
 166         for (i = 0; i < src_bytes; i++)
 167                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 168         return v;
 169 }
 170
 171 static void
 172 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 173 {
 174         int i;
 175         if (dst_bytes > 4)
 176                 dst_bytes = 4;
 177         for (i = 0; i < dst_bytes; i++)
 178                 dst[i] = src >> ((3-i) * 8);
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 static int
 183 intel_hrawclk(struct drm_device *dev)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         uint32_t clkcfg;
 187
 188         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 189         if (IS_VALLEYVIEW(dev))
 190                 return 200;
 191
 192         clkcfg = I915_READ(CLKCFG);
 193         switch (clkcfg & CLKCFG_FSB_MASK) {
 194         case CLKCFG_FSB_400:
 195                 return 100;
 196         case CLKCFG_FSB_533:
 197                 return 133;
 198         case CLKCFG_FSB_667:
 199                 return 166;
 200         case CLKCFG_FSB_800:
 201                 return 200;
 202         case CLKCFG_FSB_1067:
 203                 return 266;
 204         case CLKCFG_FSB_1333:
 205                 return 333;
 206         /* these two are just a guess; one of them might be right */
 207         case CLKCFG_FSB_1600:
 208         case CLKCFG_FSB_1600_ALT:
 209                 return 400;
 210         default:
 211                 return 133;
 212         }
 213 }
 214
 215 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 216 {
 217         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 218         struct drm_i915_private *dev_priv = dev->dev_private;
 219         u32 pp_stat_reg;
 220
 221         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 222         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 223 }
 224
 225 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 226 {
 227         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         u32 pp_ctrl_reg;
 230
 231         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 232         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 233 }
 234
 235 static void
 236 intel_dp_check_edp(struct intel_dp *intel_dp)
 237 {
 238         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 239         struct drm_i915_private *dev_priv = dev->dev_private;
 240         u32 pp_stat_reg, pp_ctrl_reg;
 241
 242         if (!is_edp(intel_dp))
 243                 return;
 244
 245         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 246         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 247
 248         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 249                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 250                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 251                                 I915_READ(pp_stat_reg),
 252                                 I915_READ(pp_ctrl_reg));
 253         }
 254 }
 255
 256 static uint32_t
 257 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct drm_device *dev = intel_dig_port->base.base.dev;
 261         struct drm_i915_private *dev_priv = dev->dev_private;
 262         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 263         uint32_t status;
 264         bool done;
 265
 266 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 267         if (has_aux_irq)
 268                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 269                                           msecs_to_jiffies(10));
 270         else
 271                 done = wait_for_atomic(C, 10) == 0;
 272         if (!done)
 273                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 274                           has_aux_irq);
 275 #undef C
 276
 277         return status;
 278 }
 279
 280 static int
 281 intel_dp_aux_ch(struct intel_dp *intel_dp,
 282                 uint8_t *send, int send_bytes,
 283                 uint8_t *recv, int recv_size)
 284 {
 285         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 286         struct drm_device *dev = intel_dig_port->base.base.dev;
 287         struct drm_i915_private *dev_priv = dev->dev_private;
 288         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 289         uint32_t ch_data = ch_ctl + 4;
 290         int i, ret, recv_bytes;
 291         uint32_t status;
 292         uint32_t aux_clock_divider;
 293         int try, precharge;
 294         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 295
 296         /* dp aux is extremely sensitive to irq latency, hence request the
 297          * lowest possible wakeup latency and so prevent the cpu from going into
 298          * deep sleep states.
 299          */
 300         pm_qos_update_request(&dev_priv->pm_qos, 0);
 301
 302         intel_dp_check_edp(intel_dp);
 303         /* The clock divider is based off the hrawclk,
 304          * and would like to run at 2MHz. So, take the
 305          * hrawclk value and divide by 2 and use that
 306          *
 307          * Note that PCH attached eDP panels should use a 125MHz input
 308          * clock divider.
 309          */
 310         if (IS_VALLEYVIEW(dev)) {
 311                 aux_clock_divider = 100;
 312         } else if (intel_dig_port->port == PORT_A) {
 313                 if (HAS_DDI(dev))
 314                         aux_clock_divider = DIV_ROUND_CLOSEST(
 315                                 intel_ddi_get_cdclk_freq(dev_priv), 2000);
 316                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 317                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 318                 else
 319                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 320         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 321                 /* Workaround for non-ULT HSW */
 322                 aux_clock_divider = 74;
 323         } else if (HAS_PCH_SPLIT(dev)) {
 324                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 325         } else {
 326                 aux_clock_divider = intel_hrawclk(dev) / 2;
 327         }
 328
 329         if (IS_GEN6(dev))
 330                 precharge = 3;
 331         else
 332                 precharge = 5;
 333
 334         /* Try to wait for any previous AUX channel activity */
 335         for (try = 0; try < 3; try++) {
 336                 status = I915_READ_NOTRACE(ch_ctl);
 337                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 338                         break;
 339                 msleep(1);
 340         }
 341
 342         if (try == 3) {
 343                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 344                      I915_READ(ch_ctl));
 345                 ret = -EBUSY;
 346                 goto out;
 347         }
 348
 349         /* Must try at least 3 times according to DP spec */
 350         for (try = 0; try < 5; try++) {
 351                 /* Load the send data into the aux channel data registers */
 352                 for (i = 0; i < send_bytes; i += 4)
 353                         I915_WRITE(ch_data + i,
 354                                    pack_aux(send + i, send_bytes - i));
 355
 356                 /* Send the command and wait for it to complete */
 357                 I915_WRITE(ch_ctl,
 358                            DP_AUX_CH_CTL_SEND_BUSY |
 359                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 360                            DP_AUX_CH_CTL_TIME_OUT_400us |
 361                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 362                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 363                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 364                            DP_AUX_CH_CTL_DONE |
 365                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 366                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 367
 368                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 369
 370                 /* Clear done status and any errors */
 371                 I915_WRITE(ch_ctl,
 372                            status |
 373                            DP_AUX_CH_CTL_DONE |
 374                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 375                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 376
 377                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 378                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 379                         continue;
 380                 if (status & DP_AUX_CH_CTL_DONE)
 381                         break;
 382         }
 383
 384         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 385                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 386                 ret = -EBUSY;
 387                 goto out;
 388         }
 389
 390         /* Check for timeout or receive error.
 391          * Timeouts occur when the sink is not connected
 392          */
 393         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 394                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 395                 ret = -EIO;
 396                 goto out;
 397         }
 398
 399         /* Timeouts occur when the device isn't connected, so they're
 400          * "normal" -- don't fill the kernel log with these */
 401         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 402                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 403                 ret = -ETIMEDOUT;
 404                 goto out;
 405         }
 406
 407         /* Unload any bytes sent back from the other side */
 408         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 409                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 410         if (recv_bytes > recv_size)
 411                 recv_bytes = recv_size;
 412
 413         for (i = 0; i < recv_bytes; i += 4)
 414                 unpack_aux(I915_READ(ch_data + i),
 415                            recv + i, recv_bytes - i);
 416
 417         ret = recv_bytes;
 418 out:
 419         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 420
 421         return ret;
 422 }
 423
 424 /* Write data to the aux channel in native mode */
 425 static int
 426 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 427                           uint16_t address, uint8_t *send, int send_bytes)
 428 {
 429         int ret;
 430         uint8_t msg[20];
 431         int msg_bytes;
 432         uint8_t ack;
 433
 434         intel_dp_check_edp(intel_dp);
 435         if (send_bytes > 16)
 436                 return -1;
 437         msg[0] = AUX_NATIVE_WRITE << 4;
 438         msg[1] = address >> 8;
 439         msg[2] = address & 0xff;
 440         msg[3] = send_bytes - 1;
 441         memcpy(&msg[4], send, send_bytes);
 442         msg_bytes = send_bytes + 4;
 443         for (;;) {
 444                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 445                 if (ret < 0)
 446                         return ret;
 447                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 448                         break;
 449                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 450                         udelay(100);
 451                 else
 452                         return -EIO;
 453         }
 454         return send_bytes;
 455 }
 456
 457 /* Write a single byte to the aux channel in native mode */
 458 static int
 459 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 460                             uint16_t address, uint8_t byte)
 461 {
 462         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 463 }
 464
 465 /* read bytes from a native aux channel */
 466 static int
 467 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 468                          uint16_t address, uint8_t *recv, int recv_bytes)
 469 {
 470         uint8_t msg[4];
 471         int msg_bytes;
 472         uint8_t reply[20];
 473         int reply_bytes;
 474         uint8_t ack;
 475         int ret;
 476
 477         intel_dp_check_edp(intel_dp);
 478         msg[0] = AUX_NATIVE_READ << 4;
 479         msg[1] = address >> 8;
 480         msg[2] = address & 0xff;
 481         msg[3] = recv_bytes - 1;
 482
 483         msg_bytes = 4;
 484         reply_bytes = recv_bytes + 1;
 485
 486         for (;;) {
 487                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 488                                       reply, reply_bytes);
 489                 if (ret == 0)
 490                         return -EPROTO;
 491                 if (ret < 0)
 492                         return ret;
 493                 ack = reply[0];
 494                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 495                         memcpy(recv, reply + 1, ret - 1);
 496                         return ret - 1;
 497                 }
 498                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 499                         udelay(100);
 500                 else
 501                         return -EIO;
 502         }
 503 }
 504
 505 static int
 506 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
 507                     uint8_t write_byte, uint8_t *read_byte)
 508 {
 509         struct iic_dp_aux_data *data = device_get_softc(adapter);
 510         struct intel_dp *intel_dp = data->priv;
 511         uint16_t address = data->address;
 512         uint8_t msg[5];
 513         uint8_t reply[2];
 514         unsigned retry;
 515         int msg_bytes;
 516         int reply_bytes;
 517         int ret;
 518
 519         intel_dp_check_edp(intel_dp);
 520         /* Set up the command byte */
 521         if (mode & MODE_I2C_READ)
 522                 msg[0] = AUX_I2C_READ << 4;
 523         else
 524                 msg[0] = AUX_I2C_WRITE << 4;
 525
 526         if (!(mode & MODE_I2C_STOP))
 527                 msg[0] |= AUX_I2C_MOT << 4;
 528
 529         msg[1] = address >> 8;
 530         msg[2] = address;
 531
 532         switch (mode) {
 533         case MODE_I2C_WRITE:
 534                 msg[3] = 0;
 535                 msg[4] = write_byte;
 536                 msg_bytes = 5;
 537                 reply_bytes = 1;
 538                 break;
 539         case MODE_I2C_READ:
 540                 msg[3] = 0;
 541                 msg_bytes = 4;
 542                 reply_bytes = 2;
 543                 break;
 544         default:
 545                 msg_bytes = 3;
 546                 reply_bytes = 1;
 547                 break;
 548         }
 549
 550         for (retry = 0; retry < 5; retry++) {
 551                 ret = intel_dp_aux_ch(intel_dp,
 552                                       msg, msg_bytes,
 553                                       reply, reply_bytes);
 554                 if (ret < 0) {
 555                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 556                         return ret;
 557                 }
 558
 559                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 560                 case AUX_NATIVE_REPLY_ACK:
 561                         /* I2C-over-AUX Reply field is only valid
 562                          * when paired with AUX ACK.
 563                          */
 564                         break;
 565                 case AUX_NATIVE_REPLY_NACK:
 566                         DRM_DEBUG_KMS("aux_ch native nack\n");
 567                         return -EREMOTEIO;
 568                 case AUX_NATIVE_REPLY_DEFER:
 569                         udelay(100);
 570                         continue;
 571                 default:
 572                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 573                                   reply[0]);
 574                         return -EREMOTEIO;
 575                 }
 576
 577                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 578                 case AUX_I2C_REPLY_ACK:
 579                         if (mode == MODE_I2C_READ) {
 580                                 *read_byte = reply[1];
 581                         }
 582                         return (0/*reply_bytes - 1*/);
 583                 case AUX_I2C_REPLY_NACK:
 584                         DRM_DEBUG_KMS("aux_i2c nack\n");
 585                         return -EREMOTEIO;
 586                 case AUX_I2C_REPLY_DEFER:
 587                         DRM_DEBUG_KMS("aux_i2c defer\n");
 588                         udelay(100);
 589                         break;
 590                 default:
 591                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 592                         return -EREMOTEIO;
 593                 }
 594         }
 595
 596         DRM_ERROR("too many retries, giving up\n");
 597         return -EREMOTEIO;
 598 }
 599
 600 static int
 601 intel_dp_i2c_init(struct intel_dp *intel_dp,
 602                   struct intel_connector *intel_connector, const char *name)
 603 {
 604         int     ret;
 605
 606         DRM_DEBUG_KMS("i2c_init %s\n", name);
 607
 608         ironlake_edp_panel_vdd_on(intel_dp);
 609         ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
 610             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
 611             &intel_dp->adapter);
 612         ironlake_edp_panel_vdd_off(intel_dp, false);
 613         return ret;
 614 }
 615
 616 static void
 617 intel_dp_set_clock(struct intel_encoder *encoder,
 618                    struct intel_crtc_config *pipe_config, int link_bw)
 619 {
 620         struct drm_device *dev = encoder->base.dev;
 621
 622         if (IS_G4X(dev)) {
 623                 if (link_bw == DP_LINK_BW_1_62) {
 624                         pipe_config->dpll.p1 = 2;
 625                         pipe_config->dpll.p2 = 10;
 626                         pipe_config->dpll.n = 2;
 627                         pipe_config->dpll.m1 = 23;
 628                         pipe_config->dpll.m2 = 8;
 629                 } else {
 630                         pipe_config->dpll.p1 = 1;
 631                         pipe_config->dpll.p2 = 10;
 632                         pipe_config->dpll.n = 1;
 633                         pipe_config->dpll.m1 = 14;
 634                         pipe_config->dpll.m2 = 2;
 635                 }
 636                 pipe_config->clock_set = true;
 637         } else if (IS_HASWELL(dev)) {
 638                 /* Haswell has special-purpose DP DDI clocks. */
 639         } else if (HAS_PCH_SPLIT(dev)) {
 640                 if (link_bw == DP_LINK_BW_1_62) {
 641                         pipe_config->dpll.n = 1;
 642                         pipe_config->dpll.p1 = 2;
 643                         pipe_config->dpll.p2 = 10;
 644                         pipe_config->dpll.m1 = 12;
 645                         pipe_config->dpll.m2 = 9;
 646                 } else {
 647                         pipe_config->dpll.n = 2;
 648                         pipe_config->dpll.p1 = 1;
 649                         pipe_config->dpll.p2 = 10;
 650                         pipe_config->dpll.m1 = 14;
 651                         pipe_config->dpll.m2 = 8;
 652                 }
 653                 pipe_config->clock_set = true;
 654         } else if (IS_VALLEYVIEW(dev)) {
 655                 /* FIXME: Need to figure out optimized DP clocks for vlv. */
 656         }
 657 }
 658
 659 bool
 660 intel_dp_compute_config(struct intel_encoder *encoder,
 661                         struct intel_crtc_config *pipe_config)
 662 {
 663         struct drm_device *dev = encoder->base.dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 666         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 667         enum port port = dp_to_dig_port(intel_dp)->port;
 668         struct intel_crtc *intel_crtc = encoder->new_crtc;
 669         struct intel_connector *intel_connector = intel_dp->attached_connector;
 670         int lane_count, clock;
 671         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 672         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 673         int bpp, mode_rate;
 674         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 675         int link_avail, link_clock;
 676
 677         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 678                 pipe_config->has_pch_encoder = true;
 679
 680         pipe_config->has_dp_encoder = true;
 681
 682         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 683                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 684                                        adjusted_mode);
 685                 if (!HAS_PCH_SPLIT(dev))
 686                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 687                                                  intel_connector->panel.fitting_mode);
 688                 else
 689                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 690                                                 intel_connector->panel.fitting_mode);
 691         }
 692
 693         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 694                 return false;
 695
 696         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 697                       "max bw %02x pixel clock %iKHz\n",
 698                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 699
 700         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 701          * bpc in between. */
 702         bpp = pipe_config->pipe_bpp;
 703         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
 704                 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
 705
 706         for (; bpp >= 6*3; bpp -= 2*3) {
 707                 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 708
 709                 for (clock = 0; clock <= max_clock; clock++) {
 710                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 711                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 712                                 link_avail = intel_dp_max_data_rate(link_clock,
 713                                                                     lane_count);
 714
 715                                 if (mode_rate <= link_avail) {
 716                                         goto found;
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return false;
 723
 724 found:
 725         if (intel_dp->color_range_auto) {
 726                 /*
 727                  * See:
 728                  * CEA-861-E - 5.1 Default Encoding Parameters
 729                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 730                  */
 731                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 732                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 733                 else
 734                         intel_dp->color_range = 0;
 735         }
 736
 737         if (intel_dp->color_range)
 738                 pipe_config->limited_color_range = true;
 739
 740         intel_dp->link_bw = bws[clock];
 741         intel_dp->lane_count = lane_count;
 742         pipe_config->pipe_bpp = bpp;
 743         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 744
 745         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 746                       intel_dp->link_bw, intel_dp->lane_count,
 747                       pipe_config->port_clock, bpp);
 748         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 749                       mode_rate, link_avail);
 750
 751         intel_link_compute_m_n(bpp, lane_count,
 752                                adjusted_mode->clock, pipe_config->port_clock,
 753                                &pipe_config->dp_m_n);
 754
 755         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 756
 757         return true;
 758 }
 759
 760 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 761 {
 762         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 763         intel_dp->link_configuration[0] = intel_dp->link_bw;
 764         intel_dp->link_configuration[1] = intel_dp->lane_count;
 765         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 766         /*
 767          * Check for DPCD version > 1.1 and enhanced framing support
 768          */
 769         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 770             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 771                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 772         }
 773 }
 774
 775 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 776 {
 777         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 778         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 779         struct drm_device *dev = crtc->base.dev;
 780         struct drm_i915_private *dev_priv = dev->dev_private;
 781         u32 dpa_ctl;
 782
 783         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 784         dpa_ctl = I915_READ(DP_A);
 785         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 786
 787         if (crtc->config.port_clock == 162000) {
 788                 /* For a long time we've carried around a ILK-DevA w/a for the
 789                  * 160MHz clock. If we're really unlucky, it's still required.
 790                  */
 791                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 792                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 793                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 794         } else {
 795                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 796                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 797         }
 798
 799         I915_WRITE(DP_A, dpa_ctl);
 800
 801         POSTING_READ(DP_A);
 802         udelay(500);
 803 }
 804
 805 static void
 806 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 807                   struct drm_display_mode *adjusted_mode)
 808 {
 809         struct drm_device *dev = encoder->dev;
 810         struct drm_i915_private *dev_priv = dev->dev_private;
 811         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 812         enum port port = dp_to_dig_port(intel_dp)->port;
 813         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 814
 815         /*
 816          * There are four kinds of DP registers:
 817          *
 818          *      IBX PCH
 819          *      SNB CPU
 820          *      IVB CPU
 821          *      CPT PCH
 822          *
 823          * IBX PCH and CPU are the same for almost everything,
 824          * except that the CPU DP PLL is configured in this
 825          * register
 826          *
 827          * CPT PCH is quite different, having many bits moved
 828          * to the TRANS_DP_CTL register instead. That
 829          * configuration happens (oddly) in ironlake_pch_enable
 830          */
 831
 832         /* Preserve the BIOS-computed detected bit. This is
 833          * supposed to be read-only.
 834          */
 835         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 836
 837         /* Handle DP bits in common between all three register formats */
 838         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 839         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 840
 841         if (intel_dp->has_audio) {
 842                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 843                                  pipe_name(crtc->pipe));
 844                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 845                 intel_write_eld(encoder, adjusted_mode);
 846         }
 847
 848         intel_dp_init_link_config(intel_dp);
 849
 850         /* Split out the IBX/CPU vs CPT settings */
 851
 852         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 853                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 854                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 855                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 856                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 857                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 858
 859                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 860                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 861
 862                 intel_dp->DP |= crtc->pipe << 29;
 863         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 864                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 865                         intel_dp->DP |= intel_dp->color_range;
 866
 867                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 868                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 869                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 870                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 871                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 872
 873                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 874                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 875
 876                 if (crtc->pipe == 1)
 877                         intel_dp->DP |= DP_PIPEB_SELECT;
 878         } else {
 879                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 880         }
 881
 882         if (port == PORT_A && !IS_VALLEYVIEW(dev))
 883                 ironlake_set_pll_cpu_edp(intel_dp);
 884 }
 885
 886 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 887 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 888
 889 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 890 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 891
 892 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 893 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 894
 895 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 896                                        u32 mask,
 897                                        u32 value)
 898 {
 899         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 900         struct drm_i915_private *dev_priv = dev->dev_private;
 901         u32 pp_stat_reg, pp_ctrl_reg;
 902
 903         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 904         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 905
 906         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 907                         mask, value,
 908                         I915_READ(pp_stat_reg),
 909                         I915_READ(pp_ctrl_reg));
 910
 911         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 912                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 913                                 I915_READ(pp_stat_reg),
 914                                 I915_READ(pp_ctrl_reg));
 915         }
 916 }
 917
 918 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 919 {
 920         DRM_DEBUG_KMS("Wait for panel power on\n");
 921         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 922 }
 923
 924 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 925 {
 926         DRM_DEBUG_KMS("Wait for panel power off time\n");
 927         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 928 }
 929
 930 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 931 {
 932         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 933         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 934 }
 935
 936
 937 /* Read the current pp_control value, unlocking the register if it
 938  * is locked
 939  */
 940
 941 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 942 {
 943         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 944         struct drm_i915_private *dev_priv = dev->dev_private;
 945         u32 control;
 946         u32 pp_ctrl_reg;
 947
 948         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 949         control = I915_READ(pp_ctrl_reg);
 950
 951         control &= ~PANEL_UNLOCK_MASK;
 952         control |= PANEL_UNLOCK_REGS;
 953         return control;
 954 }
 955
 956 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 957 {
 958         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 959         struct drm_i915_private *dev_priv = dev->dev_private;
 960         u32 pp;
 961         u32 pp_stat_reg, pp_ctrl_reg;
 962
 963         if (!is_edp(intel_dp))
 964                 return;
 965         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 966
 967         WARN(intel_dp->want_panel_vdd,
 968              "eDP VDD already requested on\n");
 969
 970         intel_dp->want_panel_vdd = true;
 971
 972         if (ironlake_edp_have_panel_vdd(intel_dp)) {
 973                 DRM_DEBUG_KMS("eDP VDD already on\n");
 974                 return;
 975         }
 976
 977         if (!ironlake_edp_have_panel_power(intel_dp))
 978                 ironlake_wait_panel_power_cycle(intel_dp);
 979
 980         pp = ironlake_get_pp_control(intel_dp);
 981         pp |= EDP_FORCE_VDD;
 982
 983         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 984         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 985
 986         I915_WRITE(pp_ctrl_reg, pp);
 987         POSTING_READ(pp_ctrl_reg);
 988         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 989                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 990         /*
 991          * If the panel wasn't on, delay before accessing aux channel
 992          */
 993         if (!ironlake_edp_have_panel_power(intel_dp)) {
 994                 DRM_DEBUG_KMS("eDP was not running\n");
 995                 msleep(intel_dp->panel_power_up_delay);
 996         }
 997 }
 998
 999 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1000 {
1001         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         u32 pp;
1004         u32 pp_stat_reg, pp_ctrl_reg;
1005
1006         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1007
1008         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1009                 pp = ironlake_get_pp_control(intel_dp);
1010                 pp &= ~EDP_FORCE_VDD;
1011
1012                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1013                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1014
1015                 I915_WRITE(pp_ctrl_reg, pp);
1016                 POSTING_READ(pp_ctrl_reg);
1017
1018                 /* Make sure sequencer is idle before allowing subsequent activity */
1019                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1020                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1021                 msleep(intel_dp->panel_power_down_delay);
1022         }
1023 }
1024
1025 static void ironlake_panel_vdd_work(struct work_struct *__work)
1026 {
1027         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1028                                                  struct intel_dp, panel_vdd_work);
1029         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1030
1031         mutex_lock(&dev->mode_config.mutex);
1032         ironlake_panel_vdd_off_sync(intel_dp);
1033         mutex_unlock(&dev->mode_config.mutex);
1034 }
1035
1036 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1037 {
1038         if (!is_edp(intel_dp))
1039                 return;
1040
1041         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1042         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1043
1044         intel_dp->want_panel_vdd = false;
1045
1046         if (sync) {
1047                 ironlake_panel_vdd_off_sync(intel_dp);
1048         } else {
1049                 /*
1050                  * Queue the timer to fire a long
1051                  * time from now (relative to the power down delay)
1052                  * to keep the panel power up across a sequence of operations
1053                  */
1054                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1055                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1056         }
1057 }
1058
1059 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1060 {
1061         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062         struct drm_i915_private *dev_priv = dev->dev_private;
1063         u32 pp;
1064         u32 pp_ctrl_reg;
1065
1066         if (!is_edp(intel_dp))
1067                 return;
1068
1069         DRM_DEBUG_KMS("Turn eDP power on\n");
1070
1071         if (ironlake_edp_have_panel_power(intel_dp)) {
1072                 DRM_DEBUG_KMS("eDP power already on\n");
1073                 return;
1074         }
1075
1076         ironlake_wait_panel_power_cycle(intel_dp);
1077
1078         pp = ironlake_get_pp_control(intel_dp);
1079         if (IS_GEN5(dev)) {
1080                 /* ILK workaround: disable reset around power sequence */
1081                 pp &= ~PANEL_POWER_RESET;
1082                 I915_WRITE(PCH_PP_CONTROL, pp);
1083                 POSTING_READ(PCH_PP_CONTROL);
1084         }
1085
1086         pp |= POWER_TARGET_ON;
1087         if (!IS_GEN5(dev))
1088                 pp |= PANEL_POWER_RESET;
1089
1090         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1091
1092         I915_WRITE(pp_ctrl_reg, pp);
1093         POSTING_READ(pp_ctrl_reg);
1094
1095         ironlake_wait_panel_on(intel_dp);
1096
1097         if (IS_GEN5(dev)) {
1098                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1099                 I915_WRITE(PCH_PP_CONTROL, pp);
1100                 POSTING_READ(PCH_PP_CONTROL);
1101         }
1102 }
1103
1104 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1105 {
1106         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1107         struct drm_i915_private *dev_priv = dev->dev_private;
1108         u32 pp;
1109         u32 pp_ctrl_reg;
1110
1111         if (!is_edp(intel_dp))
1112                 return;
1113
1114         DRM_DEBUG_KMS("Turn eDP power off\n");
1115
1116         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1117
1118         pp = ironlake_get_pp_control(intel_dp);
1119         /* We need to switch off panel power _and_ force vdd, for otherwise some
1120          * panels get very unhappy and cease to work. */
1121         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1122
1123         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1124
1125         I915_WRITE(pp_ctrl_reg, pp);
1126         POSTING_READ(pp_ctrl_reg);
1127
1128         intel_dp->want_panel_vdd = false;
1129
1130         ironlake_wait_panel_off(intel_dp);
1131 }
1132
1133 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1134 {
1135         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1136         struct drm_device *dev = intel_dig_port->base.base.dev;
1137         struct drm_i915_private *dev_priv = dev->dev_private;
1138         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1139         u32 pp;
1140         u32 pp_ctrl_reg;
1141
1142         if (!is_edp(intel_dp))
1143                 return;
1144
1145         DRM_DEBUG_KMS("\n");
1146         /*
1147          * If we enable the backlight right away following a panel power
1148          * on, we may see slight flicker as the panel syncs with the eDP
1149          * link.  So delay a bit to make sure the image is solid before
1150          * allowing it to appear.
1151          */
1152         msleep(intel_dp->backlight_on_delay);
1153         pp = ironlake_get_pp_control(intel_dp);
1154         pp |= EDP_BLC_ENABLE;
1155
1156         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1157
1158         I915_WRITE(pp_ctrl_reg, pp);
1159         POSTING_READ(pp_ctrl_reg);
1160
1161         intel_panel_enable_backlight(dev, pipe);
1162 }
1163
1164 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1165 {
1166         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1167         struct drm_i915_private *dev_priv = dev->dev_private;
1168         u32 pp;
1169         u32 pp_ctrl_reg;
1170
1171         if (!is_edp(intel_dp))
1172                 return;
1173
1174         intel_panel_disable_backlight(dev);
1175
1176         DRM_DEBUG_KMS("\n");
1177         pp = ironlake_get_pp_control(intel_dp);
1178         pp &= ~EDP_BLC_ENABLE;
1179
1180         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1181
1182         I915_WRITE(pp_ctrl_reg, pp);
1183         POSTING_READ(pp_ctrl_reg);
1184         msleep(intel_dp->backlight_off_delay);
1185 }
1186
1187 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1188 {
1189         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1190         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1191         struct drm_device *dev = crtc->dev;
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193         u32 dpa_ctl;
1194
1195         assert_pipe_disabled(dev_priv,
1196                              to_intel_crtc(crtc)->pipe);
1197
1198         DRM_DEBUG_KMS("\n");
1199         dpa_ctl = I915_READ(DP_A);
1200         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1201         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1202
1203         /* We don't adjust intel_dp->DP while tearing down the link, to
1204          * facilitate link retraining (e.g. after hotplug). Hence clear all
1205          * enable bits here to ensure that we don't enable too much. */
1206         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1207         intel_dp->DP |= DP_PLL_ENABLE;
1208         I915_WRITE(DP_A, intel_dp->DP);
1209         POSTING_READ(DP_A);
1210         udelay(200);
1211 }
1212
1213 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1214 {
1215         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1216         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1217         struct drm_device *dev = crtc->dev;
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219         u32 dpa_ctl;
1220
1221         assert_pipe_disabled(dev_priv,
1222                              to_intel_crtc(crtc)->pipe);
1223
1224         dpa_ctl = I915_READ(DP_A);
1225         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1226              "dp pll off, should be on\n");
1227         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1228
1229         /* We can't rely on the value tracked for the DP register in
1230          * intel_dp->DP because link_down must not change that (otherwise link
1231          * re-training will fail. */
1232         dpa_ctl &= ~DP_PLL_ENABLE;
1233         I915_WRITE(DP_A, dpa_ctl);
1234         POSTING_READ(DP_A);
1235         udelay(200);
1236 }
1237
1238 /* If the sink supports it, try to set the power state appropriately */
1239 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1240 {
1241         int ret, i;
1242
1243         /* Should have a valid DPCD by this point */
1244         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1245                 return;
1246
1247         if (mode != DRM_MODE_DPMS_ON) {
1248                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1249                                                   DP_SET_POWER_D3);
1250                 if (ret != 1)
1251                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1252         } else {
1253                 /*
1254                  * When turning on, we need to retry for 1ms to give the sink
1255                  * time to wake up.
1256                  */
1257                 for (i = 0; i < 3; i++) {
1258                         ret = intel_dp_aux_native_write_1(intel_dp,
1259                                                           DP_SET_POWER,
1260                                                           DP_SET_POWER_D0);
1261                         if (ret == 1)
1262                                 break;
1263                         msleep(1);
1264                 }
1265         }
1266 }
1267
1268 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1269                                   enum i915_pipe *pipe)
1270 {
1271         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1272         enum port port = dp_to_dig_port(intel_dp)->port;
1273         struct drm_device *dev = encoder->base.dev;
1274         struct drm_i915_private *dev_priv = dev->dev_private;
1275         u32 tmp = I915_READ(intel_dp->output_reg);
1276
1277         if (!(tmp & DP_PORT_EN))
1278                 return false;
1279
1280         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1281                 *pipe = PORT_TO_PIPE_CPT(tmp);
1282         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1283                 *pipe = PORT_TO_PIPE(tmp);
1284         } else {
1285                 u32 trans_sel;
1286                 u32 trans_dp;
1287                 int i;
1288
1289                 switch (intel_dp->output_reg) {
1290                 case PCH_DP_B:
1291                         trans_sel = TRANS_DP_PORT_SEL_B;
1292                         break;
1293                 case PCH_DP_C:
1294                         trans_sel = TRANS_DP_PORT_SEL_C;
1295                         break;
1296                 case PCH_DP_D:
1297                         trans_sel = TRANS_DP_PORT_SEL_D;
1298                         break;
1299                 default:
1300                         return true;
1301                 }
1302
1303                 for_each_pipe(i) {
1304                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1305                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1306                                 *pipe = i;
1307                                 return true;
1308                         }
1309                 }
1310
1311                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1312                               intel_dp->output_reg);
1313         }
1314
1315         return true;
1316 }
1317
1318 static void intel_dp_get_config(struct intel_encoder *encoder,
1319                                 struct intel_crtc_config *pipe_config)
1320 {
1321         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1322         u32 tmp, flags = 0;
1323         struct drm_device *dev = encoder->base.dev;
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325         enum port port = dp_to_dig_port(intel_dp)->port;
1326         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1327
1328         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1329                 tmp = I915_READ(intel_dp->output_reg);
1330                 if (tmp & DP_SYNC_HS_HIGH)
1331                         flags |= DRM_MODE_FLAG_PHSYNC;
1332                 else
1333                         flags |= DRM_MODE_FLAG_NHSYNC;
1334
1335                 if (tmp & DP_SYNC_VS_HIGH)
1336                         flags |= DRM_MODE_FLAG_PVSYNC;
1337                 else
1338                         flags |= DRM_MODE_FLAG_NVSYNC;
1339         } else {
1340                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1341                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1342                         flags |= DRM_MODE_FLAG_PHSYNC;
1343                 else
1344                         flags |= DRM_MODE_FLAG_NHSYNC;
1345
1346                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1347                         flags |= DRM_MODE_FLAG_PVSYNC;
1348                 else
1349                         flags |= DRM_MODE_FLAG_NVSYNC;
1350         }
1351
1352         pipe_config->adjusted_mode.flags |= flags;
1353 }
1354
1355 static void intel_disable_dp(struct intel_encoder *encoder)
1356 {
1357         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1358         enum port port = dp_to_dig_port(intel_dp)->port;
1359         struct drm_device *dev = encoder->base.dev;
1360
1361         /* Make sure the panel is off before trying to change the mode. But also
1362          * ensure that we have vdd while we switch off the panel. */
1363         ironlake_edp_panel_vdd_on(intel_dp);
1364         ironlake_edp_backlight_off(intel_dp);
1365         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1366         ironlake_edp_panel_off(intel_dp);
1367
1368         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1369         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1370                 intel_dp_link_down(intel_dp);
1371 }
1372
1373 static void intel_post_disable_dp(struct intel_encoder *encoder)
1374 {
1375         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1376         enum port port = dp_to_dig_port(intel_dp)->port;
1377         struct drm_device *dev = encoder->base.dev;
1378
1379         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1380                 intel_dp_link_down(intel_dp);
1381                 if (!IS_VALLEYVIEW(dev))
1382                         ironlake_edp_pll_off(intel_dp);
1383         }
1384 }
1385
1386 static void intel_enable_dp(struct intel_encoder *encoder)
1387 {
1388         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1389         struct drm_device *dev = encoder->base.dev;
1390         struct drm_i915_private *dev_priv = dev->dev_private;
1391         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1392
1393         if (WARN_ON(dp_reg & DP_PORT_EN))
1394                 return;
1395
1396         ironlake_edp_panel_vdd_on(intel_dp);
1397         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1398         intel_dp_start_link_train(intel_dp);
1399         ironlake_edp_panel_on(intel_dp);
1400         ironlake_edp_panel_vdd_off(intel_dp, true);
1401         intel_dp_complete_link_train(intel_dp);
1402         intel_dp_stop_link_train(intel_dp);
1403         ironlake_edp_backlight_on(intel_dp);
1404
1405         if (IS_VALLEYVIEW(dev)) {
1406                 struct intel_digital_port *dport =
1407                         enc_to_dig_port(&encoder->base);
1408                 int channel = vlv_dport_to_channel(dport);
1409
1410                 vlv_wait_port_ready(dev_priv, channel);
1411         }
1412 }
1413
1414 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1415 {
1416         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1417         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1418         struct drm_device *dev = encoder->base.dev;
1419         struct drm_i915_private *dev_priv = dev->dev_private;
1420
1421         if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1422                 ironlake_edp_pll_on(intel_dp);
1423
1424         if (IS_VALLEYVIEW(dev)) {
1425                 struct intel_crtc *intel_crtc =
1426                         to_intel_crtc(encoder->base.crtc);
1427                 int port = vlv_dport_to_channel(dport);
1428                 int pipe = intel_crtc->pipe;
1429                 u32 val;
1430
1431                 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1432                 val = 0;
1433                 if (pipe)
1434                         val |= (1<<21);
1435                 else
1436                         val &= ~(1<<21);
1437                 val |= 0x001000c4;
1438                 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1439
1440                 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1441                                  0x00760018);
1442                 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1443                                  0x00400888);
1444         }
1445 }
1446
1447 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1448 {
1449         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1450         struct drm_device *dev = encoder->base.dev;
1451         struct drm_i915_private *dev_priv = dev->dev_private;
1452         int port = vlv_dport_to_channel(dport);
1453
1454         if (!IS_VALLEYVIEW(dev))
1455                 return;
1456
1457         /* Program Tx lane resets to default */
1458         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1459                          DPIO_PCS_TX_LANE2_RESET |
1460                          DPIO_PCS_TX_LANE1_RESET);
1461         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1462                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1463                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1464                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1465                                  DPIO_PCS_CLK_SOFT_RESET);
1466
1467         /* Fix up inter-pair skew failure */
1468         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1469         vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1470         vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1471 }
1472
1473 /*
1474  * Native read with retry for link status and receiver capability reads for
1475  * cases where the sink may still be asleep.
1476  */
1477 static bool
1478 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1479                                uint8_t *recv, int recv_bytes)
1480 {
1481         int ret, i;
1482
1483         /*
1484          * Sinks are *supposed* to come up within 1ms from an off state,
1485          * but we're also supposed to retry 3 times per the spec.
1486          */
1487         for (i = 0; i < 3; i++) {
1488                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1489                                                recv_bytes);
1490                 if (ret == recv_bytes)
1491                         return true;
1492                 msleep(1);
1493         }
1494
1495         return false;
1496 }
1497
1498 /*
1499  * Fetch AUX CH registers 0x202 - 0x207 which contain
1500  * link status information
1501  */
1502 static bool
1503 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1504 {
1505         return intel_dp_aux_native_read_retry(intel_dp,
1506                                               DP_LANE0_1_STATUS,
1507                                               link_status,
1508                                               DP_LINK_STATUS_SIZE);
1509 }
1510
1511 #if 0
1512 static char     *voltage_names[] = {
1513         "0.4V", "0.6V", "0.8V", "1.2V"
1514 };
1515 static char     *pre_emph_names[] = {
1516         "0dB", "3.5dB", "6dB", "9.5dB"
1517 };
1518 static char     *link_train_names[] = {
1519         "pattern 1", "pattern 2", "idle", "off"
1520 };
1521 #endif
1522
1523 /*
1524  * These are source-specific values; current Intel hardware supports
1525  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1526  */
1527
1528 static uint8_t
1529 intel_dp_voltage_max(struct intel_dp *intel_dp)
1530 {
1531         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1532         enum port port = dp_to_dig_port(intel_dp)->port;
1533
1534         if (IS_VALLEYVIEW(dev))
1535                 return DP_TRAIN_VOLTAGE_SWING_1200;
1536         else if (IS_GEN7(dev) && port == PORT_A)
1537                 return DP_TRAIN_VOLTAGE_SWING_800;
1538         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1539                 return DP_TRAIN_VOLTAGE_SWING_1200;
1540         else
1541                 return DP_TRAIN_VOLTAGE_SWING_800;
1542 }
1543
1544 static uint8_t
1545 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1546 {
1547         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1548         enum port port = dp_to_dig_port(intel_dp)->port;
1549
1550         if (HAS_DDI(dev)) {
1551                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1552                 case DP_TRAIN_VOLTAGE_SWING_400:
1553                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1554                 case DP_TRAIN_VOLTAGE_SWING_600:
1555                         return DP_TRAIN_PRE_EMPHASIS_6;
1556                 case DP_TRAIN_VOLTAGE_SWING_800:
1557                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1558                 case DP_TRAIN_VOLTAGE_SWING_1200:
1559                 default:
1560                         return DP_TRAIN_PRE_EMPHASIS_0;
1561                 }
1562         } else if (IS_VALLEYVIEW(dev)) {
1563                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1564                 case DP_TRAIN_VOLTAGE_SWING_400:
1565                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1566                 case DP_TRAIN_VOLTAGE_SWING_600:
1567                         return DP_TRAIN_PRE_EMPHASIS_6;
1568                 case DP_TRAIN_VOLTAGE_SWING_800:
1569                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1570                 case DP_TRAIN_VOLTAGE_SWING_1200:
1571                 default:
1572                         return DP_TRAIN_PRE_EMPHASIS_0;
1573                 }
1574         } else if (IS_GEN7(dev) && port == PORT_A) {
1575                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576                 case DP_TRAIN_VOLTAGE_SWING_400:
1577                         return DP_TRAIN_PRE_EMPHASIS_6;
1578                 case DP_TRAIN_VOLTAGE_SWING_600:
1579                 case DP_TRAIN_VOLTAGE_SWING_800:
1580                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1581                 default:
1582                         return DP_TRAIN_PRE_EMPHASIS_0;
1583                 }
1584         } else {
1585                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1586                 case DP_TRAIN_VOLTAGE_SWING_400:
1587                         return DP_TRAIN_PRE_EMPHASIS_6;
1588                 case DP_TRAIN_VOLTAGE_SWING_600:
1589                         return DP_TRAIN_PRE_EMPHASIS_6;
1590                 case DP_TRAIN_VOLTAGE_SWING_800:
1591                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1592                 case DP_TRAIN_VOLTAGE_SWING_1200:
1593                 default:
1594                         return DP_TRAIN_PRE_EMPHASIS_0;
1595                 }
1596         }
1597 }
1598
1599 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1600 {
1601         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1602         struct drm_i915_private *dev_priv = dev->dev_private;
1603         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1604         unsigned long demph_reg_value, preemph_reg_value,
1605                 uniqtranscale_reg_value;
1606         uint8_t train_set = intel_dp->train_set[0];
1607         int port = vlv_dport_to_channel(dport);
1608
1609         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1610         case DP_TRAIN_PRE_EMPHASIS_0:
1611                 preemph_reg_value = 0x0004000;
1612                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1613                 case DP_TRAIN_VOLTAGE_SWING_400:
1614                         demph_reg_value = 0x2B405555;
1615                         uniqtranscale_reg_value = 0x552AB83A;
1616                         break;
1617                 case DP_TRAIN_VOLTAGE_SWING_600:
1618                         demph_reg_value = 0x2B404040;
1619                         uniqtranscale_reg_value = 0x5548B83A;
1620                         break;
1621                 case DP_TRAIN_VOLTAGE_SWING_800:
1622                         demph_reg_value = 0x2B245555;
1623                         uniqtranscale_reg_value = 0x5560B83A;
1624                         break;
1625                 case DP_TRAIN_VOLTAGE_SWING_1200:
1626                         demph_reg_value = 0x2B405555;
1627                         uniqtranscale_reg_value = 0x5598DA3A;
1628                         break;
1629                 default:
1630                         return 0;
1631                 }
1632                 break;
1633         case DP_TRAIN_PRE_EMPHASIS_3_5:
1634                 preemph_reg_value = 0x0002000;
1635                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1636                 case DP_TRAIN_VOLTAGE_SWING_400:
1637                         demph_reg_value = 0x2B404040;
1638                         uniqtranscale_reg_value = 0x5552B83A;
1639                         break;
1640                 case DP_TRAIN_VOLTAGE_SWING_600:
1641                         demph_reg_value = 0x2B404848;
1642                         uniqtranscale_reg_value = 0x5580B83A;
1643                         break;
1644                 case DP_TRAIN_VOLTAGE_SWING_800:
1645                         demph_reg_value = 0x2B404040;
1646                         uniqtranscale_reg_value = 0x55ADDA3A;
1647                         break;
1648                 default:
1649                         return 0;
1650                 }
1651                 break;
1652         case DP_TRAIN_PRE_EMPHASIS_6:
1653                 preemph_reg_value = 0x0000000;
1654                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1655                 case DP_TRAIN_VOLTAGE_SWING_400:
1656                         demph_reg_value = 0x2B305555;
1657                         uniqtranscale_reg_value = 0x5570B83A;
1658                         break;
1659                 case DP_TRAIN_VOLTAGE_SWING_600:
1660                         demph_reg_value = 0x2B2B4040;
1661                         uniqtranscale_reg_value = 0x55ADDA3A;
1662                         break;
1663                 default:
1664                         return 0;
1665                 }
1666                 break;
1667         case DP_TRAIN_PRE_EMPHASIS_9_5:
1668                 preemph_reg_value = 0x0006000;
1669                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1670                 case DP_TRAIN_VOLTAGE_SWING_400:
1671                         demph_reg_value = 0x1B405555;
1672                         uniqtranscale_reg_value = 0x55ADDA3A;
1673                         break;
1674                 default:
1675                         return 0;
1676                 }
1677                 break;
1678         default:
1679                 return 0;
1680         }
1681
1682         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1683         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1684         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1685                          uniqtranscale_reg_value);
1686         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1687         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1688         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1689         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1690
1691         return 0;
1692 }
1693
1694 static void
1695 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1696 {
1697         uint8_t v = 0;
1698         uint8_t p = 0;
1699         int lane;
1700         uint8_t voltage_max;
1701         uint8_t preemph_max;
1702
1703         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1704                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1705                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1706
1707                 if (this_v > v)
1708                         v = this_v;
1709                 if (this_p > p)
1710                         p = this_p;
1711         }
1712
1713         voltage_max = intel_dp_voltage_max(intel_dp);
1714         if (v >= voltage_max)
1715                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1716
1717         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1718         if (p >= preemph_max)
1719                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1720
1721         for (lane = 0; lane < 4; lane++)
1722                 intel_dp->train_set[lane] = v | p;
1723 }
1724
1725 static uint32_t
1726 intel_gen4_signal_levels(uint8_t train_set)
1727 {
1728         uint32_t        signal_levels = 0;
1729
1730         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1731         case DP_TRAIN_VOLTAGE_SWING_400:
1732         default:
1733                 signal_levels |= DP_VOLTAGE_0_4;
1734                 break;
1735         case DP_TRAIN_VOLTAGE_SWING_600:
1736                 signal_levels |= DP_VOLTAGE_0_6;
1737                 break;
1738         case DP_TRAIN_VOLTAGE_SWING_800:
1739                 signal_levels |= DP_VOLTAGE_0_8;
1740                 break;
1741         case DP_TRAIN_VOLTAGE_SWING_1200:
1742                 signal_levels |= DP_VOLTAGE_1_2;
1743                 break;
1744         }
1745         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1746         case DP_TRAIN_PRE_EMPHASIS_0:
1747         default:
1748                 signal_levels |= DP_PRE_EMPHASIS_0;
1749                 break;
1750         case DP_TRAIN_PRE_EMPHASIS_3_5:
1751                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1752                 break;
1753         case DP_TRAIN_PRE_EMPHASIS_6:
1754                 signal_levels |= DP_PRE_EMPHASIS_6;
1755                 break;
1756         case DP_TRAIN_PRE_EMPHASIS_9_5:
1757                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1758                 break;
1759         }
1760         return signal_levels;
1761 }
1762
1763 /* Gen6's DP voltage swing and pre-emphasis control */
1764 static uint32_t
1765 intel_gen6_edp_signal_levels(uint8_t train_set)
1766 {
1767         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1768                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1769         switch (signal_levels) {
1770         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1771         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1772                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1773         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1774                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1775         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1776         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1777                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1778         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1779         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1780                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1781         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1782         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1783                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1784         default:
1785                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1786                               "0x%x\n", signal_levels);
1787                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1788         }
1789 }
1790
1791 /* Gen7's DP voltage swing and pre-emphasis control */
1792 static uint32_t
1793 intel_gen7_edp_signal_levels(uint8_t train_set)
1794 {
1795         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1796                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1797         switch (signal_levels) {
1798         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1799                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1800         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1801                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1802         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1803                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1804
1805         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1806                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1807         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1808                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1809
1810         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1811                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1812         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1813                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1814
1815         default:
1816                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1817                               "0x%x\n", signal_levels);
1818                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1819         }
1820 }
1821
1822 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1823 static uint32_t
1824 intel_hsw_signal_levels(uint8_t train_set)
1825 {
1826         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1827                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1828         switch (signal_levels) {
1829         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1830                 return DDI_BUF_EMP_400MV_0DB_HSW;
1831         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1832                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1833         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1834                 return DDI_BUF_EMP_400MV_6DB_HSW;
1835         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1836                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1837
1838         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1839                 return DDI_BUF_EMP_600MV_0DB_HSW;
1840         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1841                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1842         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1843                 return DDI_BUF_EMP_600MV_6DB_HSW;
1844
1845         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1846                 return DDI_BUF_EMP_800MV_0DB_HSW;
1847         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1848                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1849         default:
1850                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1851                               "0x%x\n", signal_levels);
1852                 return DDI_BUF_EMP_400MV_0DB_HSW;
1853         }
1854 }
1855
1856 /* Properly updates "DP" with the correct signal levels. */
1857 static void
1858 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1859 {
1860         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1861         enum port port = intel_dig_port->port;
1862         struct drm_device *dev = intel_dig_port->base.base.dev;
1863         uint32_t signal_levels, mask;
1864         uint8_t train_set = intel_dp->train_set[0];
1865
1866         if (HAS_DDI(dev)) {
1867                 signal_levels = intel_hsw_signal_levels(train_set);
1868                 mask = DDI_BUF_EMP_MASK;
1869         } else if (IS_VALLEYVIEW(dev)) {
1870                 signal_levels = intel_vlv_signal_levels(intel_dp);
1871                 mask = 0;
1872         } else if (IS_GEN7(dev) && port == PORT_A) {
1873                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1874                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1875         } else if (IS_GEN6(dev) && port == PORT_A) {
1876                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1877                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1878         } else {
1879                 signal_levels = intel_gen4_signal_levels(train_set);
1880                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1881         }
1882
1883         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1884
1885         *DP = (*DP & ~mask) | signal_levels;
1886 }
1887
1888 static bool
1889 intel_dp_set_link_train(struct intel_dp *intel_dp,
1890                         uint32_t dp_reg_value,
1891                         uint8_t dp_train_pat)
1892 {
1893         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1894         struct drm_device *dev = intel_dig_port->base.base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         enum port port = intel_dig_port->port;
1897         int ret;
1898
1899         if (HAS_DDI(dev)) {
1900                 uint32_t temp = I915_READ(DP_TP_CTL(port));
1901
1902                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1903                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1904                 else
1905                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1906
1907                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1908                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1909                 case DP_TRAINING_PATTERN_DISABLE:
1910                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1911
1912                         break;
1913                 case DP_TRAINING_PATTERN_1:
1914                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1915                         break;
1916                 case DP_TRAINING_PATTERN_2:
1917                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1918                         break;
1919                 case DP_TRAINING_PATTERN_3:
1920                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1921                         break;
1922                 }
1923                 I915_WRITE(DP_TP_CTL(port), temp);
1924
1925         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
1926                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1927
1928                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1929                 case DP_TRAINING_PATTERN_DISABLE:
1930                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1931                         break;
1932                 case DP_TRAINING_PATTERN_1:
1933                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1934                         break;
1935                 case DP_TRAINING_PATTERN_2:
1936                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1937                         break;
1938                 case DP_TRAINING_PATTERN_3:
1939                         DRM_ERROR("DP training pattern 3 not supported\n");
1940                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1941                         break;
1942                 }
1943
1944         } else {
1945                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1946
1947                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1948                 case DP_TRAINING_PATTERN_DISABLE:
1949                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1950                         break;
1951                 case DP_TRAINING_PATTERN_1:
1952                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1953                         break;
1954                 case DP_TRAINING_PATTERN_2:
1955                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1956                         break;
1957                 case DP_TRAINING_PATTERN_3:
1958                         DRM_ERROR("DP training pattern 3 not supported\n");
1959                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1960                         break;
1961                 }
1962         }
1963
1964         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1965         POSTING_READ(intel_dp->output_reg);
1966
1967         intel_dp_aux_native_write_1(intel_dp,
1968                                     DP_TRAINING_PATTERN_SET,
1969                                     dp_train_pat);
1970
1971         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1972             DP_TRAINING_PATTERN_DISABLE) {
1973                 ret = intel_dp_aux_native_write(intel_dp,
1974                                                 DP_TRAINING_LANE0_SET,
1975                                                 intel_dp->train_set,
1976                                                 intel_dp->lane_count);
1977                 if (ret != intel_dp->lane_count)
1978                         return false;
1979         }
1980
1981         return true;
1982 }
1983
1984 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1985 {
1986         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1987         struct drm_device *dev = intel_dig_port->base.base.dev;
1988         struct drm_i915_private *dev_priv = dev->dev_private;
1989         enum port port = intel_dig_port->port;
1990         uint32_t val;
1991
1992         if (!HAS_DDI(dev))
1993                 return;
1994
1995         val = I915_READ(DP_TP_CTL(port));
1996         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1997         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1998         I915_WRITE(DP_TP_CTL(port), val);
1999
2000         /*
2001          * On PORT_A we can have only eDP in SST mode. There the only reason
2002          * we need to set idle transmission mode is to work around a HW issue
2003          * where we enable the pipe while not in idle link-training mode.
2004          * In this case there is requirement to wait for a minimum number of
2005          * idle patterns to be sent.
2006          */
2007         if (port == PORT_A)
2008                 return;
2009
2010         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2011                      1))
2012                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2013 }
2014
2015 /* Enable corresponding port and start training pattern 1 */
2016 void
2017 intel_dp_start_link_train(struct intel_dp *intel_dp)
2018 {
2019         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2020         struct drm_device *dev = encoder->dev;
2021         int i;
2022         uint8_t voltage;
2023         bool clock_recovery = false;
2024         int voltage_tries, loop_tries;
2025         uint32_t DP = intel_dp->DP;
2026
2027         if (HAS_DDI(dev))
2028                 intel_ddi_prepare_link_retrain(encoder);
2029
2030         /* Write the link configuration data */
2031         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2032                                   intel_dp->link_configuration,
2033                                   DP_LINK_CONFIGURATION_SIZE);
2034
2035         DP |= DP_PORT_EN;
2036
2037         memset(intel_dp->train_set, 0, 4);
2038         voltage = 0xff;
2039         voltage_tries = 0;
2040         loop_tries = 0;
2041         clock_recovery = false;
2042         for (;;) {
2043                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2044                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2045
2046                 intel_dp_set_signal_levels(intel_dp, &DP);
2047
2048                 /* Set training pattern 1 */
2049                 if (!intel_dp_set_link_train(intel_dp, DP,
2050                                              DP_TRAINING_PATTERN_1 |
2051                                              DP_LINK_SCRAMBLING_DISABLE))
2052                         break;
2053
2054                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2055                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2056                         DRM_ERROR("failed to get link status\n");
2057                         break;
2058                 }
2059
2060                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2061                         DRM_DEBUG_KMS("clock recovery OK\n");
2062                         clock_recovery = true;
2063                         break;
2064                 }
2065
2066                 /* Check to see if we've tried the max voltage */
2067                 for (i = 0; i < intel_dp->lane_count; i++)
2068                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2069                                 break;
2070                 if (i == intel_dp->lane_count) {
2071                         ++loop_tries;
2072                         if (loop_tries == 5) {
2073                                 DRM_DEBUG_KMS("too many full retries, give up\n");
2074                                 break;
2075                         }
2076                         memset(intel_dp->train_set, 0, 4);
2077                         voltage_tries = 0;
2078                         continue;
2079                 }
2080
2081                 /* Check to see if we've tried the same voltage 5 times */
2082                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2083                         ++voltage_tries;
2084                         if (voltage_tries == 5) {
2085                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2086                                 break;
2087                         }
2088                 } else
2089                         voltage_tries = 0;
2090                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2091
2092                 /* Compute new intel_dp->train_set as requested by target */
2093                 intel_get_adjust_train(intel_dp, link_status);
2094         }
2095
2096         intel_dp->DP = DP;
2097 }
2098
2099 void
2100 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2101 {
2102         bool channel_eq = false;
2103         int tries, cr_tries;
2104         uint32_t DP = intel_dp->DP;
2105
2106         /* channel equalization */
2107         tries = 0;
2108         cr_tries = 0;
2109         channel_eq = false;
2110         for (;;) {
2111                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2112
2113                 if (cr_tries > 5) {
2114                         DRM_ERROR("failed to train DP, aborting\n");
2115                         intel_dp_link_down(intel_dp);
2116                         break;
2117                 }
2118
2119                 intel_dp_set_signal_levels(intel_dp, &DP);
2120
2121                 /* channel eq pattern */
2122                 if (!intel_dp_set_link_train(intel_dp, DP,
2123                                              DP_TRAINING_PATTERN_2 |
2124                                              DP_LINK_SCRAMBLING_DISABLE))
2125                         break;
2126
2127                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2128                 if (!intel_dp_get_link_status(intel_dp, link_status))
2129                         break;
2130
2131                 /* Make sure clock is still ok */
2132                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2133                         intel_dp_start_link_train(intel_dp);
2134                         cr_tries++;
2135                         continue;
2136                 }
2137
2138                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2139                         channel_eq = true;
2140                         break;
2141                 }
2142
2143                 /* Try 5 times, then try clock recovery if that fails */
2144                 if (tries > 5) {
2145                         intel_dp_link_down(intel_dp);
2146                         intel_dp_start_link_train(intel_dp);
2147                         tries = 0;
2148                         cr_tries++;
2149                         continue;
2150                 }
2151
2152                 /* Compute new intel_dp->train_set as requested by target */
2153                 intel_get_adjust_train(intel_dp, link_status);
2154                 ++tries;
2155         }
2156
2157         intel_dp_set_idle_link_train(intel_dp);
2158
2159         intel_dp->DP = DP;
2160
2161         if (channel_eq)
2162                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2163
2164 }
2165
2166 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2167 {
2168         intel_dp_set_link_train(intel_dp, intel_dp->DP,
2169                                 DP_TRAINING_PATTERN_DISABLE);
2170 }
2171
2172 static void
2173 intel_dp_link_down(struct intel_dp *intel_dp)
2174 {
2175         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2176         enum port port = intel_dig_port->port;
2177         struct drm_device *dev = intel_dig_port->base.base.dev;
2178         struct drm_i915_private *dev_priv = dev->dev_private;
2179         struct intel_crtc *intel_crtc =
2180                 to_intel_crtc(intel_dig_port->base.base.crtc);
2181         uint32_t DP = intel_dp->DP;
2182
2183         /*
2184          * DDI code has a strict mode set sequence and we should try to respect
2185          * it, otherwise we might hang the machine in many different ways. So we
2186          * really should be disabling the port only on a complete crtc_disable
2187          * sequence. This function is just called under two conditions on DDI
2188          * code:
2189          * - Link train failed while doing crtc_enable, and on this case we
2190          *   really should respect the mode set sequence and wait for a
2191          *   crtc_disable.
2192          * - Someone turned the monitor off and intel_dp_check_link_status
2193          *   called us. We don't need to disable the whole port on this case, so
2194          *   when someone turns the monitor on again,
2195          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2196          *   train.
2197          */
2198         if (HAS_DDI(dev))
2199                 return;
2200
2201         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2202                 return;
2203
2204         DRM_DEBUG_KMS("\n");
2205
2206         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2207                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2208                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2209         } else {
2210                 DP &= ~DP_LINK_TRAIN_MASK;
2211                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2212         }
2213         POSTING_READ(intel_dp->output_reg);
2214
2215         /* We don't really know why we're doing this */
2216         intel_wait_for_vblank(dev, intel_crtc->pipe);
2217
2218         if (HAS_PCH_IBX(dev) &&
2219             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2220                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2221
2222                 /* Hardware workaround: leaving our transcoder select
2223                  * set to transcoder B while it's off will prevent the
2224                  * corresponding HDMI output on transcoder A.
2225                  *
2226                  * Combine this with another hardware workaround:
2227                  * transcoder select bit can only be cleared while the
2228                  * port is enabled.
2229                  */
2230                 DP &= ~DP_PIPEB_SELECT;
2231                 I915_WRITE(intel_dp->output_reg, DP);
2232
2233                 /* Changes to enable or select take place the vblank
2234                  * after being written.
2235                  */
2236                 if (WARN_ON(crtc == NULL)) {
2237                         /* We should never try to disable a port without a crtc
2238                          * attached. For paranoia keep the code around for a
2239                          * bit. */
2240                         POSTING_READ(intel_dp->output_reg);
2241                         msleep(50);
2242                 } else
2243                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2244         }
2245
2246         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2247         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2248         POSTING_READ(intel_dp->output_reg);
2249         msleep(intel_dp->panel_power_down_delay);
2250 }
2251
2252 static bool
2253 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2254 {
2255         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2256
2257         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2258                                            sizeof(intel_dp->dpcd)) == 0)
2259                 return false; /* aux transfer failed */
2260
2261         ksnprintf(dpcd_hex_dump,
2262                   sizeof(dpcd_hex_dump),
2263                   "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2264                   intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2265                   intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2266                   intel_dp->dpcd[6], intel_dp->dpcd[7]);
2267
2268         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2269
2270         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2271                 return false; /* DPCD not present */
2272
2273         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2274               DP_DWN_STRM_PORT_PRESENT))
2275                 return true; /* native DP sink */
2276
2277         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2278                 return true; /* no per-port downstream info */
2279
2280         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2281                                            intel_dp->downstream_ports,
2282                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2283                 return false; /* downstream port status fetch failed */
2284
2285         return true;
2286 }
2287
2288 static void
2289 intel_dp_probe_oui(struct intel_dp *intel_dp)
2290 {
2291         u8 buf[3];
2292
2293         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2294                 return;
2295
2296         ironlake_edp_panel_vdd_on(intel_dp);
2297
2298         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2299                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2300                               buf[0], buf[1], buf[2]);
2301
2302         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2303                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2304                               buf[0], buf[1], buf[2]);
2305
2306         ironlake_edp_panel_vdd_off(intel_dp, false);
2307 }
2308
2309 static bool
2310 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2311 {
2312         int ret;
2313
2314         ret = intel_dp_aux_native_read_retry(intel_dp,
2315                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2316                                              sink_irq_vector, 1);
2317         if (!ret)
2318                 return false;
2319
2320         return true;
2321 }
2322
2323 static void
2324 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2325 {
2326         /* NAK by default */
2327         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2328 }
2329
2330 /*
2331  * According to DP spec
2332  * 5.1.2:
2333  *  1. Read DPCD
2334  *  2. Configure link according to Receiver Capabilities
2335  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2336  *  4. Check link status on receipt of hot-plug interrupt
2337  */
2338
2339 void
2340 intel_dp_check_link_status(struct intel_dp *intel_dp)
2341 {
2342         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2343         u8 sink_irq_vector;
2344         u8 link_status[DP_LINK_STATUS_SIZE];
2345
2346         if (!intel_encoder->connectors_active)
2347                 return;
2348
2349         if (WARN_ON(!intel_encoder->base.crtc))
2350                 return;
2351
2352         /* Try to read receiver status if the link appears to be up */
2353         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2354                 intel_dp_link_down(intel_dp);
2355                 return;
2356         }
2357
2358         /* Now read the DPCD to see if it's actually running */
2359         if (!intel_dp_get_dpcd(intel_dp)) {
2360                 intel_dp_link_down(intel_dp);
2361                 return;
2362         }
2363
2364         /* Try to read the source of the interrupt */
2365         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2366             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2367                 /* Clear interrupt source */
2368                 intel_dp_aux_native_write_1(intel_dp,
2369                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2370                                             sink_irq_vector);
2371
2372                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2373                         intel_dp_handle_test_request(intel_dp);
2374                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2375                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2376         }
2377
2378         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2379                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2380                               drm_get_encoder_name(&intel_encoder->base));
2381                 intel_dp_start_link_train(intel_dp);
2382                 intel_dp_complete_link_train(intel_dp);
2383                 intel_dp_stop_link_train(intel_dp);
2384         }
2385 }
2386
2387 /* XXX this is probably wrong for multiple downstream ports */
2388 static enum drm_connector_status
2389 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2390 {
2391         uint8_t *dpcd = intel_dp->dpcd;
2392         bool hpd;
2393         uint8_t type;
2394
2395         if (!intel_dp_get_dpcd(intel_dp))
2396                 return connector_status_disconnected;
2397
2398         /* if there's no downstream port, we're done */
2399         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2400                 return connector_status_connected;
2401
2402         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2403         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2404         if (hpd) {
2405                 uint8_t reg;
2406                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2407                                                     &reg, 1))
2408                         return connector_status_unknown;
2409                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2410                                               : connector_status_disconnected;
2411         }
2412
2413         /* If no HPD, poke DDC gently */
2414         if (drm_probe_ddc(intel_dp->adapter))
2415                 return connector_status_connected;
2416
2417         /* Well we tried, say unknown for unreliable port types */
2418         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2419         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2420                 return connector_status_unknown;
2421
2422         /* Anything else is out of spec, warn and ignore */
2423         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2424         return connector_status_disconnected;
2425 }
2426
2427 static enum drm_connector_status
2428 ironlake_dp_detect(struct intel_dp *intel_dp)
2429 {
2430         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2433         enum drm_connector_status status;
2434
2435         /* Can't disconnect eDP, but you can close the lid... */
2436         if (is_edp(intel_dp)) {
2437                 status = intel_panel_detect(dev);
2438                 if (status == connector_status_unknown)
2439                         status = connector_status_connected;
2440                 return status;
2441         }
2442
2443         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2444                 return connector_status_disconnected;
2445
2446         return intel_dp_detect_dpcd(intel_dp);
2447 }
2448
2449 static enum drm_connector_status
2450 g4x_dp_detect(struct intel_dp *intel_dp)
2451 {
2452         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2455         uint32_t bit;
2456
2457         /* Can't disconnect eDP, but you can close the lid... */
2458         if (is_edp(intel_dp)) {
2459                 enum drm_connector_status status;
2460
2461                 status = intel_panel_detect(dev);
2462                 if (status == connector_status_unknown)
2463                         status = connector_status_connected;
2464                 return status;
2465         }
2466
2467         switch (intel_dig_port->port) {
2468         case PORT_B:
2469                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2470                 break;
2471         case PORT_C:
2472                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2473                 break;
2474         case PORT_D:
2475                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2476                 break;
2477         default:
2478                 return connector_status_unknown;
2479         }
2480
2481         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2482                 return connector_status_disconnected;
2483
2484         return intel_dp_detect_dpcd(intel_dp);
2485 }
2486
2487 static struct edid *
2488 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
2489 {
2490         struct intel_connector *intel_connector = to_intel_connector(connector);
2491
2492         /* use cached edid if we have one */
2493         if (intel_connector->edid) {
2494                 struct edid *edid;
2495                 int size;
2496
2497                 /* invalid edid */
2498                 if (IS_ERR(intel_connector->edid))
2499                         return NULL;
2500
2501                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2502                 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2503                 if (!edid)
2504                         return NULL;
2505
2506                 return edid;
2507         }
2508
2509         return drm_get_edid(connector, adapter);
2510 }
2511
2512 static int
2513 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
2514 {
2515         struct intel_connector *intel_connector = to_intel_connector(connector);
2516
2517         /* use cached edid if we have one */
2518         if (intel_connector->edid) {
2519                 /* invalid edid */
2520                 if (IS_ERR(intel_connector->edid))
2521                         return 0;
2522
2523                 return intel_connector_update_modes(connector,
2524                                                     intel_connector->edid);
2525         }
2526
2527         return intel_ddc_get_modes(connector, adapter);
2528 }
2529
2530 static enum drm_connector_status
2531 intel_dp_detect(struct drm_connector *connector, bool force)
2532 {
2533         struct intel_dp *intel_dp = intel_attached_dp(connector);
2534         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2535         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2536         struct drm_device *dev = connector->dev;
2537         enum drm_connector_status status;
2538         struct edid *edid = NULL;
2539
2540         intel_dp->has_audio = false;
2541
2542         if (HAS_PCH_SPLIT(dev))
2543                 status = ironlake_dp_detect(intel_dp);
2544         else
2545                 status = g4x_dp_detect(intel_dp);
2546
2547         if (status != connector_status_connected)
2548                 return status;
2549
2550         intel_dp_probe_oui(intel_dp);
2551
2552         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2553                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2554         } else {
2555                 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2556                 if (edid) {
2557                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2558                         kfree(edid);
2559                 }
2560         }
2561
2562         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2563                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2564         return connector_status_connected;
2565 }
2566
2567 static int intel_dp_get_modes(struct drm_connector *connector)
2568 {
2569         struct intel_dp *intel_dp = intel_attached_dp(connector);
2570         struct intel_connector *intel_connector = to_intel_connector(connector);
2571         struct drm_device *dev = connector->dev;
2572         int ret;
2573
2574         /* We should parse the EDID data and find out if it has an audio sink
2575          */
2576
2577         ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
2578         if (ret)
2579                 return ret;
2580
2581         /* if eDP has no EDID, fall back to fixed mode */
2582         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2583                 struct drm_display_mode *mode;
2584                 mode = drm_mode_duplicate(dev,
2585                                           intel_connector->panel.fixed_mode);
2586                 if (mode) {
2587                         drm_mode_probed_add(connector, mode);
2588                         return 1;
2589                 }
2590         }
2591         return 0;
2592 }
2593
2594 static bool
2595 intel_dp_detect_audio(struct drm_connector *connector)
2596 {
2597         struct intel_dp *intel_dp = intel_attached_dp(connector);
2598         struct edid *edid;
2599         bool has_audio = false;
2600
2601         edid = intel_dp_get_edid(connector, intel_dp->adapter);
2602         if (edid) {
2603                 has_audio = drm_detect_monitor_audio(edid);
2604                 kfree(edid);
2605         }
2606
2607         return has_audio;
2608 }
2609
2610 static int
2611 intel_dp_set_property(struct drm_connector *connector,
2612                       struct drm_property *property,
2613                       uint64_t val)
2614 {
2615         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2616         struct intel_connector *intel_connector = to_intel_connector(connector);
2617         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2618         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2619         int ret;
2620
2621         ret = drm_object_property_set_value(&connector->base, property, val);
2622         if (ret)
2623                 return ret;
2624
2625         if (property == dev_priv->force_audio_property) {
2626                 int i = val;
2627                 bool has_audio;
2628
2629                 if (i == intel_dp->force_audio)
2630                         return 0;
2631
2632                 intel_dp->force_audio = i;
2633
2634                 if (i == HDMI_AUDIO_AUTO)
2635                         has_audio = intel_dp_detect_audio(connector);
2636                 else
2637                         has_audio = (i == HDMI_AUDIO_ON);
2638
2639                 if (has_audio == intel_dp->has_audio)
2640                         return 0;
2641
2642                 intel_dp->has_audio = has_audio;
2643                 goto done;
2644         }
2645
2646         if (property == dev_priv->broadcast_rgb_property) {
2647                 bool old_auto = intel_dp->color_range_auto;
2648                 uint32_t old_range = intel_dp->color_range;
2649
2650                 switch (val) {
2651                 case INTEL_BROADCAST_RGB_AUTO:
2652                         intel_dp->color_range_auto = true;
2653                         break;
2654                 case INTEL_BROADCAST_RGB_FULL:
2655                         intel_dp->color_range_auto = false;
2656                         intel_dp->color_range = 0;
2657                         break;
2658                 case INTEL_BROADCAST_RGB_LIMITED:
2659                         intel_dp->color_range_auto = false;
2660                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2661                         break;
2662                 default:
2663                         return -EINVAL;
2664                 }
2665
2666                 if (old_auto == intel_dp->color_range_auto &&
2667                     old_range == intel_dp->color_range)
2668                         return 0;
2669
2670                 goto done;
2671         }
2672
2673         if (is_edp(intel_dp) &&
2674             property == connector->dev->mode_config.scaling_mode_property) {
2675                 if (val == DRM_MODE_SCALE_NONE) {
2676                         DRM_DEBUG_KMS("no scaling not supported\n");
2677                         return -EINVAL;
2678                 }
2679
2680                 if (intel_connector->panel.fitting_mode == val) {
2681                         /* the eDP scaling property is not changed */
2682                         return 0;
2683                 }
2684                 intel_connector->panel.fitting_mode = val;
2685
2686                 goto done;
2687         }
2688
2689         return -EINVAL;
2690
2691 done:
2692         if (intel_encoder->base.crtc)
2693                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2694
2695         return 0;
2696 }
2697
2698 static void
2699 intel_dp_connector_destroy(struct drm_connector *connector)
2700 {
2701         struct intel_connector *intel_connector = to_intel_connector(connector);
2702
2703         if (!IS_ERR_OR_NULL(intel_connector->edid))
2704                 kfree(intel_connector->edid);
2705
2706         /* Can't call is_edp() since the encoder may have been destroyed
2707          * already. */
2708         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2709                 intel_panel_fini(&intel_connector->panel);
2710
2711         drm_sysfs_connector_remove(connector);
2712         drm_connector_cleanup(connector);
2713         kfree(connector);
2714 }
2715
2716 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2717 {
2718         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2719         struct intel_dp *intel_dp = &intel_dig_port->dp;
2720         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2721
2722         if (intel_dp->dp_iic_bus != NULL) {
2723                 if (intel_dp->adapter != NULL) {
2724                         device_delete_child(intel_dp->dp_iic_bus,
2725                         intel_dp->adapter);
2726                 }
2727                 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
2728         }
2729         drm_encoder_cleanup(encoder);
2730         if (is_edp(intel_dp)) {
2731                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2732                 mutex_lock(&dev->mode_config.mutex);
2733                 ironlake_panel_vdd_off_sync(intel_dp);
2734                 mutex_unlock(&dev->mode_config.mutex);
2735         }
2736         kfree(intel_dig_port);
2737 }
2738
2739 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2740         .mode_set = intel_dp_mode_set,
2741 };
2742
2743 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2744         .dpms = intel_connector_dpms,
2745         .detect = intel_dp_detect,
2746         .fill_modes = drm_helper_probe_single_connector_modes,
2747         .set_property = intel_dp_set_property,
2748         .destroy = intel_dp_connector_destroy,
2749 };
2750
2751 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2752         .get_modes = intel_dp_get_modes,
2753         .mode_valid = intel_dp_mode_valid,
2754         .best_encoder = intel_best_encoder,
2755 };
2756
2757 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2758         .destroy = intel_dp_encoder_destroy,
2759 };
2760
2761 static void
2762 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2763 {
2764         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2765
2766         intel_dp_check_link_status(intel_dp);
2767 }
2768
2769 /* Return which DP Port should be selected for Transcoder DP control */
2770 int
2771 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2772 {
2773         struct drm_device *dev = crtc->dev;
2774         struct intel_encoder *intel_encoder;
2775         struct intel_dp *intel_dp;
2776
2777         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2778                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2779
2780                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2781                     intel_encoder->type == INTEL_OUTPUT_EDP)
2782                         return intel_dp->output_reg;
2783         }
2784
2785         return -1;
2786 }
2787
2788 /* check the VBT to see whether the eDP is on DP-D port */
2789 bool intel_dpd_is_edp(struct drm_device *dev)
2790 {
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         struct child_device_config *p_child;
2793         int i;
2794
2795         if (!dev_priv->vbt.child_dev_num)
2796                 return false;
2797
2798         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2799                 p_child = dev_priv->vbt.child_dev + i;
2800
2801                 if (p_child->dvo_port == PORT_IDPD &&
2802                     p_child->device_type == DEVICE_TYPE_eDP)
2803                         return true;
2804         }
2805         return false;
2806 }
2807
2808 static void
2809 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2810 {
2811         struct intel_connector *intel_connector = to_intel_connector(connector);
2812
2813         intel_attach_force_audio_property(connector);
2814         intel_attach_broadcast_rgb_property(connector);
2815         intel_dp->color_range_auto = true;
2816
2817         if (is_edp(intel_dp)) {
2818                 drm_mode_create_scaling_mode_property(connector->dev);
2819                 drm_object_attach_property(
2820                         &connector->base,
2821                         connector->dev->mode_config.scaling_mode_property,
2822                         DRM_MODE_SCALE_ASPECT);
2823                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2824         }
2825 }
2826
2827 static void
2828 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2829                                     struct intel_dp *intel_dp,
2830                                     struct edp_power_seq *out)
2831 {
2832         struct drm_i915_private *dev_priv = dev->dev_private;
2833         struct edp_power_seq cur, vbt, spec, final;
2834         u32 pp_on, pp_off, pp_div, pp;
2835         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2836
2837         if (HAS_PCH_SPLIT(dev)) {
2838                 pp_control_reg = PCH_PP_CONTROL;
2839                 pp_on_reg = PCH_PP_ON_DELAYS;
2840                 pp_off_reg = PCH_PP_OFF_DELAYS;
2841                 pp_div_reg = PCH_PP_DIVISOR;
2842         } else {
2843                 pp_control_reg = PIPEA_PP_CONTROL;
2844                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2845                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2846                 pp_div_reg = PIPEA_PP_DIVISOR;
2847         }
2848
2849         /* Workaround: Need to write PP_CONTROL with the unlock key as
2850          * the very first thing. */
2851         pp = ironlake_get_pp_control(intel_dp);
2852         I915_WRITE(pp_control_reg, pp);
2853
2854         pp_on = I915_READ(pp_on_reg);
2855         pp_off = I915_READ(pp_off_reg);
2856         pp_div = I915_READ(pp_div_reg);
2857
2858         /* Pull timing values out of registers */
2859         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2860                 PANEL_POWER_UP_DELAY_SHIFT;
2861
2862         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2863                 PANEL_LIGHT_ON_DELAY_SHIFT;
2864
2865         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2866                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2867
2868         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2869                 PANEL_POWER_DOWN_DELAY_SHIFT;
2870
2871         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2872                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2873
2874         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2875                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2876
2877         vbt = dev_priv->vbt.edp_pps;
2878
2879         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2880          * our hw here, which are all in 100usec. */
2881         spec.t1_t3 = 210 * 10;
2882         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2883         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2884         spec.t10 = 500 * 10;
2885         /* This one is special and actually in units of 100ms, but zero
2886          * based in the hw (so we need to add 100 ms). But the sw vbt
2887          * table multiplies it with 1000 to make it in units of 100usec,
2888          * too. */
2889         spec.t11_t12 = (510 + 100) * 10;
2890
2891         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2892                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2893
2894         /* Use the max of the register settings and vbt. If both are
2895          * unset, fall back to the spec limits. */
2896 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2897                                        spec.field : \
2898                                        max(cur.field, vbt.field))
2899         assign_final(t1_t3);
2900         assign_final(t8);
2901         assign_final(t9);
2902         assign_final(t10);
2903         assign_final(t11_t12);
2904 #undef assign_final
2905
2906 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2907         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2908         intel_dp->backlight_on_delay = get_delay(t8);
2909         intel_dp->backlight_off_delay = get_delay(t9);
2910         intel_dp->panel_power_down_delay = get_delay(t10);
2911         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2912 #undef get_delay
2913
2914         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2915                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2916                       intel_dp->panel_power_cycle_delay);
2917
2918         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2919                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2920
2921         if (out)
2922                 *out = final;
2923 }
2924
2925 static void
2926 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2927                                               struct intel_dp *intel_dp,
2928                                               struct edp_power_seq *seq)
2929 {
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931         u32 pp_on, pp_off, pp_div, port_sel = 0;
2932         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2933         int pp_on_reg, pp_off_reg, pp_div_reg;
2934
2935         if (HAS_PCH_SPLIT(dev)) {
2936                 pp_on_reg = PCH_PP_ON_DELAYS;
2937                 pp_off_reg = PCH_PP_OFF_DELAYS;
2938                 pp_div_reg = PCH_PP_DIVISOR;
2939         } else {
2940                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2941                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2942                 pp_div_reg = PIPEA_PP_DIVISOR;
2943         }
2944
2945         /* And finally store the new values in the power sequencer. */
2946         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2947                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2948         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2949                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2950         /* Compute the divisor for the pp clock, simply match the Bspec
2951          * formula. */
2952         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2953         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2954                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2955
2956         /* Haswell doesn't have any port selection bits for the panel
2957          * power sequencer any more. */
2958         if (IS_VALLEYVIEW(dev)) {
2959                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2960         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2961                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2962                         port_sel = PANEL_POWER_PORT_DP_A;
2963                 else
2964                         port_sel = PANEL_POWER_PORT_DP_D;
2965         }
2966
2967         pp_on |= port_sel;
2968
2969         I915_WRITE(pp_on_reg, pp_on);
2970         I915_WRITE(pp_off_reg, pp_off);
2971         I915_WRITE(pp_div_reg, pp_div);
2972
2973         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2974                       I915_READ(pp_on_reg),
2975                       I915_READ(pp_off_reg),
2976                       I915_READ(pp_div_reg));
2977 }
2978
2979 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
2980                                      struct intel_connector *intel_connector)
2981 {
2982         struct drm_connector *connector = &intel_connector->base;
2983         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2984         struct drm_device *dev = intel_dig_port->base.base.dev;
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986         struct drm_display_mode *fixed_mode = NULL;
2987         struct edp_power_seq power_seq = { 0 };
2988         bool has_dpcd;
2989         struct drm_display_mode *scan;
2990         struct edid *edid;
2991
2992         if (!is_edp(intel_dp))
2993                 return true;
2994
2995         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2996
2997         /* Cache DPCD and EDID for edp. */
2998         ironlake_edp_panel_vdd_on(intel_dp);
2999         has_dpcd = intel_dp_get_dpcd(intel_dp);
3000         ironlake_edp_panel_vdd_off(intel_dp, false);
3001
3002         if (has_dpcd) {
3003                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3004                         dev_priv->no_aux_handshake =
3005                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3006                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3007         } else {
3008                 /* if this fails, presume the device is a ghost */
3009                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3010                 return false;
3011         }
3012
3013         /* We now know it's not a ghost, init power sequence regs. */
3014         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3015                                                       &power_seq);
3016
3017         ironlake_edp_panel_vdd_on(intel_dp);
3018         edid = drm_get_edid(connector, intel_dp->adapter);
3019         if (edid) {
3020                 if (drm_add_edid_modes(connector, edid)) {
3021                         drm_mode_connector_update_edid_property(connector,
3022                                                                 edid);
3023                         drm_edid_to_eld(connector, edid);
3024                 } else {
3025                         kfree(edid);
3026                         edid = ERR_PTR(-EINVAL);
3027                 }
3028         } else {
3029                 edid = ERR_PTR(-ENOENT);
3030         }
3031         intel_connector->edid = edid;
3032
3033         /* prefer fixed mode from EDID if available */
3034         list_for_each_entry(scan, &connector->probed_modes, head) {
3035                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3036                         fixed_mode = drm_mode_duplicate(dev, scan);
3037                         break;
3038                 }
3039         }
3040
3041         /* fallback to VBT if available for eDP */
3042         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3043                 fixed_mode = drm_mode_duplicate(dev,
3044                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3045                 if (fixed_mode)
3046                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3047         }
3048
3049         ironlake_edp_panel_vdd_off(intel_dp, false);
3050
3051         intel_panel_init(&intel_connector->panel, fixed_mode);
3052         intel_panel_setup_backlight(connector);
3053
3054         return true;
3055 }
3056
3057 bool
3058 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3059                         struct intel_connector *intel_connector)
3060 {
3061         struct drm_connector *connector = &intel_connector->base;
3062         struct intel_dp *intel_dp = &intel_dig_port->dp;
3063         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3064         struct drm_device *dev = intel_encoder->base.dev;
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         enum port port = intel_dig_port->port;
3067         const char *name = NULL;
3068         int type, error;
3069
3070         /* Preserve the current hw state. */
3071         intel_dp->DP = I915_READ(intel_dp->output_reg);
3072         intel_dp->attached_connector = intel_connector;
3073
3074         type = DRM_MODE_CONNECTOR_DisplayPort;
3075         /*
3076          * FIXME : We need to initialize built-in panels before external panels.
3077          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3078          */
3079         switch (port) {
3080         case PORT_A:
3081                 type = DRM_MODE_CONNECTOR_eDP;
3082                 break;
3083         case PORT_C:
3084                 if (IS_VALLEYVIEW(dev))
3085                         type = DRM_MODE_CONNECTOR_eDP;
3086                 break;
3087         case PORT_D:
3088                 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3089                         type = DRM_MODE_CONNECTOR_eDP;
3090                 break;
3091         default:        /* silence GCC warning */
3092                 break;
3093         }
3094
3095         /*
3096          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3097          * for DP the encoder type can be set by the caller to
3098          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3099          */
3100         if (type == DRM_MODE_CONNECTOR_eDP)
3101                 intel_encoder->type = INTEL_OUTPUT_EDP;
3102
3103         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3104                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3105                         port_name(port));
3106
3107         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3108         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3109
3110         connector->interlace_allowed = true;
3111         connector->doublescan_allowed = 0;
3112
3113         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3114                           ironlake_panel_vdd_work);
3115
3116         intel_connector_attach_encoder(intel_connector, intel_encoder);
3117         drm_sysfs_connector_add(connector);
3118
3119         if (HAS_DDI(dev))
3120                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3121         else
3122                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3123
3124         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3125         if (HAS_DDI(dev)) {
3126                 switch (intel_dig_port->port) {
3127                 case PORT_A:
3128                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3129                         break;
3130                 case PORT_B:
3131                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3132                         break;
3133                 case PORT_C:
3134                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3135                         break;
3136                 case PORT_D:
3137                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3138                         break;
3139                 default:
3140                         BUG();
3141                 }
3142         }
3143
3144         /* Set up the DDC bus. */
3145         switch (port) {
3146         case PORT_A:
3147                 intel_encoder->hpd_pin = HPD_PORT_A;
3148                 name = "DPDDC-A";
3149                 break;
3150         case PORT_B:
3151                 intel_encoder->hpd_pin = HPD_PORT_B;
3152                 name = "DPDDC-B";
3153                 break;
3154         case PORT_C:
3155                 intel_encoder->hpd_pin = HPD_PORT_C;
3156                 name = "DPDDC-C";
3157                 break;
3158         case PORT_D:
3159                 intel_encoder->hpd_pin = HPD_PORT_D;
3160                 name = "DPDDC-D";
3161                 break;
3162         default:
3163                 BUG();
3164         }
3165
3166         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3167         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3168              error, port_name(port));
3169
3170         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3171 #if 0
3172                 i2c_del_adapter(&intel_dp->adapter);
3173 #endif
3174                 if (is_edp(intel_dp)) {
3175                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3176                         mutex_lock(&dev->mode_config.mutex);
3177                         ironlake_panel_vdd_off_sync(intel_dp);
3178                         mutex_unlock(&dev->mode_config.mutex);
3179                 }
3180                 drm_sysfs_connector_remove(connector);
3181                 drm_connector_cleanup(connector);
3182                 return false;
3183         }
3184
3185         intel_dp_add_properties(intel_dp, connector);
3186
3187         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3188          * 0xd.  Failure to do so will result in spurious interrupts being
3189          * generated on the port when a cable is not attached.
3190          */
3191         if (IS_G4X(dev) && !IS_GM45(dev)) {
3192                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3193                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3194         }
3195
3196         return true;
3197 }
3198
3199 void
3200 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3201 {
3202         struct intel_digital_port *intel_dig_port;
3203         struct intel_encoder *intel_encoder;
3204         struct drm_encoder *encoder;
3205         struct intel_connector *intel_connector;
3206
3207         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3208         if (!intel_dig_port)
3209                 return;
3210
3211         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3212         if (!intel_connector) {
3213                 kfree(intel_dig_port);
3214                 return;
3215         }
3216
3217         intel_encoder = &intel_dig_port->base;
3218         encoder = &intel_encoder->base;
3219
3220         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3221                          DRM_MODE_ENCODER_TMDS);
3222         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3223
3224         intel_encoder->compute_config = intel_dp_compute_config;
3225         intel_encoder->enable = intel_enable_dp;
3226         intel_encoder->pre_enable = intel_pre_enable_dp;
3227         intel_encoder->disable = intel_disable_dp;
3228         intel_encoder->post_disable = intel_post_disable_dp;
3229         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3230         intel_encoder->get_config = intel_dp_get_config;
3231         if (IS_VALLEYVIEW(dev))
3232                 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3233
3234         intel_dig_port->port = port;
3235         intel_dig_port->dp.output_reg = output_reg;
3236
3237         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3238         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3239         intel_encoder->cloneable = false;
3240         intel_encoder->hot_plug = intel_dp_hot_plug;
3241
3242         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3243                 drm_encoder_cleanup(encoder);
3244                 kfree(intel_dig_port);
3245                 kfree(intel_connector);
3246         }
3247 }