sys/dev/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/consumer.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 static const struct {
  40         u16 panel_id;
  41         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  42 } intel_dsi_drivers[] = {
  43         {
  44                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  45                 .init = vbt_panel_init,
  46         },
  47 };
  48
  49 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  50 {
  51         struct drm_encoder *encoder = &intel_dsi->base.base;
  52         struct drm_device *dev = encoder->dev;
  53         struct drm_i915_private *dev_priv = dev->dev_private;
  54         u32 mask;
  55
  56         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  57                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  58
  59         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
  60                 DRM_ERROR("DPI FIFOs are not empty\n");
  61 }
  62
  63 static void write_data(struct drm_i915_private *dev_priv, u32 reg,
  64                        const u8 *data, u32 len)
  65 {
  66         u32 i, j;
  67
  68         for (i = 0; i < len; i += 4) {
  69                 u32 val = 0;
  70
  71                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  72                         val |= *data++ << 8 * j;
  73
  74                 I915_WRITE(reg, val);
  75         }
  76 }
  77
  78 static void read_data(struct drm_i915_private *dev_priv, u32 reg,
  79                       u8 *data, u32 len)
  80 {
  81         u32 i, j;
  82
  83         for (i = 0; i < len; i += 4) {
  84                 u32 val = I915_READ(reg);
  85
  86                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  87                         *data++ = val >> 8 * j;
  88         }
  89 }
  90
  91 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
  92                                        const struct mipi_dsi_msg *msg)
  93 {
  94         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
  95         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
  96         struct drm_i915_private *dev_priv = dev->dev_private;
  97         enum port port = intel_dsi_host->port;
  98         struct mipi_dsi_packet packet;
  99         ssize_t ret;
 100         const u8 *header, *data;
 101         u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
 102
 103         ret = mipi_dsi_create_packet(&packet, msg);
 104         if (ret < 0)
 105                 return ret;
 106
 107         header = packet.header;
 108         data = packet.payload;
 109
 110         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 111                 data_reg = MIPI_LP_GEN_DATA(port);
 112                 data_mask = LP_DATA_FIFO_FULL;
 113                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 114                 ctrl_mask = LP_CTRL_FIFO_FULL;
 115         } else {
 116                 data_reg = MIPI_HS_GEN_DATA(port);
 117                 data_mask = HS_DATA_FIFO_FULL;
 118                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 119                 ctrl_mask = HS_CTRL_FIFO_FULL;
 120         }
 121
 122         /* note: this is never true for reads */
 123         if (packet.payload_length) {
 124
 125                 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
 126                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 127
 128                 write_data(dev_priv, data_reg, packet.payload,
 129                            packet.payload_length);
 130         }
 131
 132         if (msg->rx_len) {
 133                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 134         }
 135
 136         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
 137                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 138         }
 139
 140         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 141
 142         /* ->rx_len is set only for reads */
 143         if (msg->rx_len) {
 144                 data_mask = GEN_READ_DATA_AVAIL;
 145                 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
 146                         DRM_ERROR("Timeout waiting for read data.\n");
 147
 148                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 149         }
 150
 151         /* XXX: fix for reads and writes */
 152         return 4 + packet.payload_length;
 153 }
 154
 155 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 156                                  struct mipi_dsi_device *dsi)
 157 {
 158         return 0;
 159 }
 160
 161 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 162                                  struct mipi_dsi_device *dsi)
 163 {
 164         return 0;
 165 }
 166
 167 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 168         .attach = intel_dsi_host_attach,
 169         .detach = intel_dsi_host_detach,
 170         .transfer = intel_dsi_host_transfer,
 171 };
 172
 173 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 174                                                   enum port port)
 175 {
 176         struct intel_dsi_host *host;
 177         struct mipi_dsi_device *device;
 178
 179         host = kzalloc(sizeof(*host), GFP_KERNEL);
 180         if (!host)
 181                 return NULL;
 182
 183         host->base.ops = &intel_dsi_host_ops;
 184         host->intel_dsi = intel_dsi;
 185         host->port = port;
 186
 187         /*
 188          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 189          * have a host->dev, and we don't have OF stuff either. So just use the
 190          * dsi framework as a library and hope for the best. Create the dsi
 191          * devices by ourselves here too. Need to be careful though, because we
 192          * don't initialize any of the driver model devices here.
 193          */
 194         device = kzalloc(sizeof(*device), GFP_KERNEL);
 195         if (!device) {
 196                 kfree(host);
 197                 return NULL;
 198         }
 199
 200         device->host = &host->base;
 201         host->device = device;
 202
 203         return host;
 204 }
 205
 206 /*
 207  * send a video mode command
 208  *
 209  * XXX: commands with data in MIPI_DPI_DATA?
 210  */
 211 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 212                         enum port port)
 213 {
 214         struct drm_encoder *encoder = &intel_dsi->base.base;
 215         struct drm_device *dev = encoder->dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         u32 mask;
 218
 219         /* XXX: pipe, hs */
 220         if (hs)
 221                 cmd &= ~DPI_LP_MODE;
 222         else
 223                 cmd |= DPI_LP_MODE;
 224
 225         /* clear bit */
 226         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 227
 228         /* XXX: old code skips write if control unchanged */
 229         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 230                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 231
 232         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 233
 234         mask = SPL_PKT_SENT_INTERRUPT;
 235         if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
 236                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 237
 238         return 0;
 239 }
 240
 241 static void band_gap_reset(struct drm_i915_private *dev_priv)
 242 {
 243         mutex_lock(&dev_priv->sb_lock);
 244
 245         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 246         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 247         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 248         udelay(150);
 249         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 250         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 251
 252         mutex_unlock(&dev_priv->sb_lock);
 253 }
 254
 255 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 256 {
 257         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 258 }
 259
 260 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 261 {
 262         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 263 }
 264
 265 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 266                                      struct intel_crtc_state *config)
 267 {
 268         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 269                                                    base);
 270         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 271         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 272         struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
 273
 274         DRM_DEBUG_KMS("\n");
 275
 276         if (fixed_mode)
 277                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 278
 279         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 280         adjusted_mode->flags = 0;
 281
 282         return true;
 283 }
 284
 285 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 286 {
 287         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 288         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 289         enum port port;
 290         u32 val;
 291
 292         DRM_DEBUG_KMS("\n");
 293
 294         /* Exit Low power state in 4 steps*/
 295         for_each_dsi_port(port, intel_dsi->ports) {
 296
 297                 /* 1. Enable MIPI PHY transparent latch */
 298                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 299                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 300                 usleep_range(2000, 2500);
 301
 302                 /* 2. Enter ULPS */
 303                 val = I915_READ(MIPI_DEVICE_READY(port));
 304                 val &= ~ULPS_STATE_MASK;
 305                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 306                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 307                 usleep_range(2, 3);
 308
 309                 /* 3. Exit ULPS */
 310                 val = I915_READ(MIPI_DEVICE_READY(port));
 311                 val &= ~ULPS_STATE_MASK;
 312                 val |= (ULPS_STATE_EXIT | DEVICE_READY);
 313                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 314                 usleep_range(1000, 1500);
 315
 316                 /* Clear ULPS and set device ready */
 317                 val = I915_READ(MIPI_DEVICE_READY(port));
 318                 val &= ~ULPS_STATE_MASK;
 319                 val |= DEVICE_READY;
 320                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 321         }
 322 }
 323
 324 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 325 {
 326         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 327         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 328         enum port port;
 329         u32 val;
 330
 331         DRM_DEBUG_KMS("\n");
 332
 333         mutex_lock(&dev_priv->sb_lock);
 334         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 335          * needed everytime after power gate */
 336         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 337         mutex_unlock(&dev_priv->sb_lock);
 338
 339         /* bandgap reset is needed after everytime we do power gate */
 340         band_gap_reset(dev_priv);
 341
 342         for_each_dsi_port(port, intel_dsi->ports) {
 343
 344                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 345                 usleep_range(2500, 3000);
 346
 347                 /* Enable MIPI PHY transparent latch
 348                  * Common bit for both MIPI Port A & MIPI Port C
 349                  * No similar bit in MIPI Port C reg
 350                  */
 351                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 352                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 353                 usleep_range(1000, 1500);
 354
 355                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 356                 usleep_range(2500, 3000);
 357
 358                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 359                 usleep_range(2500, 3000);
 360         }
 361 }
 362
 363 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 364 {
 365         struct drm_device *dev = encoder->base.dev;
 366
 367         if (IS_VALLEYVIEW(dev))
 368                 vlv_dsi_device_ready(encoder);
 369         else if (IS_BROXTON(dev))
 370                 bxt_dsi_device_ready(encoder);
 371 }
 372
 373 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 374 {
 375         struct drm_device *dev = encoder->base.dev;
 376         struct drm_i915_private *dev_priv = dev->dev_private;
 377         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 378         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 379         enum port port;
 380         u32 temp;
 381         u32 port_ctrl;
 382
 383         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 384                 temp = I915_READ(VLV_CHICKEN_3);
 385                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 386                                         intel_dsi->pixel_overlap <<
 387                                         PIXEL_OVERLAP_CNT_SHIFT;
 388                 I915_WRITE(VLV_CHICKEN_3, temp);
 389         }
 390
 391         for_each_dsi_port(port, intel_dsi->ports) {
 392                 port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
 393                                                 MIPI_PORT_CTRL(port);
 394
 395                 temp = I915_READ(port_ctrl);
 396
 397                 temp &= ~LANE_CONFIGURATION_MASK;
 398                 temp &= ~DUAL_LINK_MODE_MASK;
 399
 400                 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
 401                         temp |= (intel_dsi->dual_link - 1)
 402                                                 << DUAL_LINK_MODE_SHIFT;
 403                         temp |= intel_crtc->pipe ?
 404                                         LANE_CONFIGURATION_DUAL_LINK_B :
 405                                         LANE_CONFIGURATION_DUAL_LINK_A;
 406                 }
 407                 /* assert ip_tg_enable signal */
 408                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 409                 POSTING_READ(port_ctrl);
 410         }
 411 }
 412
 413 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 414 {
 415         struct drm_device *dev = encoder->base.dev;
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 418         enum port port;
 419         u32 temp;
 420         u32 port_ctrl;
 421
 422         for_each_dsi_port(port, intel_dsi->ports) {
 423                 /* de-assert ip_tg_enable signal */
 424                 port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
 425                                                 MIPI_PORT_CTRL(port);
 426                 temp = I915_READ(port_ctrl);
 427                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 428                 POSTING_READ(port_ctrl);
 429         }
 430 }
 431
 432 static void intel_dsi_enable(struct intel_encoder *encoder)
 433 {
 434         struct drm_device *dev = encoder->base.dev;
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 437         enum port port;
 438
 439         DRM_DEBUG_KMS("\n");
 440
 441         if (is_cmd_mode(intel_dsi)) {
 442                 for_each_dsi_port(port, intel_dsi->ports)
 443                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 444         } else {
 445                 msleep(20); /* XXX */
 446                 for_each_dsi_port(port, intel_dsi->ports)
 447                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 448                 msleep(100);
 449
 450                 drm_panel_enable(intel_dsi->panel);
 451
 452                 for_each_dsi_port(port, intel_dsi->ports)
 453                         wait_for_dsi_fifo_empty(intel_dsi, port);
 454
 455                 intel_dsi_port_enable(encoder);
 456         }
 457
 458         intel_panel_enable_backlight(intel_dsi->attached_connector);
 459 }
 460
 461 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 462 {
 463         struct drm_device *dev = encoder->base.dev;
 464         struct drm_i915_private *dev_priv = dev->dev_private;
 465         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 466         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 467         enum i915_pipe pipe = intel_crtc->pipe;
 468         enum port port;
 469         u32 tmp;
 470
 471         DRM_DEBUG_KMS("\n");
 472
 473         /* Panel Enable over CRC PMIC */
 474         if (intel_dsi->gpio_panel)
 475                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 476
 477         msleep(intel_dsi->panel_on_delay);
 478
 479         if (IS_VALLEYVIEW(dev)) {
 480                 /*
 481                  * Disable DPOunit clock gating, can stall pipe
 482                  * and we need DPLL REFA always enabled
 483                  */
 484                 tmp = I915_READ(DPLL(pipe));
 485                 tmp |= DPLL_REF_CLK_ENABLE_VLV;
 486                 I915_WRITE(DPLL(pipe), tmp);
 487
 488                 /* update the hw state for DPLL */
 489                 intel_crtc->config->dpll_hw_state.dpll =
 490                                 DPLL_INTEGRATED_REF_CLK_VLV |
 491                                         DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 492
 493                 tmp = I915_READ(DSPCLK_GATE_D);
 494                 tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 495                 I915_WRITE(DSPCLK_GATE_D, tmp);
 496         }
 497
 498         /* put device in ready state */
 499         intel_dsi_device_ready(encoder);
 500
 501         drm_panel_prepare(intel_dsi->panel);
 502
 503         for_each_dsi_port(port, intel_dsi->ports)
 504                 wait_for_dsi_fifo_empty(intel_dsi, port);
 505
 506         /* Enable port in pre-enable phase itself because as per hw team
 507          * recommendation, port should be enabled befor plane & pipe */
 508         intel_dsi_enable(encoder);
 509 }
 510
 511 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 512 {
 513         DRM_DEBUG_KMS("\n");
 514
 515         /* for DSI port enable has to be done before pipe
 516          * and plane enable, so port enable is done in
 517          * pre_enable phase itself unlike other encoders
 518          */
 519 }
 520
 521 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 522 {
 523         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 524         enum port port;
 525
 526         DRM_DEBUG_KMS("\n");
 527
 528         intel_panel_disable_backlight(intel_dsi->attached_connector);
 529
 530         if (is_vid_mode(intel_dsi)) {
 531                 /* Send Shutdown command to the panel in LP mode */
 532                 for_each_dsi_port(port, intel_dsi->ports)
 533                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 534                 msleep(10);
 535         }
 536 }
 537
 538 static void intel_dsi_disable(struct intel_encoder *encoder)
 539 {
 540         struct drm_device *dev = encoder->base.dev;
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 543         enum port port;
 544         u32 temp;
 545
 546         DRM_DEBUG_KMS("\n");
 547
 548         if (is_vid_mode(intel_dsi)) {
 549                 for_each_dsi_port(port, intel_dsi->ports)
 550                         wait_for_dsi_fifo_empty(intel_dsi, port);
 551
 552                 intel_dsi_port_disable(encoder);
 553                 msleep(2);
 554         }
 555
 556         for_each_dsi_port(port, intel_dsi->ports) {
 557                 /* Panel commands can be sent when clock is in LP11 */
 558                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 559
 560                 intel_dsi_reset_clocks(encoder, port);
 561                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 562
 563                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 564                 temp &= ~VID_MODE_FORMAT_MASK;
 565                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 566
 567                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 568         }
 569         /* if disable packets are sent before sending shutdown packet then in
 570          * some next enable sequence send turn on packet error is observed */
 571         drm_panel_disable(intel_dsi->panel);
 572
 573         for_each_dsi_port(port, intel_dsi->ports)
 574                 wait_for_dsi_fifo_empty(intel_dsi, port);
 575 }
 576
 577 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 578 {
 579         struct drm_device *dev = encoder->base.dev;
 580         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 581         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 582         enum port port;
 583         u32 val;
 584         u32 port_ctrl = 0;
 585
 586         DRM_DEBUG_KMS("\n");
 587         for_each_dsi_port(port, intel_dsi->ports) {
 588
 589                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 590                                                         ULPS_STATE_ENTER);
 591                 usleep_range(2000, 2500);
 592
 593                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 594                                                         ULPS_STATE_EXIT);
 595                 usleep_range(2000, 2500);
 596
 597                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 598                                                         ULPS_STATE_ENTER);
 599                 usleep_range(2000, 2500);
 600
 601                 if (IS_BROXTON(dev))
 602                         port_ctrl = BXT_MIPI_PORT_CTRL(port);
 603                 else if (IS_VALLEYVIEW(dev))
 604                         /* Common bit for both MIPI Port A & MIPI Port C */
 605                         port_ctrl = MIPI_PORT_CTRL(PORT_A);
 606
 607                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 608                  * only. MIPI Port C has no similar bit for checking
 609                  */
 610                 if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
 611                                                 == 0x00000), 30))
 612                         DRM_ERROR("DSI LP not going Low\n");
 613
 614                 /* Disable MIPI PHY transparent latch */
 615                 val = I915_READ(port_ctrl);
 616                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 617                 usleep_range(1000, 1500);
 618
 619                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 620                 usleep_range(2000, 2500);
 621         }
 622
 623         intel_disable_dsi_pll(encoder);
 624 }
 625
 626 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 627 {
 628         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 629         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 630         u32 val;
 631
 632         DRM_DEBUG_KMS("\n");
 633
 634         intel_dsi_disable(encoder);
 635
 636         intel_dsi_clear_device_ready(encoder);
 637
 638         val = I915_READ(DSPCLK_GATE_D);
 639         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 640         I915_WRITE(DSPCLK_GATE_D, val);
 641
 642         drm_panel_unprepare(intel_dsi->panel);
 643
 644         msleep(intel_dsi->panel_off_delay);
 645         msleep(intel_dsi->panel_pwr_cycle_delay);
 646
 647         /* Panel Disable over CRC PMIC */
 648         if (intel_dsi->gpio_panel)
 649                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 650 }
 651
 652 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 653                                    enum i915_pipe *pipe)
 654 {
 655         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 656         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 657         struct drm_device *dev = encoder->base.dev;
 658         enum intel_display_power_domain power_domain;
 659         u32 dpi_enabled, func, ctrl_reg;
 660         enum port port;
 661
 662         DRM_DEBUG_KMS("\n");
 663
 664         power_domain = intel_display_port_power_domain(encoder);
 665         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 666                 return false;
 667
 668         /* XXX: this only works for one DSI output */
 669         for_each_dsi_port(port, intel_dsi->ports) {
 670                 func = I915_READ(MIPI_DSI_FUNC_PRG(port));
 671                 ctrl_reg = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
 672                                                 MIPI_PORT_CTRL(port);
 673                 dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 674
 675                 /* Due to some hardware limitations on BYT, MIPI Port C DPI
 676                  * Enable bit does not get set. To check whether DSI Port C
 677                  * was enabled in BIOS, check the Pipe B enable bit
 678                  */
 679                 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 680                     (port == PORT_C))
 681                         dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 682                                                         PIPECONF_ENABLE;
 683
 684                 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 685                         if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
 686                                 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 687                                 return true;
 688                         }
 689                 }
 690         }
 691
 692         return false;
 693 }
 694
 695 static void intel_dsi_get_config(struct intel_encoder *encoder,
 696                                  struct intel_crtc_state *pipe_config)
 697 {
 698         u32 pclk = 0;
 699         DRM_DEBUG_KMS("\n");
 700
 701         /*
 702          * DPLL_MD is not used in case of DSI, reading will get some default value
 703          * set dpll_md = 0
 704          */
 705         pipe_config->dpll_hw_state.dpll_md = 0;
 706
 707         if (IS_BROXTON(encoder->base.dev))
 708                 pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 709         else if (IS_VALLEYVIEW(encoder->base.dev))
 710                 pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 711
 712         if (!pclk)
 713                 return;
 714
 715         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 716         pipe_config->port_clock = pclk;
 717 }
 718
 719 static enum drm_mode_status
 720 intel_dsi_mode_valid(struct drm_connector *connector,
 721                      struct drm_display_mode *mode)
 722 {
 723         struct intel_connector *intel_connector = to_intel_connector(connector);
 724         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 725         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 726
 727         DRM_DEBUG_KMS("\n");
 728
 729         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 730                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 731                 return MODE_NO_DBLESCAN;
 732         }
 733
 734         if (fixed_mode) {
 735                 if (mode->hdisplay > fixed_mode->hdisplay)
 736                         return MODE_PANEL;
 737                 if (mode->vdisplay > fixed_mode->vdisplay)
 738                         return MODE_PANEL;
 739                 if (fixed_mode->clock > max_dotclk)
 740                         return MODE_CLOCK_HIGH;
 741         }
 742
 743         return MODE_OK;
 744 }
 745
 746 /* return txclkesc cycles in terms of divider and duration in us */
 747 static u16 txclkesc(u32 divider, unsigned int us)
 748 {
 749         switch (divider) {
 750         case ESCAPE_CLOCK_DIVIDER_1:
 751         default:
 752                 return 20 * us;
 753         case ESCAPE_CLOCK_DIVIDER_2:
 754                 return 10 * us;
 755         case ESCAPE_CLOCK_DIVIDER_4:
 756                 return 5 * us;
 757         }
 758 }
 759
 760 /* return pixels in terms of txbyteclkhs */
 761 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
 762                        u16 burst_mode_ratio)
 763 {
 764         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
 765                                          8 * 100), lane_count);
 766 }
 767
 768 static void set_dsi_timings(struct drm_encoder *encoder,
 769                             const struct drm_display_mode *adjusted_mode)
 770 {
 771         struct drm_device *dev = encoder->dev;
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 774         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 775         enum port port;
 776         unsigned int bpp = intel_crtc->config->pipe_bpp;
 777         unsigned int lane_count = intel_dsi->lane_count;
 778
 779         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 780
 781         hactive = adjusted_mode->crtc_hdisplay;
 782         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
 783         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
 784         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
 785
 786         if (intel_dsi->dual_link) {
 787                 hactive /= 2;
 788                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 789                         hactive += intel_dsi->pixel_overlap;
 790                 hfp /= 2;
 791                 hsync /= 2;
 792                 hbp /= 2;
 793         }
 794
 795         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
 796         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
 797         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
 798
 799         /* horizontal values are in terms of high speed byte clock */
 800         hactive = txbyteclkhs(hactive, bpp, lane_count,
 801                               intel_dsi->burst_mode_ratio);
 802         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 803         hsync = txbyteclkhs(hsync, bpp, lane_count,
 804                             intel_dsi->burst_mode_ratio);
 805         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 806
 807         for_each_dsi_port(port, intel_dsi->ports) {
 808                 if (IS_BROXTON(dev)) {
 809                         /*
 810                          * Program hdisplay and vdisplay on MIPI transcoder.
 811                          * This is different from calculated hactive and
 812                          * vactive, as they are calculated per channel basis,
 813                          * whereas these values should be based on resolution.
 814                          */
 815                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
 816                                    adjusted_mode->crtc_hdisplay);
 817                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
 818                                    adjusted_mode->crtc_vdisplay);
 819                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
 820                                    adjusted_mode->crtc_vtotal);
 821                 }
 822
 823                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
 824                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
 825
 826                 /* meaningful for video mode non-burst sync pulse mode only,
 827                  * can be zero for non-burst sync events and burst modes */
 828                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
 829                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
 830
 831                 /* vertical values are in terms of lines */
 832                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
 833                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
 834                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
 835         }
 836 }
 837
 838 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 839 {
 840         struct drm_encoder *encoder = &intel_encoder->base;
 841         struct drm_device *dev = encoder->dev;
 842         struct drm_i915_private *dev_priv = dev->dev_private;
 843         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 844         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 845         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
 846         enum port port;
 847         unsigned int bpp = intel_crtc->config->pipe_bpp;
 848         u32 val, tmp;
 849         u16 mode_hdisplay;
 850
 851         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 852
 853         mode_hdisplay = adjusted_mode->crtc_hdisplay;
 854
 855         if (intel_dsi->dual_link) {
 856                 mode_hdisplay /= 2;
 857                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 858                         mode_hdisplay += intel_dsi->pixel_overlap;
 859         }
 860
 861         for_each_dsi_port(port, intel_dsi->ports) {
 862                 if (IS_VALLEYVIEW(dev)) {
 863                         /*
 864                          * escape clock divider, 20MHz, shared for A and C.
 865                          * device ready must be off when doing this! txclkesc?
 866                          */
 867                         tmp = I915_READ(MIPI_CTRL(PORT_A));
 868                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 869                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
 870                                         ESCAPE_CLOCK_DIVIDER_1);
 871
 872                         /* read request priority is per pipe */
 873                         tmp = I915_READ(MIPI_CTRL(port));
 874                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 875                         I915_WRITE(MIPI_CTRL(port), tmp |
 876                                         READ_REQUEST_PRIORITY_HIGH);
 877                 } else if (IS_BROXTON(dev)) {
 878                         /*
 879                          * FIXME:
 880                          * BXT can connect any PIPE to any MIPI port.
 881                          * Select the pipe based on the MIPI port read from
 882                          * VBT for now. Pick PIPE A for MIPI port A and C
 883                          * for port C.
 884                          */
 885                         tmp = I915_READ(MIPI_CTRL(port));
 886                         tmp &= ~BXT_PIPE_SELECT_MASK;
 887
 888                         if (port == PORT_A)
 889                                 tmp |= BXT_PIPE_SELECT_A;
 890                         else if (port == PORT_C)
 891                                 tmp |= BXT_PIPE_SELECT_C;
 892
 893                         I915_WRITE(MIPI_CTRL(port), tmp);
 894                 }
 895
 896                 /* XXX: why here, why like this? handling in irq handler?! */
 897                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
 898                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
 899
 900                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
 901
 902                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
 903                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
 904                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 905         }
 906
 907         set_dsi_timings(encoder, adjusted_mode);
 908
 909         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 910         if (is_cmd_mode(intel_dsi)) {
 911                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 912                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 913         } else {
 914                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 915
 916                 /* XXX: cross-check bpp vs. pixel format? */
 917                 val |= intel_dsi->pixel_format;
 918         }
 919
 920         tmp = 0;
 921         if (intel_dsi->eotp_pkt == 0)
 922                 tmp |= EOT_DISABLE;
 923         if (intel_dsi->clock_stop)
 924                 tmp |= CLOCKSTOP;
 925
 926         for_each_dsi_port(port, intel_dsi->ports) {
 927                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 928
 929                 /* timeouts for recovery. one frame IIUC. if counter expires,
 930                  * EOT and stop state. */
 931
 932                 /*
 933                  * In burst mode, value greater than one DPI line Time in byte
 934                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
 935                  * said value is recommended.
 936                  *
 937                  * In non-burst mode, Value greater than one DPI frame time in
 938                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 939                  * said value is recommended.
 940                  *
 941                  * In DBI only mode, value greater than one DBI frame time in
 942                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 943                  * said value is recommended.
 944                  */
 945
 946                 if (is_vid_mode(intel_dsi) &&
 947                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 948                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 949                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
 950                                             intel_dsi->lane_count,
 951                                             intel_dsi->burst_mode_ratio) + 1);
 952                 } else {
 953                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 954                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
 955                                             adjusted_mode->crtc_htotal,
 956                                             bpp, intel_dsi->lane_count,
 957                                             intel_dsi->burst_mode_ratio) + 1);
 958                 }
 959                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
 960                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
 961                                                 intel_dsi->turn_arnd_val);
 962                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
 963                                                 intel_dsi->rst_timer_val);
 964
 965                 /* dphy stuff */
 966
 967                 /* in terms of low power clock */
 968                 I915_WRITE(MIPI_INIT_COUNT(port),
 969                                 txclkesc(intel_dsi->escape_clk_div, 100));
 970
 971                 if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
 972                         /*
 973                          * BXT spec says write MIPI_INIT_COUNT for
 974                          * both the ports, even if only one is
 975                          * getting used. So write the other port
 976                          * if not in dual link mode.
 977                          */
 978                         I915_WRITE(MIPI_INIT_COUNT(port ==
 979                                                 PORT_A ? PORT_C : PORT_A),
 980                                         intel_dsi->init_count);
 981                 }
 982
 983                 /* recovery disables */
 984                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
 985
 986                 /* in terms of low power clock */
 987                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 988
 989                 /* in terms of txbyteclkhs. actual high to low switch +
 990                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 991                  *
 992                  * XXX: write MIPI_STOP_STATE_STALL?
 993                  */
 994                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
 995                                                 intel_dsi->hs_to_lp_count);
 996
 997                 /* XXX: low power clock equivalence in terms of byte clock.
 998                  * the number of byte clocks occupied in one low power clock.
 999                  * based on txbyteclkhs and txclkesc.
1000                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1001                  * ) / 105.???
1002                  */
1003                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1004
1005                 /* the bw essential for transmitting 16 long packets containing
1006                  * 252 bytes meant for dcs write memory command is programmed in
1007                  * this register in terms of byte clocks. based on dsi transfer
1008                  * rate and the number of lanes configured the time taken to
1009                  * transmit 16 long packets in a dsi stream varies. */
1010                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1011
1012                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1013                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1014                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1015
1016                 if (is_vid_mode(intel_dsi))
1017                         /* Some panels might have resolution which is not a
1018                          * multiple of 64 like 1366 x 768. Enable RANDOM
1019                          * resolution support for such panels by default */
1020                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1021                                 intel_dsi->video_frmt_cfg_bits |
1022                                 intel_dsi->video_mode_format |
1023                                 IP_TG_CONFIG |
1024                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1025         }
1026 }
1027
1028 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
1029 {
1030         DRM_DEBUG_KMS("\n");
1031
1032         intel_dsi_prepare(encoder);
1033         intel_enable_dsi_pll(encoder);
1034
1035 }
1036
1037 static enum drm_connector_status
1038 intel_dsi_detect(struct drm_connector *connector, bool force)
1039 {
1040         return connector_status_connected;
1041 }
1042
1043 static int intel_dsi_get_modes(struct drm_connector *connector)
1044 {
1045         struct intel_connector *intel_connector = to_intel_connector(connector);
1046         struct drm_display_mode *mode;
1047
1048         DRM_DEBUG_KMS("\n");
1049
1050         if (!intel_connector->panel.fixed_mode) {
1051                 DRM_DEBUG_KMS("no fixed mode\n");
1052                 return 0;
1053         }
1054
1055         mode = drm_mode_duplicate(connector->dev,
1056                                   intel_connector->panel.fixed_mode);
1057         if (!mode) {
1058                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1059                 return 0;
1060         }
1061
1062         drm_mode_probed_add(connector, mode);
1063         return 1;
1064 }
1065
1066 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1067 {
1068         struct intel_connector *intel_connector = to_intel_connector(connector);
1069
1070         DRM_DEBUG_KMS("\n");
1071         intel_panel_fini(&intel_connector->panel);
1072         drm_connector_cleanup(connector);
1073         kfree(connector);
1074 }
1075
1076 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1077 {
1078         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1079
1080         if (intel_dsi->panel) {
1081                 drm_panel_detach(intel_dsi->panel);
1082                 /* XXX: Logically this call belongs in the panel driver. */
1083                 drm_panel_remove(intel_dsi->panel);
1084         }
1085
1086         /* dispose of the gpios */
1087         if (intel_dsi->gpio_panel)
1088                 gpiod_put(intel_dsi->gpio_panel);
1089
1090         intel_encoder_destroy(encoder);
1091 }
1092
1093 static const struct drm_encoder_funcs intel_dsi_funcs = {
1094         .destroy = intel_dsi_encoder_destroy,
1095 };
1096
1097 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1098         .get_modes = intel_dsi_get_modes,
1099         .mode_valid = intel_dsi_mode_valid,
1100         .best_encoder = intel_best_encoder,
1101 };
1102
1103 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1104         .dpms = drm_atomic_helper_connector_dpms,
1105         .detect = intel_dsi_detect,
1106         .destroy = intel_dsi_connector_destroy,
1107         .fill_modes = drm_helper_probe_single_connector_modes,
1108         .atomic_get_property = intel_connector_atomic_get_property,
1109         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1110         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1111 };
1112
1113 void intel_dsi_init(struct drm_device *dev)
1114 {
1115         struct intel_dsi *intel_dsi;
1116         struct intel_encoder *intel_encoder;
1117         struct drm_encoder *encoder;
1118         struct intel_connector *intel_connector;
1119         struct drm_connector *connector;
1120         struct drm_display_mode *scan, *fixed_mode = NULL;
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122         enum port port;
1123         unsigned int i;
1124
1125         DRM_DEBUG_KMS("\n");
1126
1127         /* There is no detection method for MIPI so rely on VBT */
1128         if (!dev_priv->vbt.has_mipi)
1129                 return;
1130
1131         if (IS_VALLEYVIEW(dev)) {
1132                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1133         } else {
1134                 DRM_ERROR("Unsupported Mipi device to reg base");
1135                 return;
1136         }
1137
1138         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1139         if (!intel_dsi)
1140                 return;
1141
1142         intel_connector = intel_connector_alloc();
1143         if (!intel_connector) {
1144                 kfree(intel_dsi);
1145                 return;
1146         }
1147
1148         intel_encoder = &intel_dsi->base;
1149         encoder = &intel_encoder->base;
1150         intel_dsi->attached_connector = intel_connector;
1151
1152         connector = &intel_connector->base;
1153
1154         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
1155
1156         /* XXX: very likely not all of these are needed */
1157         intel_encoder->compute_config = intel_dsi_compute_config;
1158         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
1159         intel_encoder->pre_enable = intel_dsi_pre_enable;
1160         intel_encoder->enable = intel_dsi_enable_nop;
1161         intel_encoder->disable = intel_dsi_pre_disable;
1162         intel_encoder->post_disable = intel_dsi_post_disable;
1163         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1164         intel_encoder->get_config = intel_dsi_get_config;
1165
1166         intel_connector->get_hw_state = intel_connector_get_hw_state;
1167         intel_connector->unregister = intel_connector_unregister;
1168
1169         /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1170         if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
1171                 intel_encoder->crtc_mask = (1 << PIPE_A);
1172                 intel_dsi->ports = (1 << PORT_A);
1173         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
1174                 intel_encoder->crtc_mask = (1 << PIPE_B);
1175                 intel_dsi->ports = (1 << PORT_C);
1176         }
1177
1178         if (dev_priv->vbt.dsi.config->dual_link)
1179                 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
1180
1181         /* Create a DSI host (and a device) for each port. */
1182         for_each_dsi_port(port, intel_dsi->ports) {
1183                 struct intel_dsi_host *host;
1184
1185                 host = intel_dsi_host_init(intel_dsi, port);
1186                 if (!host)
1187                         goto err;
1188
1189                 intel_dsi->dsi_hosts[port] = host;
1190         }
1191
1192         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1193                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1194                                                              intel_dsi_drivers[i].panel_id);
1195                 if (intel_dsi->panel)
1196                         break;
1197         }
1198
1199         if (!intel_dsi->panel) {
1200                 DRM_DEBUG_KMS("no device found\n");
1201                 goto err;
1202         }
1203
1204         /*
1205          * In case of BYT with CRC PMIC, we need to use GPIO for
1206          * Panel control.
1207          */
1208         if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1209                 intel_dsi->gpio_panel =
1210                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1211
1212                 if (IS_ERR(intel_dsi->gpio_panel)) {
1213                         DRM_ERROR("Failed to own gpio for panel control\n");
1214                         intel_dsi->gpio_panel = NULL;
1215                 }
1216         }
1217
1218         intel_encoder->type = INTEL_OUTPUT_DSI;
1219         intel_encoder->cloneable = 0;
1220         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1221                            DRM_MODE_CONNECTOR_DSI);
1222
1223         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1224
1225         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1226         connector->interlace_allowed = false;
1227         connector->doublescan_allowed = false;
1228
1229         intel_connector_attach_encoder(intel_connector, intel_encoder);
1230
1231         drm_connector_register(connector);
1232
1233         drm_panel_attach(intel_dsi->panel, connector);
1234
1235         mutex_lock(&dev->mode_config.mutex);
1236         drm_panel_get_modes(intel_dsi->panel);
1237         list_for_each_entry(scan, &connector->probed_modes, head) {
1238                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1239                         fixed_mode = drm_mode_duplicate(dev, scan);
1240                         break;
1241                 }
1242         }
1243         mutex_unlock(&dev->mode_config.mutex);
1244
1245         if (!fixed_mode) {
1246                 DRM_DEBUG_KMS("no fixed mode\n");
1247                 goto err;
1248         }
1249
1250         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1251         intel_panel_setup_backlight(connector, INVALID_PIPE);
1252
1253         return;
1254
1255 err:
1256         drm_encoder_cleanup(&intel_encoder->base);
1257         kfree(intel_dsi);
1258         kfree(intel_connector);
1259 }