1 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.12 2003/06/04 17:56:59 sam Exp $ */
2 /* $DragonFly: src/sys/dev/crypto/ubsec/ubsec.c,v 1.13 2006/12/22 23:26:15 swildner Exp $ */
3 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by Jason L. Wright
23 * 4. The name of the author may not be used to endorse or promote products
24 * derived from this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
38 * Effort sponsored in part by the Defense Advanced Research Projects
39 * Agency (DARPA) and Air Force Research Laboratory, Air Force
40 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
48 #include "opt_ubsec.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
57 #include <sys/sysctl.h>
58 #include <sys/endian.h>
62 #include <sys/random.h>
63 #include <sys/thread2.h>
68 #include <machine/clock.h>
70 #include <crypto/sha1.h>
71 #include <opencrypto/cryptodev.h>
72 #include <opencrypto/cryptosoft.h>
74 #include "cryptodev_if.h"
76 #include <bus/pci/pcivar.h>
77 #include <bus/pci/pcireg.h>
79 /* grr, #defines for gratuitous incompatibility in queue.h */
80 #define SIMPLEQ_HEAD STAILQ_HEAD
81 #define SIMPLEQ_ENTRY STAILQ_ENTRY
82 #define SIMPLEQ_INIT STAILQ_INIT
83 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
84 #define SIMPLEQ_EMPTY STAILQ_EMPTY
85 #define SIMPLEQ_FIRST STAILQ_FIRST
86 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD
87 #define SIMPLEQ_FOREACH STAILQ_FOREACH
88 /* ditto for endian.h */
89 #define letoh16(x) le16toh(x)
90 #define letoh32(x) le32toh(x)
93 #include "../rndtest/rndtest.h"
99 * Prototypes and count for the pci_device structure
101 static int ubsec_probe(device_t);
102 static int ubsec_attach(device_t);
103 static int ubsec_detach(device_t);
104 static int ubsec_suspend(device_t);
105 static int ubsec_resume(device_t);
106 static void ubsec_shutdown(device_t);
107 static void ubsec_intr(void *);
108 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
109 static int ubsec_freesession(void *, u_int64_t);
110 static int ubsec_process(void *, struct cryptop *, int);
111 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
112 static void ubsec_feed(struct ubsec_softc *);
113 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
114 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
115 static int ubsec_feed2(struct ubsec_softc *);
116 static void ubsec_rng(void *);
117 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
118 struct ubsec_dma_alloc *, int);
119 #define ubsec_dma_sync(_dma, _flags) \
120 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
121 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
122 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
124 static void ubsec_reset_board(struct ubsec_softc *sc);
125 static void ubsec_init_board(struct ubsec_softc *sc);
126 static void ubsec_init_pciregs(device_t dev);
127 static void ubsec_totalreset(struct ubsec_softc *sc);
129 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
131 static int ubsec_kprocess(void*, struct cryptkop *, int);
132 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
133 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
134 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
135 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
136 static int ubsec_ksigbits(struct crparam *);
137 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
138 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
141 static device_method_t ubsec_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, ubsec_probe),
144 DEVMETHOD(device_attach, ubsec_attach),
145 DEVMETHOD(device_detach, ubsec_detach),
146 DEVMETHOD(device_suspend, ubsec_suspend),
147 DEVMETHOD(device_resume, ubsec_resume),
148 DEVMETHOD(device_shutdown, ubsec_shutdown),
151 DEVMETHOD(bus_print_child, bus_generic_print_child),
152 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
154 /* crypto device methods */
155 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
156 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
157 DEVMETHOD(cryptodev_process, ubsec_process),
158 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess),
162 static driver_t ubsec_driver = {
165 sizeof (struct ubsec_softc)
167 static devclass_t ubsec_devclass;
169 DECLARE_DUMMY_MODULE(ubsec);
170 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
171 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
173 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
176 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
179 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
180 static void ubsec_dump_mcr(struct ubsec_mcr *);
181 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
183 static int ubsec_debug = 0;
184 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
185 0, "control debugging msgs");
188 #define READ_REG(sc,r) \
189 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
191 #define WRITE_REG(sc,reg,val) \
192 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
194 #define SWAP32(x) (x) = htole32(ntohl((x)))
195 #define HTOLE32(x) (x) = htole32(x)
198 struct ubsec_stats ubsecstats;
199 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
200 ubsec_stats, "driver statistics");
203 ubsec_probe(device_t dev)
205 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
206 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
207 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
209 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
210 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
211 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
213 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
214 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
215 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
220 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
227 ubsec_partname(struct ubsec_softc *sc)
229 /* XXX sprintf numbers when not decoded */
230 switch (pci_get_vendor(sc->sc_dev)) {
231 case PCI_VENDOR_BROADCOM:
232 switch (pci_get_device(sc->sc_dev)) {
233 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
234 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
235 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
236 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
237 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
238 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
239 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
241 return "Broadcom unknown-part";
242 case PCI_VENDOR_BLUESTEEL:
243 switch (pci_get_device(sc->sc_dev)) {
244 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
246 return "Bluesteel unknown-part";
248 switch (pci_get_device(sc->sc_dev)) {
249 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
250 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
252 return "Sun unknown-part";
254 return "Unknown-vendor unknown-part";
258 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
260 u_int32_t *p = (u_int32_t *)buf;
261 for (count /= sizeof (u_int32_t); count; count--)
262 add_true_randomness(*p++);
266 ubsec_attach(device_t dev)
268 struct ubsec_softc *sc = device_get_softc(dev);
269 struct ubsec_dma *dmap;
273 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!"));
274 bzero(sc, sizeof (*sc));
277 SIMPLEQ_INIT(&sc->sc_queue);
278 SIMPLEQ_INIT(&sc->sc_qchip);
279 SIMPLEQ_INIT(&sc->sc_queue2);
280 SIMPLEQ_INIT(&sc->sc_qchip2);
281 SIMPLEQ_INIT(&sc->sc_q2free);
283 /* XXX handle power management */
285 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
287 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
288 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
289 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
291 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
294 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
296 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
297 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
298 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
299 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
301 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
302 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
303 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
304 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
305 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
306 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
307 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
308 /* NB: the 5821/5822 defines some additional status bits */
309 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
310 BS_STAT_MCR2_ALLEMPTY;
311 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
312 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
315 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
316 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
317 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
318 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
320 if (!(cmd & PCIM_CMD_MEMEN)) {
321 device_printf(dev, "failed to enable memory mapping\n");
325 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
326 device_printf(dev, "failed to enable bus mastering\n");
331 * Setup memory-mapping of PCI registers.
334 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
335 0, ~0, 1, RF_ACTIVE);
336 if (sc->sc_sr == NULL) {
337 device_printf(dev, "cannot map register space\n");
340 sc->sc_st = rman_get_bustag(sc->sc_sr);
341 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
344 * Arrange interrupt line.
347 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
348 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
349 if (sc->sc_irq == NULL) {
350 device_printf(dev, "could not map interrupt\n");
354 * NB: Network code assumes we are blocked with splimp()
355 * so make sure the IRQ is mapped appropriately.
357 if (bus_setup_intr(dev, sc->sc_irq, 0,
360 device_printf(dev, "could not establish interrupt\n");
364 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
365 if (sc->sc_cid < 0) {
366 device_printf(dev, "could not get crypto driver id\n");
371 * Setup DMA descriptor area.
373 if (bus_dma_tag_create(NULL, /* parent */
374 1, 0, /* alignment, bounds */
375 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
376 BUS_SPACE_MAXADDR, /* highaddr */
377 NULL, NULL, /* filter, filterarg */
378 0x3ffff, /* maxsize */
379 UBS_MAX_SCATTER, /* nsegments */
380 0xffff, /* maxsegsize */
381 BUS_DMA_ALLOCNOW, /* flags */
383 device_printf(dev, "cannot allocate DMA tag\n");
386 SIMPLEQ_INIT(&sc->sc_freequeue);
388 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
391 q = kmalloc(sizeof(struct ubsec_q), M_DEVBUF, M_WAITOK);
392 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
393 &dmap->d_alloc, 0)) {
394 device_printf(dev, "cannot allocate dma buffers\n");
398 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
401 sc->sc_queuea[i] = q;
403 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
409 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
410 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
411 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
414 * Reset Broadcom chip
416 ubsec_reset_board(sc);
419 * Init Broadcom specific PCI settings
421 ubsec_init_pciregs(dev);
426 ubsec_init_board(sc);
429 if (sc->sc_flags & UBS_FLAGS_RNG) {
430 sc->sc_statmask |= BS_STAT_MCR2_DONE;
432 sc->sc_rndtest = rndtest_attach(dev);
434 sc->sc_harvest = rndtest_harvest;
436 sc->sc_harvest = default_harvest;
438 sc->sc_harvest = default_harvest;
441 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
442 &sc->sc_rng.rng_q.q_mcr, 0))
445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
446 &sc->sc_rng.rng_q.q_ctx, 0)) {
447 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
451 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
452 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
453 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
454 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
459 sc->sc_rnghz = hz / 100;
462 callout_init(&sc->sc_rngto);
463 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
467 #endif /* UBSEC_NO_RNG */
469 if (sc->sc_flags & UBS_FLAGS_KEY) {
470 sc->sc_statmask |= BS_STAT_MCR2_DONE;
472 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
474 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
479 crypto_unregister_all(sc->sc_cid);
481 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
485 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
491 * Detach a device that successfully probed.
494 ubsec_detach(device_t dev)
496 struct ubsec_softc *sc = device_get_softc(dev);
498 KASSERT(sc != NULL, ("ubsec_detach: null software carrier"));
500 /* XXX wait/abort active ops */
504 callout_stop(&sc->sc_rngto);
506 crypto_unregister_all(sc->sc_cid);
510 rndtest_detach(sc->sc_rndtest);
513 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
516 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
517 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
518 ubsec_dma_free(sc, &q->q_dma->d_alloc);
522 if (sc->sc_flags & UBS_FLAGS_RNG) {
523 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
524 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
525 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
527 #endif /* UBSEC_NO_RNG */
529 bus_generic_detach(dev);
530 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
531 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
533 bus_dma_tag_destroy(sc->sc_dmat);
534 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
542 * Stop all chip i/o so that the kernel's probe routines don't
543 * get confused by errant DMAs when rebooting.
546 ubsec_shutdown(device_t dev)
549 ubsec_stop(device_get_softc(dev));
554 * Device suspend routine.
557 ubsec_suspend(device_t dev)
559 struct ubsec_softc *sc = device_get_softc(dev);
561 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier"));
563 /* XXX stop the device and save PCI settings */
565 sc->sc_suspended = 1;
571 ubsec_resume(device_t dev)
573 struct ubsec_softc *sc = device_get_softc(dev);
575 KASSERT(sc != NULL, ("ubsec_resume: null software carrier"));
577 /* XXX retore PCI settings and start the device */
579 sc->sc_suspended = 0;
584 * UBSEC Interrupt routine
587 ubsec_intr(void *arg)
589 struct ubsec_softc *sc = arg;
590 volatile u_int32_t stat;
592 struct ubsec_dma *dmap;
595 stat = READ_REG(sc, BS_STAT);
596 stat &= sc->sc_statmask;
601 WRITE_REG(sc, BS_STAT, stat); /* IACK */
604 * Check to see if we have any packets waiting for us
606 if ((stat & BS_STAT_MCR1_DONE)) {
607 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
608 q = SIMPLEQ_FIRST(&sc->sc_qchip);
611 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
614 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
616 npkts = q->q_nstacked_mcrs;
617 sc->sc_nqchip -= 1+npkts;
619 * search for further sc_qchip ubsec_q's that share
620 * the same MCR, and complete them too, they must be
623 for (i = 0; i < npkts; i++) {
624 if(q->q_stacked_mcr[i]) {
625 ubsec_callback(sc, q->q_stacked_mcr[i]);
630 ubsec_callback(sc, q);
634 * Don't send any more packet to chip if there has been
637 if (!(stat & BS_STAT_DMAERR))
642 * Check to see if we have any key setups/rng's waiting for us
644 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
645 (stat & BS_STAT_MCR2_DONE)) {
647 struct ubsec_mcr *mcr;
649 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
650 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
652 ubsec_dma_sync(&q2->q_mcr,
653 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
657 ubsec_dma_sync(&q2->q_mcr,
658 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
661 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
662 ubsec_callback2(sc, q2);
664 * Don't send any more packet to chip if there has been
667 if (!(stat & BS_STAT_DMAERR))
673 * Check to see if we got any DMA Error
675 if (stat & BS_STAT_DMAERR) {
678 volatile u_int32_t a = READ_REG(sc, BS_ERR);
680 kprintf("dmaerr %s@%08x\n",
681 (a & BS_ERR_READ) ? "read" : "write",
684 #endif /* UBSEC_DEBUG */
685 ubsecstats.hst_dmaerr++;
686 ubsec_totalreset(sc);
690 if (sc->sc_needwakeup) { /* XXX check high watermark */
691 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
694 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
696 #endif /* UBSEC_DEBUG */
697 sc->sc_needwakeup &= ~wakeup;
698 crypto_unblock(sc->sc_cid, wakeup);
703 * ubsec_feed() - aggregate and post requests to chip
706 ubsec_feed(struct ubsec_softc *sc)
708 struct ubsec_q *q, *q2;
714 * Decide how many ops to combine in a single MCR. We cannot
715 * aggregate more than UBS_MAX_AGGR because this is the number
716 * of slots defined in the data structure. Note that
717 * aggregation only happens if ops are marked batch'able.
718 * Aggregating ops reduces the number of interrupts to the host
719 * but also (potentially) increases the latency for processing
720 * completed ops as we only get an interrupt when all aggregated
721 * ops have completed.
723 if (sc->sc_nqueue == 0)
725 if (sc->sc_nqueue > 1) {
727 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
729 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
735 * Check device status before going any further.
737 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
738 if (stat & BS_STAT_DMAERR) {
739 ubsec_totalreset(sc);
740 ubsecstats.hst_dmaerr++;
742 ubsecstats.hst_mcr1full++;
745 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
746 ubsecstats.hst_maxqueue = sc->sc_nqueue;
747 if (npkts > UBS_MAX_AGGR)
748 npkts = UBS_MAX_AGGR;
749 if (npkts < 2) /* special case 1 op */
752 ubsecstats.hst_totbatch += npkts-1;
755 kprintf("merging %d records\n", npkts);
756 #endif /* UBSEC_DEBUG */
758 q = SIMPLEQ_FIRST(&sc->sc_queue);
759 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
762 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
763 if (q->q_dst_map != NULL)
764 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
766 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
768 for (i = 0; i < q->q_nstacked_mcrs; i++) {
769 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
770 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
771 BUS_DMASYNC_PREWRITE);
772 if (q2->q_dst_map != NULL)
773 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
774 BUS_DMASYNC_PREREAD);
775 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
778 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
779 sizeof(struct ubsec_mcr_add));
780 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
781 q->q_stacked_mcr[i] = q2;
783 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
784 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
785 sc->sc_nqchip += npkts;
786 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
787 ubsecstats.hst_maxqchip = sc->sc_nqchip;
788 ubsec_dma_sync(&q->q_dma->d_alloc,
789 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
790 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
791 offsetof(struct ubsec_dmachunk, d_mcr));
795 q = SIMPLEQ_FIRST(&sc->sc_queue);
797 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
798 if (q->q_dst_map != NULL)
799 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
800 ubsec_dma_sync(&q->q_dma->d_alloc,
801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
803 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
804 offsetof(struct ubsec_dmachunk, d_mcr));
807 kprintf("feed1: q->chip %p %08x stat %08x\n",
808 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
810 #endif /* UBSEC_DEBUG */
811 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
813 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
815 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
816 ubsecstats.hst_maxqchip = sc->sc_nqchip;
821 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
824 /* Go ahead and compute key in ubsec's byte order */
825 if (algo == CRYPTO_DES_CBC) {
826 bcopy(key, &ses->ses_deskey[0], 8);
827 bcopy(key, &ses->ses_deskey[2], 8);
828 bcopy(key, &ses->ses_deskey[4], 8);
830 bcopy(key, ses->ses_deskey, 24);
832 SWAP32(ses->ses_deskey[0]);
833 SWAP32(ses->ses_deskey[1]);
834 SWAP32(ses->ses_deskey[2]);
835 SWAP32(ses->ses_deskey[3]);
836 SWAP32(ses->ses_deskey[4]);
837 SWAP32(ses->ses_deskey[5]);
841 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
847 for (i = 0; i < klen; i++)
848 key[i] ^= HMAC_IPAD_VAL;
850 if (algo == CRYPTO_MD5_HMAC) {
852 MD5Update(&md5ctx, key, klen);
853 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
854 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
857 SHA1Update(&sha1ctx, key, klen);
858 SHA1Update(&sha1ctx, hmac_ipad_buffer,
859 SHA1_HMAC_BLOCK_LEN - klen);
860 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
863 for (i = 0; i < klen; i++)
864 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
866 if (algo == CRYPTO_MD5_HMAC) {
868 MD5Update(&md5ctx, key, klen);
869 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
870 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
873 SHA1Update(&sha1ctx, key, klen);
874 SHA1Update(&sha1ctx, hmac_opad_buffer,
875 SHA1_HMAC_BLOCK_LEN - klen);
876 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
879 for (i = 0; i < klen; i++)
880 key[i] ^= HMAC_OPAD_VAL;
884 * Allocate a new 'session' and return an encoded session id. 'sidp'
885 * contains our registration id, and should contain an encoded session
886 * id on successful allocation.
889 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
891 struct cryptoini *c, *encini = NULL, *macini = NULL;
892 struct ubsec_softc *sc = arg;
893 struct ubsec_session *ses = NULL;
901 KASSERT(sc != NULL, ("ubsec_newsession: null softc"));
902 if (sidp == NULL || cri == NULL || sc == NULL)
905 for (c = cri; c != NULL; c = c->cri_next) {
906 if (c->cri_alg == CRYPTO_MD5_HMAC ||
907 c->cri_alg == CRYPTO_SHA1_HMAC) {
911 } else if (c->cri_alg == CRYPTO_DES_CBC ||
912 c->cri_alg == CRYPTO_3DES_CBC) {
919 if (encini == NULL && macini == NULL)
922 if (sc->sc_sessions == NULL) {
923 ses = sc->sc_sessions = kmalloc(sizeof(struct ubsec_session),
924 M_DEVBUF, M_INTWAIT);
926 sc->sc_nsessions = 1;
928 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
929 if (sc->sc_sessions[sesn].ses_used == 0) {
930 ses = &sc->sc_sessions[sesn];
936 sesn = sc->sc_nsessions;
937 ses = kmalloc((sesn + 1) * sizeof(struct ubsec_session),
938 M_DEVBUF, M_INTWAIT);
939 bcopy(sc->sc_sessions, ses, sesn *
940 sizeof(struct ubsec_session));
941 bzero(sc->sc_sessions, sesn *
942 sizeof(struct ubsec_session));
943 kfree(sc->sc_sessions, M_DEVBUF);
944 sc->sc_sessions = ses;
945 ses = &sc->sc_sessions[sesn];
950 bzero(ses, sizeof(struct ubsec_session));
953 read_random(ses->ses_iv, sizeof(ses->ses_iv));
954 if (encini->cri_key != NULL) {
955 ubsec_setup_enckey(ses, encini->cri_alg,
959 /* get an IV, network byte order */
960 /* XXX may read fewer than requested */
961 read_random(ses->ses_iv, sizeof(ses->ses_iv));
963 /* Go ahead and compute key in ubsec's byte order */
964 if (encini->cri_alg == CRYPTO_DES_CBC) {
965 bcopy(encini->cri_key, &ses->ses_deskey[0], 8);
966 bcopy(encini->cri_key, &ses->ses_deskey[2], 8);
967 bcopy(encini->cri_key, &ses->ses_deskey[4], 8);
969 bcopy(encini->cri_key, ses->ses_deskey, 24);
971 SWAP32(ses->ses_deskey[0]);
972 SWAP32(ses->ses_deskey[1]);
973 SWAP32(ses->ses_deskey[2]);
974 SWAP32(ses->ses_deskey[3]);
975 SWAP32(ses->ses_deskey[4]);
976 SWAP32(ses->ses_deskey[5]);
981 ses->ses_mlen = macini->cri_mlen;
982 if (ses->ses_mlen == 0) {
983 if (macini->cri_alg == CRYPTO_MD5_HMAC)
984 ses->ses_mlen = MD5_HASH_LEN;
986 ses->ses_mlen = SHA1_HASH_LEN;
989 if (macini->cri_key != NULL) {
990 ubsec_setup_mackey(ses, macini->cri_alg,
991 macini->cri_key, macini->cri_klen/8);
994 for (i = 0; i < macini->cri_klen / 8; i++)
995 macini->cri_key[i] ^= HMAC_IPAD_VAL;
997 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
999 MD5Update(&md5ctx, macini->cri_key,
1000 macini->cri_klen / 8);
1001 MD5Update(&md5ctx, hmac_ipad_buffer,
1002 MD5_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1003 bcopy(md5ctx.state, ses->ses_hminner,
1004 sizeof(md5ctx.state));
1007 SHA1Update(&sha1ctx, macini->cri_key,
1008 macini->cri_klen / 8);
1009 SHA1Update(&sha1ctx, hmac_ipad_buffer,
1010 SHA1_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1011 bcopy(sha1ctx.h.b32, ses->ses_hminner,
1012 sizeof(sha1ctx.h.b32));
1015 for (i = 0; i < macini->cri_klen / 8; i++)
1016 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
1018 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
1020 MD5Update(&md5ctx, macini->cri_key,
1021 macini->cri_klen / 8);
1022 MD5Update(&md5ctx, hmac_opad_buffer,
1023 MD5_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1024 bcopy(md5ctx.state, ses->ses_hmouter,
1025 sizeof(md5ctx.state));
1028 SHA1Update(&sha1ctx, macini->cri_key,
1029 macini->cri_klen / 8);
1030 SHA1Update(&sha1ctx, hmac_opad_buffer,
1031 SHA1_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1032 bcopy(sha1ctx.h.b32, ses->ses_hmouter,
1033 sizeof(sha1ctx.h.b32));
1036 for (i = 0; i < macini->cri_klen / 8; i++)
1037 macini->cri_key[i] ^= HMAC_OPAD_VAL;
1041 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
1046 * Deallocate a session.
1049 ubsec_freesession(void *arg, u_int64_t tid)
1051 struct ubsec_softc *sc = arg;
1053 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
1055 KASSERT(sc != NULL, ("ubsec_freesession: null softc"));
1059 session = UBSEC_SESSION(sid);
1060 if (session >= sc->sc_nsessions)
1063 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
1068 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1070 struct ubsec_operand *op = arg;
1072 KASSERT(nsegs <= UBS_MAX_SCATTER,
1073 ("Too many DMA segments returned when mapping operand"));
1076 kprintf("ubsec_op_cb: mapsize %u nsegs %d\n",
1077 (u_int) mapsize, nsegs);
1079 op->mapsize = mapsize;
1081 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1085 ubsec_process(void *arg, struct cryptop *crp, int hint)
1087 struct ubsec_q *q = NULL;
1088 int err = 0, i, j, nicealign;
1089 struct ubsec_softc *sc = arg;
1090 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1091 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1092 int sskip, dskip, stheend, dtheend;
1094 struct ubsec_session *ses;
1095 struct ubsec_pktctx ctx;
1096 struct ubsec_dma *dmap = NULL;
1098 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1099 ubsecstats.hst_invalid++;
1102 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1103 ubsecstats.hst_badsession++;
1109 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1110 ubsecstats.hst_queuefull++;
1111 sc->sc_needwakeup |= CRYPTO_SYMQ;
1115 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1116 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1119 dmap = q->q_dma; /* Save dma pointer */
1120 bzero(q, sizeof(struct ubsec_q));
1121 bzero(&ctx, sizeof(ctx));
1123 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1125 ses = &sc->sc_sessions[q->q_sesn];
1127 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1128 q->q_src_m = (struct mbuf *)crp->crp_buf;
1129 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1130 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1131 q->q_src_io = (struct uio *)crp->crp_buf;
1132 q->q_dst_io = (struct uio *)crp->crp_buf;
1134 ubsecstats.hst_badflags++;
1136 goto errout; /* XXX we don't handle contiguous blocks! */
1139 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1141 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1142 dmap->d_dma->d_mcr.mcr_flags = 0;
1145 crd1 = crp->crp_desc;
1147 ubsecstats.hst_nodesc++;
1151 crd2 = crd1->crd_next;
1154 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1155 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1158 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1159 crd1->crd_alg == CRYPTO_3DES_CBC) {
1163 ubsecstats.hst_badalg++;
1168 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1169 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1170 (crd2->crd_alg == CRYPTO_DES_CBC ||
1171 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1172 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1175 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1176 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1177 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1178 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1179 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1184 * We cannot order the ubsec as requested
1186 ubsecstats.hst_badalg++;
1193 encoffset = enccrd->crd_skip;
1194 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1196 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1197 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1199 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1200 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1202 ctx.pc_iv[0] = ses->ses_iv[0];
1203 ctx.pc_iv[1] = ses->ses_iv[1];
1206 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1207 if (crp->crp_flags & CRYPTO_F_IMBUF)
1208 m_copyback(q->q_src_m,
1210 8, (caddr_t)ctx.pc_iv);
1211 else if (crp->crp_flags & CRYPTO_F_IOV)
1212 cuio_copyback(q->q_src_io,
1214 8, (caddr_t)ctx.pc_iv);
1217 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1219 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1220 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1221 else if (crp->crp_flags & CRYPTO_F_IMBUF)
1222 m_copydata(q->q_src_m, enccrd->crd_inject,
1223 8, (caddr_t)ctx.pc_iv);
1224 else if (crp->crp_flags & CRYPTO_F_IOV)
1225 cuio_copydata(q->q_src_io,
1226 enccrd->crd_inject, 8,
1227 (caddr_t)ctx.pc_iv);
1230 ctx.pc_deskey[0] = ses->ses_deskey[0];
1231 ctx.pc_deskey[1] = ses->ses_deskey[1];
1232 ctx.pc_deskey[2] = ses->ses_deskey[2];
1233 ctx.pc_deskey[3] = ses->ses_deskey[3];
1234 ctx.pc_deskey[4] = ses->ses_deskey[4];
1235 ctx.pc_deskey[5] = ses->ses_deskey[5];
1236 SWAP32(ctx.pc_iv[0]);
1237 SWAP32(ctx.pc_iv[1]);
1241 macoffset = maccrd->crd_skip;
1243 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1244 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1246 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1248 for (i = 0; i < 5; i++) {
1249 ctx.pc_hminner[i] = ses->ses_hminner[i];
1250 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1252 HTOLE32(ctx.pc_hminner[i]);
1253 HTOLE32(ctx.pc_hmouter[i]);
1257 if (enccrd && maccrd) {
1259 * ubsec cannot handle packets where the end of encryption
1260 * and authentication are not the same, or where the
1261 * encrypted part begins before the authenticated part.
1263 if ((encoffset + enccrd->crd_len) !=
1264 (macoffset + maccrd->crd_len)) {
1265 ubsecstats.hst_lenmismatch++;
1269 if (enccrd->crd_skip < maccrd->crd_skip) {
1270 ubsecstats.hst_skipmismatch++;
1274 sskip = maccrd->crd_skip;
1275 cpskip = dskip = enccrd->crd_skip;
1276 stheend = maccrd->crd_len;
1277 dtheend = enccrd->crd_len;
1278 coffset = enccrd->crd_skip - maccrd->crd_skip;
1279 cpoffset = cpskip + dtheend;
1282 kprintf("mac: skip %d, len %d, inject %d\n",
1283 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1284 kprintf("enc: skip %d, len %d, inject %d\n",
1285 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1286 kprintf("src: skip %d, len %d\n", sskip, stheend);
1287 kprintf("dst: skip %d, len %d\n", dskip, dtheend);
1288 kprintf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1289 coffset, stheend, cpskip, cpoffset);
1293 cpskip = dskip = sskip = macoffset + encoffset;
1294 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1295 cpoffset = cpskip + dtheend;
1298 ctx.pc_offset = htole16(coffset >> 2);
1300 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1301 ubsecstats.hst_nomap++;
1305 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1306 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1307 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1308 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1309 q->q_src_map = NULL;
1310 ubsecstats.hst_noload++;
1314 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1315 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1316 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1317 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1318 q->q_src_map = NULL;
1319 ubsecstats.hst_noload++;
1324 nicealign = ubsec_dmamap_aligned(&q->q_src);
1326 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1330 kprintf("src skip: %d nicealign: %u\n", sskip, nicealign);
1332 for (i = j = 0; i < q->q_src_nsegs; i++) {
1333 struct ubsec_pktbuf *pb;
1334 bus_size_t packl = q->q_src_segs[i].ds_len;
1335 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1337 if (sskip >= packl) {
1346 if (packl > 0xfffc) {
1352 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1354 pb = &dmap->d_dma->d_sbuf[j - 1];
1356 pb->pb_addr = htole32(packp);
1359 if (packl > stheend) {
1360 pb->pb_len = htole32(stheend);
1363 pb->pb_len = htole32(packl);
1367 pb->pb_len = htole32(packl);
1369 if ((i + 1) == q->q_src_nsegs)
1372 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1373 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1377 if (enccrd == NULL && maccrd != NULL) {
1378 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1379 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1380 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1381 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1384 kprintf("opkt: %x %x %x\n",
1385 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1386 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1387 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1390 if (crp->crp_flags & CRYPTO_F_IOV) {
1392 ubsecstats.hst_iovmisaligned++;
1396 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1398 ubsecstats.hst_nomap++;
1402 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1403 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1404 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1405 q->q_dst_map = NULL;
1406 ubsecstats.hst_noload++;
1410 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1412 q->q_dst = q->q_src;
1415 struct mbuf *m, *top, **mp;
1417 ubsecstats.hst_unaligned++;
1418 totlen = q->q_src_mapsize;
1419 if (q->q_src_m->m_flags & M_PKTHDR) {
1421 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1422 if (m && !m_dup_pkthdr(m, q->q_src_m, MB_DONTWAIT)) {
1428 MGET(m, MB_DONTWAIT, MT_DATA);
1431 ubsecstats.hst_nombuf++;
1432 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1435 if (totlen >= MINCLSIZE) {
1436 MCLGET(m, MB_DONTWAIT);
1437 if ((m->m_flags & M_EXT) == 0) {
1439 ubsecstats.hst_nomcl++;
1440 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1449 while (totlen > 0) {
1451 MGET(m, MB_DONTWAIT, MT_DATA);
1454 ubsecstats.hst_nombuf++;
1455 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1460 if (top && totlen >= MINCLSIZE) {
1461 MCLGET(m, MB_DONTWAIT);
1462 if ((m->m_flags & M_EXT) == 0) {
1465 ubsecstats.hst_nomcl++;
1466 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1471 m->m_len = len = min(totlen, len);
1477 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1479 if (bus_dmamap_create(sc->sc_dmat,
1480 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1481 ubsecstats.hst_nomap++;
1485 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1486 q->q_dst_map, q->q_dst_m,
1487 ubsec_op_cb, &q->q_dst,
1488 BUS_DMA_NOWAIT) != 0) {
1489 bus_dmamap_destroy(sc->sc_dmat,
1491 q->q_dst_map = NULL;
1492 ubsecstats.hst_noload++;
1498 ubsecstats.hst_badflags++;
1505 kprintf("dst skip: %d\n", dskip);
1507 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1508 struct ubsec_pktbuf *pb;
1509 bus_size_t packl = q->q_dst_segs[i].ds_len;
1510 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1512 if (dskip >= packl) {
1521 if (packl > 0xfffc) {
1527 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1529 pb = &dmap->d_dma->d_dbuf[j - 1];
1531 pb->pb_addr = htole32(packp);
1534 if (packl > dtheend) {
1535 pb->pb_len = htole32(dtheend);
1538 pb->pb_len = htole32(packl);
1542 pb->pb_len = htole32(packl);
1544 if ((i + 1) == q->q_dst_nsegs) {
1546 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1547 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1551 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1552 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1557 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1558 offsetof(struct ubsec_dmachunk, d_ctx));
1560 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1561 struct ubsec_pktctx_long *ctxl;
1563 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1564 offsetof(struct ubsec_dmachunk, d_ctx));
1566 /* transform small context into long context */
1567 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1568 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1569 ctxl->pc_flags = ctx.pc_flags;
1570 ctxl->pc_offset = ctx.pc_offset;
1571 for (i = 0; i < 6; i++)
1572 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1573 for (i = 0; i < 5; i++)
1574 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1575 for (i = 0; i < 5; i++)
1576 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1577 ctxl->pc_iv[0] = ctx.pc_iv[0];
1578 ctxl->pc_iv[1] = ctx.pc_iv[1];
1580 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1581 offsetof(struct ubsec_dmachunk, d_ctx),
1582 sizeof(struct ubsec_pktctx));
1585 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1587 ubsecstats.hst_ipackets++;
1588 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1589 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1596 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1597 m_freem(q->q_dst_m);
1599 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1600 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1601 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1603 if (q->q_src_map != NULL) {
1604 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1605 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1609 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1612 if (err != ERESTART) {
1613 crp->crp_etype = err;
1616 sc->sc_needwakeup |= CRYPTO_SYMQ;
1622 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1624 struct cryptop *crp = (struct cryptop *)q->q_crp;
1625 struct cryptodesc *crd;
1626 struct ubsec_dma *dmap = q->q_dma;
1628 ubsecstats.hst_opackets++;
1629 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1631 ubsec_dma_sync(&dmap->d_alloc,
1632 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1633 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1634 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1635 BUS_DMASYNC_POSTREAD);
1636 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1637 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1639 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1640 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1641 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1643 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1644 m_freem(q->q_src_m);
1645 crp->crp_buf = (caddr_t)q->q_dst_m;
1647 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len;
1649 /* copy out IV for future use */
1650 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1651 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1652 if (crd->crd_alg != CRYPTO_DES_CBC &&
1653 crd->crd_alg != CRYPTO_3DES_CBC)
1655 if (crp->crp_flags & CRYPTO_F_IMBUF)
1656 m_copydata((struct mbuf *)crp->crp_buf,
1657 crd->crd_skip + crd->crd_len - 8, 8,
1658 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1659 else if (crp->crp_flags & CRYPTO_F_IOV) {
1660 cuio_copydata((struct uio *)crp->crp_buf,
1661 crd->crd_skip + crd->crd_len - 8, 8,
1662 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1668 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1669 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1670 crd->crd_alg != CRYPTO_SHA1_HMAC)
1672 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1673 sc->sc_sessions[q->q_sesn].ses_mlen,
1674 (caddr_t)dmap->d_dma->d_macbuf);
1676 if (crp->crp_flags & CRYPTO_F_IMBUF)
1677 m_copyback((struct mbuf *)crp->crp_buf,
1678 crd->crd_inject, 12,
1679 (caddr_t)dmap->d_dma->d_macbuf);
1680 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1681 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1686 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1691 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1693 int i, j, dlen, slen;
1697 sptr = srcm->m_data;
1699 dptr = dstm->m_data;
1703 for (i = 0; i < min(slen, dlen); i++) {
1704 if (j < hoffset || j >= toffset)
1711 srcm = srcm->m_next;
1714 sptr = srcm->m_data;
1718 dstm = dstm->m_next;
1721 dptr = dstm->m_data;
1728 * feed the key generator, must be called at splimp() or higher.
1731 ubsec_feed2(struct ubsec_softc *sc)
1735 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1736 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1738 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1740 ubsec_dma_sync(&q->q_mcr,
1741 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1742 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1744 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1745 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1747 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1753 * Callback for handling random numbers
1756 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1758 struct cryptkop *krp;
1759 struct ubsec_ctx_keyop *ctx;
1761 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1762 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1764 switch (q->q_type) {
1765 #ifndef UBSEC_NO_RNG
1766 case UBS_CTXOP_RNGBYPASS: {
1767 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1769 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1770 (*sc->sc_harvest)(sc->sc_rndtest,
1771 rng->rng_buf.dma_vaddr,
1772 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1774 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1778 case UBS_CTXOP_MODEXP: {
1779 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1783 rlen = (me->me_modbits + 7) / 8;
1784 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1786 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1787 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1788 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1789 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1792 krp->krp_status = E2BIG;
1794 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1795 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1796 (krp->krp_param[krp->krp_iparams].crp_nbits
1798 bcopy(me->me_C.dma_vaddr,
1799 krp->krp_param[krp->krp_iparams].crp_p,
1800 (me->me_modbits + 7) / 8);
1802 ubsec_kshift_l(me->me_shiftbits,
1803 me->me_C.dma_vaddr, me->me_normbits,
1804 krp->krp_param[krp->krp_iparams].crp_p,
1805 krp->krp_param[krp->krp_iparams].crp_nbits);
1810 /* bzero all potentially sensitive data */
1811 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1812 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1813 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1814 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1816 /* Can't free here, so put us on the free list. */
1817 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1820 case UBS_CTXOP_RSAPRIV: {
1821 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1825 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1826 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1828 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1829 bcopy(rp->rpr_msgout.dma_vaddr,
1830 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1834 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1835 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1836 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1838 /* Can't free here, so put us on the free list. */
1839 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1843 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1844 letoh16(ctx->ctx_op));
1849 #ifndef UBSEC_NO_RNG
1851 ubsec_rng(void *vsc)
1853 struct ubsec_softc *sc = vsc;
1854 struct ubsec_q2_rng *rng = &sc->sc_rng;
1855 struct ubsec_mcr *mcr;
1856 struct ubsec_ctx_rngbypass *ctx;
1859 if (rng->rng_used) {
1864 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1867 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1868 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1870 mcr->mcr_pkts = htole16(1);
1872 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1873 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1874 mcr->mcr_ipktbuf.pb_len = 0;
1875 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1876 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1877 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1879 mcr->mcr_opktbuf.pb_next = 0;
1881 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1882 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1883 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1885 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1887 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1890 ubsecstats.hst_rng++;
1897 * Something weird happened, generate our own call back.
1901 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1903 #endif /* UBSEC_NO_RNG */
1906 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1908 bus_addr_t *paddr = (bus_addr_t*) arg;
1909 *paddr = segs->ds_addr;
1914 struct ubsec_softc *sc,
1916 struct ubsec_dma_alloc *dma,
1922 /* XXX could specify sc_dmat as parent but that just adds overhead */
1923 r = bus_dma_tag_create(NULL, /* parent */
1924 1, 0, /* alignment, bounds */
1925 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1926 BUS_SPACE_MAXADDR, /* highaddr */
1927 NULL, NULL, /* filter, filterarg */
1930 size, /* maxsegsize */
1931 BUS_DMA_ALLOCNOW, /* flags */
1934 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1935 "bus_dma_tag_create failed; error %u\n", r);
1939 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1941 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1942 "bus_dmamap_create failed; error %u\n", r);
1946 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1947 BUS_DMA_NOWAIT, &dma->dma_map);
1949 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1950 "bus_dmammem_alloc failed; size %ju, error %u\n",
1955 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1959 mapflags | BUS_DMA_NOWAIT);
1961 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1962 "bus_dmamap_load failed; error %u\n", r);
1966 dma->dma_size = size;
1970 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1972 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1974 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1975 bus_dma_tag_destroy(dma->dma_tag);
1977 dma->dma_map = NULL;
1978 dma->dma_tag = NULL;
1983 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1985 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1986 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1987 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1988 bus_dma_tag_destroy(dma->dma_tag);
1992 * Resets the board. Values in the regesters are left as is
1993 * from the reset (i.e. initial values are assigned elsewhere).
1996 ubsec_reset_board(struct ubsec_softc *sc)
1998 volatile u_int32_t ctrl;
2000 ctrl = READ_REG(sc, BS_CTRL);
2001 ctrl |= BS_CTRL_RESET;
2002 WRITE_REG(sc, BS_CTRL, ctrl);
2005 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
2011 * Init Broadcom registers
2014 ubsec_init_board(struct ubsec_softc *sc)
2018 ctrl = READ_REG(sc, BS_CTRL);
2019 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
2020 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
2022 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
2023 ctrl |= BS_CTRL_MCR2INT;
2025 ctrl &= ~BS_CTRL_MCR2INT;
2027 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2028 ctrl &= ~BS_CTRL_SWNORM;
2030 WRITE_REG(sc, BS_CTRL, ctrl);
2034 * Init Broadcom PCI registers
2037 ubsec_init_pciregs(device_t dev)
2042 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
2043 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
2044 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
2045 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
2046 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
2047 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
2051 * This will set the cache line size to 1, this will
2052 * force the BCM58xx chip just to do burst read/writes.
2053 * Cache line read/writes are to slow
2055 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
2059 * Clean up after a chip crash.
2060 * It is assumed that the caller in splimp()
2063 ubsec_cleanchip(struct ubsec_softc *sc)
2067 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2068 q = SIMPLEQ_FIRST(&sc->sc_qchip);
2069 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
2070 ubsec_free_q(sc, q);
2077 * It is assumed that the caller is within spimp()
2080 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2083 struct cryptop *crp;
2087 npkts = q->q_nstacked_mcrs;
2089 for (i = 0; i < npkts; i++) {
2090 if(q->q_stacked_mcr[i]) {
2091 q2 = q->q_stacked_mcr[i];
2093 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2094 m_freem(q2->q_dst_m);
2096 crp = (struct cryptop *)q2->q_crp;
2098 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2100 crp->crp_etype = EFAULT;
2110 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2111 m_freem(q->q_dst_m);
2113 crp = (struct cryptop *)q->q_crp;
2115 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2117 crp->crp_etype = EFAULT;
2123 * Routine to reset the chip and clean up.
2124 * It is assumed that the caller is in splimp()
2127 ubsec_totalreset(struct ubsec_softc *sc)
2129 ubsec_reset_board(sc);
2130 ubsec_init_board(sc);
2131 ubsec_cleanchip(sc);
2135 ubsec_dmamap_aligned(struct ubsec_operand *op)
2139 for (i = 0; i < op->nsegs; i++) {
2140 if (op->segs[i].ds_addr & 3)
2142 if ((i != (op->nsegs - 1)) &&
2143 (op->segs[i].ds_len & 3))
2150 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2152 switch (q->q_type) {
2153 case UBS_CTXOP_MODEXP: {
2154 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2156 ubsec_dma_free(sc, &me->me_q.q_mcr);
2157 ubsec_dma_free(sc, &me->me_q.q_ctx);
2158 ubsec_dma_free(sc, &me->me_M);
2159 ubsec_dma_free(sc, &me->me_E);
2160 ubsec_dma_free(sc, &me->me_C);
2161 ubsec_dma_free(sc, &me->me_epb);
2162 kfree(me, M_DEVBUF);
2165 case UBS_CTXOP_RSAPRIV: {
2166 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2168 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2169 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2170 ubsec_dma_free(sc, &rp->rpr_msgin);
2171 ubsec_dma_free(sc, &rp->rpr_msgout);
2172 kfree(rp, M_DEVBUF);
2176 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2182 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2184 struct ubsec_softc *sc = arg;
2187 if (krp == NULL || krp->krp_callback == NULL)
2190 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2193 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2194 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2198 switch (krp->krp_op) {
2200 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2201 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2203 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2205 case CRK_MOD_EXP_CRT:
2206 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2208 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2210 krp->krp_status = EOPNOTSUPP;
2214 return (0); /* silence compiler */
2218 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2221 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2223 struct ubsec_q2_modexp *me;
2224 struct ubsec_mcr *mcr;
2225 struct ubsec_ctx_modexp *ctx;
2226 struct ubsec_pktbuf *epb;
2228 u_int nbits, normbits, mbits, shiftbits, ebits;
2230 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2232 me->me_q.q_type = UBS_CTXOP_MODEXP;
2234 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2237 else if (nbits <= 768)
2239 else if (nbits <= 1024)
2241 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2243 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2250 shiftbits = normbits - nbits;
2252 me->me_modbits = nbits;
2253 me->me_shiftbits = shiftbits;
2254 me->me_normbits = normbits;
2256 /* Sanity check: result bits must be >= true modulus bits. */
2257 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2262 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2263 &me->me_q.q_mcr, 0)) {
2267 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2269 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2270 &me->me_q.q_ctx, 0)) {
2275 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2276 if (mbits > nbits) {
2280 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2284 ubsec_kshift_r(shiftbits,
2285 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2286 me->me_M.dma_vaddr, normbits);
2288 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2292 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2294 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2295 if (ebits > nbits) {
2299 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2303 ubsec_kshift_r(shiftbits,
2304 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2305 me->me_E.dma_vaddr, normbits);
2307 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2312 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2313 epb->pb_addr = htole32(me->me_E.dma_paddr);
2315 epb->pb_len = htole32(normbits / 8);
2324 mcr->mcr_pkts = htole16(1);
2326 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2327 mcr->mcr_reserved = 0;
2328 mcr->mcr_pktlen = 0;
2330 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2331 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2332 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2334 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2335 mcr->mcr_opktbuf.pb_next = 0;
2336 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2339 /* Misaligned output buffer will hang the chip. */
2340 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2341 panic("%s: modexp invalid addr 0x%x\n",
2342 device_get_nameunit(sc->sc_dev),
2343 letoh32(mcr->mcr_opktbuf.pb_addr));
2344 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2345 panic("%s: modexp invalid len 0x%x\n",
2346 device_get_nameunit(sc->sc_dev),
2347 letoh32(mcr->mcr_opktbuf.pb_len));
2350 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2351 bzero(ctx, sizeof(*ctx));
2352 ubsec_kshift_r(shiftbits,
2353 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2354 ctx->me_N, normbits);
2355 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2356 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2357 ctx->me_E_len = htole16(nbits);
2358 ctx->me_N_len = htole16(nbits);
2362 ubsec_dump_mcr(mcr);
2363 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2368 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2371 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2372 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2373 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2374 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2376 /* Enqueue and we're done... */
2378 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2380 ubsecstats.hst_modexp++;
2387 if (me->me_q.q_mcr.dma_map != NULL)
2388 ubsec_dma_free(sc, &me->me_q.q_mcr);
2389 if (me->me_q.q_ctx.dma_map != NULL) {
2390 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2391 ubsec_dma_free(sc, &me->me_q.q_ctx);
2393 if (me->me_M.dma_map != NULL) {
2394 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2395 ubsec_dma_free(sc, &me->me_M);
2397 if (me->me_E.dma_map != NULL) {
2398 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2399 ubsec_dma_free(sc, &me->me_E);
2401 if (me->me_C.dma_map != NULL) {
2402 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2403 ubsec_dma_free(sc, &me->me_C);
2405 if (me->me_epb.dma_map != NULL)
2406 ubsec_dma_free(sc, &me->me_epb);
2407 kfree(me, M_DEVBUF);
2409 krp->krp_status = err;
2415 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2418 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2420 struct ubsec_q2_modexp *me;
2421 struct ubsec_mcr *mcr;
2422 struct ubsec_ctx_modexp *ctx;
2423 struct ubsec_pktbuf *epb;
2425 u_int nbits, normbits, mbits, shiftbits, ebits;
2427 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2429 me->me_q.q_type = UBS_CTXOP_MODEXP;
2431 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2434 else if (nbits <= 768)
2436 else if (nbits <= 1024)
2438 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2440 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2447 shiftbits = normbits - nbits;
2450 me->me_modbits = nbits;
2451 me->me_shiftbits = shiftbits;
2452 me->me_normbits = normbits;
2454 /* Sanity check: result bits must be >= true modulus bits. */
2455 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2460 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2461 &me->me_q.q_mcr, 0)) {
2465 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2467 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2468 &me->me_q.q_ctx, 0)) {
2473 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2474 if (mbits > nbits) {
2478 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2482 bzero(me->me_M.dma_vaddr, normbits / 8);
2483 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2484 me->me_M.dma_vaddr, (mbits + 7) / 8);
2486 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2490 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2492 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2493 if (ebits > nbits) {
2497 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2501 bzero(me->me_E.dma_vaddr, normbits / 8);
2502 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2503 me->me_E.dma_vaddr, (ebits + 7) / 8);
2505 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2510 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2511 epb->pb_addr = htole32(me->me_E.dma_paddr);
2513 epb->pb_len = htole32((ebits + 7) / 8);
2522 mcr->mcr_pkts = htole16(1);
2524 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2525 mcr->mcr_reserved = 0;
2526 mcr->mcr_pktlen = 0;
2528 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2529 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2530 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2532 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2533 mcr->mcr_opktbuf.pb_next = 0;
2534 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2537 /* Misaligned output buffer will hang the chip. */
2538 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2539 panic("%s: modexp invalid addr 0x%x\n",
2540 device_get_nameunit(sc->sc_dev),
2541 letoh32(mcr->mcr_opktbuf.pb_addr));
2542 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2543 panic("%s: modexp invalid len 0x%x\n",
2544 device_get_nameunit(sc->sc_dev),
2545 letoh32(mcr->mcr_opktbuf.pb_len));
2548 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2549 bzero(ctx, sizeof(*ctx));
2550 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2552 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2553 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2554 ctx->me_E_len = htole16(ebits);
2555 ctx->me_N_len = htole16(nbits);
2559 ubsec_dump_mcr(mcr);
2560 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2565 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2568 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2569 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2570 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2571 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2573 /* Enqueue and we're done... */
2575 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2583 if (me->me_q.q_mcr.dma_map != NULL)
2584 ubsec_dma_free(sc, &me->me_q.q_mcr);
2585 if (me->me_q.q_ctx.dma_map != NULL) {
2586 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2587 ubsec_dma_free(sc, &me->me_q.q_ctx);
2589 if (me->me_M.dma_map != NULL) {
2590 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2591 ubsec_dma_free(sc, &me->me_M);
2593 if (me->me_E.dma_map != NULL) {
2594 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2595 ubsec_dma_free(sc, &me->me_E);
2597 if (me->me_C.dma_map != NULL) {
2598 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2599 ubsec_dma_free(sc, &me->me_C);
2601 if (me->me_epb.dma_map != NULL)
2602 ubsec_dma_free(sc, &me->me_epb);
2603 kfree(me, M_DEVBUF);
2605 krp->krp_status = err;
2611 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2613 struct ubsec_q2_rsapriv *rp = NULL;
2614 struct ubsec_mcr *mcr;
2615 struct ubsec_ctx_rsapriv *ctx;
2617 u_int padlen, msglen;
2619 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2620 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2621 if (msglen > padlen)
2626 else if (padlen <= 384)
2628 else if (padlen <= 512)
2630 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2632 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2639 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2644 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2649 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2654 rp = kmalloc(sizeof *rp, M_DEVBUF, M_INTWAIT | M_ZERO);
2656 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2658 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2659 &rp->rpr_q.q_mcr, 0)) {
2663 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2665 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2666 &rp->rpr_q.q_ctx, 0)) {
2670 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2671 bzero(ctx, sizeof *ctx);
2674 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2675 &ctx->rpr_buf[0 * (padlen / 8)],
2676 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2679 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2680 &ctx->rpr_buf[1 * (padlen / 8)],
2681 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2684 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2685 &ctx->rpr_buf[2 * (padlen / 8)],
2686 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2689 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2690 &ctx->rpr_buf[3 * (padlen / 8)],
2691 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2694 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2695 &ctx->rpr_buf[4 * (padlen / 8)],
2696 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2698 msglen = padlen * 2;
2700 /* Copy in input message (aligned buffer/length). */
2701 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2702 /* Is this likely? */
2706 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2710 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2711 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2712 rp->rpr_msgin.dma_vaddr,
2713 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2715 /* Prepare space for output message (aligned buffer/length). */
2716 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2717 /* Is this likely? */
2721 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2725 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2727 mcr->mcr_pkts = htole16(1);
2729 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2730 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2731 mcr->mcr_ipktbuf.pb_next = 0;
2732 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2733 mcr->mcr_reserved = 0;
2734 mcr->mcr_pktlen = htole16(msglen);
2735 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2736 mcr->mcr_opktbuf.pb_next = 0;
2737 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2740 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2741 panic("%s: rsapriv: invalid msgin %x(0x%x)",
2742 device_get_nameunit(sc->sc_dev),
2743 rp->rpr_msgin.dma_paddr, rp->rpr_msgin.dma_size);
2745 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2746 panic("%s: rsapriv: invalid msgout %x(0x%x)",
2747 device_get_nameunit(sc->sc_dev),
2748 rp->rpr_msgout.dma_paddr, rp->rpr_msgout.dma_size);
2752 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2753 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2754 ctx->rpr_q_len = htole16(padlen);
2755 ctx->rpr_p_len = htole16(padlen);
2758 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2761 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2762 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2764 /* Enqueue and we're done... */
2766 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2768 ubsecstats.hst_modexpcrt++;
2774 if (rp->rpr_q.q_mcr.dma_map != NULL)
2775 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2776 if (rp->rpr_msgin.dma_map != NULL) {
2777 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2778 ubsec_dma_free(sc, &rp->rpr_msgin);
2780 if (rp->rpr_msgout.dma_map != NULL) {
2781 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2782 ubsec_dma_free(sc, &rp->rpr_msgout);
2784 kfree(rp, M_DEVBUF);
2786 krp->krp_status = err;
2793 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2795 kprintf("addr 0x%x (0x%x) next 0x%x\n",
2796 pb->pb_addr, pb->pb_len, pb->pb_next);
2800 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2802 kprintf("CTX (0x%x):\n", c->ctx_len);
2803 switch (letoh16(c->ctx_op)) {
2804 case UBS_CTXOP_RNGBYPASS:
2805 case UBS_CTXOP_RNGSHA1:
2807 case UBS_CTXOP_MODEXP:
2809 struct ubsec_ctx_modexp *cx = (void *)c;
2812 kprintf(" Elen %u, Nlen %u\n",
2813 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2814 len = (cx->me_N_len + 7)/8;
2815 for (i = 0; i < len; i++)
2816 kprintf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2821 kprintf("unknown context: %x\n", c->ctx_op);
2823 kprintf("END CTX\n");
2827 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2829 volatile struct ubsec_mcr_add *ma;
2833 kprintf(" pkts: %u, flags 0x%x\n",
2834 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2835 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2836 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2837 kprintf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2838 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2839 letoh16(ma->mcr_reserved));
2840 kprintf(" %d: ipkt ", i);
2841 ubsec_dump_pb(&ma->mcr_ipktbuf);
2842 kprintf(" %d: opkt ", i);
2843 ubsec_dump_pb(&ma->mcr_opktbuf);
2846 kprintf("END MCR\n");
2848 #endif /* UBSEC_DEBUG */
2851 * Return the number of significant bits of a big number.
2854 ubsec_ksigbits(struct crparam *cr)
2856 u_int plen = (cr->crp_nbits + 7) / 8;
2857 int i, sig = plen * 8;
2858 u_int8_t c, *p = cr->crp_p;
2860 for (i = plen - 1; i >= 0; i--) {
2863 while ((c & 0x80) == 0) {
2877 u_int8_t *src, u_int srcbits,
2878 u_int8_t *dst, u_int dstbits)
2883 slen = (srcbits + 7) / 8;
2884 dlen = (dstbits + 7) / 8;
2886 for (i = 0; i < slen; i++)
2888 for (i = 0; i < dlen - slen; i++)
2896 dst[di--] = dst[si--];
2903 for (i = dlen - 1; i > 0; i--)
2904 dst[i] = (dst[i] << n) |
2905 (dst[i - 1] >> (8 - n));
2906 dst[0] = dst[0] << n;
2913 u_int8_t *src, u_int srcbits,
2914 u_int8_t *dst, u_int dstbits)
2916 int slen, dlen, i, n;
2918 slen = (srcbits + 7) / 8;
2919 dlen = (dstbits + 7) / 8;
2922 for (i = 0; i < slen; i++)
2923 dst[i] = src[i + n];
2924 for (i = 0; i < dlen - slen; i++)
2929 for (i = 0; i < (dlen - 1); i++)
2930 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2931 dst[dlen - 1] = dst[dlen - 1] >> n;