sys/net/i4b/layer1/itjc/i4b_itjc_pci.c

   1 /*
   2  *   Copyright (c) 2000, 2001 Sergio Prallon. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_itjc_pci.c: NetJet-S hardware driver
  34  *      ----------------------------------------
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
  37  * $DragonFly: src/sys/net/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.11 2005/06/03 16:50:07 dillon Exp $
  38  *
  39  *      last edit-date: [Thu Jan 11 11:29:38 2001]
  40  *
  41  *---------------------------------------------------------------------------*/
  42
  43 #include "use_itjc.h"
  44 #include "use_pci.h"
  45 #include "opt_i4b.h"
  46
  47 #if (NITJC > 0)
  48
  49 #include <sys/param.h>
  50 #include <sys/kernel.h>
  51 #include <sys/systm.h>
  52 #include <sys/mbuf.h>
  53
  54 #include <machine/clock.h>
  55 #include <machine/bus_pio.h>
  56 #include <machine/bus.h>
  57 #include <machine/resource.h>
  58 #include <sys/bus.h>
  59 #include <sys/rman.h>
  60
  61 #include <bus/pci/pcireg.h>
  62 #include <bus/pci/pcivar.h>
  63
  64 #include <sys/socket.h>
  65 #include <sys/thread2.h>
  66 #include <net/if.h>
  67
  68 #include <net/i4b/include/machine/i4b_debug.h>
  69 #include <net/i4b/include/machine/i4b_ioctl.h>
  70 #include <net/i4b/include/machine/i4b_trace.h>
  71
  72 #include "../../include/i4b_global.h"
  73 #include "../../include/i4b_mbuf.h"
  74
  75 #include "../i4b_l1.h"
  76
  77 #include "i4b_hdlc.h"   /* XXXXXXXXXXXXXXXXXXXXXXXX */
  78
  79 #include "../isic/i4b_isic.h"
  80 #include "../isic/i4b_isac.h"
  81
  82 #include "i4b_itjc_ext.h"
  83
  84 #define PCI_TJNET_VID (0xe159)
  85 #define PCI_TJ300_DID (0x0001)
  86
  87
  88 /*
  89  * Function prototypes
  90  */
  91
  92 static int  itjc_probe(device_t dev);
  93 static int  itjc_attach(device_t dev);
  94 static void itjc_shutdown(device_t dev);
  95 static void itjc_intr(void *xsc);
  96 static int  itjc_dma_start(struct l1_softc *sc);
  97 static void itjc_dma_stop(struct l1_softc *sc);
  98 static void itjc_isac_intr(struct l1_softc *sc);
  99 static void itjc_init_linktab(struct l1_softc *sc);
 100 static void itjc_bchannel_setup(int unit, int h_chan, int bprot,
 101         int activate);
 102 static void itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp);
 103
 104
 105 /*
 106  * Shorter names to bus resource manager routines.
 107  */
 108
 109 #define itjc_bus_setup(sc)                                              \
 110         bus_space_handle_t h =                                          \
 111                 rman_get_bushandle((sc)->sc_resources.io_base[0]);      \
 112         bus_space_tag_t    t =                                          \
 113                 rman_get_bustag((sc)->sc_resources.io_base[0]);
 114
 115 #define itjc_read_1(port)       (bus_space_read_1(t, h, (port)))
 116 #define itjc_read_4(port)       (bus_space_read_4(t, h, (port)))
 117 #define itjc_write_1(port, data) (bus_space_write_1(t, h, (port), (data)))
 118 #define itjc_write_4(port, data) (bus_space_write_4(t, h, (port), (data)))
 119 #define itjc_read_multi_1(port, buf, size)                              \
 120         (bus_space_read_multi_1(t, h, (port), (buf), (size)))
 121 #define itjc_write_multi_1(port, buf, size)                             \
 122         (bus_space_write_multi_1(t, h, (port), (buf), (size)))
 123
 124
 125 /*---------------------------------------------------------------------------*
 126  *      Glue data to register ourselves as a PCI device driver.
 127  *---------------------------------------------------------------------------*/
 128
 129 static device_method_t itjc_pci_methods[] =
 130 {
 131         /* Device interface */
 132         DEVMETHOD(device_probe,         itjc_probe),
 133         DEVMETHOD(device_attach,        itjc_attach),
 134         DEVMETHOD(device_shutdown,      itjc_shutdown),
 135
 136         /* bus interface */
 137         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 138         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 139
 140         { 0, 0 }
 141 };
 142
 143 static driver_t itjc_pci_driver =
 144 {
 145         "itjc",
 146         itjc_pci_methods,
 147         sizeof(struct l1_softc)
 148 };
 149
 150 static devclass_t itjc_pci_devclass;
 151
 152 DRIVER_MODULE(netjet, pci, itjc_pci_driver, itjc_pci_devclass, 0, 0);
 153
 154 /*
 155  * Jump table for multiplex routines.
 156  */
 157
 158 struct i4b_l1mux_func itjc_l1mux_func =
 159 {
 160         itjc_ret_linktab,
 161         itjc_set_linktab,
 162         itjc_mph_command_req,
 163         itjc_ph_data_req,
 164         itjc_ph_activate_req,
 165 };
 166
 167 struct l1_softc *itjc_scp[ITJC_MAXUNIT];
 168
 169
 170 /*---------------------------------------------------------------------------*
 171  *      Tiger300/320 PCI ASIC registers.
 172  *---------------------------------------------------------------------------*/
 173
 174 /*
 175  *      Register offsets from i/o base.
 176  */
 177 enum tiger_regs
 178 {
 179         TIGER_RESET_PIB_CL_TIME = 0x00,
 180         TIGER_DMA_OPER          = 0x01,
 181         TIGER_AUX_PORT_CNTL     = 0x02,
 182         TIGER_AUX_PORT_DATA     = 0x03,
 183         TIGER_INT0_MASK         = 0x04,
 184         TIGER_INT1_MASK         = 0x05,
 185         TIGER_INT0_STATUS       = 0x06,
 186         TIGER_INT1_STATUS       = 0x07,
 187         TIGER_DMA_WR_START_ADDR = 0x08,
 188         TIGER_DMA_WR_INT_ADDR   = 0x0C,
 189         TIGER_DMA_WR_END_ADDR   = 0x10,
 190         TIGER_DMA_WR_CURR_ADDR  = 0x14,
 191         TIGER_DMA_RD_START_ADDR = 0x18,
 192         TIGER_DMA_RD_INT_ADDR   = 0x1C,
 193         TIGER_DMA_RD_END_ADDR   = 0x20,
 194         TIGER_DMA_RD_CURR_ADDR  = 0x24,
 195         TIGER_PULSE_COUNTER     = 0x28,
 196 };
 197
 198 /*
 199  * Bits on the above registers.
 200  */
 201
 202 enum tiger_reg_bits
 203 {
 204 /* Reset and PIB Cycle Timing */
 205
 206         TIGER_DMA_OP_MODE_MASK          = 0x80,
 207                 TIGER_SELF_ADDR_DMA     = 0x00, /* Wrap around ending addr */
 208                 TIGER_NORMAL_DMA        = 0x80, /* Stop at ending addr */
 209
 210         TIGER_DMA_INT_MODE_MASK         = 0x40,
 211                 TIGER_DONT_LATCH_DMA_INT= 0x00, /* Bits on int0 status will be
 212                                                    set only while curr addr
 213                                                    equals int or end addr */
 214                 TIGER_LATCH_DMA_INT     = 0x40, /* Bits on int0 status remain
 215                                                    set until cleared by CPU */
 216
 217         TIGER_PIB_CYCLE_TIMING_MASK     = 0x30,
 218                 TIGER_PIB_3_CYCLES      = 0x00,
 219                 TIGER_PIB_5_CYCLES      = 0x01,
 220                 TIGER_PIB_12_CYCLES     = 0x10,
 221
 222         TIGER_RESET_MASK                = 0x0F,
 223                 TIGER_RESET_PULSE_COUNT = 0x08,
 224                 TIGER_RESET_SERIAL_PORT = 0x04,
 225                 TIGER_RESET_DMA_LOGIC   = 0x02,
 226                 TIGER_RESET_EXTERNAL    = 0x01,
 227                 TIGER_RESET_ALL         = 0x0F,
 228
 229 /* DMA Operation */
 230         TIGER_DMA_RESTART_MASK          = 0x02,
 231                 TIGER_HOLD_DMA          = 0x00,
 232                 TIGER_RESTART_DMA       = 0x00,
 233
 234         TIGER_DMA_ENABLE_MASK           = 0x01,
 235                 TIGER_ENABLE_DMA        = 0x01,
 236                 TIGER_DISABLE_DMA       = 0x00,
 237
 238 /* AUX Port Control & Data plus Interrupt 1 Mask & Status  */
 239         TIGER_AUX_7_MASK                = 0x80,
 240         TIGER_AUX_6_MASK                = 0x40,
 241         TIGER_AUX_5_MASK                = 0x20,
 242         TIGER_AUX_4_MASK                = 0x10,
 243         TIGER_ISAC_INT_MASK             = 0x10,
 244         TIGER_AUX_3_MASK                = 0x08,
 245         TIGER_AUX_2_MASK                = 0x04,
 246         TIGER_AUX_1_MASK                = 0x02,
 247         TIGER_AUX_0_MASK                = 0x01,
 248
 249 /* AUX Port Control */
 250                 TIGER_AUX_7_IS_INPUT    = 0x00,
 251                 TIGER_AUX_7_IS_OUTPUT   = 0x80,
 252                 TIGER_AUX_6_IS_INPUT    = 0x00,
 253                 TIGER_AUX_6_IS_OUTPUT   = 0x40,
 254                 TIGER_AUX_5_IS_INPUT    = 0x00,
 255                 TIGER_AUX_5_IS_OUTPUT   = 0x20,
 256                 TIGER_AUX_4_IS_INPUT    = 0x00,
 257                 TIGER_AUX_4_IS_OUTPUT   = 0x10,
 258                 TIGER_AUX_3_IS_INPUT    = 0x00,
 259                 TIGER_AUX_3_IS_OUTPUT   = 0x80,
 260                 TIGER_AUX_2_IS_INPUT    = 0x00,
 261                 TIGER_AUX_2_IS_OUTPUT   = 0x40,
 262                 TIGER_AUX_1_IS_INPUT    = 0x00,
 263                 TIGER_AUX_1_IS_OUTPUT   = 0x20,
 264                 TIGER_AUX_0_IS_INPUT    = 0x00,
 265                 TIGER_AUX_0_IS_OUTPUT   = 0x10,
 266                 TIGER_AUX_NJ_DEFAULT    = 0xEF, /* All but ISAC int is output */
 267
 268 /* Interrupt 0 Mask & Status */
 269         TIGER_PCI_TARGET_ABORT_INT_MASK = 0x20,
 270                 TIGER_NO_TGT_ABORT_INT  = 0x00,
 271                 TIGER_TARGET_ABORT_INT  = 0x20,
 272         TIGER_PCI_MASTER_ABORT_INT_MASK = 0x10,
 273                 TIGER_NO_MST_ABORT_INT  = 0x00,
 274                 TIGER_MASTER_ABORT_INT  = 0x10,
 275         TIGER_DMA_RD_END_INT_MASK       = 0x08,
 276                 TIGER_NO_RD_END_INT     = 0x00,
 277                 TIGER_RD_END_INT        = 0x08,
 278         TIGER_DMA_RD_INT_INT_MASK       = 0x04,
 279                 TIGER_NO_RD_INT_INT     = 0x00,
 280                 TIGER_RD_INT_INT        = 0x04,
 281         TIGER_DMA_WR_END_INT_MASK       = 0x02,
 282                 TIGER_NO_WR_END_INT     = 0x00,
 283                 TIGER_WR_END_INT        = 0x02,
 284         TIGER_DMA_WR_INT_INT_MASK       = 0x01,
 285                 TIGER_NO_WR_INT_INT     = 0x00,
 286                 TIGER_WR_INT_INT        = 0x01,
 287
 288 /* Interrupt 1 Mask & Status */
 289                 TIGER_NO_AUX_7_INT      = 0x00,
 290                 TIGER_AUX_7_INT         = 0x80,
 291                 TIGER_NO_AUX_6_INT      = 0x00,
 292                 TIGER_AUX_6_INT         = 0x40,
 293                 TIGER_NO_AUX_5_INT      = 0x00,
 294                 TIGER_AUX_5_INT         = 0x20,
 295                 TIGER_NO_AUX_4_INT      = 0x00,
 296                 TIGER_AUX_4_INT         = 0x10,
 297                 TIGER_NO_ISAC_INT       = 0x00,
 298                 TIGER_ISAC_INT          = 0x10,
 299                 TIGER_NO_AUX_3_INT      = 0x00,
 300                 TIGER_AUX_3_INT         = 0x08,
 301                 TIGER_NO_AUX_2_INT      = 0x00,
 302                 TIGER_AUX_2_INT         = 0x04,
 303                 TIGER_NO_AUX_1_INT      = 0x00,
 304                 TIGER_AUX_1_INT         = 0x02,
 305                 TIGER_NO_AUX_0_INT      = 0x00,
 306                 TIGER_AUX_0_INT         = 0x01
 307 };
 308
 309 /*
 310  * Peripheral Interface Bus definitions. This is an ISA like bus
 311  * created by the Tiger ASIC to keep ISA chips like the ISAC happy
 312  * on a PCI environment.
 313  *
 314  * Since the PIB only supplies 4 addressing lines, the 2 higher bits
 315  * (A4 & A5) of the ISAC register addresses are wired on the 2 lower
 316  * AUX lines. Another restriction is that all I/O to the PIB (8bit
 317  * wide) is mapped on the PCI side as 32bit data. So the PCI address
 318  * of a given ISAC register has to be multiplied by 4 before being
 319  * added to the PIB base offset.
 320  */
 321 enum tiger_pib_regs_defs
 322 {
 323         /* Offset from the I/O base to the ISAC registers. */
 324         PIB_OFFSET              = 0xC0,
 325         PIB_LO_ADDR_MASK        = 0x0F,
 326         PIB_HI_ADDR_MASK        = 0x30,
 327         PIB_LO_ADDR_SHIFT       = 2,    /* Align on dword boundary */
 328         PIB_HI_ADDR_SHIFT       = 4     /* Right shift to AUX_1 & AUX_0 */
 329 };
 330
 331
 332 #define itjc_set_pib_addr_msb(a)                                        \
 333 (                                                                       \
 334         itjc_write_1(TIGER_AUX_PORT_DATA,                               \
 335                 ((a) & PIB_HI_ADDR_MASK) >> PIB_HI_ADDR_SHIFT)          \
 336 )
 337
 338 #define itjc_pib_2_pci(a)                                               \
 339 (                                                                       \
 340         (((a) & PIB_LO_ADDR_MASK) << PIB_LO_ADDR_SHIFT) + PIB_OFFSET    \
 341 )
 342
 343 #define itjc_get_dma_offset(ctx,reg)                                    \
 344 (                                                                       \
 345         (u_int16_t)((bus_addr_t)itjc_read_4((reg)) - (ctx)->bus_addr)   \
 346 )
 347
 348
 349 /*
 350  * IOM-2 serial channel 0 DMA data ring buffers.
 351  *
 352  * The Tiger300/320 ASIC do not nothing more than transfer via DMA the
 353  * first 32 bits of every IOM-2 frame on the serial interface to the
 354  * ISAC. So we have no framing/deframing facilities like we would have
 355  * with an HSCX, having to do the job with CPU cycles. On the plus side
 356  * we are able to specify large rings which can limit the occurrence of
 357  * over/underruns.
 358  */
 359
 360 enum
 361 {
 362         ITJC_RING_SLOT_WORDS    = 64,
 363         ITJC_RING_WORDS         = 3 * ITJC_RING_SLOT_WORDS,
 364         ITJC_RING_SLOT_BYTES    = 4 * ITJC_RING_SLOT_WORDS,
 365         ITJC_RING_BYTES         = 4 * ITJC_RING_WORDS,
 366         ITJC_DMA_POOL_WORDS     = 2 * ITJC_RING_WORDS,
 367         ITJC_DMA_POOL_BYTES     = 4 * ITJC_DMA_POOL_WORDS
 368 };
 369
 370 #define itjc_ring_add(x, d)     (((x) + 4 * (d)) % ITJC_RING_BYTES)
 371 #define itjc_ring_sub(x, d)     (((x) + ITJC_RING_BYTES - 4 * (d))      \
 372                                         % ITJC_RING_BYTES)
 373
 374
 375 enum
 376 {
 377         TIGER_CH_A              = 0,
 378         TIGER_CH_B              = 1,
 379
 380         HSCX_CH_A               = 0,    /* For compatibility reasons. */
 381         HSCX_CH_B               = 1,
 382 };
 383
 384 enum
 385 {
 386         ITJC_TEL_SILENCE_BYTE   = 0x00,
 387         ITJC_HDLC_FLAG_BYTE     = 0x7E,
 388         ITJC_HDLC_ABORT_BYTE    = 0xFF
 389 };
 390
 391 /*
 392  * Hardware DMA control block (one per card).
 393  */
 394 typedef enum
 395 {
 396         ITJC_DS_LOAD_FAILED     = -1,
 397         ITJC_DS_FREE            =  0,
 398         ITJC_DS_LOADING,
 399         ITJC_DS_STOPPED,
 400         ITJC_DS_RUNNING
 401 }
 402         dma_state_t;
 403
 404 typedef struct
 405 {
 406         dma_state_t     state;
 407         u_int8_t        *pool;
 408         bus_addr_t      bus_addr;
 409         bus_dma_tag_t   tag;
 410         bus_dmamap_t    map;
 411         int             error;
 412 }
 413         dma_context_t;
 414
 415 dma_context_t
 416         dma_context     [ ITJC_MAXUNIT ];
 417
 418 /*
 419  * B-channel DMA control blocks (4 per card -- 1 RX & 1 TX per channel).
 420  */
 421 typedef enum
 422 {
 423         ITJC_RS_IDLE    = 0,
 424         ITJC_RS_ACTIVE
 425 }
 426         dma_rx_state_t;
 427
 428 typedef enum
 429 {
 430         ITJC_TS_IDLE    = 0,
 431         ITJC_TS_ACTIVE,
 432         ITJC_TS_AFTER_XDU
 433 }
 434         dma_tx_state_t;
 435
 436 typedef struct
 437 {
 438         u_int8_t        *ring;
 439         bus_addr_t      bus_addr;
 440         u_int16_t       next_read;
 441         u_int16_t       hdlc_len;
 442         u_int16_t       hdlc_tmp;
 443         u_int16_t       hdlc_crc;
 444         u_int16_t       hdlc_ib;
 445         u_int8_t        hdlc_blevel;
 446         u_int8_t        hdlc_flag;
 447         dma_rx_state_t  state;
 448 }
 449         dma_rx_context_t;
 450
 451 typedef struct
 452 {
 453         u_int8_t        *ring;
 454         bus_addr_t      bus_addr;
 455         u_int16_t       next_write;
 456         u_int32_t       hdlc_tmp;
 457         u_int16_t       hdlc_blevel;
 458         u_int16_t       hdlc_crc;
 459         u_int16_t       hdlc_ib;
 460         u_int16_t       next_frame;
 461         u_int16_t       filled;
 462         u_int8_t        hdlc_flag;
 463         dma_tx_state_t  state;
 464 }
 465         dma_tx_context_t;
 466
 467 dma_rx_context_t
 468         dma_rx_context  [ ITJC_MAXUNIT ] [ 2 ];
 469
 470 dma_tx_context_t
 471         dma_tx_context  [ ITJC_MAXUNIT ] [ 2 ];
 472
 473 /*
 474  * Used by the mbuf handling functions.
 475  */
 476 typedef enum
 477 {
 478         ITJC_MB_CURR = 0,
 479         ITJC_MB_NEXT = 1,
 480         ITJC_MB_NEW  = 2
 481 }
 482         which_mb_t;
 483
 484
 485 /*---------------------------------------------------------------------------*
 486  *      itjc_map_callback - get DMA bus address from resource mgr.
 487  *---------------------------------------------------------------------------*/
 488 static void
 489 itjc_map_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 490 {
 491         dma_context_t           *ctx = (dma_context_t *)arg;
 492
 493         if (error)
 494         {
 495                 ctx->error = error;
 496                 ctx->state = ITJC_DS_LOAD_FAILED;
 497                 return;
 498         }
 499
 500         ctx->bus_addr = segs->ds_addr;
 501         ctx->state = ITJC_DS_STOPPED;
 502 }
 503
 504
 505 /*---------------------------------------------------------------------------*
 506  *      itjc_dma_start - Complete DMA setup & start the Tiger DMA engine.
 507  *---------------------------------------------------------------------------*/
 508 static int
 509 itjc_dma_start(struct l1_softc *sc)
 510 {
 511         int                     unit    = sc->sc_unit;
 512         dma_context_t           *ctx    = &dma_context[unit];
 513         dma_rx_context_t        *rxc    = &dma_rx_context[unit][0];
 514         dma_tx_context_t        *txc    = &dma_tx_context[unit][0];
 515         bus_addr_t              ba;
 516         u_int8_t                i;
 517         u_int32_t               *pool_end,
 518                                 *ip;
 519
 520         itjc_bus_setup(sc);
 521
 522         /* See if it is already running. */
 523
 524         if (ctx->state == ITJC_DS_RUNNING)
 525                 return 0;
 526
 527         if (ctx->state == ITJC_DS_LOAD_FAILED)
 528         {
 529                 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA map loading "
 530                         "failed (error=%d).\n", unit, ctx->error);
 531                 return 1;
 532         }
 533
 534         if (ctx->state != ITJC_DS_STOPPED)
 535         {
 536                 NDBGL1(L1_ERROR, "itjc%d: dma_start: Unexpected DMA "
 537                         "state (%d).\n", unit, ctx->state);
 538                 return 1;
 539         }
 540
 541         /*
 542          * Initialize the DMA control structures (hardware & B-channel).
 543          */
 544         ba = ctx->bus_addr;
 545
 546         txc->ring = ctx->pool + TIGER_CH_A;
 547         rxc->ring = ctx->pool + TIGER_CH_A + ITJC_RING_BYTES;
 548
 549         txc->bus_addr = ba;
 550         rxc->bus_addr = ba + ITJC_RING_BYTES;
 551
 552         ++rxc; ++txc;
 553
 554         txc->ring = ctx->pool + TIGER_CH_B;
 555         rxc->ring = ctx->pool + TIGER_CH_B + ITJC_RING_BYTES;
 556
 557         txc->bus_addr = ba;
 558         rxc->bus_addr = ba + ITJC_RING_BYTES;
 559
 560         /*
 561          * Fill the DMA ring buffers with IOM-2 channel 0 frames made of
 562          * idle/abort sequences for the B & D channels and NOP for IOM-2
 563          * cmd/ind, monitor handshake & data.
 564          */
 565         pool_end = (u_int32_t *)ctx->pool + ITJC_DMA_POOL_WORDS;
 566         for (ip = (u_int32_t *)ctx->pool; ip < pool_end; ++ip)
 567                 *ip = 0xFFFFFFFF;
 568
 569         /*
 570          * Program the Tiger DMA gears.
 571          */
 572
 573         itjc_write_4(TIGER_DMA_WR_START_ADDR, ba);
 574         itjc_write_4(TIGER_DMA_WR_INT_ADDR, ba + ITJC_RING_SLOT_BYTES - 4);
 575         itjc_write_4(TIGER_DMA_WR_END_ADDR, ba + ITJC_RING_BYTES - 4);
 576
 577         ba += ITJC_RING_BYTES;
 578
 579         itjc_write_4(TIGER_DMA_RD_START_ADDR, ba);
 580         itjc_write_4(TIGER_DMA_RD_INT_ADDR, ba + ITJC_RING_SLOT_BYTES * 2 - 4);
 581         itjc_write_4(TIGER_DMA_RD_END_ADDR, ba + ITJC_RING_BYTES - 4);
 582
 583         itjc_write_1(TIGER_INT0_MASK,
 584                 TIGER_WR_END_INT | TIGER_WR_INT_INT | TIGER_RD_INT_INT);
 585
 586         itjc_write_1(TIGER_DMA_OPER, TIGER_ENABLE_DMA);
 587
 588         /*
 589          * See if it really started.
 590          */
 591         ba = itjc_read_4(TIGER_DMA_RD_CURR_ADDR);
 592         for (i = 0; i < 10; ++i)
 593         {
 594                 DELAY(SEC_DELAY/1000);
 595                 if (ba != itjc_read_4(TIGER_DMA_RD_CURR_ADDR))
 596                 {
 597                         ctx->state = ITJC_DS_RUNNING;
 598                         return 0;
 599                 }
 600         }
 601
 602         NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA start failed.\n ", unit);
 603         return 1;
 604 }
 605
 606
 607 /*---------------------------------------------------------------------------*
 608  *      itjc_dma_stop - Stop the Tiger DMA engine.
 609  *---------------------------------------------------------------------------*/
 610 void
 611 itjc_dma_stop(struct l1_softc *sc)
 612 {
 613         dma_context_t           *ctx    = &dma_context[sc->sc_unit];
 614
 615         itjc_bus_setup(sc);
 616
 617         /* Only stop the DMA if it is running. */
 618
 619         if (ctx->state != ITJC_DS_RUNNING)
 620                 return;
 621
 622         itjc_write_1(TIGER_DMA_OPER, TIGER_DISABLE_DMA);
 623         DELAY(SEC_DELAY/1000);
 624
 625         ctx->state = ITJC_DS_STOPPED;
 626 }
 627
 628
 629 /*---------------------------------------------------------------------------*
 630  *      itjc_bchannel_dma_setup - The DMA side of itjc_bchannel_setup.
 631  *---------------------------------------------------------------------------*/
 632 static void
 633 itjc_bchannel_dma_setup(struct l1_softc *sc, int h_chan, int activate)
 634 {
 635         dma_rx_context_t        *rxc  = &dma_rx_context[sc->sc_unit][h_chan];
 636         dma_tx_context_t        *txc  = &dma_tx_context[sc->sc_unit][h_chan];
 637
 638         l1_bchan_state_t        *chan = &sc->sc_chan[h_chan];
 639
 640         u_int8_t                fill_byte,
 641                                 *ring_end,
 642                                 *cp;
 643
 644         crit_enter();
 645         itjc_bus_setup(sc);
 646
 647         if (activate)
 648         {
 649                 /*
 650                  * Get the DMA engine going if it's not running already.
 651                  */
 652                 itjc_dma_start(sc);
 653
 654                 rxc->hdlc_len   = rxc->hdlc_tmp    = rxc->hdlc_crc  = 0;
 655                 rxc->hdlc_ib    = rxc->hdlc_blevel = rxc->hdlc_flag = 0;
 656
 657                 txc->hdlc_tmp   = txc->hdlc_blevel = txc->hdlc_crc  = 0;
 658                 txc->hdlc_ib    = 0;
 659                 txc->hdlc_flag  = 2;
 660                 txc->filled     = 0;
 661
 662                 if (chan->bprot == BPROT_NONE)
 663                         fill_byte = ITJC_TEL_SILENCE_BYTE;
 664                 else
 665                         fill_byte = ITJC_HDLC_ABORT_BYTE;
 666
 667                 ring_end = rxc->ring + ITJC_RING_BYTES;
 668                 for (cp = rxc->ring; cp < ring_end; cp += 4)
 669                         *cp = fill_byte;
 670
 671                 ring_end = txc->ring + ITJC_RING_BYTES;
 672                 for (cp = txc->ring; cp < ring_end; cp += 4)
 673                         *cp = fill_byte;
 674
 675                 rxc->next_read  =
 676                         itjc_get_dma_offset(rxc, TIGER_DMA_RD_CURR_ADDR);
 677
 678                 txc->next_frame = txc->next_write =
 679                         itjc_get_dma_offset(txc, TIGER_DMA_WR_CURR_ADDR);
 680
 681                 rxc->state      = ITJC_RS_ACTIVE;
 682                 txc->state      = ITJC_TS_AFTER_XDU;
 683         }
 684         else
 685         {
 686                 dma_rx_context_t        *rxc2;
 687
 688                 txc->state      = ITJC_TS_IDLE;
 689                 rxc->state      = ITJC_RS_IDLE;
 690
 691                 rxc2 = &dma_rx_context[sc->sc_unit][0];
 692
 693                 if (rxc2->state == ITJC_RS_IDLE
 694                 && rxc2[1].state == ITJC_RS_IDLE)
 695                         itjc_dma_stop(sc);
 696         }
 697
 698         crit_exit();
 699 }
 700
 701
 702 /*---------------------------------------------------------------------------*
 703  *      Mbuf & if_queues management routines.
 704  *---------------------------------------------------------------------------*/
 705
 706 static u_int8_t *
 707 itjc_get_rx_mbuf(l1_bchan_state_t *chan, u_int8_t **dst_end_p,
 708 which_mb_t which)
 709 {
 710         struct mbuf     *mbuf = chan->in_mbuf;
 711
 712         if (mbuf == NULL && which == ITJC_MB_NEW)
 713         {
 714                 if ((mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 715                         panic("itjc_get_rx_mbuf: cannot allocate mbuf!");
 716
 717                 chan->in_mbuf  = mbuf;
 718                 chan->in_cbptr = (u_int8_t *)mbuf->m_data;
 719                 chan->in_len   = 0;
 720         }
 721
 722         if (dst_end_p != NULL)
 723         {
 724                 if (mbuf != NULL)
 725                         *dst_end_p = (u_int8_t *)(mbuf->m_data)
 726                                 + BCH_MAX_DATALEN;
 727                 else
 728                         *dst_end_p = NULL;
 729         }
 730
 731         return chan->in_cbptr;
 732 }
 733
 734
 735 static void
 736 itjc_save_rx_mbuf(l1_bchan_state_t *chan, u_int8_t * dst)
 737 {
 738         struct mbuf     *mbuf = chan->in_mbuf;
 739
 740         if (dst != NULL && mbuf != NULL)
 741         {
 742                 chan->in_cbptr = dst;
 743                 chan->in_len   = dst - (u_int8_t *)mbuf->m_data;
 744         }
 745         else if (dst == NULL && mbuf == NULL)
 746         {
 747                 chan->in_cbptr = NULL;
 748                 chan->in_len   = 0;
 749         }
 750         else
 751                 panic("itjc_save_rx_mbuf: stale pointer dst=%p mbuf=%p "
 752                         "in_cbptr=%p in_len=%d", dst, mbuf,
 753                         chan->in_cbptr, chan->in_len);
 754 }
 755
 756
 757 static void
 758 itjc_free_rx_mbuf(l1_bchan_state_t *chan)
 759 {
 760         struct mbuf     *mbuf = chan->in_mbuf;
 761
 762         if (mbuf != NULL)
 763                 i4b_Bfreembuf(mbuf);
 764
 765         chan->in_mbuf  = NULL;
 766         chan->in_cbptr = NULL;
 767         chan->in_len   = 0;
 768 }
 769
 770
 771 static void
 772 itjc_put_rx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan, u_int16_t len)
 773 {
 774         i4b_trace_hdr_t hdr;
 775         struct mbuf     *mbuf    = chan->in_mbuf;
 776         u_int8_t        *data    = mbuf->m_data;
 777         int             activity = 1;
 778
 779         mbuf->m_pkthdr.len = mbuf->m_len = len;
 780
 781         if (sc->sc_trace & TRACE_B_RX)
 782         {
 783                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 784                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 785                 hdr.dir = FROM_NT;
 786                 hdr.count = ++sc->sc_trace_bcount;
 787                 MICROTIME(hdr.time);
 788                 i4b_l1_trace_ind(&hdr, len, data);
 789         }
 790
 791         if (chan->bprot == BPROT_NONE)
 792         {
 793                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 794
 795                 /* move rx'd data to rx queue */
 796
 797                 if (!IF_QFULL(&chan->rx_queue))
 798                 {
 799                         IF_ENQUEUE(&chan->rx_queue, mbuf);
 800                 }
 801                 else
 802                 {
 803                         i4b_Bfreembuf(mbuf);
 804                         len = 0;
 805                 }
 806         }
 807
 808         if (len != 0)
 809         {
 810                 chan->rxcount += len;
 811
 812                 (*chan->isic_drvr_linktab->bch_rx_data_ready)
 813                         (chan->isic_drvr_linktab->unit);
 814         }
 815
 816         if (activity)
 817                 (*chan->isic_drvr_linktab->bch_activity)
 818                         (chan->isic_drvr_linktab->unit, ACT_RX);
 819
 820         chan->in_mbuf  = NULL;
 821         chan->in_cbptr = NULL;
 822         chan->in_len   = 0;
 823 }
 824
 825
 826 #define itjc_free_tx_mbufs(chan)                                        \
 827 {                                                                       \
 828         i4b_Bfreembuf((chan)->out_mbuf_head);                           \
 829         (chan)->out_mbuf_cur = (chan)->out_mbuf_head = NULL;            \
 830         (chan)->out_mbuf_cur_ptr = NULL;                                \
 831         (chan)->out_mbuf_cur_len = 0;                                   \
 832 }
 833
 834
 835 static u_int16_t
 836 itjc_get_tx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan,
 837         u_int8_t **src_p, which_mb_t which)
 838 {
 839         i4b_trace_hdr_t hdr;
 840         struct mbuf     *mbuf = chan->out_mbuf_cur;
 841         u_int8_t        activity = 1;
 842         u_int16_t       len;
 843         void            *data;
 844
 845         switch (which)
 846         {
 847         case ITJC_MB_CURR:
 848                 if (mbuf != NULL)
 849                 {
 850                         *src_p = chan->out_mbuf_cur_ptr;
 851                         return   chan->out_mbuf_cur_len;
 852                 }
 853
 854                 break;
 855
 856         case ITJC_MB_NEXT:
 857                 if (mbuf != NULL)
 858                 {
 859                         chan->txcount += mbuf->m_len;
 860
 861                         mbuf = mbuf->m_next;
 862
 863                         if (mbuf != NULL)
 864                                 goto new_mbuf;
 865                 }
 866
 867                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 868                 chan->out_mbuf_cur_len = 0;
 869
 870                 if (chan->out_mbuf_head != NULL)
 871                 {
 872                         i4b_Bfreembuf(chan->out_mbuf_head);
 873                         chan->out_mbuf_head = NULL;
 874                 }
 875
 876                 return 0;
 877
 878         case ITJC_MB_NEW:
 879                 if (mbuf != NULL)
 880                         chan->txcount += mbuf->m_len;
 881         }
 882
 883         if (chan->out_mbuf_head != NULL)
 884                 i4b_Bfreembuf(chan->out_mbuf_head);
 885
 886         IF_DEQUEUE(&chan->tx_queue, mbuf);
 887
 888         if (mbuf == NULL)
 889         {
 890                 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 891                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 892                 chan->out_mbuf_cur_len = 0;
 893
 894                 chan->state &= ~(HSCX_TX_ACTIVE);
 895
 896                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)
 897                         (chan->isic_drvr_linktab->unit);
 898
 899                 return 0;
 900         }
 901
 902         chan->out_mbuf_head = mbuf;
 903
 904 new_mbuf:
 905         chan->out_mbuf_cur      = mbuf;
 906         chan->out_mbuf_cur_ptr  = data = mbuf->m_data;
 907         chan->out_mbuf_cur_len  = len  = mbuf->m_len;
 908
 909         chan->state |= HSCX_TX_ACTIVE;
 910
 911         if (sc->sc_trace & TRACE_B_TX)
 912         {
 913                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 914                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 915                 hdr.dir = FROM_TE;
 916                 hdr.count = ++sc->sc_trace_bcount;
 917                 MICROTIME(hdr.time);
 918                 i4b_l1_trace_ind(&hdr, len, data);
 919         }
 920
 921         if (chan->bprot == BPROT_NONE)
 922                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 923
 924         if (activity)
 925                 (*chan->isic_drvr_linktab->bch_activity)
 926                         (chan->isic_drvr_linktab->unit, ACT_TX);
 927
 928         *src_p = data;
 929         return len;
 930 }
 931
 932
 933 #define itjc_save_tx_mbuf(chan, src, dst)                               \
 934 (                                                                       \
 935         (chan)->out_mbuf_cur != NULL ?                                  \
 936         (                                                               \
 937                 (chan)->out_mbuf_cur_ptr = (src),                       \
 938                 (chan)->out_mbuf_cur_len = (len)                        \
 939         )                                                               \
 940         :                                                               \
 941                 0                                                       \
 942 )
 943
 944
 945 /*---------------------------------------------------------------------------*
 946  *      B-channel interrupt service routines.
 947  *---------------------------------------------------------------------------*/
 948
 949 /*
 950  * Since the Tiger ASIC doesn't produce a XMIT underflow indication,
 951  * we need to deduce it ourselves. This is somewhat tricky because we
 952  * are dealing with modulo m arithmetic. The idea here is to have a
 953  * "XDU zone" ahead of the writing pointer sized 1/3 of total ring
 954  * length (a ring slot). If the hardware DMA pointer is found there we
 955  * consider that a XDU has occurred. To complete the scheme, we never
 956  * let the ring have more than 2 slots of (unsent) data and adjust the
 957  * interrupt registers to cause an interrupt at every slot.
 958  */
 959 static u_int8_t
 960 itjc_xdu(struct l1_softc *sc, l1_bchan_state_t *chan, dma_tx_context_t *ctx,
 961 u_int16_t *dst_p, u_int16_t *dst_end_p, u_int8_t tx_restart)
 962 {
 963         u_int8_t        xdu;
 964
 965         u_int16_t       dst_end,
 966                         dst,
 967                         dma,
 968                         dma_l,
 969                         dma_h,
 970                         xdu_l,
 971                         xdu_h;
 972
 973         itjc_bus_setup(sc);
 974
 975         /*
 976          * Since the hardware is running, be conservative and assume
 977          * the pointer location has a `fuzy' error factor.
 978          */
 979         dma   = itjc_get_dma_offset(ctx, TIGER_DMA_WR_CURR_ADDR);
 980         dma_l = dma;
 981         dma_h = itjc_ring_add(dma, 1);
 982
 983         dst_end = itjc_ring_sub(dma_l, ITJC_RING_SLOT_WORDS);
 984
 985         if (ctx->state != ITJC_TS_ACTIVE)
 986         {
 987                 xdu = (ctx->state == ITJC_TS_AFTER_XDU);
 988                 dst = itjc_ring_add(dma_h, 4);
 989                 goto done;
 990         }
 991
 992         /*
 993          * Check for xmit underruns.
 994          */
 995         xdu_l = dst = ctx->next_write;
 996         xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
 997
 998         if (xdu_l < xdu_h)
 999                 xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1000                         || (xdu_l <= dma_h && dma_h < xdu_h);
1001         else
1002                 xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1003                         || (xdu_l <= dma_h || dma_h < xdu_h);
1004
1005         if (xdu)
1006         {
1007                 ctx->state = ITJC_TS_AFTER_XDU;
1008
1009                 dst = itjc_ring_add(dma_h, 4);
1010         }
1011         else if (tx_restart)
1012         {
1013                 /*
1014                  * See if we still can restart from immediately
1015                  * after the last frame sent. It's a XDU test but
1016                  * using the real data end on the comparsions. We
1017                  * don't consider XDU an error here because we were
1018                  * just trying to avoid send a filling gap between
1019                  * frames. If it's already sent no harm is done.
1020                  */
1021                 xdu_l = dst = ctx->next_frame;
1022                 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1023
1024                 if (xdu_l < xdu_h)
1025                         xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1026                                 || (xdu_l <= dma_h && dma_h < xdu_h);
1027                 else
1028                         xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1029                                 || (xdu_l <= dma_h || dma_h < xdu_h);
1030
1031                 if (xdu)
1032                         dst = itjc_ring_add(dma_h, 4);
1033
1034                 xdu = 0;
1035         }
1036
1037 done:
1038         if (dst_p != NULL)
1039                 *dst_p = dst;
1040
1041         if (dst_end_p != NULL)
1042                 *dst_end_p = dst_end;
1043
1044         ctx->next_write = dst_end;
1045
1046         return xdu;
1047 }
1048
1049
1050 #define itjc_rotate_hdlc_flag(blevel)                                   \
1051         ((u_int8_t)(0x7E7E >> (8 - (u_int8_t)((blevel) >> 8))))
1052
1053
1054 static void
1055 itjc_dma_rx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1056 dma_rx_context_t *ctx)
1057 {
1058         u_int8_t        *ring,
1059                         *dst,
1060                         *dst_end,
1061                         flag,
1062                         blevel;
1063
1064         u_int16_t       dma,
1065                         src,
1066                         tmp2,
1067                         tmp,
1068                         len,
1069                         crc,
1070                         ib;
1071
1072         itjc_bus_setup(sc);
1073
1074
1075         if (ctx->state == ITJC_RS_IDLE)
1076                 return;
1077
1078         ring = ctx->ring;
1079         dma = itjc_get_dma_offset(ctx, TIGER_DMA_RD_CURR_ADDR);
1080         dma = itjc_ring_sub(dma, 1);
1081         src = ctx->next_read;
1082
1083         if (chan->bprot == BPROT_NONE)
1084         {
1085                 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_CURR);
1086
1087                 while (src != dma)
1088                 {
1089                         if (dst == NULL)
1090                                 dst = itjc_get_rx_mbuf(chan, &dst_end,
1091                                         ITJC_MB_NEW);
1092
1093                         *dst++ = ring[src];
1094                         src = itjc_ring_add(src, 1);
1095
1096                         if (dst >= dst_end)
1097                         {
1098                                 itjc_put_rx_mbuf(sc, chan, BCH_MAX_DATALEN);
1099                                 dst = dst_end = NULL;
1100                         }
1101                 }
1102                 ctx->next_read = src;
1103                 itjc_save_rx_mbuf(chan, dst);
1104                 return;
1105         }
1106
1107         blevel = ctx->hdlc_blevel;
1108         flag   = ctx->hdlc_flag;
1109         len    = ctx->hdlc_len;
1110         tmp    = ctx->hdlc_tmp;
1111         crc    = ctx->hdlc_crc;
1112         ib     = ctx->hdlc_ib;
1113
1114         dst = itjc_get_rx_mbuf(chan, NULL, ITJC_MB_CURR);
1115
1116         while (src != dma)
1117         {
1118                 HDLC_DECODE(*dst++, len, tmp, tmp2, blevel, ib, crc, flag,
1119                 {/* rdd */
1120                         tmp2 = ring[src];
1121                         src = itjc_ring_add(src, 1);
1122                 },
1123                 {/* nfr */
1124                         if (dst != NULL)
1125                                 panic("itjc_dma_rx_intr: nfrcmd with "
1126                                         "valid current frame");
1127
1128                         dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_NEW);
1129                         len = dst_end - dst;
1130                 },
1131                 {/* cfr */
1132                         len = BCH_MAX_DATALEN - len;
1133
1134                         if ((!len) || (len > BCH_MAX_DATALEN))
1135                         {
1136                                 /*
1137                                  * NOTE: frames without any data, only crc
1138                                  * field, should be silently discared.
1139                                  */
1140                                 NDBGL1(L1_S_MSG, "itjc_dma_rx_intr: "
1141                                         "bad frame (len=%d, unit=%d)",
1142                                         len, sc->sc_unit);
1143
1144                                 itjc_free_rx_mbuf(chan);
1145
1146                                 goto s0;
1147                         }
1148
1149                         if (crc)
1150                         {
1151                                 NDBGL1(L1_S_ERR,
1152                                         "CRC (crc=0x%04x, len=%d, unit=%d)",
1153                                         crc, len, sc->sc_unit);
1154
1155                                 itjc_free_rx_mbuf(chan);
1156
1157                                 goto s0;
1158                         }
1159
1160                         itjc_put_rx_mbuf(sc, chan, len);
1161
1162                 s0:
1163                         dst = NULL;
1164                         len = 0;
1165                 },
1166                 {/* rab */
1167                         NDBGL1(L1_S_ERR, "Read Abort (unit=%d)", sc->sc_unit);
1168
1169                         itjc_free_rx_mbuf(chan);
1170                         dst = NULL;
1171                         len = 0;
1172                 },
1173                 {/* rdo */
1174                         NDBGL1(L1_S_ERR, "RDO (unit=%d) dma=%d src=%d",
1175                                 sc->sc_unit, dma, src);
1176
1177                         itjc_free_rx_mbuf(chan);
1178                         dst = NULL;
1179                         len = 0;
1180                 },
1181                 continue,
1182                 d);
1183         }
1184
1185         itjc_save_rx_mbuf(chan, dst);
1186
1187         ctx->next_read  = src;
1188         ctx->hdlc_blevel= blevel;
1189         ctx->hdlc_flag  = flag;
1190         ctx->hdlc_len   = len;
1191         ctx->hdlc_tmp   = tmp;
1192         ctx->hdlc_crc   = crc;
1193         ctx->hdlc_ib    = ib;
1194 }
1195
1196
1197 /*
1198  * The HDLC side of itjc_dma_tx_intr. We made a separate function
1199  * to improve readability and (perhaps) help the compiler with
1200  * register allocation.
1201  */
1202 static void
1203 itjc_hdlc_encode(struct l1_softc *sc, l1_bchan_state_t *chan,
1204 dma_tx_context_t * ctx)
1205 {
1206         u_int8_t        *ring,
1207                         *src,
1208                         xdu,
1209                         flag,
1210                         flag_byte,
1211                         tx_restart;
1212
1213         u_int16_t       saved_len,
1214                         dst_end,
1215                         dst_end1,
1216                         dst,
1217                         filled,
1218                         blevel,
1219                         tmp2,
1220                         len,
1221                         crc,
1222                         ib;
1223
1224         u_int32_t       tmp;
1225
1226
1227         saved_len = len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1228
1229         filled = ctx->filled;
1230         flag   = ctx->hdlc_flag;
1231
1232         if (src == NULL && flag == 2 && filled >= ITJC_RING_WORDS)
1233                 return;
1234
1235         tx_restart = (flag == 2 && src != NULL);
1236         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, tx_restart);
1237
1238         ring   = ctx->ring;
1239
1240         ib     = ctx->hdlc_ib;
1241         crc    = ctx->hdlc_crc;
1242         tmp    = ctx->hdlc_tmp;
1243         blevel = ctx->hdlc_blevel;
1244
1245         if (xdu)
1246         {
1247                 if (flag != 2)
1248                 {
1249                         NDBGL1(L1_H_XFRERR, "XDU");
1250                         ++chan->stat_XDU;
1251
1252                         /*
1253                          * Abort the current frame and
1254                          * prepare for a full restart.
1255                          */
1256                         itjc_free_tx_mbufs(chan);
1257                         saved_len = len = filled = 0;
1258                         flag = (u_int8_t)-2;
1259                 }
1260                 else if (filled < ITJC_RING_SLOT_WORDS)
1261                 {
1262                         /*
1263                          * A little garbage may have been retransmitted.
1264                          * Send an abort before any new data.
1265                          */
1266                         filled = 0;
1267                         flag = (u_int8_t)-2;
1268                 }
1269         }
1270
1271         if (flag != 3)
1272                 len = 0;
1273
1274         while (dst != dst_end)
1275         {
1276                 HDLC_ENCODE(
1277                 *src++, len, tmp, tmp2, blevel, ib, crc, flag,
1278                 {/* gfr */
1279                         if ((len = saved_len) == 0)
1280                                 len = itjc_get_tx_mbuf(sc, chan, &src,
1281                                         ITJC_MB_NEW);
1282
1283                         if (len == 0)
1284                         {
1285                                 ctx->next_frame = dst;
1286
1287                                 flag_byte = itjc_rotate_hdlc_flag(blevel);
1288
1289                                 for (dst_end1 = itjc_ring_sub(dst_end, 1);
1290                                 dst != dst_end1;
1291                                 dst = itjc_ring_add(dst, 1))
1292                                 {
1293                                         ring[dst] = flag_byte;
1294                                         ++filled;
1295                                 }
1296                         }
1297                         else
1298                                 filled = 0;
1299
1300                         ctx->state = ITJC_TS_ACTIVE;
1301                 },
1302                 {/* nmb */
1303                         saved_len = 0;
1304                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1305                 },
1306                 {/* wrd */
1307                         ring[dst] = (u_int8_t)tmp;
1308                         dst = itjc_ring_add(dst, 1);
1309                 },
1310                 d1);
1311         }
1312
1313         ctx->hdlc_blevel = blevel;
1314         ctx->hdlc_flag   = flag;
1315         ctx->hdlc_tmp    = tmp;
1316         ctx->hdlc_crc    = crc;
1317         ctx->hdlc_ib     = ib;
1318
1319         ctx->filled = filled;
1320         ctx->next_write = dst;
1321
1322         itjc_save_tx_mbuf(chan, src, len);
1323 }
1324
1325
1326 static void
1327 itjc_dma_tx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1328 dma_tx_context_t * ctx)
1329 {
1330         u_int8_t        *data_end,
1331                         *ring,
1332                         *src,
1333                         xdu;
1334
1335         u_int16_t       dst,
1336                         dst_end,
1337                         filled,
1338                         len;
1339
1340
1341         if (ctx->state == ITJC_TS_IDLE)
1342                 goto done;
1343
1344         if (chan->bprot != BPROT_NONE)
1345         {
1346                 itjc_hdlc_encode(sc, chan, ctx);
1347                 goto done;
1348         }
1349
1350         ring   = ctx->ring;
1351         filled = ctx->filled;
1352
1353         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1354
1355         if (len == 0 && filled >= ITJC_RING_WORDS)
1356                 goto done;
1357
1358         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, len != 0);
1359
1360         if (xdu && filled < ITJC_RING_WORDS)
1361         {
1362                 NDBGL1(L1_H_XFRERR, "XDU");
1363                 ++chan->stat_XDU;
1364                 filled = 0;
1365         }
1366
1367         if (len == 0)
1368                 goto fill_ring;
1369
1370         ctx->state = ITJC_TS_ACTIVE;
1371
1372         data_end = src + len;
1373         while (dst != dst_end)
1374         {
1375                 ring[dst] = *src++; --len;
1376
1377                 dst = itjc_ring_add(dst, 1);
1378
1379                 if (src >= data_end)
1380                 {
1381                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1382                         if (len == 0)
1383                                 len = itjc_get_tx_mbuf(sc, chan,
1384                                          &src, ITJC_MB_NEW);
1385
1386                         if (len == 0)
1387                         {
1388                                 data_end = NULL;
1389                                 break;
1390                         }
1391                         data_end = src + len;
1392                 }
1393         }
1394
1395         itjc_save_tx_mbuf(chan, src, len);
1396
1397         filled = 0;
1398
1399 fill_ring:
1400         ctx->next_frame = dst;
1401
1402         for (; dst != dst_end; dst = itjc_ring_add(dst, 1))
1403         {
1404                 ring[dst] = ITJC_TEL_SILENCE_BYTE;
1405                 ++filled;
1406         }
1407
1408         ctx->next_write = dst;
1409         ctx->filled = filled;
1410
1411 done:
1412         ;
1413 }
1414
1415
1416 /*---------------------------------------------------------------------------*
1417  *      NetJet fifo read/write routines.
1418  *---------------------------------------------------------------------------*/
1419
1420 static void
1421 itjc_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1422 {
1423         itjc_bus_setup(sc);
1424
1425         if (what != ISIC_WHAT_ISAC)
1426                 panic("itjc_write_fifo: Trying to read from HSCX fifo.\n");
1427
1428         itjc_set_pib_addr_msb(0);
1429         itjc_read_multi_1(PIB_OFFSET, buf, size);
1430 }
1431
1432
1433 static void
1434 itjc_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1435 {
1436         itjc_bus_setup(sc);
1437
1438         if (what != ISIC_WHAT_ISAC)
1439                 panic("itjc_write_fifo: Trying to write to HSCX fifo.\n");
1440
1441         itjc_set_pib_addr_msb(0);
1442         itjc_write_multi_1(PIB_OFFSET, buf, size);
1443 }
1444
1445
1446 /*---------------------------------------------------------------------------*
1447  *      Read an ISAC register.
1448  *---------------------------------------------------------------------------*/
1449 static u_int8_t
1450 itjc_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
1451 {
1452         itjc_bus_setup(sc);
1453
1454         if (what != ISIC_WHAT_ISAC)
1455         {
1456                 panic("itjc_read_reg: what(%d) != ISIC_WHAT_ISAC\n",
1457                         what);
1458                 return 0;
1459         }
1460
1461         itjc_set_pib_addr_msb(offs);
1462         return itjc_read_1(itjc_pib_2_pci(offs));
1463 }
1464
1465
1466 /*---------------------------------------------------------------------------*
1467  *      Write an ISAC register.
1468  *---------------------------------------------------------------------------*/
1469 static void
1470 itjc_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
1471 {
1472         itjc_bus_setup(sc);
1473
1474         if (what != ISIC_WHAT_ISAC)
1475         {
1476                 panic("itjc_write_reg: what(%d) != ISIC_WHAT_ISAC\n",
1477                         what);
1478                 return;
1479         }
1480
1481         itjc_set_pib_addr_msb(offs);
1482         itjc_write_1(itjc_pib_2_pci(offs), data);
1483 }
1484
1485
1486 /*---------------------------------------------------------------------------*
1487  *      itjc_probe - probe for a card.
1488  *---------------------------------------------------------------------------*/
1489 static int itjc_probe(device_t dev)
1490 {
1491         u_int16_t       vid = pci_get_vendor(dev),
1492                         did = pci_get_device(dev);
1493
1494         if ((vid == PCI_TJNET_VID) && (did == PCI_TJ300_DID))
1495         {
1496                 device_set_desc(dev, "NetJet-S");
1497                 return 0;
1498         }
1499
1500         return ENXIO;
1501 }
1502
1503
1504 /*---------------------------------------------------------------------------*
1505  *      itjc_attach - attach a (previously probed) card.
1506  *---------------------------------------------------------------------------*/
1507 int
1508 itjc_attach(device_t dev)
1509 {
1510         bus_space_handle_t      h;
1511         bus_space_tag_t         t;
1512
1513         struct l1_softc         *sc = device_get_softc(dev);
1514
1515         u_int16_t               vid = pci_get_vendor(dev),
1516                                 did = pci_get_device(dev);
1517
1518         int                     unit = device_get_unit(dev),
1519                                 res_init_level = 0,
1520                                 error = 0;
1521
1522         void                    *ih = 0;
1523
1524         dma_context_t           *ctx = &dma_context[unit];
1525
1526         crit_enter();
1527         bzero(sc, sizeof(struct l1_softc));
1528
1529         /* Probably not really required. */
1530         if (unit > ITJC_MAXUNIT)
1531         {
1532                 printf("itjc%d: Error, unit > ITJC_MAXUNIT!\n", unit);
1533                 crit_exit();
1534                 return ENXIO;
1535         }
1536
1537         if (!(vid == PCI_TJNET_VID && did == PCI_TJ300_DID))
1538         {
1539                 printf("itjc%d: unknown device (%04X,%04X)!\n", unit, vid, did);
1540                 goto fail;
1541         }
1542
1543         itjc_scp[unit] = sc;
1544
1545         sc->sc_resources.io_rid[0] = PCIR_MAPS+0;
1546         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
1547                 &sc->sc_resources.io_rid[0], 0, ~0, 1, RF_ACTIVE);
1548
1549         if (sc->sc_resources.io_base[0] == NULL)
1550         {
1551                 printf("itjc%d: couldn't map IO port\n", unit);
1552                 error = ENXIO;
1553                 goto fail;
1554         }
1555
1556         h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1557         t = rman_get_bustag(sc->sc_resources.io_base[0]);
1558
1559         ++res_init_level;
1560
1561         /* Allocate interrupt. */
1562         sc->sc_resources.irq_rid = 0;
1563         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
1564                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
1565
1566         if (sc->sc_resources.irq == NULL)
1567         {
1568                 printf("itjc%d: couldn't map interrupt\n", unit);
1569                 error = ENXIO;
1570                 goto fail;
1571         }
1572
1573         ++res_init_level;
1574
1575         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
1576                                itjc_intr, sc, &ih, NULL);
1577
1578         if (error)
1579         {
1580                 printf("itjc%d: couldn't set up irq handler\n", unit);
1581                 error = ENXIO;
1582                 goto fail;
1583         }
1584
1585         /*
1586          * Reset the ASIC & the ISAC.
1587          */
1588         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1589
1590         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1591
1592         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1593                 TIGER_SELF_ADDR_DMA | TIGER_PIB_3_CYCLES);
1594
1595         DELAY(SEC_DELAY/100); /* ... and more 10 to recover. */
1596
1597         /*
1598          * First part of DMA initialization. Create & map the memory
1599          * pool that will be used to bear the rx & tx ring buffers.
1600          */
1601         ctx->state = ITJC_DS_LOADING;
1602
1603         error = bus_dma_tag_create(
1604                 NULL,                                   /* parent */
1605                 4,                                      /* alignment*/
1606                 0,                                      /* boundary*/
1607                 BUS_SPACE_MAXADDR_32BIT,                /* lowaddr*/
1608                 BUS_SPACE_MAXADDR,                      /* highaddr*/
1609                 NULL,                                   /* filter*/
1610                 NULL,                                   /* filterarg*/
1611                 ITJC_DMA_POOL_BYTES,                    /* maxsize*/
1612                 1,                                      /* nsegments*/
1613                 ITJC_DMA_POOL_BYTES,                    /* maxsegsz*/
1614                 BUS_DMA_ALLOCNOW | BUS_DMA_COHERENT,    /* flags*/
1615                 &ctx->tag);
1616
1617         if (error)
1618         {
1619                 printf("itjc%d: couldn't create bus DMA tag.\n", unit);
1620                 goto fail;
1621         }
1622
1623         ++res_init_level;
1624
1625         error = bus_dmamem_alloc(
1626                 ctx->tag,                               /* DMA tag */
1627                 (void **)&ctx->pool,    /* KV addr of the allocated memory */
1628                 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,      /* flags */
1629                 &ctx->map);                             /* KV <-> PCI map */
1630
1631         if (error)
1632                 goto fail;
1633
1634         /*
1635          * Load the KV <-> PCI map so the device sees the same
1636          * memory segment as pointed by pool. Note: since the
1637          * load may happen assyncronously (completion indicated by
1638          * the execution of the callback function) we have to
1639          * delay the initialization of the DMA engine to a moment we
1640          * actually have the proper bus addresses to feed the Tiger
1641          * and our DMA control blocks. This will be done in
1642          * itjc_bchannel_setup via a call to itjc_dma_start.
1643          */
1644         bus_dmamap_load(
1645                 ctx->tag,               /* DMA tag */
1646                 ctx->map,               /* DMA map */
1647                 ctx->pool,              /* KV addr of buffer */
1648                 ITJC_DMA_POOL_BYTES,    /* buffer size */
1649                 itjc_map_callback,      /* this receive the bus addr/error */
1650                 ctx,                    /* callback aux arg */
1651                 0);                     /* flags */
1652
1653         ++res_init_level;
1654
1655         /*
1656          * Setup the AUX port so we can talk to the ISAC.
1657          */
1658         itjc_write_1(TIGER_AUX_PORT_CNTL, TIGER_AUX_NJ_DEFAULT);
1659         itjc_write_1(TIGER_INT1_MASK, TIGER_ISAC_INT);
1660
1661         /*
1662          * From now on, almost like a `normal' ISIC driver.
1663          */
1664
1665         sc->sc_unit = unit;
1666
1667         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
1668
1669         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
1670         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
1671
1672         /* setup access routines */
1673
1674         sc->clearirq = NULL;
1675         sc->readreg = itjc_read_reg;
1676         sc->writereg = itjc_write_reg;
1677
1678         sc->readfifo = itjc_read_fifo;
1679         sc->writefifo = itjc_write_fifo;
1680
1681         /* setup card type */
1682
1683         sc->sc_cardtyp = CARD_TYPEP_NETJET_S;
1684
1685         /* setup IOM bus type */
1686
1687         sc->sc_bustyp = BUS_TYPE_IOM2;
1688
1689         /* set up some other miscellaneous things */
1690         sc->sc_ipac = 0;
1691         sc->sc_bfifolen = 2 * ITJC_RING_SLOT_WORDS;
1692
1693         printf("itjc%d: ISAC 2186 Version 1.1 (IOM-2)\n", unit);
1694
1695         /* init the ISAC */
1696         itjc_isac_init(sc);
1697
1698         /* init the "HSCX" */
1699         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
1700
1701         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
1702
1703         /* can't use the normal B-Channel stuff */
1704         itjc_init_linktab(sc);
1705
1706         /* set trace level */
1707
1708         sc->sc_trace = TRACE_OFF;
1709
1710         sc->sc_state = ISAC_IDLE;
1711
1712         sc->sc_ibuf = NULL;
1713         sc->sc_ib = NULL;
1714         sc->sc_ilen = 0;
1715
1716         sc->sc_obuf = NULL;
1717         sc->sc_op = NULL;
1718         sc->sc_ol = 0;
1719         sc->sc_freeflag = 0;
1720
1721         sc->sc_obuf2 = NULL;
1722         sc->sc_freeflag2 = 0;
1723
1724         callout_init(&sc->sc_T3_timeout);
1725         callout_init(&sc->sc_T4_timeout);
1726
1727         /* init higher protocol layers */
1728
1729         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_ATTACH,
1730                 sc->sc_cardtyp, &itjc_l1mux_func);
1731
1732         crit_exit();
1733         return 0;
1734
1735   fail:
1736         switch (res_init_level)
1737         {
1738         case 5:
1739                 bus_dmamap_unload(ctx->tag, ctx->map);
1740                 /* FALL TRHU */
1741
1742         case 4:
1743                 bus_dmamem_free(ctx->tag, ctx->pool, ctx->map);
1744                 bus_dmamap_destroy(ctx->tag, ctx->map);
1745                 /* FALL TRHU */
1746
1747         case 3:
1748                 bus_dma_tag_destroy(ctx->tag);
1749                 /* FALL TRHU */
1750
1751         case 2:
1752                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
1753                 /* FALL TRHU */
1754
1755         case 1:
1756                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+0,
1757                         sc->sc_resources.io_base[0]);
1758                 /* FALL TRHU */
1759
1760         case 0:
1761                 break;
1762         }
1763
1764         itjc_scp[unit] = NULL;
1765
1766         crit_exit();
1767         return error;
1768 }
1769
1770
1771 /*---------------------------------------------------------------------------*
1772  *      itjc_intr - main interrupt service routine.
1773  *---------------------------------------------------------------------------*/
1774 static void
1775 itjc_intr(void *xsc)
1776 {
1777         struct l1_softc         *sc     = xsc;
1778         l1_bchan_state_t        *chan   = &sc->sc_chan[0];
1779         dma_context_t           *dma    = &dma_context[sc->sc_unit];
1780         dma_rx_context_t        *rxc    = &dma_rx_context[sc->sc_unit][0];
1781         dma_tx_context_t        *txc    = &dma_tx_context[sc->sc_unit][0];
1782
1783         itjc_bus_setup(sc);
1784
1785         /* Honor interrupts from successfully configured cards only. */
1786         if (dma->state < ITJC_DS_STOPPED)
1787                 return;
1788
1789         /* First, we check the ISAC... */
1790         if (! (itjc_read_1(TIGER_AUX_PORT_DATA) & TIGER_ISAC_INT_MASK))
1791         {
1792                 itjc_write_1(TIGER_INT1_STATUS, TIGER_ISAC_INT);
1793                 NDBGL1(L1_H_IRQ, "ISAC");
1794                 itjc_isac_intr(sc);
1795         }
1796
1797         /* ... after what we always have a look at the DMA rings. */
1798
1799         NDBGL1(L1_H_IRQ, "Tiger");
1800
1801         itjc_read_1(TIGER_INT0_STATUS);
1802         itjc_write_1(TIGER_INT0_STATUS, TIGER_TARGET_ABORT_INT
1803                 | TIGER_MASTER_ABORT_INT | TIGER_RD_END_INT
1804                 | TIGER_RD_INT_INT       | TIGER_WR_END_INT | TIGER_WR_INT_INT);
1805
1806         itjc_dma_rx_intr(sc, chan, rxc);
1807         itjc_dma_tx_intr(sc, chan, txc);
1808
1809         ++chan; ++rxc; ++txc;
1810
1811         itjc_dma_rx_intr(sc, chan, rxc);
1812         itjc_dma_tx_intr(sc, chan, txc);
1813 }
1814
1815
1816 /*---------------------------------------------------------------------------*
1817  *      itjc_bchannel_setup - (Re)initialize and start/stop a Bchannel.
1818  *---------------------------------------------------------------------------*/
1819 static void
1820 itjc_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1821 {
1822 #if defined(__DragonFly__) || defined(__FreeBSD__)
1823         struct l1_softc         *sc     = itjc_scp[unit];
1824 #else
1825         struct l1_softc         *sc     = isic_find_sc(unit);
1826 #endif
1827         l1_bchan_state_t        *chan   = &sc->sc_chan[h_chan];
1828
1829         crit_enter();
1830
1831         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1832                 unit, h_chan, activate ? "activate" : "deactivate");
1833
1834         /*
1835          * If we are deactivating the channel, we have to stop
1836          * the DMA before we reset the channel control structures.
1837          */
1838         if (! activate)
1839                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1840
1841         /* general part */
1842
1843         chan->state = HSCX_IDLE;
1844
1845         chan->unit = sc->sc_unit;       /* unit number */
1846         chan->channel = h_chan;         /* B channel */
1847         chan->bprot = bprot;            /* B channel protocol */
1848
1849         /* receiver part */
1850
1851         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1852
1853         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1854
1855         chan->rxcount = 0;              /* reset rx counter */
1856
1857         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1858
1859         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1860         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1861         chan->in_len = 0;               /* reset mbuf data len */
1862
1863         /* transmitter part */
1864
1865         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1866
1867         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1868
1869         chan->txcount = 0;              /* reset tx counter */
1870
1871         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1872
1873         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1874         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1875         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1876         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1877
1878         /*
1879          * Only setup & start the DMA after all other channel
1880          * control structures are in place.
1881          */
1882         if (activate)
1883                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1884
1885         crit_exit();
1886 }
1887
1888
1889 /*---------------------------------------------------------------------------*
1890  *      itjc_bchannel_start - Signal us we have more data to send.
1891  *---------------------------------------------------------------------------*/
1892 static void
1893 itjc_bchannel_start(int unit, int h_chan)
1894 {
1895 #if Buggy_code
1896         /*
1897          * I disabled this routine because it was causing crashes when
1898          * this driver was used with the ISP (kernel SPPP) protocol driver.
1899          * The scenario is reproductible:
1900          *      Use the -link1 (dial on demand) ifconfig option.
1901          *      Start an interactive  TCP connection to somewhere.
1902          *      Wait until the PPP connection times out and is dropped.
1903          *      Try to send something on the TCP connection.
1904          *      The machine will print some garbage and halt or reboot
1905          *      (no panic messages).
1906          *
1907          * I've nailed down the problem to the fact that this routine
1908          * was being called before the B channel had been setup again.
1909          *
1910          * For now, I don't have a good solution other than this one.
1911          * But, don't despair. The impact of it is unnoticeable.
1912          */
1913
1914 #if defined(__DragonFly__) || defined(__FreeBSD__)
1915         struct l1_softc  *sc    = itjc_scp[unit];
1916 #else
1917         struct l1_softc  *sc    = isic_find_sc(unit);
1918 #endif
1919         l1_bchan_state_t *chan  = &sc->sc_chan[h_chan];
1920         dma_tx_context_t *txc   = &dma_tx_context[unit][h_chan];
1921
1922         crit_enter();
1923
1924         if (chan->state & HSCX_TX_ACTIVE)
1925         {
1926                 crit_exit();
1927                 return;
1928         }
1929
1930         itjc_dma_tx_intr(sc, chan, txc);
1931
1932         crit_exit();
1933 #endif
1934 }
1935
1936
1937 /*---------------------------------------------------------------------------*
1938  *      itjc_shutdown - Stop the driver and reset the card.
1939  *---------------------------------------------------------------------------*/
1940 static void
1941 itjc_shutdown(device_t dev)
1942 {
1943         struct l1_softc *sc = device_get_softc(dev);
1944
1945         itjc_bus_setup(sc);
1946
1947         /*
1948          * Stop the DMA the nice and easy way.
1949          */
1950         itjc_bchannel_setup(sc->sc_unit, 0, BPROT_NONE, 0);
1951         itjc_bchannel_setup(sc->sc_unit, 1, BPROT_NONE, 0);
1952
1953         /*
1954          * Reset the card.
1955          */
1956         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1957
1958         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1959
1960         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1961                 TIGER_SELF_ADDR_DMA | TIGER_LATCH_DMA_INT | TIGER_PIB_3_CYCLES);
1962
1963         DELAY(SEC_DELAY/100); /* ... and more 10 to recover */
1964 }
1965
1966
1967 /*---------------------------------------------------------------------------*
1968  *      itjc_ret_linktab - Return the address of itjc drivers linktab.
1969  *---------------------------------------------------------------------------*/
1970 isdn_link_t *
1971 itjc_ret_linktab(int unit, int channel)
1972 {
1973 #if defined(__DragonFly__) || defined(__FreeBSD__)
1974         struct l1_softc         *sc = itjc_scp[unit];
1975 #else
1976         struct l1_softc         *sc = isic_find_sc(unit);
1977 #endif
1978         l1_bchan_state_t        *chan = &sc->sc_chan[channel];
1979
1980         return(&chan->isic_isdn_linktab);
1981 }
1982
1983 /*---------------------------------------------------------------------------*
1984  *      itjc_set_linktab - Set the driver linktab in the b channel softc.
1985  *---------------------------------------------------------------------------*/
1986 void
1987 itjc_set_linktab(int unit, int channel, drvr_link_t *dlt)
1988 {
1989 #if defined(__DragonFly__) || defined(__FreeBSD__)
1990         struct l1_softc *sc     = itjc_scp[unit];
1991 #else
1992         struct l1_softc *sc     = isic_find_sc(unit);
1993 #endif
1994         l1_bchan_state_t *chan  = &sc->sc_chan[channel];
1995
1996         chan->isic_drvr_linktab = dlt;
1997 }
1998
1999
2000 /*---------------------------------------------------------------------------*
2001  *      itjc_init_linktab - Initialize our local linktab.
2002  *---------------------------------------------------------------------------*/
2003 static void
2004 itjc_init_linktab(struct l1_softc *sc)
2005 {
2006         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
2007         isdn_link_t *lt = &chan->isic_isdn_linktab;
2008
2009         /* make sure the hardware driver is known to layer 4 */
2010         /* avoid overwriting if already set */
2011         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
2012         {
2013                 ctrl_types[CTRL_PASSIVE].set_linktab = itjc_set_linktab;
2014                 ctrl_types[CTRL_PASSIVE].get_linktab = itjc_ret_linktab;
2015         }
2016
2017         /* local setup */
2018         lt->unit = sc->sc_unit;
2019         lt->channel = HSCX_CH_A;
2020         lt->bch_config = itjc_bchannel_setup;
2021         lt->bch_tx_start = itjc_bchannel_start;
2022         lt->bch_stat = itjc_bchannel_stat;
2023         lt->tx_queue = &chan->tx_queue;
2024
2025         /* used by non-HDLC data transfers, i.e. telephony drivers */
2026         lt->rx_queue = &chan->rx_queue;
2027
2028         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2029         lt->rx_mbuf = &chan->in_mbuf;
2030
2031         chan = &sc->sc_chan[HSCX_CH_B];
2032         lt = &chan->isic_isdn_linktab;
2033
2034         lt->unit = sc->sc_unit;
2035         lt->channel = HSCX_CH_B;
2036         lt->bch_config = itjc_bchannel_setup;
2037         lt->bch_tx_start = itjc_bchannel_start;
2038         lt->bch_stat = itjc_bchannel_stat;
2039         lt->tx_queue = &chan->tx_queue;
2040
2041         /* used by non-HDLC data transfers, i.e. telephony drivers */
2042         lt->rx_queue = &chan->rx_queue;
2043
2044         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2045         lt->rx_mbuf = &chan->in_mbuf;
2046 }
2047
2048
2049 /*---------------------------------------------------------------------------*
2050  *      itjc_bchannel_stat - Collect link statistics for a given B channel.
2051  *---------------------------------------------------------------------------*/
2052 static void
2053 itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
2054 {
2055 #if defined(__DragonFly__) || defined(__FreeBSD__)
2056         struct l1_softc *sc = itjc_scp[unit];
2057 #else
2058         struct l1_softc *sc = isic_find_sc(unit);
2059 #endif
2060         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
2061
2062         crit_enter();
2063
2064         bsp->outbytes = chan->txcount;
2065         bsp->inbytes = chan->rxcount;
2066
2067         chan->txcount = 0;
2068         chan->rxcount = 0;
2069
2070         crit_exit();
2071 }
2072
2073
2074 /*---------------------------------------------------------------------------*
2075  *      Netjet - ISAC interrupt routine.
2076  *---------------------------------------------------------------------------*/
2077 static void
2078 itjc_isac_intr(struct l1_softc *sc)
2079 {
2080         u_char irq_stat;
2081
2082         do
2083         {
2084                 /* get isac irq status */
2085                 irq_stat = ISAC_READ(I_ISTA);
2086
2087                 if(irq_stat)
2088                         itjc_isac_irq(sc, irq_stat); /* isac handler */
2089         }
2090         while(irq_stat);
2091
2092         ISAC_WRITE(I_MASK, 0xff);
2093
2094         DELAY(100);
2095
2096         ISAC_WRITE(I_MASK, ISAC_IMASK);
2097 }
2098
2099
2100 /*---------------------------------------------------------------------------*
2101  *      itjc_recover - Try to recover from ISAC irq lockup.
2102  *---------------------------------------------------------------------------*/
2103 void
2104 itjc_recover(struct l1_softc *sc)
2105 {
2106         u_char byte;
2107
2108         /* get isac irq status */
2109
2110         byte = ISAC_READ(I_ISTA);
2111
2112         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
2113
2114         if(byte & ISAC_ISTA_EXI)
2115                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
2116
2117         if(byte & ISAC_ISTA_CISQ)
2118         {
2119                 byte = ISAC_READ(I_CIRR);
2120
2121                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
2122
2123                 if(byte & ISAC_CIRR_SQC)
2124                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
2125         }
2126
2127         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
2128
2129         ISAC_WRITE(I_MASK, 0xff);
2130         DELAY(100);
2131         ISAC_WRITE(I_MASK, ISAC_IMASK);
2132 }
2133
2134 #endif /* NITJC > 0 */