2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2006 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: ar5211_recv.c,v 1.4 2008/11/10 04:08:02 sam Exp $
23 #include "ah_internal.h"
26 #include "ar5211/ar5211.h"
27 #include "ar5211/ar5211reg.h"
28 #include "ar5211/ar5211desc.h"
34 ar5211GetRxDP(struct ath_hal *ah)
36 return OS_REG_READ(ah, AR_RXDP);
43 ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp)
45 OS_REG_WRITE(ah, AR_RXDP, rxdp);
46 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
51 * Set Receive Enable bits.
54 ar5211EnableReceive(struct ath_hal *ah)
56 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
60 * Stop Receive at the DMA engine
63 ar5211StopDmaReceive(struct ath_hal *ah)
65 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
66 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
68 ath_hal_printf(ah, "%s failed to stop in 10ms\n"
69 "AR_CR=0x%08X\nAR_DIAG_SW=0x%08X\n"
71 , OS_REG_READ(ah, AR_CR)
72 , OS_REG_READ(ah, AR_DIAG_SW)
82 * Start Transmit at the PCU engine (unpause receive)
85 ar5211StartPcuReceive(struct ath_hal *ah)
87 OS_REG_WRITE(ah, AR_DIAG_SW,
88 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
92 * Stop Transmit at the PCU engine (pause receive)
95 ar5211StopPcuReceive(struct ath_hal *ah)
97 OS_REG_WRITE(ah, AR_DIAG_SW,
98 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
102 * Set multicast filter 0 (lower 32-bits)
103 * filter 1 (upper 32-bits)
106 ar5211SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
108 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
109 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
113 * Clear multicast filter by index
116 ar5211ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
123 val = OS_REG_READ(ah, AR_MCAST_FIL1);
124 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
126 val = OS_REG_READ(ah, AR_MCAST_FIL0);
127 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
133 * Set multicast filter by index
136 ar5211SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
143 val = OS_REG_READ(ah, AR_MCAST_FIL1);
144 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
146 val = OS_REG_READ(ah, AR_MCAST_FIL0);
147 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
153 * Get receive filter.
156 ar5211GetRxFilter(struct ath_hal *ah)
158 return OS_REG_READ(ah, AR_RX_FILTER);
162 * Set receive filter.
165 ar5211SetRxFilter(struct ath_hal *ah, uint32_t bits)
167 OS_REG_WRITE(ah, AR_RX_FILTER, bits);
171 * Initialize RX descriptor, by clearing the status and clearing
172 * the size. This is not strictly HW dependent, but we want the
173 * control and status words to be opaque above the hal.
176 ar5211SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
177 uint32_t size, u_int flags)
179 struct ar5211_desc *ads = AR5211DESC(ds);
182 ads->ds_ctl1 = size & AR_BufLen;
183 if (ads->ds_ctl1 != size) {
184 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
188 if (flags & HAL_RXDESC_INTREQ)
189 ads->ds_ctl1 |= AR_RxInterReq;
190 ads->ds_status0 = ads->ds_status1 = 0;
196 * Process an RX descriptor, and return the status to the caller.
197 * Copy some hardware specific items into the software portion
200 * NB: the caller is responsible for validating the memory contents
201 * of the descriptor (e.g. flushing any cached copy).
204 ar5211ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
205 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
206 struct ath_rx_status *rs)
208 struct ar5211_desc *ads = AR5211DESC(ds);
209 struct ar5211_desc *ands = AR5211DESC(nds);
211 if ((ads->ds_status1 & AR_Done) == 0)
212 return HAL_EINPROGRESS;
214 * Given the use of a self-linked tail be very sure that the hw is
215 * done with this descriptor; the hw may have done this descriptor
216 * once and picked it up again...make sure the hw has moved on.
218 if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
219 return HAL_EINPROGRESS;
221 rs->rs_datalen = ads->ds_status0 & AR_DataLen;
222 rs->rs_tstamp = MS(ads->ds_status1, AR_RcvTimestamp);
224 if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
225 if (ads->ds_status1 & AR_CRCErr)
226 rs->rs_status |= HAL_RXERR_CRC;
227 else if (ads->ds_status1 & AR_DecryptCRCErr)
228 rs->rs_status |= HAL_RXERR_DECRYPT;
230 rs->rs_status |= HAL_RXERR_PHY;
231 rs->rs_phyerr = MS(ads->ds_status1, AR_PHYErr);
234 /* XXX what about KeyCacheMiss? */
235 rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
236 if (ads->ds_status1 & AR_KeyIdxValid)
237 rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
239 rs->rs_keyix = HAL_RXKEYIX_INVALID;
240 /* NB: caller expected to do rate table mapping */
241 rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
242 rs->rs_antenna = MS(ads->ds_status0, AR_RcvAntenna);
243 rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;