2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9285_attach.c 203930 2010-02-15 17:49:49Z rpaulo $
23 #include "ah_internal.h"
26 #include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
28 #include "ar5416/ar9280.h"
29 #include "ar5416/ar9285.h"
30 #include "ar5416/ar5416reg.h"
31 #include "ar5416/ar5416phy.h"
33 #include "ar5416/ar9285.ini"
34 #include "ar5416/ar9285v2.ini"
35 #include "ar5416/ar9280v2.ini" /* XXX ini for tx/rx gain */
37 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
38 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
39 .calNumSamples = MIN_CAL_SAMPLES,
40 .calCountMax = PER_MAX_LOG_COUNT,
41 .calCollect = ar5416IQCalCollect,
42 .calPostProc = ar5416IQCalibration
44 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
45 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
46 .calNumSamples = MIN_CAL_SAMPLES,
47 .calCountMax = PER_MIN_LOG_COUNT,
48 .calCollect = ar5416AdcGainCalCollect,
49 .calPostProc = ar5416AdcGainCalibration
51 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
52 .calName = "ADC DC", .calType = ADC_DC_CAL,
53 .calNumSamples = MIN_CAL_SAMPLES,
54 .calCountMax = PER_MIN_LOG_COUNT,
55 .calCollect = ar5416AdcDcCalCollect,
56 .calPostProc = ar5416AdcDcCalibration
58 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
59 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
60 .calNumSamples = MIN_CAL_SAMPLES,
61 .calCountMax = INIT_LOG_COUNT,
62 .calCollect = ar5416AdcDcCalCollect,
63 .calPostProc = ar5416AdcDcCalibration
66 static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
67 static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
68 static void ar9285WriteIni(struct ath_hal *ah,
69 const struct ieee80211_channel *chan);
72 ar9285AniSetup(struct ath_hal *ah)
74 /* NB: disable ANI for reliable RIFS rx */
75 ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
79 * Attach for an AR9285 part.
81 static struct ath_hal *
82 ar9285Attach(uint16_t devid, HAL_SOFTC sc,
83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
85 struct ath_hal_9285 *ahp9285;
86 struct ath_hal_5212 *ahp;
92 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
93 __func__, sc, (void*) st, (void*) sh);
95 /* NB: memory is returned zero'd */
96 ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
97 if (ahp9285 == AH_NULL) {
98 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
99 "%s: cannot allocate memory for state block\n", __func__);
100 *status = HAL_ENOMEM;
103 ahp = AH5212(ahp9285);
104 ah = &ahp->ah_priv.h;
106 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
108 /* XXX override with 9285 specific state */
109 /* override 5416 methods for our needs */
110 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
111 ah->ah_configPCIE = ar9285ConfigPCIE;
112 ah->ah_setTxPower = ar9285SetTransmitPower;
113 ah->ah_setBoardValues = ar9285SetBoardValues;
115 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
116 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
117 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
118 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
119 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
121 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
122 AH5416(ah)->ah_writeIni = ar9285WriteIni;
123 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
124 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
126 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
128 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
134 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
135 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
140 /* Read Revisions from Chips before taking out of reset */
141 val = OS_REG_READ(ah, AR_SREV);
142 HALDEBUG(ah, HAL_DEBUG_ATTACH,
143 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
144 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
145 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
146 /* NB: include chip type to differentiate from pre-Sowl versions */
147 AH_PRIVATE(ah)->ah_macVersion =
148 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
149 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
150 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
152 /* setup common ini data; rf backends handle remainder */
153 if (AR_SREV_KITE_12_OR_LATER(ah)) {
154 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
155 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
156 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
157 ar9285PciePhy_clkreq_always_on_L1_v2, 2);
159 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
160 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
161 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
162 ar9285PciePhy_clkreq_always_on_L1, 2);
164 ar5416AttachPCIE(ah);
166 ecode = ath_hal_v4kEepromAttach(ah);
170 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
171 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
177 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
179 if (!ar5212ChipTest(ah)) {
180 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
182 ecode = HAL_ESELFTEST;
187 * Set correct Baseband to analog shift
188 * setting to access analog chips.
190 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
192 /* Read Radio Chip Rev Extract */
193 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
194 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
195 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
196 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
199 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
200 AH_PRIVATE(ah)->ah_analog5GhzRev =
201 AR_RAD5133_SREV_MAJOR;
205 HALDEBUG(ah, HAL_DEBUG_ANY,
206 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
207 "this driver\n", __func__,
208 AH_PRIVATE(ah)->ah_analog5GhzRev);
209 ecode = HAL_ENOTSUPP;
213 rfStatus = ar9285RfAttach(ah, &ecode);
215 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
220 HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
222 /* setup txgain table */
223 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
224 case AR5416_EEP_TXGAIN_HIGH_POWER:
225 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
226 ar9285Modes_high_power_tx_gain_v2, 6);
228 case AR5416_EEP_TXGAIN_ORIG:
229 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
230 ar9285Modes_original_tx_gain_v2, 6);
234 goto bad; /* XXX ? try to continue */
238 * Got everything we need now to setup the capabilities.
240 if (!ar9285FillCapabilityInfo(ah)) {
245 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
246 if (ecode != HAL_OK) {
247 HALDEBUG(ah, HAL_DEBUG_ANY,
248 "%s: error getting mac address from EEPROM\n", __func__);
251 /* XXX How about the serial number ? */
252 /* Read Reg Domain */
253 AH_PRIVATE(ah)->ah_currentRD =
254 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
257 * ah_miscMode is populated by ar5416FillCapabilityInfo()
258 * starting from griffin. Set here to make sure that
259 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
260 * placed into hardware.
262 if (ahp->ah_miscMode != 0)
263 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
265 ar9285AniSetup(ah); /* Anti Noise Immunity */
266 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
268 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
280 ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
282 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
283 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
285 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
286 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
291 ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
293 u_int modesIndex, freqIndex;
296 /* Setup the indices for the next set of register array writes */
297 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
299 if (IEEE80211_IS_CHAN_HT40(chan))
301 else if (IEEE80211_IS_CHAN_108G(chan))
306 /* Set correct Baseband to analog shift setting to access analog chips. */
307 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
308 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
309 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
310 modesIndex, regWrites);
311 if (AR_SREV_KITE_12_OR_LATER(ah)) {
312 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
313 modesIndex, regWrites);
315 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
321 * Fill all software cached or static hardware state information.
322 * Return failure if capabilities are to come from EEPROM and
326 ar9285FillCapabilityInfo(struct ath_hal *ah)
328 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
330 if (!ar5416FillCapabilityInfo(ah))
332 pCap->halNumGpioPins = 12;
333 pCap->halWowSupport = AH_TRUE;
334 pCap->halWowMatchPatternExact = AH_TRUE;
336 pCap->halWowMatchPatternDword = AH_TRUE;
338 pCap->halCSTSupport = AH_TRUE;
339 pCap->halRifsRxSupport = AH_TRUE;
340 pCap->halRifsTxSupport = AH_TRUE;
341 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
342 pCap->halExtChanDfsSupport = AH_TRUE;
345 pCap->halBtCoexSupport = AH_TRUE;
347 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
349 pCap->hal4kbSplitTransSupport = AH_FALSE;
351 pCap->halRxStbcSupport = 1;
352 pCap->halTxStbcSupport = 1;
358 ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
360 #define ANTENNA0_CHAINMASK 0x1
361 #define ANTENNA1_CHAINMASK 0x2
362 struct ath_hal_5416 *ahp = AH5416(ah);
364 /* Antenna selection is done by setting the tx/rx chainmasks approp. */
366 case HAL_ANT_FIXED_A:
367 /* Enable first antenna only */
368 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK;
369 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK;
371 case HAL_ANT_FIXED_B:
372 /* Enable second antenna only, after checking capability */
373 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
374 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK;
375 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK;
377 case HAL_ANT_VARIABLE:
378 /* Restore original chainmask settings */
380 ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
381 ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
385 #undef ANTENNA0_CHAINMASK
386 #undef ANTENNA1_CHAINMASK
390 ar9285Probe(uint16_t vendorid, uint16_t devid)
392 if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
393 return "Atheros 9285";
396 AH_CHIP(AR9285, ar9285Probe, ar9285Attach);