2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <machine/md_var.h>
58 #include <drm/drm_vma_manager.h>
59 #include <drm/i915_drm.h>
61 #include "i915_trace.h"
62 #include "intel_drv.h"
63 #include <linux/shmem_fs.h>
64 #include <linux/slab.h>
65 #include <linux/swap.h>
66 #include <linux/pci.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
71 static __must_check int
72 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
75 i915_gem_object_retire(struct drm_i915_gem_object *obj);
77 static void i915_gem_write_fence(struct drm_device *dev, int reg,
78 struct drm_i915_gem_object *obj);
79 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
80 struct drm_i915_fence_reg *fence,
83 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
85 static bool cpu_cache_is_coherent(struct drm_device *dev,
86 enum i915_cache_level level)
88 return HAS_LLC(dev) || level != I915_CACHE_NONE;
91 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
93 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
96 return obj->pin_display;
99 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
101 if (obj->tiling_mode)
102 i915_gem_release_mmap(obj);
104 /* As we do not have an associated fence register, we will force
105 * a tiling change if we ever need to acquire one.
107 obj->fence_dirty = false;
108 obj->fence_reg = I915_FENCE_REG_NONE;
111 /* some bookkeeping */
112 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
115 spin_lock(&dev_priv->mm.object_stat_lock);
116 dev_priv->mm.object_count++;
117 dev_priv->mm.object_memory += size;
118 spin_unlock(&dev_priv->mm.object_stat_lock);
121 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
124 spin_lock(&dev_priv->mm.object_stat_lock);
125 dev_priv->mm.object_count--;
126 dev_priv->mm.object_memory -= size;
127 spin_unlock(&dev_priv->mm.object_stat_lock);
131 i915_gem_wait_for_error(struct i915_gpu_error *error)
135 #define EXIT_COND (!i915_reset_in_progress(error) || \
136 i915_terminally_wedged(error))
141 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
142 * userspace. If it takes that long something really bad is going on and
143 * we should simply try to bail out and fail as gracefully as possible.
145 ret = wait_event_interruptible_timeout(error->reset_queue,
149 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
151 } else if (ret < 0) {
159 int i915_mutex_lock_interruptible(struct drm_device *dev)
161 struct drm_i915_private *dev_priv = dev->dev_private;
164 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
168 ret = mutex_lock_interruptible(&dev->struct_mutex);
172 WARN_ON(i915_verify_lists(dev));
177 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
179 return i915_gem_obj_bound_any(obj) && !obj->active;
183 i915_gem_init_ioctl(struct drm_device *dev, void *data,
184 struct drm_file *file)
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct drm_i915_gem_init *args = data;
189 if (drm_core_check_feature(dev, DRIVER_MODESET))
192 if (args->gtt_start >= args->gtt_end ||
193 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
196 /* GEM with user mode setting was never supported on ilk and later. */
197 if (INTEL_INFO(dev)->gen >= 5)
200 mutex_lock(&dev->struct_mutex);
201 kprintf("INITGLOBALGTT GTT_START %016jx\n", (uintmax_t)args->gtt_start);
202 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
204 dev_priv->gtt.mappable_end = args->gtt_end;
205 mutex_unlock(&dev->struct_mutex);
211 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
212 struct drm_file *file)
214 struct drm_i915_private *dev_priv = dev->dev_private;
215 struct drm_i915_gem_get_aperture *args = data;
216 struct drm_i915_gem_object *obj;
220 mutex_lock(&dev->struct_mutex);
221 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
222 if (i915_gem_obj_is_pinned(obj))
223 pinned += i915_gem_obj_ggtt_size(obj);
224 mutex_unlock(&dev->struct_mutex);
226 args->aper_size = dev_priv->gtt.base.total;
227 args->aper_available_size = args->aper_size - pinned;
232 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
234 drm_dma_handle_t *phys = obj->phys_handle;
239 if (obj->madv == I915_MADV_WILLNEED) {
240 struct vm_object *mapping = obj->base.vm_obj;
241 char *vaddr = phys->vaddr;
244 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
245 struct vm_page *page = shmem_read_mapping_page(mapping, i);
247 char *dst = kmap_atomic(page);
248 memcpy(dst, vaddr, PAGE_SIZE);
249 drm_clflush_virt_range(dst, PAGE_SIZE);
252 set_page_dirty(page);
253 mark_page_accessed(page);
255 page_cache_release(page);
260 i915_gem_chipset_flush(obj->base.dev);
264 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
266 drm_pci_free(obj->base.dev, phys);
267 obj->phys_handle = NULL;
271 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
274 drm_dma_handle_t *phys;
275 struct vm_object *mapping;
279 if (obj->phys_handle) {
280 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
286 if (obj->madv != I915_MADV_WILLNEED)
290 if (obj->base.filp == NULL)
294 /* create a new object */
295 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
301 set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
303 mapping = obj->base.vm_obj;
304 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
305 struct vm_page *page;
308 page = shmem_read_mapping_page(mapping, i);
311 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
313 drm_pci_free(obj->base.dev, phys);
314 return PTR_ERR(page);
317 src = kmap_atomic(page);
318 memcpy(vaddr, src, PAGE_SIZE);
321 mark_page_accessed(page);
323 page_cache_release(page);
329 obj->phys_handle = phys;
334 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
335 struct drm_i915_gem_pwrite *args,
336 struct drm_file *file_priv)
338 struct drm_device *dev = obj->base.dev;
339 void *vaddr = (char *)obj->phys_handle->vaddr + args->offset;
340 char __user *user_data = to_user_ptr(args->data_ptr);
342 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
343 unsigned long unwritten;
345 /* The physical object once assigned is fixed for the lifetime
346 * of the obj, so we can safely drop the lock and continue
349 mutex_unlock(&dev->struct_mutex);
350 unwritten = copy_from_user(vaddr, user_data, args->size);
351 mutex_lock(&dev->struct_mutex);
356 i915_gem_chipset_flush(dev);
360 void *i915_gem_object_alloc(struct drm_device *dev)
362 return kmalloc(sizeof(struct drm_i915_gem_object),
363 M_DRM, M_WAITOK | M_ZERO);
366 void i915_gem_object_free(struct drm_i915_gem_object *obj)
372 i915_gem_create(struct drm_file *file,
373 struct drm_device *dev,
377 struct drm_i915_gem_object *obj;
381 size = roundup(size, PAGE_SIZE);
385 /* Allocate the new object */
386 obj = i915_gem_alloc_object(dev, size);
390 ret = drm_gem_handle_create(file, &obj->base, &handle);
391 /* drop reference from allocate - handle holds it now */
392 drm_gem_object_unreference_unlocked(&obj->base);
401 i915_gem_dumb_create(struct drm_file *file,
402 struct drm_device *dev,
403 struct drm_mode_create_dumb *args)
405 /* have to work out size/pitch and return them */
406 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
407 args->size = args->pitch * args->height;
408 return i915_gem_create(file, dev,
409 args->size, &args->handle);
413 * Creates a new mm object and returns a handle to it.
416 i915_gem_create_ioctl(struct drm_device *dev, void *data,
417 struct drm_file *file)
419 struct drm_i915_gem_create *args = data;
421 return i915_gem_create(file, dev,
422 args->size, &args->handle);
426 __copy_to_user_swizzled(char __user *cpu_vaddr,
427 const char *gpu_vaddr, int gpu_offset,
430 int ret, cpu_offset = 0;
433 int cacheline_end = ALIGN(gpu_offset + 1, 64);
434 int this_length = min(cacheline_end - gpu_offset, length);
435 int swizzled_gpu_offset = gpu_offset ^ 64;
437 ret = __copy_to_user(cpu_vaddr + cpu_offset,
438 gpu_vaddr + swizzled_gpu_offset,
443 cpu_offset += this_length;
444 gpu_offset += this_length;
445 length -= this_length;
452 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
453 const char __user *cpu_vaddr,
456 int ret, cpu_offset = 0;
459 int cacheline_end = ALIGN(gpu_offset + 1, 64);
460 int this_length = min(cacheline_end - gpu_offset, length);
461 int swizzled_gpu_offset = gpu_offset ^ 64;
463 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
464 cpu_vaddr + cpu_offset,
469 cpu_offset += this_length;
470 gpu_offset += this_length;
471 length -= this_length;
478 * Pins the specified object's pages and synchronizes the object with
479 * GPU accesses. Sets needs_clflush to non-zero if the caller should
480 * flush the object from the CPU cache.
482 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
494 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
495 /* If we're not in the cpu read domain, set ourself into the gtt
496 * read domain and manually flush cachelines (if required). This
497 * optimizes for the case when the gpu will dirty the data
498 * anyway again before the next pread happens. */
499 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
501 ret = i915_gem_object_wait_rendering(obj, true);
505 i915_gem_object_retire(obj);
508 ret = i915_gem_object_get_pages(obj);
512 i915_gem_object_pin_pages(obj);
517 /* Per-page copy function for the shmem pread fastpath.
518 * Flushes invalid cachelines before reading the target if
519 * needs_clflush is set. */
521 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
522 char __user *user_data,
523 bool page_do_bit17_swizzling, bool needs_clflush)
528 if (unlikely(page_do_bit17_swizzling))
531 vaddr = kmap_atomic(page);
533 drm_clflush_virt_range(vaddr + shmem_page_offset,
535 ret = __copy_to_user_inatomic(user_data,
536 vaddr + shmem_page_offset,
538 kunmap_atomic(vaddr);
540 return ret ? -EFAULT : 0;
544 shmem_clflush_swizzled_range(char *addr, unsigned long length,
547 if (unlikely(swizzled)) {
548 unsigned long start = (unsigned long) addr;
549 unsigned long end = (unsigned long) addr + length;
551 /* For swizzling simply ensure that we always flush both
552 * channels. Lame, but simple and it works. Swizzled
553 * pwrite/pread is far from a hotpath - current userspace
554 * doesn't use it at all. */
555 start = round_down(start, 128);
556 end = round_up(end, 128);
558 drm_clflush_virt_range((void *)start, end - start);
560 drm_clflush_virt_range(addr, length);
565 /* Only difference to the fast-path function is that this can handle bit17
566 * and uses non-atomic copy and kmap functions. */
568 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
569 char __user *user_data,
570 bool page_do_bit17_swizzling, bool needs_clflush)
577 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
579 page_do_bit17_swizzling);
581 if (page_do_bit17_swizzling)
582 ret = __copy_to_user_swizzled(user_data,
583 vaddr, shmem_page_offset,
586 ret = __copy_to_user(user_data,
587 vaddr + shmem_page_offset,
591 return ret ? - EFAULT : 0;
595 i915_gem_shmem_pread(struct drm_device *dev,
596 struct drm_i915_gem_object *obj,
597 struct drm_i915_gem_pread *args,
598 struct drm_file *file)
600 char __user *user_data;
603 int shmem_page_offset, page_length, ret = 0;
604 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
606 int needs_clflush = 0;
609 user_data = to_user_ptr(args->data_ptr);
612 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
614 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
618 offset = args->offset;
620 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
621 struct vm_page *page = obj->pages[i];
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset = offset_in_page(offset);
632 page_length = remain;
633 if ((shmem_page_offset + page_length) > PAGE_SIZE)
634 page_length = PAGE_SIZE - shmem_page_offset;
636 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
637 (page_to_phys(page) & (1 << 17)) != 0;
639 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
640 user_data, page_do_bit17_swizzling,
645 mutex_unlock(&dev->struct_mutex);
647 if (likely(!i915.prefault_disable) && !prefaulted) {
648 ret = fault_in_multipages_writeable(user_data, remain);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
658 user_data, page_do_bit17_swizzling,
661 mutex_lock(&dev->struct_mutex);
667 remain -= page_length;
668 user_data += page_length;
669 offset += page_length;
673 i915_gem_object_unpin_pages(obj);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
685 struct drm_file *file)
687 struct drm_i915_gem_pread *args = data;
688 struct drm_i915_gem_object *obj;
694 ret = i915_mutex_lock_interruptible(dev);
698 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
699 if (&obj->base == NULL) {
704 /* Bounds check source. */
705 if (args->offset > obj->base.size ||
706 args->size > obj->base.size - args->offset) {
711 trace_i915_gem_object_pread(obj, args->offset, args->size);
713 ret = i915_gem_shmem_pread(dev, obj, args, file);
716 drm_gem_object_unreference(&obj->base);
718 mutex_unlock(&dev->struct_mutex);
722 /* This is the fast write path which cannot handle
723 * page faults in the source data
727 fast_user_write(struct io_mapping *mapping,
728 loff_t page_base, int page_offset,
729 char __user *user_data,
732 void __iomem *vaddr_atomic;
734 unsigned long unwritten;
736 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
737 /* We can use the cpu mem copy function because this is X86. */
738 vaddr = (char __force*)vaddr_atomic + page_offset;
739 unwritten = __copy_from_user_inatomic_nocache(vaddr,
741 io_mapping_unmap_atomic(vaddr_atomic);
746 * This is the fast pwrite path, where we copy the data directly from the
747 * user into the GTT, uncached.
750 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
751 struct drm_i915_gem_object *obj,
752 struct drm_i915_gem_pwrite *args,
753 struct drm_file *file)
755 struct drm_i915_private *dev_priv = dev->dev_private;
757 loff_t offset, page_base;
758 char __user *user_data;
759 int page_offset, page_length, ret;
761 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
765 ret = i915_gem_object_set_to_gtt_domain(obj, true);
769 ret = i915_gem_object_put_fence(obj);
773 user_data = to_user_ptr(args->data_ptr);
776 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
779 /* Operation in this page
781 * page_base = page offset within aperture
782 * page_offset = offset within page
783 * page_length = bytes to copy for this page
785 page_base = offset & ~PAGE_MASK;
786 page_offset = offset_in_page(offset);
787 page_length = remain;
788 if ((page_offset + remain) > PAGE_SIZE)
789 page_length = PAGE_SIZE - page_offset;
791 /* If we get a fault while copying data, then (presumably) our
792 * source page isn't available. Return the error and we'll
793 * retry in the slow path.
795 if (fast_user_write(dev_priv->gtt.mappable, page_base,
796 page_offset, user_data, page_length)) {
801 remain -= page_length;
802 user_data += page_length;
803 offset += page_length;
807 i915_gem_object_ggtt_unpin(obj);
812 /* Per-page copy function for the shmem pwrite fastpath.
813 * Flushes invalid cachelines before writing to the target if
814 * needs_clflush_before is set and flushes out any written cachelines after
815 * writing if needs_clflush is set. */
817 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
818 char __user *user_data,
819 bool page_do_bit17_swizzling,
820 bool needs_clflush_before,
821 bool needs_clflush_after)
826 if (unlikely(page_do_bit17_swizzling))
829 vaddr = kmap_atomic(page);
830 if (needs_clflush_before)
831 drm_clflush_virt_range(vaddr + shmem_page_offset,
833 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
834 user_data, page_length);
835 if (needs_clflush_after)
836 drm_clflush_virt_range(vaddr + shmem_page_offset,
838 kunmap_atomic(vaddr);
840 return ret ? -EFAULT : 0;
843 /* Only difference to the fast-path function is that this can handle bit17
844 * and uses non-atomic copy and kmap functions. */
846 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
847 char __user *user_data,
848 bool page_do_bit17_swizzling,
849 bool needs_clflush_before,
850 bool needs_clflush_after)
856 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
857 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
859 page_do_bit17_swizzling);
860 if (page_do_bit17_swizzling)
861 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
865 ret = __copy_from_user(vaddr + shmem_page_offset,
868 if (needs_clflush_after)
869 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
871 page_do_bit17_swizzling);
874 return ret ? -EFAULT : 0;
878 i915_gem_shmem_pwrite(struct drm_device *dev,
879 struct drm_i915_gem_object *obj,
880 struct drm_i915_gem_pwrite *args,
881 struct drm_file *file)
885 char __user *user_data;
886 int shmem_page_offset, page_length, ret = 0;
887 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
888 int hit_slowpath = 0;
889 int needs_clflush_after = 0;
890 int needs_clflush_before = 0;
893 user_data = to_user_ptr(args->data_ptr);
896 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
898 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
899 /* If we're not in the cpu write domain, set ourself into the gtt
900 * write domain and manually flush cachelines (if required). This
901 * optimizes for the case when the gpu will use the data
902 * right away and we therefore have to clflush anyway. */
903 needs_clflush_after = cpu_write_needs_clflush(obj);
904 ret = i915_gem_object_wait_rendering(obj, false);
908 i915_gem_object_retire(obj);
910 /* Same trick applies to invalidate partially written cachelines read
912 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
913 needs_clflush_before =
914 !cpu_cache_is_coherent(dev, obj->cache_level);
916 ret = i915_gem_object_get_pages(obj);
920 i915_gem_object_pin_pages(obj);
922 offset = args->offset;
925 VM_OBJECT_LOCK(obj->base.vm_obj);
926 vm_object_pip_add(obj->base.vm_obj, 1);
927 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
928 struct vm_page *page = obj->pages[i];
929 int partial_cacheline_write;
931 if (i < offset >> PAGE_SHIFT)
937 /* Operation in this page
939 * shmem_page_offset = offset within page in shmem file
940 * page_length = bytes to copy for this page
942 shmem_page_offset = offset_in_page(offset);
944 page_length = remain;
945 if ((shmem_page_offset + page_length) > PAGE_SIZE)
946 page_length = PAGE_SIZE - shmem_page_offset;
948 /* If we don't overwrite a cacheline completely we need to be
949 * careful to have up-to-date data by first clflushing. Don't
950 * overcomplicate things and flush the entire patch. */
951 partial_cacheline_write = needs_clflush_before &&
952 ((shmem_page_offset | page_length)
953 & (cpu_clflush_line_size - 1));
955 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
956 (page_to_phys(page) & (1 << 17)) != 0;
958 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
959 user_data, page_do_bit17_swizzling,
960 partial_cacheline_write,
961 needs_clflush_after);
966 mutex_unlock(&dev->struct_mutex);
967 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
968 user_data, page_do_bit17_swizzling,
969 partial_cacheline_write,
970 needs_clflush_after);
972 mutex_lock(&dev->struct_mutex);
978 remain -= page_length;
979 user_data += page_length;
980 offset += page_length;
982 vm_object_pip_wakeup(obj->base.vm_obj);
983 VM_OBJECT_UNLOCK(obj->base.vm_obj);
986 i915_gem_object_unpin_pages(obj);
990 * Fixup: Flush cpu caches in case we didn't flush the dirty
991 * cachelines in-line while writing and the object moved
992 * out of the cpu write domain while we've dropped the lock.
994 if (!needs_clflush_after &&
995 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
996 if (i915_gem_clflush_object(obj, obj->pin_display))
997 i915_gem_chipset_flush(dev);
1001 if (needs_clflush_after)
1002 i915_gem_chipset_flush(dev);
1008 * Writes data to the object referenced by handle.
1010 * On error, the contents of the buffer that were to be modified are undefined.
1013 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1014 struct drm_file *file)
1016 struct drm_i915_gem_pwrite *args = data;
1017 struct drm_i915_gem_object *obj;
1020 if (args->size == 0)
1023 if (likely(!i915.prefault_disable)) {
1024 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1030 ret = i915_mutex_lock_interruptible(dev);
1034 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1035 if (&obj->base == NULL) {
1040 /* Bounds check destination. */
1041 if (args->offset > obj->base.size ||
1042 args->size > obj->base.size - args->offset) {
1047 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1050 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1051 * it would end up going through the fenced access, and we'll get
1052 * different detiling behavior between reading and writing.
1053 * pread/pwrite currently are reading and writing from the CPU
1054 * perspective, requiring manual detiling by the client.
1056 if (obj->phys_handle) {
1057 ret = i915_gem_phys_pwrite(obj, args, file);
1061 if (obj->tiling_mode == I915_TILING_NONE &&
1062 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1063 cpu_write_needs_clflush(obj)) {
1064 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1065 /* Note that the gtt paths might fail with non-page-backed user
1066 * pointers (e.g. gtt mappings when moving data between
1067 * textures). Fallback to the shmem path in that case. */
1070 if (ret == -EFAULT || ret == -ENOSPC)
1071 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1074 drm_gem_object_unreference(&obj->base);
1076 mutex_unlock(&dev->struct_mutex);
1081 i915_gem_check_wedge(struct i915_gpu_error *error,
1084 if (i915_reset_in_progress(error)) {
1085 /* Non-interruptible callers can't handle -EAGAIN, hence return
1086 * -EIO unconditionally for these. */
1090 /* Recovery complete, but the reset failed ... */
1091 if (i915_terminally_wedged(error))
1095 * Check if GPU Reset is in progress - we need intel_ring_begin
1096 * to work properly to reinit the hw state while the gpu is
1097 * still marked as reset-in-progress. Handle this with a flag.
1099 if (!error->reload_in_reset)
1107 * Compare seqno against outstanding lazy request. Emit a request if they are
1111 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1115 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1118 if (seqno == ring->outstanding_lazy_seqno)
1119 ret = i915_add_request(ring, NULL);
1125 static void fake_irq(unsigned long data)
1127 wake_up_process((struct task_struct *)data);
1130 static bool missed_irq(struct drm_i915_private *dev_priv,
1131 struct intel_engine_cs *ring)
1133 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1136 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1138 if (file_priv == NULL)
1141 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1146 * __wait_seqno - wait until execution of seqno has finished
1147 * @ring: the ring expected to report seqno
1149 * @reset_counter: reset sequence associated with the given seqno
1150 * @interruptible: do an interruptible wait (normally yes)
1151 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1153 * Note: It is of utmost importance that the passed in seqno and reset_counter
1154 * values have been read by the caller in an smp safe manner. Where read-side
1155 * locks are involved, it is sufficient to read the reset_counter before
1156 * unlocking the lock that protects the seqno. For lockless tricks, the
1157 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1160 * Returns 0 if the seqno was found within the alloted time. Else returns the
1161 * errno with remaining time filled in timeout argument.
1163 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1164 unsigned reset_counter,
1166 struct timespec *timeout,
1167 struct drm_i915_file_private *file_priv)
1169 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1170 struct timespec before, now, wait_time={1,0};
1171 unsigned long timeout_jiffies;
1173 bool wait_forever = true;
1176 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1178 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1181 if (timeout != NULL) {
1182 wait_time = *timeout;
1183 wait_forever = false;
1186 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1188 if (WARN_ON(!ring->irq_get(ring)))
1191 /* Record current time in case interrupted by signal, or wedged */
1192 trace_i915_gem_request_wait_begin(ring, seqno);
1193 getrawmonotonic(&before);
1196 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1197 i915_reset_in_progress(&dev_priv->gpu_error) || \
1198 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1201 end = wait_event_interruptible_timeout(ring->irq_queue,
1205 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1208 /* We need to check whether any gpu reset happened in between
1209 * the caller grabbing the seqno and now ... */
1210 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1213 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1215 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1218 } while (end == 0 && wait_forever);
1220 getrawmonotonic(&now);
1222 ring->irq_put(ring);
1223 trace_i915_gem_request_wait_end(ring, seqno);
1227 struct timespec sleep_time = timespec_sub(now, before);
1228 *timeout = timespec_sub(*timeout, sleep_time);
1229 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1230 set_normalized_timespec(timeout, 0, 0);
1235 case -EAGAIN: /* Wedged */
1236 case -ERESTARTSYS: /* Signal */
1238 case 0: /* Timeout */
1239 return -ETIMEDOUT; /* -ETIME on Linux */
1240 default: /* Completed */
1241 WARN_ON(end < 0); /* We're not aware of other errors */
1247 * Waits for a sequence number to be signaled, and cleans up the
1248 * request and object lists appropriately for that event.
1251 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1253 struct drm_device *dev = ring->dev;
1254 struct drm_i915_private *dev_priv = dev->dev_private;
1255 bool interruptible = dev_priv->mm.interruptible;
1258 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1261 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1265 ret = i915_gem_check_olr(ring, seqno);
1269 return __wait_seqno(ring, seqno,
1270 atomic_read(&dev_priv->gpu_error.reset_counter),
1271 interruptible, NULL, NULL);
1275 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1276 struct intel_engine_cs *ring)
1281 /* Manually manage the write flush as we may have not yet
1282 * retired the buffer.
1284 * Note that the last_write_seqno is always the earlier of
1285 * the two (read/write) seqno, so if we haved successfully waited,
1286 * we know we have passed the last write.
1288 obj->last_write_seqno = 0;
1294 * Ensures that all rendering to the object has completed and the object is
1295 * safe to unbind from the GTT or access from the CPU.
1297 static __must_check int
1298 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1301 struct intel_engine_cs *ring = obj->ring;
1305 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1309 ret = i915_wait_seqno(ring, seqno);
1313 return i915_gem_object_wait_rendering__tail(obj, ring);
1316 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1317 * as the object state may change during this call.
1319 static __must_check int
1320 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1321 struct drm_i915_file_private *file_priv,
1324 struct drm_device *dev = obj->base.dev;
1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326 struct intel_engine_cs *ring = obj->ring;
1327 unsigned reset_counter;
1331 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1332 BUG_ON(!dev_priv->mm.interruptible);
1334 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1338 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1342 ret = i915_gem_check_olr(ring, seqno);
1346 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1347 mutex_unlock(&dev->struct_mutex);
1348 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1349 mutex_lock(&dev->struct_mutex);
1353 return i915_gem_object_wait_rendering__tail(obj, ring);
1357 * Called when user space prepares to use an object with the CPU, either
1358 * through the mmap ioctl's mapping or a GTT mapping.
1361 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1362 struct drm_file *file)
1364 struct drm_i915_gem_set_domain *args = data;
1365 struct drm_i915_gem_object *obj;
1366 uint32_t read_domains = args->read_domains;
1367 uint32_t write_domain = args->write_domain;
1370 /* Only handle setting domains to types used by the CPU. */
1371 if (write_domain & I915_GEM_GPU_DOMAINS)
1374 if (read_domains & I915_GEM_GPU_DOMAINS)
1377 /* Having something in the write domain implies it's in the read
1378 * domain, and only that read domain. Enforce that in the request.
1380 if (write_domain != 0 && read_domains != write_domain)
1383 ret = i915_mutex_lock_interruptible(dev);
1387 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1388 if (&obj->base == NULL) {
1393 /* Try to flush the object off the GPU without holding the lock.
1394 * We will repeat the flush holding the lock in the normal manner
1395 * to catch cases where we are gazumped.
1397 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1403 if (read_domains & I915_GEM_DOMAIN_GTT) {
1404 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1406 /* Silently promote "you're not bound, there was nothing to do"
1407 * to success, since the client was just asking us to
1408 * make sure everything was done.
1413 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1417 drm_gem_object_unreference(&obj->base);
1419 mutex_unlock(&dev->struct_mutex);
1424 * Called when user space has done writes to this buffer
1427 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1428 struct drm_file *file)
1430 struct drm_i915_gem_sw_finish *args = data;
1431 struct drm_i915_gem_object *obj;
1434 ret = i915_mutex_lock_interruptible(dev);
1438 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1439 if (&obj->base == NULL) {
1444 /* Pinned buffers may be scanout, so flush the cache */
1445 if (obj->pin_display)
1446 i915_gem_object_flush_cpu_write_domain(obj, true);
1448 drm_gem_object_unreference(&obj->base);
1450 mutex_unlock(&dev->struct_mutex);
1455 * Maps the contents of an object, returning the address it is mapped
1458 * While the mapping holds a reference on the contents of the object, it doesn't
1459 * imply a ref on the object itself.
1462 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1463 struct drm_file *file)
1465 struct drm_i915_gem_mmap *args = data;
1466 struct drm_gem_object *obj;
1468 struct proc *p = curproc;
1469 vm_map_t map = &p->p_vmspace->vm_map;
1473 obj = drm_gem_object_lookup(dev, file, args->handle);
1477 if (args->size == 0)
1480 size = round_page(args->size);
1481 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1487 * Call hint to ensure that NULL is not returned as a valid address
1488 * and to reduce vm_map traversals. XXX causes instability, use a
1489 * fixed low address as the start point instead to avoid the NULL
1495 * Use 256KB alignment. It is unclear why this matters for a
1496 * virtual address but it appears to fix a number of application/X
1497 * crashes and kms console switching is much faster.
1499 vm_object_hold(obj->vm_obj);
1500 vm_object_reference_locked(obj->vm_obj);
1501 vm_object_drop(obj->vm_obj);
1503 rv = vm_map_find(map, obj->vm_obj, NULL,
1504 args->offset, &addr, args->size,
1505 256 * 1024, /* align */
1507 VM_MAPTYPE_NORMAL, /* maptype */
1508 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1509 VM_PROT_READ | VM_PROT_WRITE, /* max */
1510 MAP_SHARED /* cow */);
1511 if (rv != KERN_SUCCESS) {
1512 vm_object_deallocate(obj->vm_obj);
1513 error = -vm_mmap_to_errno(rv);
1515 args->addr_ptr = (uint64_t)addr;
1518 drm_gem_object_unreference(obj);
1523 * i915_gem_fault - fault a page into the GTT
1525 * vm_obj is locked on entry and expected to be locked on return.
1527 * The vm_pager has placemarked the object with an anonymous memory page
1528 * which we must replace atomically to avoid races against concurrent faults
1529 * on the same page. XXX we currently are unable to do this atomically.
1531 * If we are to return an error we should not touch the anonymous page,
1532 * the caller will deallocate it.
1534 * XXX Most GEM calls appear to be interruptable, but we can't hard loop
1535 * in that case. Release all resources and wait 1 tick before retrying.
1536 * This is a huge problem which needs to be fixed by getting rid of most
1537 * of the interruptability. The linux code does not retry but does appear
1538 * to have some sort of mechanism (VM_FAULT_NOPAGE ?) for the higher level
1539 * to be able to retry.
1543 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1544 * from userspace. The fault handler takes care of binding the object to
1545 * the GTT (if needed), allocating and programming a fence register (again,
1546 * only if needed based on whether the old reg is still valid or the object
1547 * is tiled) and inserting a new PTE into the faulting process.
1549 * Note that the faulting process may involve evicting existing objects
1550 * from the GTT and/or fence registers to make room. So performance may
1551 * suffer if the GTT working set is large or there are few fence registers
1554 * vm_obj is locked on entry and expected to be locked on return. The VM
1555 * pager has placed an anonymous memory page at (obj,offset) which we have
1558 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres)
1560 struct drm_i915_gem_object *obj = to_intel_bo(vm_obj->handle);
1561 struct drm_device *dev = obj->base.dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 unsigned long page_offset;
1564 vm_page_t m, oldm = NULL;
1567 bool write = !!(prot & VM_PROT_WRITE);
1569 intel_runtime_pm_get(dev_priv);
1571 /* We don't use vmf->pgoff since that has the fake offset */
1572 page_offset = (unsigned long)offset;
1575 ret = i915_mutex_lock_interruptible(dev);
1579 trace_i915_gem_object_fault(obj, page_offset, true, write);
1581 /* Try to flush the object off the GPU first without holding the lock.
1582 * Upon reacquiring the lock, we will perform our sanity checks and then
1583 * repeat the flush holding the lock in the normal manner to catch cases
1584 * where we are gazumped.
1586 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1590 /* Access to snoopable pages through the GTT is incoherent. */
1591 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1596 /* Now bind it into the GTT if needed */
1597 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1601 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1605 ret = i915_gem_object_get_fence(obj);
1610 * START FREEBSD MAGIC
1612 * Add a pip count to avoid destruction and certain other
1613 * complex operations (such as collapses?) while unlocked.
1616 vm_object_pip_add(vm_obj, 1);
1621 * XXX We must currently remove the placeholder page now to avoid
1622 * a deadlock against a concurrent i915_gem_release_mmap().
1623 * Otherwise concurrent operation will block on the busy page
1624 * while holding locks which we need to obtain.
1626 if (*mres != NULL) {
1628 if ((oldm->flags & PG_BUSY) == 0)
1629 kprintf("i915_gem_fault: Page was not busy\n");
1631 vm_page_remove(oldm);
1637 VM_OBJECT_UNLOCK(vm_obj);
1642 * Since the object lock was dropped, another thread might have
1643 * faulted on the same GTT address and instantiated the mapping.
1646 VM_OBJECT_LOCK(vm_obj);
1647 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1650 * Try to busy the page, retry on failure (non-zero ret).
1652 if (vm_page_busy_try(m, false)) {
1653 kprintf("i915_gem_fault: PG_BUSY\n");
1664 * Object must be unlocked here to avoid deadlock during
1665 * other GEM calls. All goto targets expect the object to
1668 VM_OBJECT_UNLOCK(vm_obj);
1670 obj->fault_mappable = true;
1673 * Relock object for insertion, leave locked for return.
1675 VM_OBJECT_LOCK(vm_obj);
1676 m = vm_phys_fictitious_to_vm_page(dev_priv->gtt.mappable_base +
1677 i915_gem_obj_ggtt_offset(obj) +
1683 KASSERT((m->flags & PG_FICTITIOUS) != 0, ("not fictitious %p", m));
1684 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1687 * Try to busy the page. Fails on non-zero return.
1689 if (vm_page_busy_try(m, false)) {
1690 kprintf("i915_gem_fault: PG_BUSY(2)\n");
1694 m->valid = VM_PAGE_BITS_ALL;
1697 * Finally, remap it using the new GTT offset.
1699 * (object expected to be in a locked state)
1701 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1705 i915_gem_object_ggtt_unpin(obj);
1706 mutex_unlock(&dev->struct_mutex);
1711 * ALTERNATIVE ERROR RETURN.
1713 * OBJECT EXPECTED TO BE LOCKED.
1716 i915_gem_object_ggtt_unpin(obj);
1718 mutex_unlock(&dev->struct_mutex);
1723 * We eat errors when the gpu is terminally wedged to avoid
1724 * userspace unduly crashing (gl has no provisions for mmaps to
1725 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1726 * and so needs to be reported.
1728 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1729 // ret = VM_FAULT_SIGBUS;
1735 * EAGAIN means the gpu is hung and we'll wait for the error
1736 * handler to reset everything when re-faulting in
1737 * i915_mutex_lock_interruptible.
1742 VM_OBJECT_UNLOCK(vm_obj);
1744 tsleep(&dummy, 0, "delay", 1); /* XXX */
1745 VM_OBJECT_LOCK(vm_obj);
1748 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1749 ret = VM_PAGER_ERROR;
1757 vm_object_pip_wakeup(vm_obj);
1759 intel_runtime_pm_put(dev_priv);
1764 * i915_gem_release_mmap - remove physical page mappings
1765 * @obj: obj in question
1767 * Preserve the reservation of the mmapping with the DRM core code, but
1768 * relinquish ownership of the pages back to the system.
1770 * It is vital that we remove the page mapping if we have mapped a tiled
1771 * object through the GTT and then lose the fence register due to
1772 * resource pressure. Similarly if the object has been moved out of the
1773 * aperture, than pages mapped into userspace must be revoked. Removing the
1774 * mapping will then trigger a page fault on the next user access, allowing
1775 * fixup by i915_gem_fault().
1778 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1784 if (!obj->fault_mappable)
1787 devobj = cdev_pager_lookup(obj);
1788 if (devobj != NULL) {
1789 page_count = OFF_TO_IDX(obj->base.size);
1791 VM_OBJECT_LOCK(devobj);
1792 for (i = 0; i < page_count; i++) {
1793 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1796 cdev_pager_free_page(devobj, m);
1798 VM_OBJECT_UNLOCK(devobj);
1799 vm_object_deallocate(devobj);
1802 obj->fault_mappable = false;
1806 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1808 struct drm_i915_gem_object *obj;
1810 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1811 i915_gem_release_mmap(obj);
1815 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1819 if (INTEL_INFO(dev)->gen >= 4 ||
1820 tiling_mode == I915_TILING_NONE)
1823 /* Previous chips need a power-of-two fence region when tiling */
1824 if (INTEL_INFO(dev)->gen == 3)
1825 gtt_size = 1024*1024;
1827 gtt_size = 512*1024;
1829 while (gtt_size < size)
1836 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1837 * @obj: object to check
1839 * Return the required GTT alignment for an object, taking into account
1840 * potential fence register mapping.
1843 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1844 int tiling_mode, bool fenced)
1847 * Minimum alignment is 4k (GTT page size), but might be greater
1848 * if a fence register is needed for the object.
1850 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1851 tiling_mode == I915_TILING_NONE)
1855 * Previous chips need to be aligned to the size of the smallest
1856 * fence register that can contain the object.
1858 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1861 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1863 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1867 if (drm_vma_node_has_offset(&obj->base.vma_node))
1871 dev_priv->mm.shrinker_no_lock_stealing = true;
1873 ret = drm_gem_create_mmap_offset(&obj->base);
1877 /* Badly fragmented mmap space? The only way we can recover
1878 * space is by destroying unwanted objects. We can't randomly release
1879 * mmap_offsets as userspace expects them to be persistent for the
1880 * lifetime of the objects. The closest we can is to release the
1881 * offsets on purgeable objects by truncating it and marking it purged,
1882 * which prevents userspace from ever using that object again.
1884 i915_gem_shrink(dev_priv,
1885 obj->base.size >> PAGE_SHIFT,
1887 I915_SHRINK_UNBOUND |
1888 I915_SHRINK_PURGEABLE);
1889 ret = drm_gem_create_mmap_offset(&obj->base);
1893 i915_gem_shrink_all(dev_priv);
1894 ret = drm_gem_create_mmap_offset(&obj->base);
1896 dev_priv->mm.shrinker_no_lock_stealing = false;
1901 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1903 drm_gem_free_mmap_offset(&obj->base);
1907 i915_gem_mmap_gtt(struct drm_file *file,
1908 struct drm_device *dev,
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1913 struct drm_i915_gem_object *obj;
1916 ret = i915_mutex_lock_interruptible(dev);
1920 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1921 if (&obj->base == NULL) {
1926 if (obj->base.size > dev_priv->gtt.mappable_end) {
1931 if (obj->madv != I915_MADV_WILLNEED) {
1932 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1937 ret = i915_gem_object_create_mmap_offset(obj);
1941 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1942 DRM_GEM_MAPPING_KEY;
1945 drm_gem_object_unreference(&obj->base);
1947 mutex_unlock(&dev->struct_mutex);
1952 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1954 * @data: GTT mapping ioctl data
1955 * @file: GEM object info
1957 * Simply returns the fake offset to userspace so it can mmap it.
1958 * The mmap call will end up in drm_gem_mmap(), which will set things
1959 * up so we can get faults in the handler above.
1961 * The fault handler will take care of binding the object into the GTT
1962 * (since it may have been evicted to make room for something), allocating
1963 * a fence register, and mapping the appropriate aperture address into
1967 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1968 struct drm_file *file)
1970 struct drm_i915_gem_mmap_gtt *args = data;
1972 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1976 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1978 return obj->madv == I915_MADV_DONTNEED;
1981 /* Immediately discard the backing storage */
1983 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1987 vm_obj = obj->base.vm_obj;
1988 VM_OBJECT_LOCK(vm_obj);
1989 vm_object_page_remove(vm_obj, 0, 0, false);
1990 VM_OBJECT_UNLOCK(vm_obj);
1992 obj->madv = __I915_MADV_PURGED;
1995 /* Try to discard unwanted pages */
1997 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2000 struct address_space *mapping;
2003 switch (obj->madv) {
2004 case I915_MADV_DONTNEED:
2005 i915_gem_object_truncate(obj);
2006 case __I915_MADV_PURGED:
2011 if (obj->base.filp == NULL)
2014 mapping = file_inode(obj->base.filp)->i_mapping,
2015 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2020 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2022 int page_count = obj->base.size / PAGE_SIZE;
2028 BUG_ON(obj->madv == __I915_MADV_PURGED);
2030 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2032 /* In the event of a disaster, abandon all caches and
2033 * hope for the best.
2035 WARN_ON(ret != -EIO);
2036 i915_gem_clflush_object(obj, true);
2037 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2040 if (i915_gem_object_needs_bit17_swizzle(obj))
2041 i915_gem_object_save_bit_17_swizzle(obj);
2043 if (obj->madv == I915_MADV_DONTNEED)
2046 for (i = 0; i < page_count; i++) {
2047 struct vm_page *page = obj->pages[i];
2050 set_page_dirty(page);
2052 if (obj->madv == I915_MADV_WILLNEED)
2053 mark_page_accessed(page);
2055 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
2056 vm_page_unwire(obj->pages[i], 1);
2057 vm_page_wakeup(obj->pages[i]);
2066 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2068 const struct drm_i915_gem_object_ops *ops = obj->ops;
2070 if (obj->pages == NULL)
2073 if (obj->pages_pin_count)
2076 BUG_ON(i915_gem_obj_bound_any(obj));
2078 /* ->put_pages might need to allocate memory for the bit17 swizzle
2079 * array, hence protect them from being reaped by removing them from gtt
2081 list_del(&obj->global_list);
2083 ops->put_pages(obj);
2086 i915_gem_object_invalidate(obj);
2092 i915_gem_shrink(struct drm_i915_private *dev_priv,
2093 long target, unsigned flags)
2095 const bool purgeable_only = flags & I915_SHRINK_PURGEABLE;
2096 unsigned long count = 0;
2099 * As we may completely rewrite the (un)bound list whilst unbinding
2100 * (due to retiring requests) we have to strictly process only
2101 * one element of the list at the time, and recheck the list
2102 * on every iteration.
2104 * In particular, we must hold a reference whilst removing the
2105 * object as we may end up waiting for and/or retiring the objects.
2106 * This might release the final reference (held by the active list)
2107 * and result in the object being freed from under us. This is
2108 * similar to the precautions the eviction code must take whilst
2111 * Also note that although these lists do not hold a reference to
2112 * the object we can safely grab one here: The final object
2113 * unreferencing and the bound_list are both protected by the
2114 * dev->struct_mutex and so we won't ever be able to observe an
2115 * object on the bound_list with a reference count equals 0.
2117 if (flags & I915_SHRINK_UNBOUND) {
2118 struct list_head still_in_list;
2120 INIT_LIST_HEAD(&still_in_list);
2121 while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
2122 struct drm_i915_gem_object *obj;
2124 obj = list_first_entry(&dev_priv->mm.unbound_list,
2125 typeof(*obj), global_list);
2126 list_move_tail(&obj->global_list, &still_in_list);
2128 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
2131 drm_gem_object_reference(&obj->base);
2133 if (i915_gem_object_put_pages(obj) == 0)
2134 count += obj->base.size >> PAGE_SHIFT;
2136 drm_gem_object_unreference(&obj->base);
2138 list_splice(&still_in_list, &dev_priv->mm.unbound_list);
2141 if (flags & I915_SHRINK_BOUND) {
2142 struct list_head still_in_list;
2144 INIT_LIST_HEAD(&still_in_list);
2145 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
2146 struct drm_i915_gem_object *obj;
2147 struct i915_vma *vma, *v;
2149 obj = list_first_entry(&dev_priv->mm.bound_list,
2150 typeof(*obj), global_list);
2151 list_move_tail(&obj->global_list, &still_in_list);
2153 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
2156 drm_gem_object_reference(&obj->base);
2158 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
2159 if (i915_vma_unbind(vma))
2162 if (i915_gem_object_put_pages(obj) == 0)
2163 count += obj->base.size >> PAGE_SHIFT;
2165 drm_gem_object_unreference(&obj->base);
2167 list_splice(&still_in_list, &dev_priv->mm.bound_list);
2173 static unsigned long
2174 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2176 i915_gem_evict_everything(dev_priv->dev);
2177 return i915_gem_shrink(dev_priv, LONG_MAX,
2178 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2182 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2184 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2185 int page_count, i, j;
2187 struct vm_page *page;
2189 /* Assert that the object is not currently in any GPU domain. As it
2190 * wasn't in the GTT, there shouldn't be any way it could have been in
2193 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2194 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2196 page_count = obj->base.size / PAGE_SIZE;
2197 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
2200 /* Get the list of pages out of our struct file. They'll be pinned
2201 * at this point until we release them.
2203 * Fail silently without starting the shrinker
2205 vm_obj = obj->base.vm_obj;
2206 VM_OBJECT_LOCK(vm_obj);
2207 for (i = 0; i < page_count; i++) {
2208 page = shmem_read_mapping_page(vm_obj, i);
2210 i915_gem_shrink(dev_priv,
2213 I915_SHRINK_UNBOUND |
2214 I915_SHRINK_PURGEABLE);
2215 page = shmem_read_mapping_page(vm_obj, i);
2218 /* We've tried hard to allocate the memory by reaping
2219 * our own buffer, now let the real VM do its job and
2220 * go down in flames if truly OOM.
2223 i915_gem_shrink_all(dev_priv);
2224 page = shmem_read_mapping_page(vm_obj, i);
2228 #ifdef CONFIG_SWIOTLB
2229 if (swiotlb_nr_tbl()) {
2231 sg_set_page(sg, page, PAGE_SIZE, 0);
2236 obj->pages[i] = page;
2238 #ifdef CONFIG_SWIOTLB
2239 if (!swiotlb_nr_tbl())
2241 VM_OBJECT_UNLOCK(vm_obj);
2243 if (i915_gem_object_needs_bit17_swizzle(obj))
2244 i915_gem_object_do_bit_17_swizzle(obj);
2249 for (j = 0; j < i; j++) {
2250 page = obj->pages[j];
2251 vm_page_busy_wait(page, FALSE, "i915gem");
2252 vm_page_unwire(page, 0);
2253 vm_page_wakeup(page);
2255 VM_OBJECT_UNLOCK(vm_obj);
2261 /* Ensure that the associated pages are gathered from the backing storage
2262 * and pinned into our object. i915_gem_object_get_pages() may be called
2263 * multiple times before they are released by a single call to
2264 * i915_gem_object_put_pages() - once the pages are no longer referenced
2265 * either as a result of memory pressure (reaping pages under the shrinker)
2266 * or as the object is itself released.
2269 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2271 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2272 const struct drm_i915_gem_object_ops *ops = obj->ops;
2278 if (obj->madv != I915_MADV_WILLNEED) {
2279 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2283 BUG_ON(obj->pages_pin_count);
2285 ret = ops->get_pages(obj);
2289 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2294 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2295 struct intel_engine_cs *ring)
2297 u32 seqno = intel_ring_get_seqno(ring);
2299 BUG_ON(ring == NULL);
2300 if (obj->ring != ring && obj->last_write_seqno) {
2301 /* Keep the seqno relative to the current ring */
2302 obj->last_write_seqno = seqno;
2306 /* Add a reference if we're newly entering the active list. */
2308 drm_gem_object_reference(&obj->base);
2312 list_move_tail(&obj->ring_list, &ring->active_list);
2314 obj->last_read_seqno = seqno;
2317 void i915_vma_move_to_active(struct i915_vma *vma,
2318 struct intel_engine_cs *ring)
2320 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2321 return i915_gem_object_move_to_active(vma->obj, ring);
2325 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2327 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2328 struct i915_address_space *vm;
2329 struct i915_vma *vma;
2331 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2332 BUG_ON(!obj->active);
2334 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2335 vma = i915_gem_obj_to_vma(obj, vm);
2336 if (vma && !list_empty(&vma->mm_list))
2337 list_move_tail(&vma->mm_list, &vm->inactive_list);
2340 intel_fb_obj_flush(obj, true);
2342 list_del_init(&obj->ring_list);
2345 obj->last_read_seqno = 0;
2346 obj->last_write_seqno = 0;
2347 obj->base.write_domain = 0;
2349 obj->last_fenced_seqno = 0;
2352 drm_gem_object_unreference(&obj->base);
2354 WARN_ON(i915_verify_lists(dev));
2358 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2360 struct intel_engine_cs *ring = obj->ring;
2365 if (i915_seqno_passed(ring->get_seqno(ring, true),
2366 obj->last_read_seqno))
2367 i915_gem_object_move_to_inactive(obj);
2371 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_engine_cs *ring;
2377 /* Carefully retire all requests without writing to the rings */
2378 for_each_ring(ring, dev_priv, i) {
2379 ret = intel_ring_idle(ring);
2383 i915_gem_retire_requests(dev);
2385 /* Finally reset hw state */
2386 for_each_ring(ring, dev_priv, i) {
2387 intel_ring_init_seqno(ring, seqno);
2389 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2390 ring->semaphore.sync_seqno[j] = 0;
2396 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2404 /* HWS page needs to be set less than what we
2405 * will inject to ring
2407 ret = i915_gem_init_seqno(dev, seqno - 1);
2411 /* Carefully set the last_seqno value so that wrap
2412 * detection still works
2414 dev_priv->next_seqno = seqno;
2415 dev_priv->last_seqno = seqno - 1;
2416 if (dev_priv->last_seqno == 0)
2417 dev_priv->last_seqno--;
2423 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2427 /* reserve 0 for non-seqno */
2428 if (dev_priv->next_seqno == 0) {
2429 int ret = i915_gem_init_seqno(dev, 0);
2433 dev_priv->next_seqno = 1;
2436 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2440 int __i915_add_request(struct intel_engine_cs *ring,
2441 struct drm_file *file,
2442 struct drm_i915_gem_object *obj,
2445 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2446 struct drm_i915_gem_request *request;
2447 struct intel_ringbuffer *ringbuf;
2448 u32 request_ring_position, request_start;
2451 request = ring->preallocated_lazy_request;
2452 if (WARN_ON(request == NULL))
2455 if (i915.enable_execlists) {
2456 struct intel_context *ctx = request->ctx;
2457 ringbuf = ctx->engine[ring->id].ringbuf;
2459 ringbuf = ring->buffer;
2461 request_start = intel_ring_get_tail(ringbuf);
2463 * Emit any outstanding flushes - execbuf can fail to emit the flush
2464 * after having emitted the batchbuffer command. Hence we need to fix
2465 * things up similar to emitting the lazy request. The difference here
2466 * is that the flush _must_ happen before the next request, no matter
2469 if (i915.enable_execlists) {
2470 ret = logical_ring_flush_all_caches(ringbuf);
2474 ret = intel_ring_flush_all_caches(ring);
2479 /* Record the position of the start of the request so that
2480 * should we detect the updated seqno part-way through the
2481 * GPU processing the request, we never over-estimate the
2482 * position of the head.
2484 request_ring_position = intel_ring_get_tail(ringbuf);
2486 if (i915.enable_execlists) {
2487 ret = ring->emit_request(ringbuf);
2491 ret = ring->add_request(ring);
2496 request->seqno = intel_ring_get_seqno(ring);
2497 request->ring = ring;
2498 request->head = request_start;
2499 request->tail = request_ring_position;
2501 /* Whilst this request exists, batch_obj will be on the
2502 * active_list, and so will hold the active reference. Only when this
2503 * request is retired will the the batch_obj be moved onto the
2504 * inactive_list and lose its active reference. Hence we do not need
2505 * to explicitly hold another reference here.
2507 request->batch_obj = obj;
2509 if (!i915.enable_execlists) {
2510 /* Hold a reference to the current context so that we can inspect
2511 * it later in case a hangcheck error event fires.
2513 request->ctx = ring->last_context;
2515 i915_gem_context_reference(request->ctx);
2518 request->emitted_jiffies = jiffies;
2519 list_add_tail(&request->list, &ring->request_list);
2520 request->file_priv = NULL;
2523 struct drm_i915_file_private *file_priv = file->driver_priv;
2525 spin_lock(&file_priv->mm.lock);
2526 request->file_priv = file_priv;
2527 list_add_tail(&request->client_list,
2528 &file_priv->mm.request_list);
2529 spin_unlock(&file_priv->mm.lock);
2532 trace_i915_gem_request_add(ring, request->seqno);
2533 ring->outstanding_lazy_seqno = 0;
2534 ring->preallocated_lazy_request = NULL;
2536 if (!dev_priv->ums.mm_suspended) {
2537 i915_queue_hangcheck(ring->dev);
2539 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2540 queue_delayed_work(dev_priv->wq,
2541 &dev_priv->mm.retire_work,
2542 round_jiffies_up_relative(HZ));
2543 intel_mark_busy(dev_priv->dev);
2547 *out_seqno = request->seqno;
2552 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2554 struct drm_i915_file_private *file_priv = request->file_priv;
2559 spin_lock(&file_priv->mm.lock);
2560 list_del(&request->client_list);
2561 request->file_priv = NULL;
2562 spin_unlock(&file_priv->mm.lock);
2565 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2566 const struct intel_context *ctx)
2568 unsigned long elapsed;
2570 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2572 if (ctx->hang_stats.banned)
2575 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2576 if (!i915_gem_context_is_default(ctx)) {
2577 DRM_DEBUG("context hanging too fast, banning!\n");
2579 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2580 if (i915_stop_ring_allow_warn(dev_priv))
2581 DRM_ERROR("gpu hanging too fast, banning!\n");
2589 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2590 struct intel_context *ctx,
2593 struct i915_ctx_hang_stats *hs;
2598 hs = &ctx->hang_stats;
2601 hs->banned = i915_context_is_banned(dev_priv, ctx);
2603 hs->guilty_ts = get_seconds();
2605 hs->batch_pending++;
2609 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2611 list_del(&request->list);
2612 i915_gem_request_remove_from_client(request);
2615 i915_gem_context_unreference(request->ctx);
2620 struct drm_i915_gem_request *
2621 i915_gem_find_active_request(struct intel_engine_cs *ring)
2623 struct drm_i915_gem_request *request;
2624 u32 completed_seqno;
2626 completed_seqno = ring->get_seqno(ring, false);
2628 list_for_each_entry(request, &ring->request_list, list) {
2629 if (i915_seqno_passed(completed_seqno, request->seqno))
2638 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2639 struct intel_engine_cs *ring)
2641 struct drm_i915_gem_request *request;
2644 request = i915_gem_find_active_request(ring);
2646 if (request == NULL)
2649 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2651 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2653 list_for_each_entry_continue(request, &ring->request_list, list)
2654 i915_set_reset_status(dev_priv, request->ctx, false);
2657 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2658 struct intel_engine_cs *ring)
2660 while (!list_empty(&ring->active_list)) {
2661 struct drm_i915_gem_object *obj;
2663 obj = list_first_entry(&ring->active_list,
2664 struct drm_i915_gem_object,
2667 i915_gem_object_move_to_inactive(obj);
2671 * We must free the requests after all the corresponding objects have
2672 * been moved off active lists. Which is the same order as the normal
2673 * retire_requests function does. This is important if object hold
2674 * implicit references on things like e.g. ppgtt address spaces through
2677 while (!list_empty(&ring->request_list)) {
2678 struct drm_i915_gem_request *request;
2680 request = list_first_entry(&ring->request_list,
2681 struct drm_i915_gem_request,
2684 i915_gem_free_request(request);
2687 while (!list_empty(&ring->execlist_queue)) {
2688 struct intel_ctx_submit_request *submit_req;
2690 submit_req = list_first_entry(&ring->execlist_queue,
2691 struct intel_ctx_submit_request,
2693 list_del(&submit_req->execlist_link);
2694 intel_runtime_pm_put(dev_priv);
2695 i915_gem_context_unreference(submit_req->ctx);
2699 /* These may not have been flush before the reset, do so now */
2700 kfree(ring->preallocated_lazy_request);
2701 ring->preallocated_lazy_request = NULL;
2702 ring->outstanding_lazy_seqno = 0;
2705 void i915_gem_restore_fences(struct drm_device *dev)
2707 struct drm_i915_private *dev_priv = dev->dev_private;
2710 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2711 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2714 * Commit delayed tiling changes if we have an object still
2715 * attached to the fence, otherwise just clear the fence.
2718 i915_gem_object_update_fence(reg->obj, reg,
2719 reg->obj->tiling_mode);
2721 i915_gem_write_fence(dev, i, NULL);
2726 void i915_gem_reset(struct drm_device *dev)
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 struct intel_engine_cs *ring;
2733 * Before we free the objects from the requests, we need to inspect
2734 * them for finding the guilty party. As the requests only borrow
2735 * their reference to the objects, the inspection must be done first.
2737 for_each_ring(ring, dev_priv, i)
2738 i915_gem_reset_ring_status(dev_priv, ring);
2740 for_each_ring(ring, dev_priv, i)
2741 i915_gem_reset_ring_cleanup(dev_priv, ring);
2743 i915_gem_context_reset(dev);
2745 i915_gem_restore_fences(dev);
2749 * This function clears the request list as sequence numbers are passed.
2752 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2756 if (list_empty(&ring->request_list))
2759 WARN_ON(i915_verify_lists(ring->dev));
2761 seqno = ring->get_seqno(ring, true);
2763 /* Move any buffers on the active list that are no longer referenced
2764 * by the ringbuffer to the flushing/inactive lists as appropriate,
2765 * before we free the context associated with the requests.
2767 while (!list_empty(&ring->active_list)) {
2768 struct drm_i915_gem_object *obj;
2770 obj = list_first_entry(&ring->active_list,
2771 struct drm_i915_gem_object,
2774 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2777 i915_gem_object_move_to_inactive(obj);
2781 while (!list_empty(&ring->request_list)) {
2782 struct drm_i915_gem_request *request;
2783 struct intel_ringbuffer *ringbuf;
2785 request = list_first_entry(&ring->request_list,
2786 struct drm_i915_gem_request,
2789 if (!i915_seqno_passed(seqno, request->seqno))
2792 trace_i915_gem_request_retire(ring, request->seqno);
2794 /* This is one of the few common intersection points
2795 * between legacy ringbuffer submission and execlists:
2796 * we need to tell them apart in order to find the correct
2797 * ringbuffer to which the request belongs to.
2799 if (i915.enable_execlists) {
2800 struct intel_context *ctx = request->ctx;
2801 ringbuf = ctx->engine[ring->id].ringbuf;
2803 ringbuf = ring->buffer;
2805 /* We know the GPU must have read the request to have
2806 * sent us the seqno + interrupt, so use the position
2807 * of tail of the request to update the last known position
2810 ringbuf->last_retired_head = request->tail;
2812 i915_gem_free_request(request);
2815 if (unlikely(ring->trace_irq_seqno &&
2816 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2817 ring->irq_put(ring);
2818 ring->trace_irq_seqno = 0;
2821 WARN_ON(i915_verify_lists(ring->dev));
2825 i915_gem_retire_requests(struct drm_device *dev)
2827 struct drm_i915_private *dev_priv = dev->dev_private;
2828 struct intel_engine_cs *ring;
2832 for_each_ring(ring, dev_priv, i) {
2833 i915_gem_retire_requests_ring(ring);
2834 idle &= list_empty(&ring->request_list);
2838 mod_delayed_work(dev_priv->wq,
2839 &dev_priv->mm.idle_work,
2840 msecs_to_jiffies(100));
2846 i915_gem_retire_work_handler(struct work_struct *work)
2848 struct drm_i915_private *dev_priv =
2849 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2850 struct drm_device *dev = dev_priv->dev;
2853 /* Come back later if the device is busy... */
2855 if (mutex_trylock(&dev->struct_mutex)) {
2856 idle = i915_gem_retire_requests(dev);
2857 mutex_unlock(&dev->struct_mutex);
2860 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2861 round_jiffies_up_relative(HZ));
2865 i915_gem_idle_work_handler(struct work_struct *work)
2867 struct drm_i915_private *dev_priv =
2868 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2870 intel_mark_idle(dev_priv->dev);
2874 * Ensures that an object will eventually get non-busy by flushing any required
2875 * write domains, emitting any outstanding lazy request and retiring and
2876 * completed requests.
2879 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2884 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2888 i915_gem_retire_requests_ring(obj->ring);
2895 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2896 * @DRM_IOCTL_ARGS: standard ioctl arguments
2898 * Returns 0 if successful, else an error is returned with the remaining time in
2899 * the timeout parameter.
2900 * -ETIME: object is still busy after timeout
2901 * -ERESTARTSYS: signal interrupted the wait
2902 * -ENONENT: object doesn't exist
2903 * Also possible, but rare:
2904 * -EAGAIN: GPU wedged
2906 * -ENODEV: Internal IRQ fail
2907 * -E?: The add request failed
2909 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2910 * non-zero timeout parameter the wait ioctl will wait for the given number of
2911 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2912 * without holding struct_mutex the object may become re-busied before this
2913 * function completes. A similar but shorter * race condition exists in the busy
2917 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2919 struct drm_i915_private *dev_priv = dev->dev_private;
2920 struct drm_i915_gem_wait *args = data;
2921 struct drm_i915_gem_object *obj;
2922 struct intel_engine_cs *ring = NULL;
2923 struct timespec timeout_stack, *timeout = NULL;
2924 unsigned reset_counter;
2928 if (args->timeout_ns >= 0) {
2929 timeout_stack = ns_to_timespec(args->timeout_ns);
2930 timeout = &timeout_stack;
2933 ret = i915_mutex_lock_interruptible(dev);
2937 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2938 if (&obj->base == NULL) {
2939 mutex_unlock(&dev->struct_mutex);
2943 /* Need to make sure the object gets inactive eventually. */
2944 ret = i915_gem_object_flush_active(obj);
2949 seqno = obj->last_read_seqno;
2956 /* Do this after OLR check to make sure we make forward progress polling
2957 * on this IOCTL with a 0 timeout (like busy ioctl)
2959 if (!args->timeout_ns) {
2964 drm_gem_object_unreference(&obj->base);
2965 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2966 mutex_unlock(&dev->struct_mutex);
2968 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2970 args->timeout_ns = timespec_to_ns(timeout);
2974 drm_gem_object_unreference(&obj->base);
2975 mutex_unlock(&dev->struct_mutex);
2980 * i915_gem_object_sync - sync an object to a ring.
2982 * @obj: object which may be in use on another ring.
2983 * @to: ring we wish to use the object on. May be NULL.
2985 * This code is meant to abstract object synchronization with the GPU.
2986 * Calling with NULL implies synchronizing the object with the CPU
2987 * rather than a particular GPU ring.
2989 * Returns 0 if successful, else propagates up the lower layer error.
2992 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2993 struct intel_engine_cs *to)
2995 struct intel_engine_cs *from = obj->ring;
2999 if (from == NULL || to == from)
3002 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
3003 return i915_gem_object_wait_rendering(obj, false);
3005 idx = intel_ring_sync_index(from, to);
3007 seqno = obj->last_read_seqno;
3008 /* Optimization: Avoid semaphore sync when we are sure we already
3009 * waited for an object with higher seqno */
3010 if (seqno <= from->semaphore.sync_seqno[idx])
3013 ret = i915_gem_check_olr(obj->ring, seqno);
3017 trace_i915_gem_ring_sync_to(from, to, seqno);
3018 ret = to->semaphore.sync_to(to, from, seqno);
3020 /* We use last_read_seqno because sync_to()
3021 * might have just caused seqno wrap under
3024 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
3029 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3031 u32 old_write_domain, old_read_domains;
3033 /* Force a pagefault for domain tracking on next user access */
3034 i915_gem_release_mmap(obj);
3036 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3039 /* Wait for any direct GTT access to complete */
3042 old_read_domains = obj->base.read_domains;
3043 old_write_domain = obj->base.write_domain;
3045 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3046 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3048 trace_i915_gem_object_change_domain(obj,
3053 int i915_vma_unbind(struct i915_vma *vma)
3055 struct drm_i915_gem_object *obj = vma->obj;
3056 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3059 if (list_empty(&vma->vma_link))
3062 if (!drm_mm_node_allocated(&vma->node)) {
3063 i915_gem_vma_destroy(vma);
3070 BUG_ON(obj->pages == NULL);
3072 ret = i915_gem_object_finish_gpu(obj);
3075 /* Continue on if we fail due to EIO, the GPU is hung so we
3076 * should be safe and we need to cleanup or else we might
3077 * cause memory corruption through use-after-free.
3080 /* Throw away the active reference before moving to the unbound list */
3081 i915_gem_object_retire(obj);
3083 if (i915_is_ggtt(vma->vm)) {
3084 i915_gem_object_finish_gtt(obj);
3086 /* release the fence reg _after_ flushing */
3087 ret = i915_gem_object_put_fence(obj);
3092 trace_i915_vma_unbind(vma);
3094 vma->unbind_vma(vma);
3096 list_del_init(&vma->mm_list);
3097 if (i915_is_ggtt(vma->vm))
3098 obj->map_and_fenceable = false;
3100 drm_mm_remove_node(&vma->node);
3101 i915_gem_vma_destroy(vma);
3103 /* Since the unbound list is global, only move to that list if
3104 * no more VMAs exist. */
3105 if (list_empty(&obj->vma_list)) {
3106 i915_gem_gtt_finish_object(obj);
3107 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3110 /* And finally now the object is completely decoupled from this vma,
3111 * we can drop its hold on the backing storage and allow it to be
3112 * reaped by the shrinker.
3114 i915_gem_object_unpin_pages(obj);
3119 int i915_gpu_idle(struct drm_device *dev)
3121 struct drm_i915_private *dev_priv = dev->dev_private;
3122 struct intel_engine_cs *ring;
3125 /* Flush everything onto the inactive list. */
3126 for_each_ring(ring, dev_priv, i) {
3127 if (!i915.enable_execlists) {
3128 ret = i915_switch_context(ring, ring->default_context);
3133 ret = intel_ring_idle(ring);
3141 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3142 struct drm_i915_gem_object *obj)
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3146 int fence_pitch_shift;
3148 if (INTEL_INFO(dev)->gen >= 6) {
3149 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3150 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3152 fence_reg = FENCE_REG_965_0;
3153 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3156 fence_reg += reg * 8;
3158 /* To w/a incoherency with non-atomic 64-bit register updates,
3159 * we split the 64-bit update into two 32-bit writes. In order
3160 * for a partial fence not to be evaluated between writes, we
3161 * precede the update with write to turn off the fence register,
3162 * and only enable the fence as the last step.
3164 * For extra levels of paranoia, we make sure each step lands
3165 * before applying the next step.
3167 I915_WRITE(fence_reg, 0);
3168 POSTING_READ(fence_reg);
3171 u32 size = i915_gem_obj_ggtt_size(obj);
3174 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3176 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3177 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3178 if (obj->tiling_mode == I915_TILING_Y)
3179 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3180 val |= I965_FENCE_REG_VALID;
3182 I915_WRITE(fence_reg + 4, val >> 32);
3183 POSTING_READ(fence_reg + 4);
3185 I915_WRITE(fence_reg + 0, val);
3186 POSTING_READ(fence_reg);
3188 I915_WRITE(fence_reg + 4, 0);
3189 POSTING_READ(fence_reg + 4);
3193 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3194 struct drm_i915_gem_object *obj)
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3200 u32 size = i915_gem_obj_ggtt_size(obj);
3204 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3205 (size & -size) != size ||
3206 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3207 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3208 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3210 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3215 /* Note: pitch better be a power of two tile widths */
3216 pitch_val = obj->stride / tile_width;
3217 pitch_val = ffs(pitch_val) - 1;
3219 val = i915_gem_obj_ggtt_offset(obj);
3220 if (obj->tiling_mode == I915_TILING_Y)
3221 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3222 val |= I915_FENCE_SIZE_BITS(size);
3223 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3224 val |= I830_FENCE_REG_VALID;
3229 reg = FENCE_REG_830_0 + reg * 4;
3231 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3233 I915_WRITE(reg, val);
3237 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3238 struct drm_i915_gem_object *obj)
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3244 u32 size = i915_gem_obj_ggtt_size(obj);
3247 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3248 (size & -size) != size ||
3249 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3250 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3251 i915_gem_obj_ggtt_offset(obj), size);
3253 pitch_val = obj->stride / 128;
3254 pitch_val = ffs(pitch_val) - 1;
3256 val = i915_gem_obj_ggtt_offset(obj);
3257 if (obj->tiling_mode == I915_TILING_Y)
3258 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3259 val |= I830_FENCE_SIZE_BITS(size);
3260 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3261 val |= I830_FENCE_REG_VALID;
3265 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3266 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3269 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3271 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3274 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3275 struct drm_i915_gem_object *obj)
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3279 /* Ensure that all CPU reads are completed before installing a fence
3280 * and all writes before removing the fence.
3282 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3285 WARN(obj && (!obj->stride || !obj->tiling_mode),
3286 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3287 obj->stride, obj->tiling_mode);
3289 switch (INTEL_INFO(dev)->gen) {
3294 case 4: i965_write_fence_reg(dev, reg, obj); break;
3295 case 3: i915_write_fence_reg(dev, reg, obj); break;
3296 case 2: i830_write_fence_reg(dev, reg, obj); break;
3300 /* And similarly be paranoid that no direct access to this region
3301 * is reordered to before the fence is installed.
3303 if (i915_gem_object_needs_mb(obj))
3307 static inline int fence_number(struct drm_i915_private *dev_priv,
3308 struct drm_i915_fence_reg *fence)
3310 return fence - dev_priv->fence_regs;
3313 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3314 struct drm_i915_fence_reg *fence,
3317 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3318 int reg = fence_number(dev_priv, fence);
3320 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3323 obj->fence_reg = reg;
3325 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3327 obj->fence_reg = I915_FENCE_REG_NONE;
3329 list_del_init(&fence->lru_list);
3331 obj->fence_dirty = false;
3335 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3337 if (obj->last_fenced_seqno) {
3338 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3342 obj->last_fenced_seqno = 0;
3349 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3351 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3352 struct drm_i915_fence_reg *fence;
3355 ret = i915_gem_object_wait_fence(obj);
3359 if (obj->fence_reg == I915_FENCE_REG_NONE)
3362 fence = &dev_priv->fence_regs[obj->fence_reg];
3364 if (WARN_ON(fence->pin_count))
3367 i915_gem_object_fence_lost(obj);
3368 i915_gem_object_update_fence(obj, fence, false);
3373 static struct drm_i915_fence_reg *
3374 i915_find_fence_reg(struct drm_device *dev)
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 struct drm_i915_fence_reg *reg, *avail;
3380 /* First try to find a free reg */
3382 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3383 reg = &dev_priv->fence_regs[i];
3387 if (!reg->pin_count)
3394 /* None available, try to steal one or wait for a user to finish */
3395 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3403 /* Wait for completion of pending flips which consume fences */
3404 if (intel_has_pending_fb_unpin(dev))
3405 return ERR_PTR(-EAGAIN);
3407 return ERR_PTR(-EDEADLK);
3411 * i915_gem_object_get_fence - set up fencing for an object
3412 * @obj: object to map through a fence reg
3414 * When mapping objects through the GTT, userspace wants to be able to write
3415 * to them without having to worry about swizzling if the object is tiled.
3416 * This function walks the fence regs looking for a free one for @obj,
3417 * stealing one if it can't find any.
3419 * It then sets up the reg based on the object's properties: address, pitch
3420 * and tiling format.
3422 * For an untiled surface, this removes any existing fence.
3425 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3427 struct drm_device *dev = obj->base.dev;
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 bool enable = obj->tiling_mode != I915_TILING_NONE;
3430 struct drm_i915_fence_reg *reg;
3433 /* Have we updated the tiling parameters upon the object and so
3434 * will need to serialise the write to the associated fence register?
3436 if (obj->fence_dirty) {
3437 ret = i915_gem_object_wait_fence(obj);
3442 /* Just update our place in the LRU if our fence is getting reused. */
3443 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3444 reg = &dev_priv->fence_regs[obj->fence_reg];
3445 if (!obj->fence_dirty) {
3446 list_move_tail(®->lru_list,
3447 &dev_priv->mm.fence_list);
3450 } else if (enable) {
3451 if (WARN_ON(!obj->map_and_fenceable))
3454 reg = i915_find_fence_reg(dev);
3456 return PTR_ERR(reg);
3459 struct drm_i915_gem_object *old = reg->obj;
3461 ret = i915_gem_object_wait_fence(old);
3465 i915_gem_object_fence_lost(old);
3470 i915_gem_object_update_fence(obj, reg, enable);
3475 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3476 unsigned long cache_level)
3478 struct drm_mm_node *gtt_space = &vma->node;
3479 struct drm_mm_node *other;
3482 * On some machines we have to be careful when putting differing types
3483 * of snoopable memory together to avoid the prefetcher crossing memory
3484 * domains and dying. During vm initialisation, we decide whether or not
3485 * these constraints apply and set the drm_mm.color_adjust
3488 if (vma->vm->mm.color_adjust == NULL)
3491 if (!drm_mm_node_allocated(gtt_space))
3494 if (list_empty(>t_space->node_list))
3497 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3498 if (other->allocated && !other->hole_follows && other->color != cache_level)
3501 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3502 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3508 static void i915_gem_verify_gtt(struct drm_device *dev)
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct drm_i915_gem_object *obj;
3515 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3516 if (obj->gtt_space == NULL) {
3517 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3522 if (obj->cache_level != obj->gtt_space->color) {
3523 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3524 i915_gem_obj_ggtt_offset(obj),
3525 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3527 obj->gtt_space->color);
3532 if (!i915_gem_valid_gtt_space(dev,
3534 obj->cache_level)) {
3535 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3536 i915_gem_obj_ggtt_offset(obj),
3537 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3549 * Finds free space in the GTT aperture and binds the object there.
3551 static struct i915_vma *
3552 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3553 struct i915_address_space *vm,
3557 struct drm_device *dev = obj->base.dev;
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 u32 size, fence_size, fence_alignment, unfenced_alignment;
3560 unsigned long start =
3561 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3563 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3564 struct i915_vma *vma;
3567 fence_size = i915_gem_get_gtt_size(dev,
3570 fence_alignment = i915_gem_get_gtt_alignment(dev,
3572 obj->tiling_mode, true);
3573 unfenced_alignment =
3574 i915_gem_get_gtt_alignment(dev,
3576 obj->tiling_mode, false);
3579 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3581 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3582 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3583 return ERR_PTR(-EINVAL);
3586 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3588 /* If the object is bigger than the entire aperture, reject it early
3589 * before evicting everything in a vain attempt to find space.
3591 if (obj->base.size > end) {
3592 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3594 flags & PIN_MAPPABLE ? "mappable" : "total",
3596 return ERR_PTR(-E2BIG);
3599 ret = i915_gem_object_get_pages(obj);
3601 return ERR_PTR(ret);
3603 i915_gem_object_pin_pages(obj);
3605 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3610 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3614 DRM_MM_SEARCH_DEFAULT,
3615 DRM_MM_CREATE_DEFAULT);
3617 ret = i915_gem_evict_something(dev, vm, size, alignment,
3626 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3628 goto err_remove_node;
3631 ret = i915_gem_gtt_prepare_object(obj);
3633 goto err_remove_node;
3635 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3636 list_add_tail(&vma->mm_list, &vm->inactive_list);
3638 if (i915_is_ggtt(vm)) {
3639 bool mappable, fenceable;
3641 fenceable = (vma->node.size == fence_size &&
3642 (vma->node.start & (fence_alignment - 1)) == 0);
3644 mappable = (vma->node.start + obj->base.size <=
3645 dev_priv->gtt.mappable_end);
3647 obj->map_and_fenceable = mappable && fenceable;
3650 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3652 trace_i915_vma_bind(vma, flags);
3653 vma->bind_vma(vma, obj->cache_level,
3654 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3656 i915_gem_verify_gtt(dev);
3660 drm_mm_remove_node(&vma->node);
3662 i915_gem_vma_destroy(vma);
3665 i915_gem_object_unpin_pages(obj);
3670 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3673 /* If we don't have a page list set up, then we're not pinned
3674 * to GPU, and we can ignore the cache flush because it'll happen
3675 * again at bind time.
3677 if (obj->pages == NULL)
3681 * Stolen memory is always coherent with the GPU as it is explicitly
3682 * marked as wc by the system, or the system is cache-coherent.
3687 /* If the GPU is snooping the contents of the CPU cache,
3688 * we do not need to manually clear the CPU cache lines. However,
3689 * the caches are only snooped when the render cache is
3690 * flushed/invalidated. As we always have to emit invalidations
3691 * and flushes when moving into and out of the RENDER domain, correct
3692 * snooping behaviour occurs naturally as the result of our domain
3695 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3698 trace_i915_gem_object_clflush(obj);
3699 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3704 /** Flushes the GTT write domain for the object if it's dirty. */
3706 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3708 uint32_t old_write_domain;
3710 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3713 /* No actual flushing is required for the GTT write domain. Writes
3714 * to it immediately go to main memory as far as we know, so there's
3715 * no chipset flush. It also doesn't land in render cache.
3717 * However, we do have to enforce the order so that all writes through
3718 * the GTT land before any writes to the device, such as updates to
3723 old_write_domain = obj->base.write_domain;
3724 obj->base.write_domain = 0;
3726 intel_fb_obj_flush(obj, false);
3728 intel_fb_obj_flush(obj, false);
3730 trace_i915_gem_object_change_domain(obj,
3731 obj->base.read_domains,
3735 /** Flushes the CPU write domain for the object if it's dirty. */
3737 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3740 uint32_t old_write_domain;
3742 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3745 if (i915_gem_clflush_object(obj, force))
3746 i915_gem_chipset_flush(obj->base.dev);
3748 old_write_domain = obj->base.write_domain;
3749 obj->base.write_domain = 0;
3751 trace_i915_gem_object_change_domain(obj,
3752 obj->base.read_domains,
3757 * Moves a single object to the GTT read, and possibly write domain.
3759 * This function returns when the move is complete, including waiting on
3763 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3765 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3766 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3767 uint32_t old_write_domain, old_read_domains;
3770 /* Not valid to be called on unbound objects. */
3774 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3777 ret = i915_gem_object_wait_rendering(obj, !write);
3781 i915_gem_object_retire(obj);
3782 i915_gem_object_flush_cpu_write_domain(obj, false);
3784 /* Serialise direct access to this object with the barriers for
3785 * coherent writes from the GPU, by effectively invalidating the
3786 * GTT domain upon first access.
3788 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3791 old_write_domain = obj->base.write_domain;
3792 old_read_domains = obj->base.read_domains;
3794 /* It should now be out of any other write domains, and we can update
3795 * the domain values for our changes.
3797 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3798 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3800 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3801 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3806 intel_fb_obj_invalidate(obj, NULL);
3808 trace_i915_gem_object_change_domain(obj,
3812 /* And bump the LRU for this access */
3813 if (i915_gem_object_is_inactive(obj))
3814 list_move_tail(&vma->mm_list,
3815 &dev_priv->gtt.base.inactive_list);
3820 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3821 enum i915_cache_level cache_level)
3823 struct drm_device *dev = obj->base.dev;
3824 struct i915_vma *vma, *next;
3827 if (obj->cache_level == cache_level)
3830 if (i915_gem_obj_is_pinned(obj)) {
3831 DRM_DEBUG("can not change the cache level of pinned objects\n");
3835 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3836 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3837 ret = i915_vma_unbind(vma);
3843 if (i915_gem_obj_bound_any(obj)) {
3844 ret = i915_gem_object_finish_gpu(obj);
3848 i915_gem_object_finish_gtt(obj);
3850 /* Before SandyBridge, you could not use tiling or fence
3851 * registers with snooped memory, so relinquish any fences
3852 * currently pointing to our region in the aperture.
3854 if (INTEL_INFO(dev)->gen < 6) {
3855 ret = i915_gem_object_put_fence(obj);
3860 list_for_each_entry(vma, &obj->vma_list, vma_link)
3861 if (drm_mm_node_allocated(&vma->node))
3862 vma->bind_vma(vma, cache_level,
3863 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3866 list_for_each_entry(vma, &obj->vma_list, vma_link)
3867 vma->node.color = cache_level;
3868 obj->cache_level = cache_level;
3870 if (cpu_write_needs_clflush(obj)) {
3871 u32 old_read_domains, old_write_domain;
3873 /* If we're coming from LLC cached, then we haven't
3874 * actually been tracking whether the data is in the
3875 * CPU cache or not, since we only allow one bit set
3876 * in obj->write_domain and have been skipping the clflushes.
3877 * Just set it to the CPU cache for now.
3879 i915_gem_object_retire(obj);
3880 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3882 old_read_domains = obj->base.read_domains;
3883 old_write_domain = obj->base.write_domain;
3885 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3886 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3888 trace_i915_gem_object_change_domain(obj,
3893 i915_gem_verify_gtt(dev);
3897 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3898 struct drm_file *file)
3900 struct drm_i915_gem_caching *args = data;
3901 struct drm_i915_gem_object *obj;
3904 ret = i915_mutex_lock_interruptible(dev);
3908 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3909 if (&obj->base == NULL) {
3914 switch (obj->cache_level) {
3915 case I915_CACHE_LLC:
3916 case I915_CACHE_L3_LLC:
3917 args->caching = I915_CACHING_CACHED;
3921 args->caching = I915_CACHING_DISPLAY;
3925 args->caching = I915_CACHING_NONE;
3929 drm_gem_object_unreference(&obj->base);
3931 mutex_unlock(&dev->struct_mutex);
3935 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3936 struct drm_file *file)
3938 struct drm_i915_gem_caching *args = data;
3939 struct drm_i915_gem_object *obj;
3940 enum i915_cache_level level;
3943 switch (args->caching) {
3944 case I915_CACHING_NONE:
3945 level = I915_CACHE_NONE;
3947 case I915_CACHING_CACHED:
3948 level = I915_CACHE_LLC;
3950 case I915_CACHING_DISPLAY:
3951 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3957 ret = i915_mutex_lock_interruptible(dev);
3961 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3962 if (&obj->base == NULL) {
3967 ret = i915_gem_object_set_cache_level(obj, level);
3969 drm_gem_object_unreference(&obj->base);
3971 mutex_unlock(&dev->struct_mutex);
3975 static bool is_pin_display(struct drm_i915_gem_object *obj)
3977 struct i915_vma *vma;
3979 vma = i915_gem_obj_to_ggtt(obj);
3983 /* There are 3 sources that pin objects:
3984 * 1. The display engine (scanouts, sprites, cursors);
3985 * 2. Reservations for execbuffer;
3988 * We can ignore reservations as we hold the struct_mutex and
3989 * are only called outside of the reservation path. The user
3990 * can only increment pin_count once, and so if after
3991 * subtracting the potential reference by the user, any pin_count
3992 * remains, it must be due to another use by the display engine.
3994 return vma->pin_count - !!obj->user_pin_count;
3998 * Prepare buffer for display plane (scanout, cursors, etc).
3999 * Can be called from an uninterruptible phase (modesetting) and allows
4000 * any flushes to be pipelined (for pageflips).
4003 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4005 struct intel_engine_cs *pipelined)
4007 u32 old_read_domains, old_write_domain;
4008 bool was_pin_display;
4011 if (pipelined != obj->ring) {
4012 ret = i915_gem_object_sync(obj, pipelined);
4017 /* Mark the pin_display early so that we account for the
4018 * display coherency whilst setting up the cache domains.
4020 was_pin_display = obj->pin_display;
4021 obj->pin_display = true;
4023 /* The display engine is not coherent with the LLC cache on gen6. As
4024 * a result, we make sure that the pinning that is about to occur is
4025 * done with uncached PTEs. This is lowest common denominator for all
4028 * However for gen6+, we could do better by using the GFDT bit instead
4029 * of uncaching, which would allow us to flush all the LLC-cached data
4030 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4032 ret = i915_gem_object_set_cache_level(obj,
4033 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4035 goto err_unpin_display;
4037 /* As the user may map the buffer once pinned in the display plane
4038 * (e.g. libkms for the bootup splash), we have to ensure that we
4039 * always use map_and_fenceable for all scanout buffers.
4041 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
4043 goto err_unpin_display;
4045 i915_gem_object_flush_cpu_write_domain(obj, true);
4047 old_write_domain = obj->base.write_domain;
4048 old_read_domains = obj->base.read_domains;
4050 /* It should now be out of any other write domains, and we can update
4051 * the domain values for our changes.
4053 obj->base.write_domain = 0;
4054 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4056 trace_i915_gem_object_change_domain(obj,
4063 WARN_ON(was_pin_display != is_pin_display(obj));
4064 obj->pin_display = was_pin_display;
4069 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4071 i915_gem_object_ggtt_unpin(obj);
4072 obj->pin_display = is_pin_display(obj);
4076 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4080 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4083 ret = i915_gem_object_wait_rendering(obj, false);
4087 /* Ensure that we invalidate the GPU's caches and TLBs. */
4088 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4093 * Moves a single object to the CPU read, and possibly write domain.
4095 * This function returns when the move is complete, including waiting on
4099 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4101 uint32_t old_write_domain, old_read_domains;
4104 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4107 ret = i915_gem_object_wait_rendering(obj, !write);
4111 i915_gem_object_retire(obj);
4112 i915_gem_object_flush_gtt_write_domain(obj);
4114 old_write_domain = obj->base.write_domain;
4115 old_read_domains = obj->base.read_domains;
4117 /* Flush the CPU cache if it's still invalid. */
4118 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4119 i915_gem_clflush_object(obj, false);
4121 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4124 /* It should now be out of any other write domains, and we can update
4125 * the domain values for our changes.
4127 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4129 /* If we're writing through the CPU, then the GPU read domains will
4130 * need to be invalidated at next use.
4133 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4134 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4138 intel_fb_obj_invalidate(obj, NULL);
4140 trace_i915_gem_object_change_domain(obj,
4147 /* Throttle our rendering by waiting until the ring has completed our requests
4148 * emitted over 20 msec ago.
4150 * Note that if we were to use the current jiffies each time around the loop,
4151 * we wouldn't escape the function with any frames outstanding if the time to
4152 * render a frame was over 20ms.
4154 * This should get us reasonable parallelism between CPU and GPU but also
4155 * relatively low latency when blocking on a particular request to finish.
4158 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4160 struct drm_i915_private *dev_priv = dev->dev_private;
4161 struct drm_i915_file_private *file_priv = file->driver_priv;
4162 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4163 struct drm_i915_gem_request *request;
4164 struct intel_engine_cs *ring = NULL;
4165 unsigned reset_counter;
4169 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4173 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4177 spin_lock(&file_priv->mm.lock);
4178 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4179 if (time_after_eq(request->emitted_jiffies, recent_enough))
4182 ring = request->ring;
4183 seqno = request->seqno;
4185 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4186 spin_unlock(&file_priv->mm.lock);
4191 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4193 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4199 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4201 struct drm_i915_gem_object *obj = vma->obj;
4204 vma->node.start & (alignment - 1))
4207 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4210 if (flags & PIN_OFFSET_BIAS &&
4211 vma->node.start < (flags & PIN_OFFSET_MASK))
4218 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4219 struct i915_address_space *vm,
4223 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4224 struct i915_vma *vma;
4227 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4230 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4233 vma = i915_gem_obj_to_vma(obj, vm);
4235 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4238 if (i915_vma_misplaced(vma, alignment, flags)) {
4239 WARN(vma->pin_count,
4240 "bo is already pinned with incorrect alignment:"
4241 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4242 " obj->map_and_fenceable=%d\n",
4243 i915_gem_obj_offset(obj, vm), alignment,
4244 !!(flags & PIN_MAPPABLE),
4245 obj->map_and_fenceable);
4246 ret = i915_vma_unbind(vma);
4254 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4255 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4257 return PTR_ERR(vma);
4260 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4261 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4264 if (flags & PIN_MAPPABLE)
4265 obj->pin_mappable |= true;
4271 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4273 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4276 BUG_ON(vma->pin_count == 0);
4277 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4279 if (--vma->pin_count == 0)
4280 obj->pin_mappable = false;
4284 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4286 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4287 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4288 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4290 WARN_ON(!ggtt_vma ||
4291 dev_priv->fence_regs[obj->fence_reg].pin_count >
4292 ggtt_vma->pin_count);
4293 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4300 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4302 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4303 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4304 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4305 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4310 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4311 struct drm_file *file)
4313 struct drm_i915_gem_pin *args = data;
4314 struct drm_i915_gem_object *obj;
4317 if (INTEL_INFO(dev)->gen >= 6)
4320 ret = i915_mutex_lock_interruptible(dev);
4324 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4325 if (&obj->base == NULL) {
4330 if (obj->madv != I915_MADV_WILLNEED) {
4331 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4336 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4337 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4343 if (obj->user_pin_count == ULONG_MAX) {
4348 if (obj->user_pin_count == 0) {
4349 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4354 obj->user_pin_count++;
4355 obj->pin_filp = file;
4357 args->offset = i915_gem_obj_ggtt_offset(obj);
4359 drm_gem_object_unreference(&obj->base);
4361 mutex_unlock(&dev->struct_mutex);
4366 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4367 struct drm_file *file)
4369 struct drm_i915_gem_pin *args = data;
4370 struct drm_i915_gem_object *obj;
4373 ret = i915_mutex_lock_interruptible(dev);
4377 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4378 if (&obj->base == NULL) {
4383 if (obj->pin_filp != file) {
4384 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4389 obj->user_pin_count--;
4390 if (obj->user_pin_count == 0) {
4391 obj->pin_filp = NULL;
4392 i915_gem_object_ggtt_unpin(obj);
4396 drm_gem_object_unreference(&obj->base);
4398 mutex_unlock(&dev->struct_mutex);
4403 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4404 struct drm_file *file)
4406 struct drm_i915_gem_busy *args = data;
4407 struct drm_i915_gem_object *obj;
4410 ret = i915_mutex_lock_interruptible(dev);
4414 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4415 if (&obj->base == NULL) {
4420 /* Count all active objects as busy, even if they are currently not used
4421 * by the gpu. Users of this interface expect objects to eventually
4422 * become non-busy without any further actions, therefore emit any
4423 * necessary flushes here.
4425 ret = i915_gem_object_flush_active(obj);
4427 args->busy = obj->active;
4429 args->busy |= intel_ring_flag(obj->ring) << 16;
4432 drm_gem_object_unreference(&obj->base);
4434 mutex_unlock(&dev->struct_mutex);
4439 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4440 struct drm_file *file_priv)
4442 return i915_gem_ring_throttle(dev, file_priv);
4446 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4447 struct drm_file *file_priv)
4449 struct drm_i915_gem_madvise *args = data;
4450 struct drm_i915_gem_object *obj;
4453 switch (args->madv) {
4454 case I915_MADV_DONTNEED:
4455 case I915_MADV_WILLNEED:
4461 ret = i915_mutex_lock_interruptible(dev);
4465 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4466 if (&obj->base == NULL) {
4471 if (i915_gem_obj_is_pinned(obj)) {
4476 if (obj->madv != __I915_MADV_PURGED)
4477 obj->madv = args->madv;
4479 /* if the object is no longer attached, discard its backing storage */
4480 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4481 i915_gem_object_truncate(obj);
4483 args->retained = obj->madv != __I915_MADV_PURGED;
4486 drm_gem_object_unreference(&obj->base);
4488 mutex_unlock(&dev->struct_mutex);
4492 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4493 const struct drm_i915_gem_object_ops *ops)
4495 INIT_LIST_HEAD(&obj->global_list);
4496 INIT_LIST_HEAD(&obj->ring_list);
4497 INIT_LIST_HEAD(&obj->obj_exec_link);
4498 INIT_LIST_HEAD(&obj->vma_list);
4502 obj->fence_reg = I915_FENCE_REG_NONE;
4503 obj->madv = I915_MADV_WILLNEED;
4505 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4508 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4509 .get_pages = i915_gem_object_get_pages_gtt,
4510 .put_pages = i915_gem_object_put_pages_gtt,
4513 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4516 struct drm_i915_gem_object *obj;
4518 struct address_space *mapping;
4522 obj = i915_gem_object_alloc(dev);
4526 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4527 i915_gem_object_free(obj);
4532 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4533 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4534 /* 965gm cannot relocate objects above 4GiB. */
4535 mask &= ~__GFP_HIGHMEM;
4536 mask |= __GFP_DMA32;
4539 mapping = file_inode(obj->base.filp)->i_mapping;
4540 mapping_set_gfp_mask(mapping, mask);
4543 i915_gem_object_init(obj, &i915_gem_object_ops);
4545 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4546 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4549 /* On some devices, we can have the GPU use the LLC (the CPU
4550 * cache) for about a 10% performance improvement
4551 * compared to uncached. Graphics requests other than
4552 * display scanout are coherent with the CPU in
4553 * accessing this cache. This means in this mode we
4554 * don't need to clflush on the CPU side, and on the
4555 * GPU side we only need to flush internal caches to
4556 * get data visible to the CPU.
4558 * However, we maintain the display planes as UC, and so
4559 * need to rebind when first used as such.
4561 obj->cache_level = I915_CACHE_LLC;
4563 obj->cache_level = I915_CACHE_NONE;
4565 trace_i915_gem_object_create(obj);
4570 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4572 /* If we are the last user of the backing storage (be it shmemfs
4573 * pages or stolen etc), we know that the pages are going to be
4574 * immediately released. In this case, we can then skip copying
4575 * back the contents from the GPU.
4578 if (obj->madv != I915_MADV_WILLNEED)
4581 if (obj->base.vm_obj == NULL)
4584 /* At first glance, this looks racy, but then again so would be
4585 * userspace racing mmap against close. However, the first external
4586 * reference to the filp can only be obtained through the
4587 * i915_gem_mmap_ioctl() which safeguards us against the user
4588 * acquiring such a reference whilst we are in the middle of
4589 * freeing the object.
4592 return atomic_long_read(&obj->base.filp->f_count) == 1;
4598 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4600 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4601 struct drm_device *dev = obj->base.dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 struct i915_vma *vma, *next;
4605 intel_runtime_pm_get(dev_priv);
4607 trace_i915_gem_object_destroy(obj);
4609 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4613 ret = i915_vma_unbind(vma);
4614 if (WARN_ON(ret == -ERESTARTSYS)) {
4615 bool was_interruptible;
4617 was_interruptible = dev_priv->mm.interruptible;
4618 dev_priv->mm.interruptible = false;
4620 WARN_ON(i915_vma_unbind(vma));
4622 dev_priv->mm.interruptible = was_interruptible;
4626 i915_gem_object_detach_phys(obj);
4628 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4629 * before progressing. */
4631 i915_gem_object_unpin_pages(obj);
4633 WARN_ON(obj->frontbuffer_bits);
4635 if (WARN_ON(obj->pages_pin_count))
4636 obj->pages_pin_count = 0;
4637 if (discard_backing_storage(obj))
4638 obj->madv = I915_MADV_DONTNEED;
4639 i915_gem_object_put_pages(obj);
4640 i915_gem_object_free_mmap_offset(obj);
4645 if (obj->base.import_attach)
4646 drm_prime_gem_destroy(&obj->base, NULL);
4649 if (obj->ops->release)
4650 obj->ops->release(obj);
4652 drm_gem_object_release(&obj->base);
4653 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4656 i915_gem_object_free(obj);
4658 intel_runtime_pm_put(dev_priv);
4661 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4662 struct i915_address_space *vm)
4664 struct i915_vma *vma;
4665 list_for_each_entry(vma, &obj->vma_list, vma_link)
4672 void i915_gem_vma_destroy(struct i915_vma *vma)
4674 struct i915_address_space *vm = NULL;
4675 WARN_ON(vma->node.allocated);
4677 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4678 if (!list_empty(&vma->exec_list))
4683 if (!i915_is_ggtt(vm))
4684 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4686 list_del(&vma->vma_link);
4692 i915_gem_stop_ringbuffers(struct drm_device *dev)
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 struct intel_engine_cs *ring;
4698 for_each_ring(ring, dev_priv, i)
4699 dev_priv->gt.stop_ring(ring);
4703 i915_gem_suspend(struct drm_device *dev)
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4708 mutex_lock(&dev->struct_mutex);
4709 if (dev_priv->ums.mm_suspended)
4712 ret = i915_gpu_idle(dev);
4716 i915_gem_retire_requests(dev);
4718 /* Under UMS, be paranoid and evict. */
4719 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4720 i915_gem_evict_everything(dev);
4722 i915_kernel_lost_context(dev);
4723 i915_gem_stop_ringbuffers(dev);
4725 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4726 * We need to replace this with a semaphore, or something.
4727 * And not confound ums.mm_suspended!
4729 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4731 mutex_unlock(&dev->struct_mutex);
4733 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4734 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4736 flush_delayed_work(&dev_priv->mm.idle_work);
4742 mutex_unlock(&dev->struct_mutex);
4746 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4748 struct drm_device *dev = ring->dev;
4749 struct drm_i915_private *dev_priv = dev->dev_private;
4750 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4751 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4754 if (!HAS_L3_DPF(dev) || !remap_info)
4757 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4762 * Note: We do not worry about the concurrent register cacheline hang
4763 * here because no other code should access these registers other than
4764 * at initialization time.
4766 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4767 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4768 intel_ring_emit(ring, reg_base + i);
4769 intel_ring_emit(ring, remap_info[i/4]);
4772 intel_ring_advance(ring);
4777 void i915_gem_init_swizzling(struct drm_device *dev)
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4781 if (INTEL_INFO(dev)->gen < 5 ||
4782 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4785 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4786 DISP_TILE_SURFACE_SWIZZLING);
4791 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4793 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4794 else if (IS_GEN7(dev))
4795 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4796 else if (IS_GEN8(dev))
4797 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4803 intel_enable_blt(struct drm_device *dev)
4810 /* The blitter was dysfunctional on early prototypes */
4811 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
4812 if (IS_GEN6(dev) && revision < 8) {
4813 DRM_INFO("BLT not supported on this pre-production hardware;"
4814 " graphics performance will be degraded.\n");
4821 static void init_unused_ring(struct drm_device *dev, u32 base)
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4825 I915_WRITE(RING_CTL(base), 0);
4826 I915_WRITE(RING_HEAD(base), 0);
4827 I915_WRITE(RING_TAIL(base), 0);
4828 I915_WRITE(RING_START(base), 0);
4831 static void init_unused_rings(struct drm_device *dev)
4834 init_unused_ring(dev, PRB1_BASE);
4835 init_unused_ring(dev, SRB0_BASE);
4836 init_unused_ring(dev, SRB1_BASE);
4837 init_unused_ring(dev, SRB2_BASE);
4838 init_unused_ring(dev, SRB3_BASE);
4839 } else if (IS_GEN2(dev)) {
4840 init_unused_ring(dev, SRB0_BASE);
4841 init_unused_ring(dev, SRB1_BASE);
4842 } else if (IS_GEN3(dev)) {
4843 init_unused_ring(dev, PRB1_BASE);
4844 init_unused_ring(dev, PRB2_BASE);
4848 int i915_gem_init_rings(struct drm_device *dev)
4850 struct drm_i915_private *dev_priv = dev->dev_private;
4854 * At least 830 can leave some of the unused rings
4855 * "active" (ie. head != tail) after resume which
4856 * will prevent c3 entry. Makes sure all unused rings
4859 init_unused_rings(dev);
4861 ret = intel_init_render_ring_buffer(dev);
4866 ret = intel_init_bsd_ring_buffer(dev);
4868 goto cleanup_render_ring;
4871 if (intel_enable_blt(dev)) {
4872 ret = intel_init_blt_ring_buffer(dev);
4874 goto cleanup_bsd_ring;
4877 if (HAS_VEBOX(dev)) {
4878 ret = intel_init_vebox_ring_buffer(dev);
4880 goto cleanup_blt_ring;
4883 if (HAS_BSD2(dev)) {
4884 ret = intel_init_bsd2_ring_buffer(dev);
4886 goto cleanup_vebox_ring;
4889 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4891 goto cleanup_bsd2_ring;
4896 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4898 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4900 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4902 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4903 cleanup_render_ring:
4904 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4910 i915_gem_init_hw(struct drm_device *dev)
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4916 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4920 if (dev_priv->ellc_size)
4921 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4923 if (IS_HASWELL(dev))
4924 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4925 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4927 if (HAS_PCH_NOP(dev)) {
4928 if (IS_IVYBRIDGE(dev)) {
4929 u32 temp = I915_READ(GEN7_MSG_CTL);
4930 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4931 I915_WRITE(GEN7_MSG_CTL, temp);
4932 } else if (INTEL_INFO(dev)->gen >= 7) {
4933 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4934 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4935 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4939 i915_gem_init_swizzling(dev);
4941 ret = dev_priv->gt.init_rings(dev);
4945 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4946 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4949 * XXX: Contexts should only be initialized once. Doing a switch to the
4950 * default context switch however is something we'd like to do after
4951 * reset or thaw (the latter may not actually be necessary for HW, but
4952 * goes with our code better). Context switching requires rings (for
4953 * the do_switch), but before enabling PPGTT. So don't move this.
4955 ret = i915_gem_context_enable(dev_priv);
4956 if (ret && ret != -EIO) {
4957 DRM_ERROR("Context enable failed %d\n", ret);
4958 i915_gem_cleanup_ringbuffer(dev);
4963 ret = i915_ppgtt_init_hw(dev);
4964 if (ret && ret != -EIO) {
4965 DRM_ERROR("PPGTT enable failed %d\n", ret);
4966 i915_gem_cleanup_ringbuffer(dev);
4972 int i915_gem_init(struct drm_device *dev)
4974 struct drm_i915_private *dev_priv = dev->dev_private;
4977 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4978 i915.enable_execlists);
4980 mutex_lock(&dev->struct_mutex);
4982 if (IS_VALLEYVIEW(dev)) {
4983 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4984 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4985 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4986 VLV_GTLC_ALLOWWAKEACK), 10))
4987 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4990 if (!i915.enable_execlists) {
4991 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4992 dev_priv->gt.init_rings = i915_gem_init_rings;
4993 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4994 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4996 dev_priv->gt.do_execbuf = intel_execlists_submission;
4997 dev_priv->gt.init_rings = intel_logical_rings_init;
4998 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4999 dev_priv->gt.stop_ring = intel_logical_ring_stop;
5002 ret = i915_gem_init_userptr(dev);
5004 mutex_unlock(&dev->struct_mutex);
5008 i915_gem_init_global_gtt(dev);
5010 ret = i915_gem_context_init(dev);
5012 mutex_unlock(&dev->struct_mutex);
5016 ret = i915_gem_init_hw(dev);
5018 /* Allow ring initialisation to fail by marking the GPU as
5019 * wedged. But we only want to do this where the GPU is angry,
5020 * for all other failure, such as an allocation failure, bail.
5022 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5023 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5026 mutex_unlock(&dev->struct_mutex);
5028 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
5029 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5030 dev_priv->dri1.allow_batchbuffer = 1;
5035 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5037 struct drm_i915_private *dev_priv = dev->dev_private;
5038 struct intel_engine_cs *ring;
5041 for_each_ring(ring, dev_priv, i)
5042 dev_priv->gt.cleanup_ring(ring);
5046 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
5047 struct drm_file *file_priv)
5049 struct drm_i915_private *dev_priv = dev->dev_private;
5052 if (drm_core_check_feature(dev, DRIVER_MODESET))
5055 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
5056 DRM_ERROR("Reenabling wedged hardware, good luck\n");
5057 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
5060 mutex_lock(&dev->struct_mutex);
5061 dev_priv->ums.mm_suspended = 0;
5063 ret = i915_gem_init_hw(dev);
5065 mutex_unlock(&dev->struct_mutex);
5069 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
5071 ret = drm_irq_install(dev, dev->irq);
5073 goto cleanup_ringbuffer;
5074 mutex_unlock(&dev->struct_mutex);
5079 i915_gem_cleanup_ringbuffer(dev);
5080 dev_priv->ums.mm_suspended = 1;
5081 mutex_unlock(&dev->struct_mutex);
5087 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
5088 struct drm_file *file_priv)
5090 if (drm_core_check_feature(dev, DRIVER_MODESET))
5093 mutex_lock(&dev->struct_mutex);
5094 drm_irq_uninstall(dev);
5095 mutex_unlock(&dev->struct_mutex);
5097 return i915_gem_suspend(dev);
5101 i915_gem_lastclose(struct drm_device *dev)
5105 if (drm_core_check_feature(dev, DRIVER_MODESET))
5108 ret = i915_gem_suspend(dev);
5110 DRM_ERROR("failed to idle hardware: %d\n", ret);
5114 init_ring_lists(struct intel_engine_cs *ring)
5116 INIT_LIST_HEAD(&ring->active_list);
5117 INIT_LIST_HEAD(&ring->request_list);
5120 void i915_init_vm(struct drm_i915_private *dev_priv,
5121 struct i915_address_space *vm)
5123 if (!i915_is_ggtt(vm))
5124 drm_mm_init(&vm->mm, vm->start, vm->total);
5125 vm->dev = dev_priv->dev;
5126 INIT_LIST_HEAD(&vm->active_list);
5127 INIT_LIST_HEAD(&vm->inactive_list);
5128 INIT_LIST_HEAD(&vm->global_link);
5129 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5133 i915_gem_load(struct drm_device *dev)
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5138 INIT_LIST_HEAD(&dev_priv->vm_list);
5139 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5141 INIT_LIST_HEAD(&dev_priv->context_list);
5142 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5143 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5144 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5145 for (i = 0; i < I915_NUM_RINGS; i++)
5146 init_ring_lists(&dev_priv->ring[i]);
5147 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5148 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5149 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5150 i915_gem_retire_work_handler);
5151 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5152 i915_gem_idle_work_handler);
5153 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5155 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5156 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5157 I915_WRITE(MI_ARB_STATE,
5158 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5161 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5163 /* Old X drivers will take 0-2 for front, back, depth buffers */
5164 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5165 dev_priv->fence_reg_start = 3;
5167 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5168 dev_priv->num_fence_regs = 32;
5169 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5170 dev_priv->num_fence_regs = 16;
5172 dev_priv->num_fence_regs = 8;
5174 /* Initialize fence registers to zero */
5175 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5176 i915_gem_restore_fences(dev);
5178 i915_gem_detect_bit_6_swizzle(dev);
5179 init_waitqueue_head(&dev_priv->pending_flip_queue);
5181 dev_priv->mm.interruptible = true;
5184 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5185 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5186 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5187 register_shrinker(&dev_priv->mm.shrinker);
5189 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5190 register_oom_notifier(&dev_priv->mm.oom_notifier);
5193 lockinit(&dev_priv->fb_tracking.lock, "drmftl", 0, LK_CANRECURSE);
5196 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5198 struct drm_i915_file_private *file_priv = file->driver_priv;
5200 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5202 /* Clean up our request list when the client is going away, so that
5203 * later retire_requests won't dereference our soon-to-be-gone
5206 spin_lock(&file_priv->mm.lock);
5207 while (!list_empty(&file_priv->mm.request_list)) {
5208 struct drm_i915_gem_request *request;
5210 request = list_first_entry(&file_priv->mm.request_list,
5211 struct drm_i915_gem_request,
5213 list_del(&request->client_list);
5214 request->file_priv = NULL;
5216 spin_unlock(&file_priv->mm.lock);
5220 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
5221 vm_ooffset_t foff, struct ucred *cred, u_short *color)
5223 *color = 0; /* XXXKIB */
5228 i915_gem_pager_dtor(void *handle)
5230 struct drm_gem_object *obj;
5231 struct drm_device *dev;
5236 mutex_lock(&dev->struct_mutex);
5237 drm_gem_free_mmap_offset(obj);
5238 i915_gem_release_mmap(to_intel_bo(obj));
5239 drm_gem_object_unreference(obj);
5240 mutex_unlock(&dev->struct_mutex);
5244 i915_gem_file_idle_work_handler(struct work_struct *work)
5246 struct drm_i915_file_private *file_priv =
5247 container_of(work, typeof(*file_priv), mm.idle_work.work);
5249 atomic_set(&file_priv->rps_wait_boost, false);
5252 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5254 struct drm_i915_file_private *file_priv;
5257 DRM_DEBUG_DRIVER("\n");
5259 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5263 file->driver_priv = file_priv;
5264 file_priv->dev_priv = dev->dev_private;
5265 file_priv->file = file;
5267 spin_init(&file_priv->mm.lock, "i915_priv");
5268 INIT_LIST_HEAD(&file_priv->mm.request_list);
5269 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5270 i915_gem_file_idle_work_handler);
5272 ret = i915_gem_context_open(dev, file);
5279 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5280 struct drm_i915_gem_object *new,
5281 unsigned frontbuffer_bits)
5284 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5285 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5286 old->frontbuffer_bits &= ~frontbuffer_bits;
5290 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5291 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5292 new->frontbuffer_bits |= frontbuffer_bits;
5297 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5299 if (!mutex_is_locked(mutex))
5302 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5303 return mutex->owner == task;
5305 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5312 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5314 if (!mutex_trylock(&dev->struct_mutex)) {
5315 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5318 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5328 static int num_vma_bound(struct drm_i915_gem_object *obj)
5330 struct i915_vma *vma;
5333 list_for_each_entry(vma, &obj->vma_list, vma_link)
5334 if (drm_mm_node_allocated(&vma->node))
5340 static unsigned long
5341 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
5343 struct drm_i915_private *dev_priv =
5344 container_of(shrinker,
5345 struct drm_i915_private,
5346 mm.inactive_shrinker);
5347 struct drm_device *dev = dev_priv->dev;
5348 struct drm_i915_gem_object *obj;
5349 unsigned long count;
5352 if (!i915_gem_shrinker_lock(dev, &unlock))
5356 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5357 if (obj->pages_pin_count == 0)
5358 count += obj->base.size >> PAGE_SHIFT;
5360 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5361 if (!i915_gem_obj_is_pinned(obj) &&
5362 obj->pages_pin_count == num_vma_bound(obj))
5363 count += obj->base.size >> PAGE_SHIFT;
5367 mutex_unlock(&dev->struct_mutex);
5373 /* All the new VM stuff */
5374 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5375 struct i915_address_space *vm)
5377 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5378 struct i915_vma *vma;
5380 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5382 list_for_each_entry(vma, &o->vma_list, vma_link) {
5384 return vma->node.start;
5387 WARN(1, "%s vma for this object not found.\n",
5388 i915_is_ggtt(vm) ? "global" : "ppgtt");
5392 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5393 struct i915_address_space *vm)
5395 struct i915_vma *vma;
5397 list_for_each_entry(vma, &o->vma_list, vma_link)
5398 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5404 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5406 struct i915_vma *vma;
5408 list_for_each_entry(vma, &o->vma_list, vma_link)
5409 if (drm_mm_node_allocated(&vma->node))
5415 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5416 struct i915_address_space *vm)
5418 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5419 struct i915_vma *vma;
5421 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5423 BUG_ON(list_empty(&o->vma_list));
5425 list_for_each_entry(vma, &o->vma_list, vma_link)
5427 return vma->node.size;
5433 static unsigned long
5434 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5436 struct drm_i915_private *dev_priv =
5437 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5438 struct drm_device *dev = dev_priv->dev;
5439 unsigned long freed;
5442 if (!i915_gem_shrinker_lock(dev, &unlock))
5445 freed = i915_gem_shrink(dev_priv,
5448 I915_SHRINK_UNBOUND |
5449 I915_SHRINK_PURGEABLE);
5450 if (freed < sc->nr_to_scan)
5451 freed += i915_gem_shrink(dev_priv,
5452 sc->nr_to_scan - freed,
5454 I915_SHRINK_UNBOUND);
5456 mutex_unlock(&dev->struct_mutex);
5462 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5464 struct i915_vma *vma;
5466 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5467 if (vma->vm != i915_obj_to_ggtt(obj))