sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_ifpoll.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
 139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
 140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
 141 static void     igb_add_sysctl(struct igb_softc *);
 142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 145 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 146 #ifdef IFPOLL_ENABLE
 147 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 148 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 149 #endif
 150
 151 static void     igb_vf_init_stats(struct igb_softc *);
 152 static void     igb_reset(struct igb_softc *);
 153 static void     igb_update_stats_counters(struct igb_softc *);
 154 static void     igb_update_vf_stats_counters(struct igb_softc *);
 155 static void     igb_update_link_status(struct igb_softc *);
 156 static void     igb_init_tx_unit(struct igb_softc *);
 157 static void     igb_init_rx_unit(struct igb_softc *);
 158
 159 static void     igb_set_vlan(struct igb_softc *);
 160 static void     igb_set_multi(struct igb_softc *);
 161 static void     igb_set_promisc(struct igb_softc *);
 162 static void     igb_disable_promisc(struct igb_softc *);
 163
 164 static int      igb_alloc_rings(struct igb_softc *);
 165 static void     igb_free_rings(struct igb_softc *);
 166 static int      igb_create_tx_ring(struct igb_tx_ring *);
 167 static int      igb_create_rx_ring(struct igb_rx_ring *);
 168 static void     igb_free_tx_ring(struct igb_tx_ring *);
 169 static void     igb_free_rx_ring(struct igb_rx_ring *);
 170 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 171 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 172 static void     igb_init_tx_ring(struct igb_tx_ring *);
 173 static int      igb_init_rx_ring(struct igb_rx_ring *);
 174 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 175 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
 176
 177 static void     igb_stop(struct igb_softc *);
 178 static void     igb_init(void *);
 179 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 180 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 181 static int      igb_media_change(struct ifnet *);
 182 static void     igb_timer(void *);
 183 static void     igb_watchdog(struct ifnet *);
 184 static void     igb_start(struct ifnet *);
 185 #ifdef IFPOLL_ENABLE
 186 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
 187 static void     igb_npoll_rx(struct ifnet *, void *, int);
 188 static void     igb_npoll_tx(struct ifnet *, void *, int);
 189 static void     igb_npoll_status(struct ifnet *);
 190 #endif
 191 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 192 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 193 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 194 #ifdef INVARIANTS
 195 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 196                     boolean_t);
 197 #endif
 198
 199 static void     igb_intr(void *);
 200 static void     igb_intr_shared(void *);
 201 static void     igb_rxeof(struct igb_rx_ring *, int);
 202 static void     igb_txeof(struct igb_tx_ring *);
 203 static void     igb_set_eitr(struct igb_softc *, int, int);
 204 static void     igb_enable_intr(struct igb_softc *);
 205 static void     igb_disable_intr(struct igb_softc *);
 206 static void     igb_init_unshared_intr(struct igb_softc *);
 207 static void     igb_init_intr(struct igb_softc *);
 208 static int      igb_setup_intr(struct igb_softc *);
 209 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 210 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 211 static void     igb_set_intr_mask(struct igb_softc *);
 212 static int      igb_alloc_intr(struct igb_softc *);
 213 static void     igb_free_intr(struct igb_softc *);
 214 static void     igb_teardown_intr(struct igb_softc *);
 215 static void     igb_msix_try_alloc(struct igb_softc *);
 216 static void     igb_msix_free(struct igb_softc *, boolean_t);
 217 static int      igb_msix_setup(struct igb_softc *);
 218 static void     igb_msix_teardown(struct igb_softc *, int);
 219 static void     igb_msix_rx(void *);
 220 static void     igb_msix_tx(void *);
 221 static void     igb_msix_status(void *);
 222
 223 /* Management and WOL Support */
 224 static void     igb_get_mgmt(struct igb_softc *);
 225 static void     igb_rel_mgmt(struct igb_softc *);
 226 static void     igb_get_hw_control(struct igb_softc *);
 227 static void     igb_rel_hw_control(struct igb_softc *);
 228 static void     igb_enable_wol(device_t);
 229
 230 static device_method_t igb_methods[] = {
 231         /* Device interface */
 232         DEVMETHOD(device_probe,         igb_probe),
 233         DEVMETHOD(device_attach,        igb_attach),
 234         DEVMETHOD(device_detach,        igb_detach),
 235         DEVMETHOD(device_shutdown,      igb_shutdown),
 236         DEVMETHOD(device_suspend,       igb_suspend),
 237         DEVMETHOD(device_resume,        igb_resume),
 238         { 0, 0 }
 239 };
 240
 241 static driver_t igb_driver = {
 242         "igb",
 243         igb_methods,
 244         sizeof(struct igb_softc),
 245 };
 246
 247 static devclass_t igb_devclass;
 248
 249 DECLARE_DUMMY_MODULE(if_igb);
 250 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 251 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 252
 253 static int      igb_rxd = IGB_DEFAULT_RXD;
 254 static int      igb_txd = IGB_DEFAULT_TXD;
 255 static int      igb_rxr = 0;
 256 static int      igb_msi_enable = 1;
 257 static int      igb_msix_enable = 1;
 258 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 259 static int      igb_fc_setting = e1000_fc_full;
 260
 261 /*
 262  * DMA Coalescing, only for i350 - default to off,
 263  * this feature is for power savings
 264  */
 265 static int      igb_dma_coalesce = 0;
 266
 267 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 268 TUNABLE_INT("hw.igb.txd", &igb_txd);
 269 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 270 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 271 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 272 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 273
 274 /* i350 specific */
 275 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 276 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 277
 278 static __inline void
 279 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 280 {
 281         /* Ignore Checksum bit is set */
 282         if (staterr & E1000_RXD_STAT_IXSM)
 283                 return;
 284
 285         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 286             E1000_RXD_STAT_IPCS)
 287                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 288
 289         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 290                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 291                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 292                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 293                         mp->m_pkthdr.csum_data = htons(0xffff);
 294                 }
 295         }
 296 }
 297
 298 static __inline struct pktinfo *
 299 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 300     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 301 {
 302         switch (hashtype) {
 303         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 304                 pi->pi_netisr = NETISR_IP;
 305                 pi->pi_flags = 0;
 306                 pi->pi_l3proto = IPPROTO_TCP;
 307                 break;
 308
 309         case E1000_RXDADV_RSSTYPE_IPV4:
 310                 if (staterr & E1000_RXD_STAT_IXSM)
 311                         return NULL;
 312
 313                 if ((staterr &
 314                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 315                     E1000_RXD_STAT_TCPCS) {
 316                         pi->pi_netisr = NETISR_IP;
 317                         pi->pi_flags = 0;
 318                         pi->pi_l3proto = IPPROTO_UDP;
 319                         break;
 320                 }
 321                 /* FALL THROUGH */
 322         default:
 323                 return NULL;
 324         }
 325
 326         m->m_flags |= M_HASH;
 327         m->m_pkthdr.hash = toeplitz_hash(hash);
 328         return pi;
 329 }
 330
 331 static int
 332 igb_probe(device_t dev)
 333 {
 334         const struct igb_device *d;
 335         uint16_t vid, did;
 336
 337         vid = pci_get_vendor(dev);
 338         did = pci_get_device(dev);
 339
 340         for (d = igb_devices; d->desc != NULL; ++d) {
 341                 if (vid == d->vid && did == d->did) {
 342                         device_set_desc(dev, d->desc);
 343                         return 0;
 344                 }
 345         }
 346         return ENXIO;
 347 }
 348
 349 static int
 350 igb_attach(device_t dev)
 351 {
 352         struct igb_softc *sc = device_get_softc(dev);
 353         uint16_t eeprom_data;
 354         int error = 0, i, j, ring_max;
 355 #ifdef IFPOLL_ENABLE
 356         int offset, offset_def;
 357 #endif
 358
 359 #ifdef notyet
 360         /* SYSCTL stuff */
 361         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 362             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 363             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 364             igb_sysctl_nvm_info, "I", "NVM Information");
 365         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 366             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 367             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 368             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 369 #endif
 370
 371         callout_init_mp(&sc->timer);
 372         lwkt_serialize_init(&sc->main_serialize);
 373
 374         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
 375             device_get_unit(dev));
 376         sc->dev = sc->osdep.dev = dev;
 377
 378         /*
 379          * Determine hardware and mac type
 380          */
 381         sc->hw.vendor_id = pci_get_vendor(dev);
 382         sc->hw.device_id = pci_get_device(dev);
 383         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 384         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 385         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 386
 387         if (e1000_set_mac_type(&sc->hw))
 388                 return ENXIO;
 389
 390         /* Are we a VF device? */
 391         if (sc->hw.mac.type == e1000_vfadapt ||
 392             sc->hw.mac.type == e1000_vfadapt_i350)
 393                 sc->vf_ifp = 1;
 394         else
 395                 sc->vf_ifp = 0;
 396
 397         /*
 398          * Configure total supported RX/TX ring count
 399          */
 400         switch (sc->hw.mac.type) {
 401         case e1000_82575:
 402                 ring_max = IGB_MAX_RING_82575;
 403                 break;
 404         case e1000_82580:
 405                 ring_max = IGB_MAX_RING_82580;
 406                 break;
 407         case e1000_i350:
 408                 ring_max = IGB_MAX_RING_I350;
 409                 break;
 410         case e1000_82576:
 411                 ring_max = IGB_MAX_RING_82576;
 412                 break;
 413         default:
 414                 ring_max = IGB_MIN_RING;
 415                 break;
 416         }
 417         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 418         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 419 #ifdef IGB_RSS_DEBUG
 420         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 421 #endif
 422         sc->rx_ring_inuse = sc->rx_ring_cnt;
 423         sc->tx_ring_cnt = 1; /* XXX */
 424
 425         if (sc->hw.mac.type == e1000_82575)
 426                 sc->flags |= IGB_FLAG_TSO_IPLEN0;
 427
 428         /* Enable bus mastering */
 429         pci_enable_busmaster(dev);
 430
 431         /*
 432          * Allocate IO memory
 433          */
 434         sc->mem_rid = PCIR_BAR(0);
 435         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 436             RF_ACTIVE);
 437         if (sc->mem_res == NULL) {
 438                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 439                 error = ENXIO;
 440                 goto failed;
 441         }
 442         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 443         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 444
 445         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 446
 447         /* Save PCI command register for Shared Code */
 448         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 449         sc->hw.back = &sc->osdep;
 450
 451         /* Do Shared Code initialization */
 452         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 453                 device_printf(dev, "Setup of Shared code failed\n");
 454                 error = ENXIO;
 455                 goto failed;
 456         }
 457
 458         e1000_get_bus_info(&sc->hw);
 459
 460         sc->hw.mac.autoneg = DO_AUTO_NEG;
 461         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 462         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 463
 464         /* Copper options */
 465         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 466                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 467                 sc->hw.phy.disable_polarity_correction = FALSE;
 468                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 469         }
 470
 471         /* Set the frame limits assuming  standard ethernet sized frames. */
 472         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 473
 474         /* Allocate RX/TX rings */
 475         error = igb_alloc_rings(sc);
 476         if (error)
 477                 goto failed;
 478
 479 #ifdef IFPOLL_ENABLE
 480         /*
 481          * NPOLLING RX CPU offset
 482          */
 483         if (sc->rx_ring_cnt == ncpus2) {
 484                 offset = 0;
 485         } else {
 486                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 487                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 488                 if (offset >= ncpus2 ||
 489                     offset % sc->rx_ring_cnt != 0) {
 490                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 491                             offset, offset_def);
 492                         offset = offset_def;
 493                 }
 494         }
 495         sc->rx_npoll_off = offset;
 496
 497         /*
 498          * NPOLLING TX CPU offset
 499          */
 500         offset_def = sc->rx_npoll_off;
 501         offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 502         if (offset >= ncpus2) {
 503                 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 504                     offset, offset_def);
 505                 offset = offset_def;
 506         }
 507         sc->tx_npoll_off = offset;
 508 #endif
 509
 510         /* Allocate interrupt */
 511         error = igb_alloc_intr(sc);
 512         if (error)
 513                 goto failed;
 514
 515         /*
 516          * Setup serializers
 517          */
 518         i = 0;
 519         sc->serializes[i++] = &sc->main_serialize;
 520
 521         sc->tx_serialize = i;
 522         for (j = 0; j < sc->tx_ring_cnt; ++j)
 523                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 524
 525         sc->rx_serialize = i;
 526         for (j = 0; j < sc->rx_ring_cnt; ++j)
 527                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 528
 529         sc->serialize_cnt = i;
 530         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 531
 532         /* Allocate the appropriate stats memory */
 533         if (sc->vf_ifp) {
 534                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 535                     M_WAITOK | M_ZERO);
 536                 igb_vf_init_stats(sc);
 537         } else {
 538                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 539                     M_WAITOK | M_ZERO);
 540         }
 541
 542         /* Allocate multicast array memory. */
 543         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 544             M_DEVBUF, M_WAITOK);
 545
 546         /* Some adapter-specific advanced features */
 547         if (sc->hw.mac.type >= e1000_i350) {
 548 #ifdef notyet
 549                 igb_set_sysctl_value(adapter, "dma_coalesce",
 550                     "configure dma coalesce",
 551                     &adapter->dma_coalesce, igb_dma_coalesce);
 552                 igb_set_sysctl_value(adapter, "eee_disabled",
 553                     "enable Energy Efficient Ethernet",
 554                     &adapter->hw.dev_spec._82575.eee_disable,
 555                     igb_eee_disabled);
 556 #else
 557                 sc->dma_coalesce = igb_dma_coalesce;
 558                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 559 #endif
 560                 e1000_set_eee_i350(&sc->hw);
 561         }
 562
 563         /*
 564          * Start from a known state, this is important in reading the nvm and
 565          * mac from that.
 566          */
 567         e1000_reset_hw(&sc->hw);
 568
 569         /* Make sure we have a good EEPROM before we read from it */
 570         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 571                 /*
 572                  * Some PCI-E parts fail the first check due to
 573                  * the link being in sleep state, call it again,
 574                  * if it fails a second time its a real issue.
 575                  */
 576                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 577                         device_printf(dev,
 578                             "The EEPROM Checksum Is Not Valid\n");
 579                         error = EIO;
 580                         goto failed;
 581                 }
 582         }
 583
 584         /* Copy the permanent MAC address out of the EEPROM */
 585         if (e1000_read_mac_addr(&sc->hw) < 0) {
 586                 device_printf(dev, "EEPROM read error while reading MAC"
 587                     " address\n");
 588                 error = EIO;
 589                 goto failed;
 590         }
 591         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 592                 device_printf(dev, "Invalid MAC address\n");
 593                 error = EIO;
 594                 goto failed;
 595         }
 596
 597         /* Setup OS specific network interface */
 598         igb_setup_ifp(sc);
 599
 600         /* Add sysctl tree, must after igb_setup_ifp() */
 601         igb_add_sysctl(sc);
 602
 603         /* Now get a good starting state */
 604         igb_reset(sc);
 605
 606         /* Initialize statistics */
 607         igb_update_stats_counters(sc);
 608
 609         sc->hw.mac.get_link_status = 1;
 610         igb_update_link_status(sc);
 611
 612         /* Indicate SOL/IDER usage */
 613         if (e1000_check_reset_block(&sc->hw)) {
 614                 device_printf(dev,
 615                     "PHY reset is blocked due to SOL/IDER session.\n");
 616         }
 617
 618         /* Determine if we have to control management hardware */
 619         if (e1000_enable_mng_pass_thru(&sc->hw))
 620                 sc->flags |= IGB_FLAG_HAS_MGMT;
 621
 622         /*
 623          * Setup Wake-on-Lan
 624          */
 625         /* APME bit in EEPROM is mapped to WUC.APME */
 626         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 627         if (eeprom_data)
 628                 sc->wol = E1000_WUFC_MAG;
 629         /* XXX disable WOL */
 630         sc->wol = 0;
 631
 632 #ifdef notyet
 633         /* Register for VLAN events */
 634         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 635              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 636         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 637              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 638 #endif
 639
 640 #ifdef notyet
 641         igb_add_hw_stats(adapter);
 642 #endif
 643
 644         error = igb_setup_intr(sc);
 645         if (error) {
 646                 ether_ifdetach(&sc->arpcom.ac_if);
 647                 goto failed;
 648         }
 649         return 0;
 650
 651 failed:
 652         igb_detach(dev);
 653         return error;
 654 }
 655
 656 static int
 657 igb_detach(device_t dev)
 658 {
 659         struct igb_softc *sc = device_get_softc(dev);
 660
 661         if (device_is_attached(dev)) {
 662                 struct ifnet *ifp = &sc->arpcom.ac_if;
 663
 664                 ifnet_serialize_all(ifp);
 665
 666                 igb_stop(sc);
 667
 668                 e1000_phy_hw_reset(&sc->hw);
 669
 670                 /* Give control back to firmware */
 671                 igb_rel_mgmt(sc);
 672                 igb_rel_hw_control(sc);
 673
 674                 if (sc->wol) {
 675                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 676                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 677                         igb_enable_wol(dev);
 678                 }
 679
 680                 igb_teardown_intr(sc);
 681
 682                 ifnet_deserialize_all(ifp);
 683
 684                 ether_ifdetach(ifp);
 685         } else if (sc->mem_res != NULL) {
 686                 igb_rel_hw_control(sc);
 687         }
 688         bus_generic_detach(dev);
 689
 690         if (sc->sysctl_tree != NULL)
 691                 sysctl_ctx_free(&sc->sysctl_ctx);
 692
 693         igb_free_intr(sc);
 694
 695         if (sc->msix_mem_res != NULL) {
 696                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 697                     sc->msix_mem_res);
 698         }
 699         if (sc->mem_res != NULL) {
 700                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 701                     sc->mem_res);
 702         }
 703
 704         igb_free_rings(sc);
 705
 706         if (sc->mta != NULL)
 707                 kfree(sc->mta, M_DEVBUF);
 708         if (sc->stats != NULL)
 709                 kfree(sc->stats, M_DEVBUF);
 710
 711         return 0;
 712 }
 713
 714 static int
 715 igb_shutdown(device_t dev)
 716 {
 717         return igb_suspend(dev);
 718 }
 719
 720 static int
 721 igb_suspend(device_t dev)
 722 {
 723         struct igb_softc *sc = device_get_softc(dev);
 724         struct ifnet *ifp = &sc->arpcom.ac_if;
 725
 726         ifnet_serialize_all(ifp);
 727
 728         igb_stop(sc);
 729
 730         igb_rel_mgmt(sc);
 731         igb_rel_hw_control(sc);
 732
 733         if (sc->wol) {
 734                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 735                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 736                 igb_enable_wol(dev);
 737         }
 738
 739         ifnet_deserialize_all(ifp);
 740
 741         return bus_generic_suspend(dev);
 742 }
 743
 744 static int
 745 igb_resume(device_t dev)
 746 {
 747         struct igb_softc *sc = device_get_softc(dev);
 748         struct ifnet *ifp = &sc->arpcom.ac_if;
 749
 750         ifnet_serialize_all(ifp);
 751
 752         igb_init(sc);
 753         igb_get_mgmt(sc);
 754
 755         if_devstart(ifp);
 756
 757         ifnet_deserialize_all(ifp);
 758
 759         return bus_generic_resume(dev);
 760 }
 761
 762 static int
 763 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 764 {
 765         struct igb_softc *sc = ifp->if_softc;
 766         struct ifreq *ifr = (struct ifreq *)data;
 767         int max_frame_size, mask, reinit;
 768         int error = 0;
 769
 770         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 771
 772         switch (command) {
 773         case SIOCSIFMTU:
 774                 max_frame_size = 9234;
 775                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 776                     ETHER_CRC_LEN) {
 777                         error = EINVAL;
 778                         break;
 779                 }
 780
 781                 ifp->if_mtu = ifr->ifr_mtu;
 782                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 783                     ETHER_CRC_LEN;
 784
 785                 if (ifp->if_flags & IFF_RUNNING)
 786                         igb_init(sc);
 787                 break;
 788
 789         case SIOCSIFFLAGS:
 790                 if (ifp->if_flags & IFF_UP) {
 791                         if (ifp->if_flags & IFF_RUNNING) {
 792                                 if ((ifp->if_flags ^ sc->if_flags) &
 793                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 794                                         igb_disable_promisc(sc);
 795                                         igb_set_promisc(sc);
 796                                 }
 797                         } else {
 798                                 igb_init(sc);
 799                         }
 800                 } else if (ifp->if_flags & IFF_RUNNING) {
 801                         igb_stop(sc);
 802                 }
 803                 sc->if_flags = ifp->if_flags;
 804                 break;
 805
 806         case SIOCADDMULTI:
 807         case SIOCDELMULTI:
 808                 if (ifp->if_flags & IFF_RUNNING) {
 809                         igb_disable_intr(sc);
 810                         igb_set_multi(sc);
 811 #ifdef IFPOLL_ENABLE
 812                         if (!(ifp->if_flags & IFF_NPOLLING))
 813 #endif
 814                                 igb_enable_intr(sc);
 815                 }
 816                 break;
 817
 818         case SIOCSIFMEDIA:
 819                 /*
 820                  * As the speed/duplex settings are being
 821                  * changed, we need toreset the PHY.
 822                  */
 823                 sc->hw.phy.reset_disable = FALSE;
 824
 825                 /* Check SOL/IDER usage */
 826                 if (e1000_check_reset_block(&sc->hw)) {
 827                         if_printf(ifp, "Media change is "
 828                             "blocked due to SOL/IDER session.\n");
 829                         break;
 830                 }
 831                 /* FALL THROUGH */
 832
 833         case SIOCGIFMEDIA:
 834                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 835                 break;
 836
 837         case SIOCSIFCAP:
 838                 reinit = 0;
 839                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 840                 if (mask & IFCAP_RXCSUM) {
 841                         ifp->if_capenable ^= IFCAP_RXCSUM;
 842                         reinit = 1;
 843                 }
 844                 if (mask & IFCAP_VLAN_HWTAGGING) {
 845                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 846                         reinit = 1;
 847                 }
 848                 if (mask & IFCAP_TXCSUM) {
 849                         ifp->if_capenable ^= IFCAP_TXCSUM;
 850                         if (ifp->if_capenable & IFCAP_TXCSUM)
 851                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
 852                         else
 853                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
 854                 }
 855                 if (mask & IFCAP_TSO) {
 856                         ifp->if_capenable ^= IFCAP_TSO;
 857                         if (ifp->if_capenable & IFCAP_TSO)
 858                                 ifp->if_hwassist |= CSUM_TSO;
 859                         else
 860                                 ifp->if_hwassist &= ~CSUM_TSO;
 861                 }
 862                 if (mask & IFCAP_RSS)
 863                         ifp->if_capenable ^= IFCAP_RSS;
 864                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 865                         igb_init(sc);
 866                 break;
 867
 868         default:
 869                 error = ether_ioctl(ifp, command, data);
 870                 break;
 871         }
 872         return error;
 873 }
 874
 875 static void
 876 igb_init(void *xsc)
 877 {
 878         struct igb_softc *sc = xsc;
 879         struct ifnet *ifp = &sc->arpcom.ac_if;
 880         boolean_t polling;
 881         int i;
 882
 883         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 884
 885         igb_stop(sc);
 886
 887         /* Get the latest mac address, User can use a LAA */
 888         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 889
 890         /* Put the address into the Receive Address Array */
 891         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 892
 893         igb_reset(sc);
 894         igb_update_link_status(sc);
 895
 896         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 897
 898         /* Configure for OS presence */
 899         igb_get_mgmt(sc);
 900
 901         polling = FALSE;
 902 #ifdef IFPOLL_ENABLE
 903         if (ifp->if_flags & IFF_NPOLLING)
 904                 polling = TRUE;
 905 #endif
 906
 907         /* Configured used RX/TX rings */
 908         igb_set_ring_inuse(sc, polling);
 909
 910         /* Initialize interrupt */
 911         igb_init_intr(sc);
 912
 913         /* Prepare transmit descriptors and buffers */
 914         for (i = 0; i < sc->tx_ring_cnt; ++i)
 915                 igb_init_tx_ring(&sc->tx_rings[i]);
 916         igb_init_tx_unit(sc);
 917
 918         /* Setup Multicast table */
 919         igb_set_multi(sc);
 920
 921 #if 0
 922         /*
 923          * Figure out the desired mbuf pool
 924          * for doing jumbo/packetsplit
 925          */
 926         if (adapter->max_frame_size <= 2048)
 927                 adapter->rx_mbuf_sz = MCLBYTES;
 928         else if (adapter->max_frame_size <= 4096)
 929                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 930         else
 931                 adapter->rx_mbuf_sz = MJUM9BYTES;
 932 #endif
 933
 934         /* Prepare receive descriptors and buffers */
 935         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 936                 int error;
 937
 938                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 939                 if (error) {
 940                         if_printf(ifp, "Could not setup receive structures\n");
 941                         igb_stop(sc);
 942                         return;
 943                 }
 944         }
 945         igb_init_rx_unit(sc);
 946
 947         /* Enable VLAN support */
 948         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 949                 igb_set_vlan(sc);
 950
 951         /* Don't lose promiscuous settings */
 952         igb_set_promisc(sc);
 953
 954         ifp->if_flags |= IFF_RUNNING;
 955         ifp->if_flags &= ~IFF_OACTIVE;
 956
 957         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
 958                 sc->timer_cpuid = 0; /* XXX fixed */
 959         else
 960                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
 961         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
 962         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 963
 964         /* This clears any pending interrupts */
 965         E1000_READ_REG(&sc->hw, E1000_ICR);
 966
 967         /*
 968          * Only enable interrupts if we are not polling, make sure
 969          * they are off otherwise.
 970          */
 971         if (polling) {
 972                 igb_disable_intr(sc);
 973         } else {
 974                 igb_enable_intr(sc);
 975                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 976         }
 977
 978         /* Set Energy Efficient Ethernet */
 979         e1000_set_eee_i350(&sc->hw);
 980
 981         /* Don't reset the phy next time init gets called */
 982         sc->hw.phy.reset_disable = TRUE;
 983 }
 984
 985 static void
 986 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 987 {
 988         struct igb_softc *sc = ifp->if_softc;
 989         u_char fiber_type = IFM_1000_SX;
 990
 991         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 992
 993         igb_update_link_status(sc);
 994
 995         ifmr->ifm_status = IFM_AVALID;
 996         ifmr->ifm_active = IFM_ETHER;
 997
 998         if (!sc->link_active)
 999                 return;
1000
1001         ifmr->ifm_status |= IFM_ACTIVE;
1002
1003         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1004             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1005                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1006         } else {
1007                 switch (sc->link_speed) {
1008                 case 10:
1009                         ifmr->ifm_active |= IFM_10_T;
1010                         break;
1011
1012                 case 100:
1013                         ifmr->ifm_active |= IFM_100_TX;
1014                         break;
1015
1016                 case 1000:
1017                         ifmr->ifm_active |= IFM_1000_T;
1018                         break;
1019                 }
1020                 if (sc->link_duplex == FULL_DUPLEX)
1021                         ifmr->ifm_active |= IFM_FDX;
1022                 else
1023                         ifmr->ifm_active |= IFM_HDX;
1024         }
1025 }
1026
1027 static int
1028 igb_media_change(struct ifnet *ifp)
1029 {
1030         struct igb_softc *sc = ifp->if_softc;
1031         struct ifmedia *ifm = &sc->media;
1032
1033         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1034
1035         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1036                 return EINVAL;
1037
1038         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1039         case IFM_AUTO:
1040                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1041                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1042                 break;
1043
1044         case IFM_1000_LX:
1045         case IFM_1000_SX:
1046         case IFM_1000_T:
1047                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1048                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1049                 break;
1050
1051         case IFM_100_TX:
1052                 sc->hw.mac.autoneg = FALSE;
1053                 sc->hw.phy.autoneg_advertised = 0;
1054                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1055                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1056                 else
1057                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1058                 break;
1059
1060         case IFM_10_T:
1061                 sc->hw.mac.autoneg = FALSE;
1062                 sc->hw.phy.autoneg_advertised = 0;
1063                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1064                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1065                 else
1066                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1067                 break;
1068
1069         default:
1070                 if_printf(ifp, "Unsupported media type\n");
1071                 break;
1072         }
1073
1074         igb_init(sc);
1075
1076         return 0;
1077 }
1078
1079 static void
1080 igb_set_promisc(struct igb_softc *sc)
1081 {
1082         struct ifnet *ifp = &sc->arpcom.ac_if;
1083         struct e1000_hw *hw = &sc->hw;
1084         uint32_t reg;
1085
1086         if (sc->vf_ifp) {
1087                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1088                 return;
1089         }
1090
1091         reg = E1000_READ_REG(hw, E1000_RCTL);
1092         if (ifp->if_flags & IFF_PROMISC) {
1093                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1094                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1095         } else if (ifp->if_flags & IFF_ALLMULTI) {
1096                 reg |= E1000_RCTL_MPE;
1097                 reg &= ~E1000_RCTL_UPE;
1098                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1099         }
1100 }
1101
1102 static void
1103 igb_disable_promisc(struct igb_softc *sc)
1104 {
1105         struct e1000_hw *hw = &sc->hw;
1106         uint32_t reg;
1107
1108         if (sc->vf_ifp) {
1109                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1110                 return;
1111         }
1112         reg = E1000_READ_REG(hw, E1000_RCTL);
1113         reg &= ~E1000_RCTL_UPE;
1114         reg &= ~E1000_RCTL_MPE;
1115         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1116 }
1117
1118 static void
1119 igb_set_multi(struct igb_softc *sc)
1120 {
1121         struct ifnet *ifp = &sc->arpcom.ac_if;
1122         struct ifmultiaddr *ifma;
1123         uint32_t reg_rctl = 0;
1124         uint8_t *mta;
1125         int mcnt = 0;
1126
1127         mta = sc->mta;
1128         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1129
1130         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1131                 if (ifma->ifma_addr->sa_family != AF_LINK)
1132                         continue;
1133
1134                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1135                         break;
1136
1137                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1138                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1139                 mcnt++;
1140         }
1141
1142         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1143                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1144                 reg_rctl |= E1000_RCTL_MPE;
1145                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1146         } else {
1147                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1148         }
1149 }
1150
1151 static void
1152 igb_timer(void *xsc)
1153 {
1154         struct igb_softc *sc = xsc;
1155
1156         lwkt_serialize_enter(&sc->main_serialize);
1157
1158         igb_update_link_status(sc);
1159         igb_update_stats_counters(sc);
1160
1161         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1162
1163         lwkt_serialize_exit(&sc->main_serialize);
1164 }
1165
1166 static void
1167 igb_update_link_status(struct igb_softc *sc)
1168 {
1169         struct ifnet *ifp = &sc->arpcom.ac_if;
1170         struct e1000_hw *hw = &sc->hw;
1171         uint32_t link_check, thstat, ctrl;
1172
1173         link_check = thstat = ctrl = 0;
1174
1175         /* Get the cached link value or read for real */
1176         switch (hw->phy.media_type) {
1177         case e1000_media_type_copper:
1178                 if (hw->mac.get_link_status) {
1179                         /* Do the work to read phy */
1180                         e1000_check_for_link(hw);
1181                         link_check = !hw->mac.get_link_status;
1182                 } else {
1183                         link_check = TRUE;
1184                 }
1185                 break;
1186
1187         case e1000_media_type_fiber:
1188                 e1000_check_for_link(hw);
1189                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1190                 break;
1191
1192         case e1000_media_type_internal_serdes:
1193                 e1000_check_for_link(hw);
1194                 link_check = hw->mac.serdes_has_link;
1195                 break;
1196
1197         /* VF device is type_unknown */
1198         case e1000_media_type_unknown:
1199                 e1000_check_for_link(hw);
1200                 link_check = !hw->mac.get_link_status;
1201                 /* Fall thru */
1202         default:
1203                 break;
1204         }
1205
1206         /* Check for thermal downshift or shutdown */
1207         if (hw->mac.type == e1000_i350) {
1208                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1209                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1210         }
1211
1212         /* Now we check if a transition has happened */
1213         if (link_check && sc->link_active == 0) {
1214                 e1000_get_speed_and_duplex(hw,
1215                     &sc->link_speed, &sc->link_duplex);
1216                 if (bootverbose) {
1217                         if_printf(ifp, "Link is up %d Mbps %s\n",
1218                             sc->link_speed,
1219                             sc->link_duplex == FULL_DUPLEX ?
1220                             "Full Duplex" : "Half Duplex");
1221                 }
1222                 sc->link_active = 1;
1223
1224                 ifp->if_baudrate = sc->link_speed * 1000000;
1225                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1226                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1227                         if_printf(ifp, "Link: thermal downshift\n");
1228                 /* This can sleep */
1229                 ifp->if_link_state = LINK_STATE_UP;
1230                 if_link_state_change(ifp);
1231         } else if (!link_check && sc->link_active == 1) {
1232                 ifp->if_baudrate = sc->link_speed = 0;
1233                 sc->link_duplex = 0;
1234                 if (bootverbose)
1235                         if_printf(ifp, "Link is Down\n");
1236                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1237                     (thstat & E1000_THSTAT_PWR_DOWN))
1238                         if_printf(ifp, "Link: thermal shutdown\n");
1239                 sc->link_active = 0;
1240                 /* This can sleep */
1241                 ifp->if_link_state = LINK_STATE_DOWN;
1242                 if_link_state_change(ifp);
1243         }
1244 }
1245
1246 static void
1247 igb_stop(struct igb_softc *sc)
1248 {
1249         struct ifnet *ifp = &sc->arpcom.ac_if;
1250         int i;
1251
1252         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1253
1254         igb_disable_intr(sc);
1255
1256         callout_stop(&sc->timer);
1257
1258         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1259         ifp->if_timer = 0;
1260
1261         e1000_reset_hw(&sc->hw);
1262         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1263
1264         e1000_led_off(&sc->hw);
1265         e1000_cleanup_led(&sc->hw);
1266
1267         for (i = 0; i < sc->tx_ring_cnt; ++i)
1268                 igb_free_tx_ring(&sc->tx_rings[i]);
1269         for (i = 0; i < sc->rx_ring_cnt; ++i)
1270                 igb_free_rx_ring(&sc->rx_rings[i]);
1271 }
1272
1273 static void
1274 igb_reset(struct igb_softc *sc)
1275 {
1276         struct ifnet *ifp = &sc->arpcom.ac_if;
1277         struct e1000_hw *hw = &sc->hw;
1278         struct e1000_fc_info *fc = &hw->fc;
1279         uint32_t pba = 0;
1280         uint16_t hwm;
1281
1282         /* Let the firmware know the OS is in control */
1283         igb_get_hw_control(sc);
1284
1285         /*
1286          * Packet Buffer Allocation (PBA)
1287          * Writing PBA sets the receive portion of the buffer
1288          * the remainder is used for the transmit buffer.
1289          */
1290         switch (hw->mac.type) {
1291         case e1000_82575:
1292                 pba = E1000_PBA_32K;
1293                 break;
1294
1295         case e1000_82576:
1296         case e1000_vfadapt:
1297                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1298                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1299                 break;
1300
1301         case e1000_82580:
1302         case e1000_i350:
1303         case e1000_vfadapt_i350:
1304                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1305                 pba = e1000_rxpbs_adjust_82580(pba);
1306                 break;
1307                 /* XXX pba = E1000_PBA_35K; */
1308
1309         default:
1310                 break;
1311         }
1312
1313         /* Special needs in case of Jumbo frames */
1314         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1315                 uint32_t tx_space, min_tx, min_rx;
1316
1317                 pba = E1000_READ_REG(hw, E1000_PBA);
1318                 tx_space = pba >> 16;
1319                 pba &= 0xffff;
1320
1321                 min_tx = (sc->max_frame_size +
1322                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1323                 min_tx = roundup2(min_tx, 1024);
1324                 min_tx >>= 10;
1325                 min_rx = sc->max_frame_size;
1326                 min_rx = roundup2(min_rx, 1024);
1327                 min_rx >>= 10;
1328                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1329                         pba = pba - (min_tx - tx_space);
1330                         /*
1331                          * if short on rx space, rx wins
1332                          * and must trump tx adjustment
1333                          */
1334                         if (pba < min_rx)
1335                                 pba = min_rx;
1336                 }
1337                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1338         }
1339
1340         /*
1341          * These parameters control the automatic generation (Tx) and
1342          * response (Rx) to Ethernet PAUSE frames.
1343          * - High water mark should allow for at least two frames to be
1344          *   received after sending an XOFF.
1345          * - Low water mark works best when it is very near the high water mark.
1346          *   This allows the receiver to restart by sending XON when it has
1347          *   drained a bit.
1348          */
1349         hwm = min(((pba << 10) * 9 / 10),
1350             ((pba << 10) - 2 * sc->max_frame_size));
1351
1352         if (hw->mac.type < e1000_82576) {
1353                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1354                 fc->low_water = fc->high_water - 8;
1355         } else {
1356                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1357                 fc->low_water = fc->high_water - 16;
1358         }
1359         fc->pause_time = IGB_FC_PAUSE_TIME;
1360         fc->send_xon = TRUE;
1361
1362         /* Issue a global reset */
1363         e1000_reset_hw(hw);
1364         E1000_WRITE_REG(hw, E1000_WUC, 0);
1365
1366         if (e1000_init_hw(hw) < 0)
1367                 if_printf(ifp, "Hardware Initialization Failed\n");
1368
1369         /* Setup DMA Coalescing */
1370         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1371                 uint32_t reg;
1372
1373                 hwm = (pba - 4) << 10;
1374                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1375                     & E1000_DMACR_DMACTHR_MASK;
1376
1377                 /* transition to L0x or L1 if available..*/
1378                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1379
1380                 /* timer = +-1000 usec in 32usec intervals */
1381                 reg |= (1000 >> 5);
1382                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1383
1384                 /* No lower threshold */
1385                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1386
1387                 /* set hwm to PBA -  2 * max frame size */
1388                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1389
1390                 /* Set the interval before transition */
1391                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1392                 reg |= 0x800000FF; /* 255 usec */
1393                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1394
1395                 /* free space in tx packet buffer to wake from DMA coal */
1396                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1397                     (20480 - (2 * sc->max_frame_size)) >> 6);
1398
1399                 /* make low power state decision controlled by DMA coal */
1400                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1401                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1402                     reg | E1000_PCIEMISC_LX_DECISION);
1403                 if_printf(ifp, "DMA Coalescing enabled\n");
1404         }
1405
1406         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1407         e1000_get_phy_info(hw);
1408         e1000_check_for_link(hw);
1409 }
1410
1411 static void
1412 igb_setup_ifp(struct igb_softc *sc)
1413 {
1414         struct ifnet *ifp = &sc->arpcom.ac_if;
1415
1416         ifp->if_softc = sc;
1417         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1418         ifp->if_init = igb_init;
1419         ifp->if_ioctl = igb_ioctl;
1420         ifp->if_start = igb_start;
1421         ifp->if_serialize = igb_serialize;
1422         ifp->if_deserialize = igb_deserialize;
1423         ifp->if_tryserialize = igb_tryserialize;
1424 #ifdef INVARIANTS
1425         ifp->if_serialize_assert = igb_serialize_assert;
1426 #endif
1427 #ifdef IFPOLL_ENABLE
1428         ifp->if_npoll = igb_npoll;
1429 #endif
1430         ifp->if_watchdog = igb_watchdog;
1431
1432         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1433         ifq_set_ready(&ifp->if_snd);
1434
1435         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1436
1437         ifp->if_capabilities =
1438             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1439         if (IGB_ENABLE_HWRSS(sc))
1440                 ifp->if_capabilities |= IFCAP_RSS;
1441         ifp->if_capenable = ifp->if_capabilities;
1442         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1443
1444         /*
1445          * Tell the upper layer(s) we support long frames
1446          */
1447         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1448
1449         /*
1450          * Specify the media types supported by this adapter and register
1451          * callbacks to update media and link information
1452          */
1453         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1454         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1455             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1456                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1457                     0, NULL);
1458                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1459         } else {
1460                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1461                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1462                     0, NULL);
1463                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1464                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1465                     0, NULL);
1466                 if (sc->hw.phy.type != e1000_phy_ife) {
1467                         ifmedia_add(&sc->media,
1468                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1469                         ifmedia_add(&sc->media,
1470                             IFM_ETHER | IFM_1000_T, 0, NULL);
1471                 }
1472         }
1473         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1474         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1475 }
1476
1477 static void
1478 igb_add_sysctl(struct igb_softc *sc)
1479 {
1480         char node[32];
1481         int i;
1482
1483         sysctl_ctx_init(&sc->sysctl_ctx);
1484         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1485             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1486             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1487         if (sc->sysctl_tree == NULL) {
1488                 device_printf(sc->dev, "can't add sysctl node\n");
1489                 return;
1490         }
1491
1492         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1493             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1494         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1495             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1496             "# of RX rings used");
1497         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1498             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1499             "# of RX descs");
1500         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1501             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1502             "# of TX descs");
1503
1504         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1505                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1506                     SYSCTL_CHILDREN(sc->sysctl_tree),
1507                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1508                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1509         } else {
1510                 for (i = 0; i < sc->msix_cnt; ++i) {
1511                         struct igb_msix_data *msix = &sc->msix_data[i];
1512
1513                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1514                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1515                             SYSCTL_CHILDREN(sc->sysctl_tree),
1516                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1517                             msix, 0, igb_sysctl_msix_rate, "I",
1518                             msix->msix_rate_desc);
1519                 }
1520         }
1521
1522         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1523             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1524             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1525             "# of segments per TX interrupt");
1526
1527         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1528             OID_AUTO, "tx_wreg_nsegs", CTLFLAG_RW,
1529             &sc->tx_rings[0].wreg_nsegs, 0,
1530             "# of segments before write to hardare register");
1531
1532 #ifdef IFPOLL_ENABLE
1533         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1534             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1535             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1536         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1537             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1538             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1539 #endif
1540
1541 #ifdef IGB_RSS_DEBUG
1542         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1543             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1544             "RSS debug level");
1545         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1546                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1547                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1548                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1549                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1550         }
1551 #endif
1552 }
1553
1554 static int
1555 igb_alloc_rings(struct igb_softc *sc)
1556 {
1557         int error, i;
1558
1559         /*
1560          * Create top level busdma tag
1561          */
1562         error = bus_dma_tag_create(NULL, 1, 0,
1563             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1564             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1565             &sc->parent_tag);
1566         if (error) {
1567                 device_printf(sc->dev, "could not create top level DMA tag\n");
1568                 return error;
1569         }
1570
1571         /*
1572          * Allocate TX descriptor rings and buffers
1573          */
1574         sc->tx_rings = kmalloc_cachealign(
1575             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1576             M_DEVBUF, M_WAITOK | M_ZERO);
1577         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1578                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1579
1580                 /* Set up some basics */
1581                 txr->sc = sc;
1582                 txr->me = i;
1583                 lwkt_serialize_init(&txr->tx_serialize);
1584
1585                 error = igb_create_tx_ring(txr);
1586                 if (error)
1587                         return error;
1588         }
1589
1590         /*
1591          * Allocate RX descriptor rings and buffers
1592          */
1593         sc->rx_rings = kmalloc_cachealign(
1594             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1595             M_DEVBUF, M_WAITOK | M_ZERO);
1596         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1597                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1598
1599                 /* Set up some basics */
1600                 rxr->sc = sc;
1601                 rxr->me = i;
1602                 lwkt_serialize_init(&rxr->rx_serialize);
1603
1604                 error = igb_create_rx_ring(rxr);
1605                 if (error)
1606                         return error;
1607         }
1608
1609         return 0;
1610 }
1611
1612 static void
1613 igb_free_rings(struct igb_softc *sc)
1614 {
1615         int i;
1616
1617         if (sc->tx_rings != NULL) {
1618                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1619                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1620
1621                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1622                 }
1623                 kfree(sc->tx_rings, M_DEVBUF);
1624         }
1625
1626         if (sc->rx_rings != NULL) {
1627                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1628                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1629
1630                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1631                 }
1632                 kfree(sc->rx_rings, M_DEVBUF);
1633         }
1634 }
1635
1636 static int
1637 igb_create_tx_ring(struct igb_tx_ring *txr)
1638 {
1639         int tsize, error, i, ntxd;
1640
1641         /*
1642          * Validate number of transmit descriptors. It must not exceed
1643          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1644          */
1645         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1646         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1647             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1648                 device_printf(txr->sc->dev,
1649                     "Using %d TX descriptors instead of %d!\n",
1650                     IGB_DEFAULT_TXD, ntxd);
1651                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1652         } else {
1653                 txr->num_tx_desc = ntxd;
1654         }
1655
1656         /*
1657          * Allocate TX descriptor ring
1658          */
1659         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1660             IGB_DBA_ALIGN);
1661         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1662             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1663             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1664         if (txr->txdma.dma_vaddr == NULL) {
1665                 device_printf(txr->sc->dev,
1666                     "Unable to allocate TX Descriptor memory\n");
1667                 return ENOMEM;
1668         }
1669         txr->tx_base = txr->txdma.dma_vaddr;
1670         bzero(txr->tx_base, tsize);
1671
1672         tsize = __VM_CACHELINE_ALIGN(
1673             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1674         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1675
1676         /*
1677          * Allocate TX head write-back buffer
1678          */
1679         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1680             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1681             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1682         if (txr->tx_hdr == NULL) {
1683                 device_printf(txr->sc->dev,
1684                     "Unable to allocate TX head write-back buffer\n");
1685                 return ENOMEM;
1686         }
1687
1688         /*
1689          * Create DMA tag for TX buffers
1690          */
1691         error = bus_dma_tag_create(txr->sc->parent_tag,
1692             1, 0,               /* alignment, bounds */
1693             BUS_SPACE_MAXADDR,  /* lowaddr */
1694             BUS_SPACE_MAXADDR,  /* highaddr */
1695             NULL, NULL,         /* filter, filterarg */
1696             IGB_TSO_SIZE,       /* maxsize */
1697             IGB_MAX_SCATTER,    /* nsegments */
1698             PAGE_SIZE,          /* maxsegsize */
1699             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1700             BUS_DMA_ONEBPAGE,   /* flags */
1701             &txr->tx_tag);
1702         if (error) {
1703                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1704                 kfree(txr->tx_buf, M_DEVBUF);
1705                 txr->tx_buf = NULL;
1706                 return error;
1707         }
1708
1709         /*
1710          * Create DMA maps for TX buffers
1711          */
1712         for (i = 0; i < txr->num_tx_desc; ++i) {
1713                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1714
1715                 error = bus_dmamap_create(txr->tx_tag,
1716                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1717                 if (error) {
1718                         device_printf(txr->sc->dev,
1719                             "Unable to create TX DMA map\n");
1720                         igb_destroy_tx_ring(txr, i);
1721                         return error;
1722                 }
1723         }
1724
1725         /*
1726          * Initialize various watermark
1727          */
1728         txr->spare_desc = IGB_TX_SPARE;
1729         txr->intr_nsegs = txr->num_tx_desc / 16;
1730         txr->wreg_nsegs = 8;
1731         txr->oact_hi_desc = txr->num_tx_desc / 2;
1732         txr->oact_lo_desc = txr->num_tx_desc / 8;
1733         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1734                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1735         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1736                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1737
1738         return 0;
1739 }
1740
1741 static void
1742 igb_free_tx_ring(struct igb_tx_ring *txr)
1743 {
1744         int i;
1745
1746         for (i = 0; i < txr->num_tx_desc; ++i) {
1747                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1748
1749                 if (txbuf->m_head != NULL) {
1750                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1751                         m_freem(txbuf->m_head);
1752                         txbuf->m_head = NULL;
1753                 }
1754         }
1755 }
1756
1757 static void
1758 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1759 {
1760         int i;
1761
1762         if (txr->txdma.dma_vaddr != NULL) {
1763                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1764                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1765                     txr->txdma.dma_map);
1766                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1767                 txr->txdma.dma_vaddr = NULL;
1768         }
1769
1770         if (txr->tx_hdr != NULL) {
1771                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1772                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1773                     txr->tx_hdr_dmap);
1774                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1775                 txr->tx_hdr = NULL;
1776         }
1777
1778         if (txr->tx_buf == NULL)
1779                 return;
1780
1781         for (i = 0; i < ndesc; ++i) {
1782                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1783
1784                 KKASSERT(txbuf->m_head == NULL);
1785                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1786         }
1787         bus_dma_tag_destroy(txr->tx_tag);
1788
1789         kfree(txr->tx_buf, M_DEVBUF);
1790         txr->tx_buf = NULL;
1791 }
1792
1793 static void
1794 igb_init_tx_ring(struct igb_tx_ring *txr)
1795 {
1796         /* Clear the old descriptor contents */
1797         bzero(txr->tx_base,
1798             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1799
1800         /* Clear TX head write-back buffer */
1801         *(txr->tx_hdr) = 0;
1802
1803         /* Reset indices */
1804         txr->next_avail_desc = 0;
1805         txr->next_to_clean = 0;
1806         txr->tx_nsegs = 0;
1807
1808         /* Set number of descriptors available */
1809         txr->tx_avail = txr->num_tx_desc;
1810 }
1811
1812 static void
1813 igb_init_tx_unit(struct igb_softc *sc)
1814 {
1815         struct e1000_hw *hw = &sc->hw;
1816         uint32_t tctl;
1817         int i;
1818
1819         /* Setup the Tx Descriptor Rings */
1820         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1821                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1822                 uint64_t bus_addr = txr->txdma.dma_paddr;
1823                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1824                 uint32_t txdctl = 0;
1825                 uint32_t dca_txctrl;
1826
1827                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1828                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1829                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1830                     (uint32_t)(bus_addr >> 32));
1831                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1832                     (uint32_t)bus_addr);
1833
1834                 /* Setup the HW Tx Head and Tail descriptor pointers */
1835                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1836                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1837
1838                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1839                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1840                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1841
1842                 /*
1843                  * Don't set WB_on_EITR:
1844                  * - 82575 does not have it
1845                  * - It almost has no effect on 82576, see:
1846                  *   82576 specification update errata #26
1847                  * - It causes unnecessary bus traffic
1848                  */
1849                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1850                     (uint32_t)(hdr_paddr >> 32));
1851                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1852                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1853
1854                 /*
1855                  * WTHRESH is ignored by the hardware, since header
1856                  * write back mode is used.
1857                  */
1858                 txdctl |= IGB_TX_PTHRESH;
1859                 txdctl |= IGB_TX_HTHRESH << 8;
1860                 txdctl |= IGB_TX_WTHRESH << 16;
1861                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1862                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1863         }
1864
1865         if (sc->vf_ifp)
1866                 return;
1867
1868         e1000_config_collision_dist(hw);
1869
1870         /* Program the Transmit Control Register */
1871         tctl = E1000_READ_REG(hw, E1000_TCTL);
1872         tctl &= ~E1000_TCTL_CT;
1873         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1874             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1875
1876         /* This write will effectively turn on the transmit unit. */
1877         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1878 }
1879
1880 static boolean_t
1881 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1882 {
1883         struct e1000_adv_tx_context_desc *TXD;
1884         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1885         int ehdrlen, ctxd, ip_hlen = 0;
1886         boolean_t offload = TRUE;
1887
1888         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1889                 offload = FALSE;
1890
1891         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1892
1893         ctxd = txr->next_avail_desc;
1894         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1895
1896         /*
1897          * In advanced descriptors the vlan tag must
1898          * be placed into the context descriptor, thus
1899          * we need to be here just for that setup.
1900          */
1901         if (mp->m_flags & M_VLANTAG) {
1902                 uint16_t vlantag;
1903
1904                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1905                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1906         } else if (!offload) {
1907                 return FALSE;
1908         }
1909
1910         ehdrlen = mp->m_pkthdr.csum_lhlen;
1911         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1912
1913         /* Set the ether header length */
1914         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1915         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1916                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1917                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1918                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1919         }
1920         vlan_macip_lens |= ip_hlen;
1921
1922         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1923         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1924                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1925         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1926                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1927
1928         /* 82575 needs the queue index added */
1929         if (txr->sc->hw.mac.type == e1000_82575)
1930                 mss_l4len_idx = txr->me << 4;
1931
1932         /* Now copy bits into descriptor */
1933         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1934         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1935         TXD->seqnum_seed = htole32(0);
1936         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1937
1938         /* We've consumed the first desc, adjust counters */
1939         if (++ctxd == txr->num_tx_desc)
1940                 ctxd = 0;
1941         txr->next_avail_desc = ctxd;
1942         --txr->tx_avail;
1943
1944         return offload;
1945 }
1946
1947 static void
1948 igb_txeof(struct igb_tx_ring *txr)
1949 {
1950         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1951         int first, hdr, avail;
1952
1953         if (txr->tx_avail == txr->num_tx_desc)
1954                 return;
1955
1956         first = txr->next_to_clean;
1957         hdr = *(txr->tx_hdr);
1958
1959         if (first == hdr)
1960                 return;
1961
1962         avail = txr->tx_avail;
1963         while (first != hdr) {
1964                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1965
1966                 ++avail;
1967                 if (txbuf->m_head) {
1968                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1969                         m_freem(txbuf->m_head);
1970                         txbuf->m_head = NULL;
1971                         ++ifp->if_opackets;
1972                 }
1973                 if (++first == txr->num_tx_desc)
1974                         first = 0;
1975         }
1976         txr->next_to_clean = first;
1977         txr->tx_avail = avail;
1978
1979         /*
1980          * If we have a minimum free, clear IFF_OACTIVE
1981          * to tell the stack that it is OK to send packets.
1982          */
1983         if (IGB_IS_NOT_OACTIVE(txr)) {
1984                 ifp->if_flags &= ~IFF_OACTIVE;
1985
1986                 /*
1987                  * We have enough TX descriptors, turn off
1988                  * the watchdog.  We allow small amount of
1989                  * packets (roughly intr_nsegs) pending on
1990                  * the transmit ring.
1991                  */
1992                 ifp->if_timer = 0;
1993         }
1994 }
1995
1996 static int
1997 igb_create_rx_ring(struct igb_rx_ring *rxr)
1998 {
1999         int rsize, i, error, nrxd;
2000
2001         /*
2002          * Validate number of receive descriptors. It must not exceed
2003          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2004          */
2005         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2006         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2007             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2008                 device_printf(rxr->sc->dev,
2009                     "Using %d RX descriptors instead of %d!\n",
2010                     IGB_DEFAULT_RXD, nrxd);
2011                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2012         } else {
2013                 rxr->num_rx_desc = nrxd;
2014         }
2015
2016         /*
2017          * Allocate RX descriptor ring
2018          */
2019         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2020             IGB_DBA_ALIGN);
2021         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2022             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2023             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2024             &rxr->rxdma.dma_paddr);
2025         if (rxr->rxdma.dma_vaddr == NULL) {
2026                 device_printf(rxr->sc->dev,
2027                     "Unable to allocate RxDescriptor memory\n");
2028                 return ENOMEM;
2029         }
2030         rxr->rx_base = rxr->rxdma.dma_vaddr;
2031         bzero(rxr->rx_base, rsize);
2032
2033         rsize = __VM_CACHELINE_ALIGN(
2034             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2035         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2036
2037         /*
2038          * Create DMA tag for RX buffers
2039          */
2040         error = bus_dma_tag_create(rxr->sc->parent_tag,
2041             1, 0,               /* alignment, bounds */
2042             BUS_SPACE_MAXADDR,  /* lowaddr */
2043             BUS_SPACE_MAXADDR,  /* highaddr */
2044             NULL, NULL,         /* filter, filterarg */
2045             MCLBYTES,           /* maxsize */
2046             1,                  /* nsegments */
2047             MCLBYTES,           /* maxsegsize */
2048             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2049             &rxr->rx_tag);
2050         if (error) {
2051                 device_printf(rxr->sc->dev,
2052                     "Unable to create RX payload DMA tag\n");
2053                 kfree(rxr->rx_buf, M_DEVBUF);
2054                 rxr->rx_buf = NULL;
2055                 return error;
2056         }
2057
2058         /*
2059          * Create spare DMA map for RX buffers
2060          */
2061         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2062             &rxr->rx_sparemap);
2063         if (error) {
2064                 device_printf(rxr->sc->dev,
2065                     "Unable to create spare RX DMA maps\n");
2066                 bus_dma_tag_destroy(rxr->rx_tag);
2067                 kfree(rxr->rx_buf, M_DEVBUF);
2068                 rxr->rx_buf = NULL;
2069                 return error;
2070         }
2071
2072         /*
2073          * Create DMA maps for RX buffers
2074          */
2075         for (i = 0; i < rxr->num_rx_desc; i++) {
2076                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2077
2078                 error = bus_dmamap_create(rxr->rx_tag,
2079                     BUS_DMA_WAITOK, &rxbuf->map);
2080                 if (error) {
2081                         device_printf(rxr->sc->dev,
2082                             "Unable to create RX DMA maps\n");
2083                         igb_destroy_rx_ring(rxr, i);
2084                         return error;
2085                 }
2086         }
2087         return 0;
2088 }
2089
2090 static void
2091 igb_free_rx_ring(struct igb_rx_ring *rxr)
2092 {
2093         int i;
2094
2095         for (i = 0; i < rxr->num_rx_desc; ++i) {
2096                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2097
2098                 if (rxbuf->m_head != NULL) {
2099                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2100                         m_freem(rxbuf->m_head);
2101                         rxbuf->m_head = NULL;
2102                 }
2103         }
2104
2105         if (rxr->fmp != NULL)
2106                 m_freem(rxr->fmp);
2107         rxr->fmp = NULL;
2108         rxr->lmp = NULL;
2109 }
2110
2111 static void
2112 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2113 {
2114         int i;
2115
2116         if (rxr->rxdma.dma_vaddr != NULL) {
2117                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2118                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2119                     rxr->rxdma.dma_map);
2120                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2121                 rxr->rxdma.dma_vaddr = NULL;
2122         }
2123
2124         if (rxr->rx_buf == NULL)
2125                 return;
2126
2127         for (i = 0; i < ndesc; ++i) {
2128                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2129
2130                 KKASSERT(rxbuf->m_head == NULL);
2131                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2132         }
2133         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2134         bus_dma_tag_destroy(rxr->rx_tag);
2135
2136         kfree(rxr->rx_buf, M_DEVBUF);
2137         rxr->rx_buf = NULL;
2138 }
2139
2140 static void
2141 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2142 {
2143         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2144         rxd->wb.upper.status_error = 0;
2145 }
2146
2147 static int
2148 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2149 {
2150         struct mbuf *m;
2151         bus_dma_segment_t seg;
2152         bus_dmamap_t map;
2153         struct igb_rx_buf *rxbuf;
2154         int error, nseg;
2155
2156         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2157         if (m == NULL) {
2158                 if (wait) {
2159                         if_printf(&rxr->sc->arpcom.ac_if,
2160                             "Unable to allocate RX mbuf\n");
2161                 }
2162                 return ENOBUFS;
2163         }
2164         m->m_len = m->m_pkthdr.len = MCLBYTES;
2165
2166         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2167                 m_adj(m, ETHER_ALIGN);
2168
2169         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2170             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2171         if (error) {
2172                 m_freem(m);
2173                 if (wait) {
2174                         if_printf(&rxr->sc->arpcom.ac_if,
2175                             "Unable to load RX mbuf\n");
2176                 }
2177                 return error;
2178         }
2179
2180         rxbuf = &rxr->rx_buf[i];
2181         if (rxbuf->m_head != NULL)
2182                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2183
2184         map = rxbuf->map;
2185         rxbuf->map = rxr->rx_sparemap;
2186         rxr->rx_sparemap = map;
2187
2188         rxbuf->m_head = m;
2189         rxbuf->paddr = seg.ds_addr;
2190
2191         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2192         return 0;
2193 }
2194
2195 static int
2196 igb_init_rx_ring(struct igb_rx_ring *rxr)
2197 {
2198         int i;
2199
2200         /* Clear the ring contents */
2201         bzero(rxr->rx_base,
2202             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2203
2204         /* Now replenish the ring mbufs */
2205         for (i = 0; i < rxr->num_rx_desc; ++i) {
2206                 int error;
2207
2208                 error = igb_newbuf(rxr, i, TRUE);
2209                 if (error)
2210                         return error;
2211         }
2212
2213         /* Setup our descriptor indices */
2214         rxr->next_to_check = 0;
2215
2216         rxr->fmp = NULL;
2217         rxr->lmp = NULL;
2218         rxr->discard = FALSE;
2219
2220         return 0;
2221 }
2222
2223 static void
2224 igb_init_rx_unit(struct igb_softc *sc)
2225 {
2226         struct ifnet *ifp = &sc->arpcom.ac_if;
2227         struct e1000_hw *hw = &sc->hw;
2228         uint32_t rctl, rxcsum, srrctl = 0;
2229         int i;
2230
2231         /*
2232          * Make sure receives are disabled while setting
2233          * up the descriptor ring
2234          */
2235         rctl = E1000_READ_REG(hw, E1000_RCTL);
2236         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2237
2238 #if 0
2239         /*
2240         ** Set up for header split
2241         */
2242         if (igb_header_split) {
2243                 /* Use a standard mbuf for the header */
2244                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2245                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2246         } else
2247 #endif
2248                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2249
2250         /*
2251         ** Set up for jumbo frames
2252         */
2253         if (ifp->if_mtu > ETHERMTU) {
2254                 rctl |= E1000_RCTL_LPE;
2255 #if 0
2256                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2257                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2258                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2259                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2260                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2261                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2262                 }
2263                 /* Set maximum packet len */
2264                 psize = adapter->max_frame_size;
2265                 /* are we on a vlan? */
2266                 if (adapter->ifp->if_vlantrunk != NULL)
2267                         psize += VLAN_TAG_SIZE;
2268                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2269 #else
2270                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2271                 rctl |= E1000_RCTL_SZ_2048;
2272 #endif
2273         } else {
2274                 rctl &= ~E1000_RCTL_LPE;
2275                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2276                 rctl |= E1000_RCTL_SZ_2048;
2277         }
2278
2279         /* Setup the Base and Length of the Rx Descriptor Rings */
2280         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2281                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2282                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2283                 uint32_t rxdctl;
2284
2285                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2286                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2287                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2288                     (uint32_t)(bus_addr >> 32));
2289                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2290                     (uint32_t)bus_addr);
2291                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2292                 /* Enable this Queue */
2293                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2294                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2295                 rxdctl &= 0xFFF00000;
2296                 rxdctl |= IGB_RX_PTHRESH;
2297                 rxdctl |= IGB_RX_HTHRESH << 8;
2298                 /*
2299                  * Don't set WTHRESH to a value above 1 on 82576, see:
2300                  * 82576 specification update errata #26
2301                  */
2302                 rxdctl |= IGB_RX_WTHRESH << 16;
2303                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2304         }
2305
2306         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2307         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2308
2309         /*
2310          * Receive Checksum Offload for TCP and UDP
2311          *
2312          * Checksum offloading is also enabled if multiple receive
2313          * queue is to be supported, since we need it to figure out
2314          * fragments.
2315          */
2316         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2317                 /*
2318                  * NOTE:
2319                  * PCSD must be enabled to enable multiple
2320                  * receive queues.
2321                  */
2322                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2323                     E1000_RXCSUM_PCSD;
2324         } else {
2325                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2326                     E1000_RXCSUM_PCSD);
2327         }
2328         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2329
2330         if (IGB_ENABLE_HWRSS(sc)) {
2331                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2332                 uint32_t reta_shift;
2333                 int j, r;
2334
2335                 /*
2336                  * NOTE:
2337                  * When we reach here, RSS has already been disabled
2338                  * in igb_stop(), so we could safely configure RSS key
2339                  * and redirect table.
2340                  */
2341
2342                 /*
2343                  * Configure RSS key
2344                  */
2345                 toeplitz_get_key(key, sizeof(key));
2346                 for (i = 0; i < IGB_NRSSRK; ++i) {
2347                         uint32_t rssrk;
2348
2349                         rssrk = IGB_RSSRK_VAL(key, i);
2350                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2351
2352                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2353                 }
2354
2355                 /*
2356                  * Configure RSS redirect table in following fashion:
2357                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2358                  */
2359                 reta_shift = IGB_RETA_SHIFT;
2360                 if (hw->mac.type == e1000_82575)
2361                         reta_shift = IGB_RETA_SHIFT_82575;
2362
2363                 r = 0;
2364                 for (j = 0; j < IGB_NRETA; ++j) {
2365                         uint32_t reta = 0;
2366
2367                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2368                                 uint32_t q;
2369
2370                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2371                                 reta |= q << (8 * i);
2372                                 ++r;
2373                         }
2374                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2375                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2376                 }
2377
2378                 /*
2379                  * Enable multiple receive queues.
2380                  * Enable IPv4 RSS standard hash functions.
2381                  * Disable RSS interrupt on 82575
2382                  */
2383                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2384                                 E1000_MRQC_ENABLE_RSS_4Q |
2385                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2386                                 E1000_MRQC_RSS_FIELD_IPV4);
2387         }
2388
2389         /* Setup the Receive Control Register */
2390         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2391         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2392             E1000_RCTL_RDMTS_HALF |
2393             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2394         /* Strip CRC bytes. */
2395         rctl |= E1000_RCTL_SECRC;
2396         /* Make sure VLAN Filters are off */
2397         rctl &= ~E1000_RCTL_VFE;
2398         /* Don't store bad packets */
2399         rctl &= ~E1000_RCTL_SBP;
2400
2401         /* Enable Receives */
2402         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2403
2404         /*
2405          * Setup the HW Rx Head and Tail Descriptor Pointers
2406          *   - needs to be after enable
2407          */
2408         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2409                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2410
2411                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2412                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2413         }
2414 }
2415
2416 static void
2417 igb_rxeof(struct igb_rx_ring *rxr, int count)
2418 {
2419         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2420         union e1000_adv_rx_desc *cur;
2421         uint32_t staterr;
2422         int i;
2423
2424         i = rxr->next_to_check;
2425         cur = &rxr->rx_base[i];
2426         staterr = le32toh(cur->wb.upper.status_error);
2427
2428         if ((staterr & E1000_RXD_STAT_DD) == 0)
2429                 return;
2430
2431         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2432                 struct pktinfo *pi = NULL, pi0;
2433                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2434                 struct mbuf *m = NULL;
2435                 boolean_t eop;
2436
2437                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2438                 if (eop)
2439                         --count;
2440
2441                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2442                     !rxr->discard) {
2443                         struct mbuf *mp = rxbuf->m_head;
2444                         uint32_t hash, hashtype;
2445                         uint16_t vlan;
2446                         int len;
2447
2448                         len = le16toh(cur->wb.upper.length);
2449                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2450                             (staterr & E1000_RXDEXT_STATERR_LB))
2451                                 vlan = be16toh(cur->wb.upper.vlan);
2452                         else
2453                                 vlan = le16toh(cur->wb.upper.vlan);
2454
2455                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2456                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2457                             E1000_RXDADV_RSSTYPE_MASK;
2458
2459                         IGB_RSS_DPRINTF(rxr->sc, 10,
2460                             "ring%d, hash 0x%08x, hashtype %u\n",
2461                             rxr->me, hash, hashtype);
2462
2463                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2464                             BUS_DMASYNC_POSTREAD);
2465
2466                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2467                                 ifp->if_iqdrops++;
2468                                 goto discard;
2469                         }
2470
2471                         mp->m_len = len;
2472                         if (rxr->fmp == NULL) {
2473                                 mp->m_pkthdr.len = len;
2474                                 rxr->fmp = mp;
2475                                 rxr->lmp = mp;
2476                         } else {
2477                                 rxr->lmp->m_next = mp;
2478                                 rxr->lmp = rxr->lmp->m_next;
2479                                 rxr->fmp->m_pkthdr.len += len;
2480                         }
2481
2482                         if (eop) {
2483                                 m = rxr->fmp;
2484                                 rxr->fmp = NULL;
2485                                 rxr->lmp = NULL;
2486
2487                                 m->m_pkthdr.rcvif = ifp;
2488                                 ifp->if_ipackets++;
2489
2490                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2491                                         igb_rxcsum(staterr, m);
2492
2493                                 if (staterr & E1000_RXD_STAT_VP) {
2494                                         m->m_pkthdr.ether_vlantag = vlan;
2495                                         m->m_flags |= M_VLANTAG;
2496                                 }
2497
2498                                 if (ifp->if_capenable & IFCAP_RSS) {
2499                                         pi = igb_rssinfo(m, &pi0,
2500                                             hash, hashtype, staterr);
2501                                 }
2502 #ifdef IGB_RSS_DEBUG
2503                                 rxr->rx_packets++;
2504 #endif
2505                         }
2506                 } else {
2507                         ifp->if_ierrors++;
2508 discard:
2509                         igb_setup_rxdesc(cur, rxbuf);
2510                         if (!eop)
2511                                 rxr->discard = TRUE;
2512                         else
2513                                 rxr->discard = FALSE;
2514                         if (rxr->fmp != NULL) {
2515                                 m_freem(rxr->fmp);
2516                                 rxr->fmp = NULL;
2517                                 rxr->lmp = NULL;
2518                         }
2519                         m = NULL;
2520                 }
2521
2522                 if (m != NULL)
2523                         ether_input_pkt(ifp, m, pi);
2524
2525                 /* Advance our pointers to the next descriptor. */
2526                 if (++i == rxr->num_rx_desc)
2527                         i = 0;
2528
2529                 cur = &rxr->rx_base[i];
2530                 staterr = le32toh(cur->wb.upper.status_error);
2531         }
2532         rxr->next_to_check = i;
2533
2534         if (--i < 0)
2535                 i = rxr->num_rx_desc - 1;
2536         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2537 }
2538
2539
2540 static void
2541 igb_set_vlan(struct igb_softc *sc)
2542 {
2543         struct e1000_hw *hw = &sc->hw;
2544         uint32_t reg;
2545 #if 0
2546         struct ifnet *ifp = sc->arpcom.ac_if;
2547 #endif
2548
2549         if (sc->vf_ifp) {
2550                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2551                 return;
2552         }
2553
2554         reg = E1000_READ_REG(hw, E1000_CTRL);
2555         reg |= E1000_CTRL_VME;
2556         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2557
2558 #if 0
2559         /* Enable the Filter Table */
2560         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2561                 reg = E1000_READ_REG(hw, E1000_RCTL);
2562                 reg &= ~E1000_RCTL_CFIEN;
2563                 reg |= E1000_RCTL_VFE;
2564                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2565         }
2566 #endif
2567
2568         /* Update the frame size */
2569         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2570             sc->max_frame_size + VLAN_TAG_SIZE);
2571
2572 #if 0
2573         /* Don't bother with table if no vlans */
2574         if ((adapter->num_vlans == 0) ||
2575             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2576                 return;
2577         /*
2578         ** A soft reset zero's out the VFTA, so
2579         ** we need to repopulate it now.
2580         */
2581         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2582                 if (adapter->shadow_vfta[i] != 0) {
2583                         if (adapter->vf_ifp)
2584                                 e1000_vfta_set_vf(hw,
2585                                     adapter->shadow_vfta[i], TRUE);
2586                         else
2587                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2588                                  i, adapter->shadow_vfta[i]);
2589                 }
2590 #endif
2591 }
2592
2593 static void
2594 igb_enable_intr(struct igb_softc *sc)
2595 {
2596         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2597                 lwkt_serialize_handler_enable(&sc->main_serialize);
2598         } else {
2599                 int i;
2600
2601                 for (i = 0; i < sc->msix_cnt; ++i) {
2602                         lwkt_serialize_handler_enable(
2603                             sc->msix_data[i].msix_serialize);
2604                 }
2605         }
2606
2607         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2608                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2609                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2610                 else
2611                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2612                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2613                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2614                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2615         } else {
2616                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2617         }
2618         E1000_WRITE_FLUSH(&sc->hw);
2619 }
2620
2621 static void
2622 igb_disable_intr(struct igb_softc *sc)
2623 {
2624         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2625                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2626                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2627         }
2628         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2629         E1000_WRITE_FLUSH(&sc->hw);
2630
2631         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2632                 lwkt_serialize_handler_disable(&sc->main_serialize);
2633         } else {
2634                 int i;
2635
2636                 for (i = 0; i < sc->msix_cnt; ++i) {
2637                         lwkt_serialize_handler_disable(
2638                             sc->msix_data[i].msix_serialize);
2639                 }
2640         }
2641 }
2642
2643 /*
2644  * Bit of a misnomer, what this really means is
2645  * to enable OS management of the system... aka
2646  * to disable special hardware management features
2647  */
2648 static void
2649 igb_get_mgmt(struct igb_softc *sc)
2650 {
2651         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2652                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2653                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2654
2655                 /* disable hardware interception of ARP */
2656                 manc &= ~E1000_MANC_ARP_EN;
2657
2658                 /* enable receiving management packets to the host */
2659                 manc |= E1000_MANC_EN_MNG2HOST;
2660                 manc2h |= 1 << 5; /* Mng Port 623 */
2661                 manc2h |= 1 << 6; /* Mng Port 664 */
2662                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2663                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2664         }
2665 }
2666
2667 /*
2668  * Give control back to hardware management controller
2669  * if there is one.
2670  */
2671 static void
2672 igb_rel_mgmt(struct igb_softc *sc)
2673 {
2674         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2675                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2676
2677                 /* Re-enable hardware interception of ARP */
2678                 manc |= E1000_MANC_ARP_EN;
2679                 manc &= ~E1000_MANC_EN_MNG2HOST;
2680
2681                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2682         }
2683 }
2684
2685 /*
2686  * Sets CTRL_EXT:DRV_LOAD bit.
2687  *
2688  * For ASF and Pass Through versions of f/w this means that
2689  * the driver is loaded.
2690  */
2691 static void
2692 igb_get_hw_control(struct igb_softc *sc)
2693 {
2694         uint32_t ctrl_ext;
2695
2696         if (sc->vf_ifp)
2697                 return;
2698
2699         /* Let firmware know the driver has taken over */
2700         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2701         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2702             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2703 }
2704
2705 /*
2706  * Resets CTRL_EXT:DRV_LOAD bit.
2707  *
2708  * For ASF and Pass Through versions of f/w this means that the
2709  * driver is no longer loaded.
2710  */
2711 static void
2712 igb_rel_hw_control(struct igb_softc *sc)
2713 {
2714         uint32_t ctrl_ext;
2715
2716         if (sc->vf_ifp)
2717                 return;
2718
2719         /* Let firmware taken over control of h/w */
2720         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2721         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2722             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2723 }
2724
2725 static int
2726 igb_is_valid_ether_addr(const uint8_t *addr)
2727 {
2728         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2729
2730         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2731                 return FALSE;
2732         return TRUE;
2733 }
2734
2735 /*
2736  * Enable PCI Wake On Lan capability
2737  */
2738 static void
2739 igb_enable_wol(device_t dev)
2740 {
2741         uint16_t cap, status;
2742         uint8_t id;
2743
2744         /* First find the capabilities pointer*/
2745         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2746
2747         /* Read the PM Capabilities */
2748         id = pci_read_config(dev, cap, 1);
2749         if (id != PCIY_PMG)     /* Something wrong */
2750                 return;
2751
2752         /*
2753          * OK, we have the power capabilities,
2754          * so now get the status register
2755          */
2756         cap += PCIR_POWER_STATUS;
2757         status = pci_read_config(dev, cap, 2);
2758         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2759         pci_write_config(dev, cap, status, 2);
2760 }
2761
2762 static void
2763 igb_update_stats_counters(struct igb_softc *sc)
2764 {
2765         struct e1000_hw *hw = &sc->hw;
2766         struct e1000_hw_stats *stats;
2767         struct ifnet *ifp = &sc->arpcom.ac_if;
2768
2769         /*
2770          * The virtual function adapter has only a
2771          * small controlled set of stats, do only
2772          * those and return.
2773          */
2774         if (sc->vf_ifp) {
2775                 igb_update_vf_stats_counters(sc);
2776                 return;
2777         }
2778         stats = sc->stats;
2779
2780         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2781             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2782                 stats->symerrs +=
2783                     E1000_READ_REG(hw,E1000_SYMERRS);
2784                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2785         }
2786
2787         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2788         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2789         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2790         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2791
2792         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2793         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2794         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2795         stats->dc += E1000_READ_REG(hw, E1000_DC);
2796         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2797         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2798         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2799
2800         /*
2801          * For watchdog management we need to know if we have been
2802          * paused during the last interval, so capture that here.
2803          */
2804         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2805         stats->xoffrxc += sc->pause_frames;
2806         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2807         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2808         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2809         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2810         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2811         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2812         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2813         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2814         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2815         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2816         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2817         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2818
2819         /* For the 64-bit byte counters the low dword must be read first. */
2820         /* Both registers clear on the read of the high dword */
2821
2822         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2823             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2824         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2825             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2826
2827         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2828         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2829         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2830         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2831         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2832
2833         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2834         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2835
2836         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2837         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2838         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2839         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2840         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2841         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2842         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2843         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2844         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2845         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2846
2847         /* Interrupt Counts */
2848
2849         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2850         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2851         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2852         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2853         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2854         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2855         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2856         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2857         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2858
2859         /* Host to Card Statistics */
2860
2861         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2862         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2863         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2864         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2865         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2866         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2867         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2868         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2869             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2870         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2871             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2872         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2873         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2874         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2875
2876         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2877         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2878         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2879         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2880         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2881         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2882
2883         ifp->if_collisions = stats->colc;
2884
2885         /* Rx Errors */
2886         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2887             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2888
2889         /* Tx Errors */
2890         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2891
2892         /* Driver specific counters */
2893         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2894         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2895         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2896         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2897         sc->packet_buf_alloc_tx =
2898             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2899         sc->packet_buf_alloc_rx =
2900             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2901 }
2902
2903 static void
2904 igb_vf_init_stats(struct igb_softc *sc)
2905 {
2906         struct e1000_hw *hw = &sc->hw;
2907         struct e1000_vf_stats *stats;
2908
2909         stats = sc->stats;
2910         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2911         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2912         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2913         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2914         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2915 }
2916
2917 static void
2918 igb_update_vf_stats_counters(struct igb_softc *sc)
2919 {
2920         struct e1000_hw *hw = &sc->hw;
2921         struct e1000_vf_stats *stats;
2922
2923         if (sc->link_speed == 0)
2924                 return;
2925
2926         stats = sc->stats;
2927         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2928         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2929         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2930         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2931         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2932 }
2933
2934 #ifdef IFPOLL_ENABLE
2935
2936 static void
2937 igb_npoll_status(struct ifnet *ifp)
2938 {
2939         struct igb_softc *sc = ifp->if_softc;
2940         uint32_t reg_icr;
2941
2942         ASSERT_SERIALIZED(&sc->main_serialize);
2943
2944         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2945         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2946                 sc->hw.mac.get_link_status = 1;
2947                 igb_update_link_status(sc);
2948         }
2949 }
2950
2951 static void
2952 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
2953 {
2954         struct igb_tx_ring *txr = arg;
2955
2956         ASSERT_SERIALIZED(&txr->tx_serialize);
2957
2958         igb_txeof(txr);
2959         if (!ifq_is_empty(&ifp->if_snd))
2960                 if_devstart(ifp);
2961 }
2962
2963 static void
2964 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
2965 {
2966         struct igb_rx_ring *rxr = arg;
2967
2968         ASSERT_SERIALIZED(&rxr->rx_serialize);
2969
2970         igb_rxeof(rxr, cycle);
2971 }
2972
2973 static void
2974 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2975 {
2976         struct igb_softc *sc = ifp->if_softc;
2977
2978         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2979
2980         if (info) {
2981                 struct igb_tx_ring *txr;
2982                 int i, off;
2983
2984                 info->ifpi_status.status_func = igb_npoll_status;
2985                 info->ifpi_status.serializer = &sc->main_serialize;
2986
2987                 off = sc->tx_npoll_off;
2988                 KKASSERT(off < ncpus2);
2989                 txr = &sc->tx_rings[0];
2990                 info->ifpi_tx[off].poll_func = igb_npoll_tx;
2991                 info->ifpi_tx[off].arg = txr;
2992                 info->ifpi_tx[off].serializer = &txr->tx_serialize;
2993
2994                 off = sc->rx_npoll_off;
2995                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2996                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2997                         int idx = i + off;
2998
2999                         KKASSERT(idx < ncpus2);
3000                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3001                         info->ifpi_rx[idx].arg = rxr;
3002                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3003                 }
3004
3005                 if (ifp->if_flags & IFF_RUNNING) {
3006                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3007                                 igb_disable_intr(sc);
3008                         else
3009                                 igb_init(sc);
3010                 }
3011                 ifp->if_npoll_cpuid = sc->tx_npoll_off;
3012         } else {
3013                 if (ifp->if_flags & IFF_RUNNING) {
3014                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3015                                 igb_enable_intr(sc);
3016                         else
3017                                 igb_init(sc);
3018                 }
3019                 ifp->if_npoll_cpuid = -1;
3020         }
3021 }
3022
3023 #endif /* IFPOLL_ENABLE */
3024
3025 static void
3026 igb_intr(void *xsc)
3027 {
3028         struct igb_softc *sc = xsc;
3029         struct ifnet *ifp = &sc->arpcom.ac_if;
3030         uint32_t eicr;
3031
3032         ASSERT_SERIALIZED(&sc->main_serialize);
3033
3034         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3035
3036         if (eicr == 0)
3037                 return;
3038
3039         if (ifp->if_flags & IFF_RUNNING) {
3040                 struct igb_tx_ring *txr;
3041                 int i;
3042
3043                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3044                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3045
3046                         if (eicr & rxr->rx_intr_mask) {
3047                                 lwkt_serialize_enter(&rxr->rx_serialize);
3048                                 igb_rxeof(rxr, -1);
3049                                 lwkt_serialize_exit(&rxr->rx_serialize);
3050                         }
3051                 }
3052
3053                 txr = &sc->tx_rings[0];
3054                 if (eicr & txr->tx_intr_mask) {
3055                         lwkt_serialize_enter(&txr->tx_serialize);
3056                         igb_txeof(txr);
3057                         if (!ifq_is_empty(&ifp->if_snd))
3058                                 if_devstart(ifp);
3059                         lwkt_serialize_exit(&txr->tx_serialize);
3060                 }
3061         }
3062
3063         if (eicr & E1000_EICR_OTHER) {
3064                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3065
3066                 /* Link status change */
3067                 if (icr & E1000_ICR_LSC) {
3068                         sc->hw.mac.get_link_status = 1;
3069                         igb_update_link_status(sc);
3070                 }
3071         }
3072
3073         /*
3074          * Reading EICR has the side effect to clear interrupt mask,
3075          * so all interrupts need to be enabled here.
3076          */
3077         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3078 }
3079
3080 static void
3081 igb_intr_shared(void *xsc)
3082 {
3083         struct igb_softc *sc = xsc;
3084         struct ifnet *ifp = &sc->arpcom.ac_if;
3085         uint32_t reg_icr;
3086
3087         ASSERT_SERIALIZED(&sc->main_serialize);
3088
3089         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3090
3091         /* Hot eject?  */
3092         if (reg_icr == 0xffffffff)
3093                 return;
3094
3095         /* Definitely not our interrupt.  */
3096         if (reg_icr == 0x0)
3097                 return;
3098
3099         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3100                 return;
3101
3102         if (ifp->if_flags & IFF_RUNNING) {
3103                 if (reg_icr &
3104                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3105                         int i;
3106
3107                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3108                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3109
3110                                 lwkt_serialize_enter(&rxr->rx_serialize);
3111                                 igb_rxeof(rxr, -1);
3112                                 lwkt_serialize_exit(&rxr->rx_serialize);
3113                         }
3114                 }
3115
3116                 if (reg_icr & E1000_ICR_TXDW) {
3117                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3118
3119                         lwkt_serialize_enter(&txr->tx_serialize);
3120                         igb_txeof(txr);
3121                         if (!ifq_is_empty(&ifp->if_snd))
3122                                 if_devstart(ifp);
3123                         lwkt_serialize_exit(&txr->tx_serialize);
3124                 }
3125         }
3126
3127         /* Link status change */
3128         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3129                 sc->hw.mac.get_link_status = 1;
3130                 igb_update_link_status(sc);
3131         }
3132
3133         if (reg_icr & E1000_ICR_RXO)
3134                 sc->rx_overruns++;
3135 }
3136
3137 static int
3138 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3139     int *segs_used, int *idx)
3140 {
3141         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3142         bus_dmamap_t map;
3143         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3144         union e1000_adv_tx_desc *txd = NULL;
3145         struct mbuf *m_head = *m_headp;
3146         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3147         int maxsegs, nsegs, i, j, error, last = 0;
3148         uint32_t hdrlen = 0;
3149
3150         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3151                 error = igb_tso_pullup(txr, m_headp);
3152                 if (error)
3153                         return error;
3154                 m_head = *m_headp;
3155         }
3156
3157         /* Set basic descriptor constants */
3158         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3159         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3160         if (m_head->m_flags & M_VLANTAG)
3161                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3162
3163         /*
3164          * Map the packet for DMA.
3165          */
3166         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3167         tx_buf_mapped = tx_buf;
3168         map = tx_buf->map;
3169
3170         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3171         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3172         if (maxsegs > IGB_MAX_SCATTER)
3173                 maxsegs = IGB_MAX_SCATTER;
3174
3175         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3176             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3177         if (error) {
3178                 if (error == ENOBUFS)
3179                         txr->sc->mbuf_defrag_failed++;
3180                 else
3181                         txr->sc->no_tx_dma_setup++;
3182
3183                 m_freem(*m_headp);
3184                 *m_headp = NULL;
3185                 return error;
3186         }
3187         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3188
3189         m_head = *m_headp;
3190
3191         /*
3192          * Set up the TX context descriptor, if any hardware offloading is
3193          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3194          * TX descriptor.
3195          *
3196          * Unlike these chips' predecessors (em/emx), TX context descriptor
3197          * will _not_ interfere TX data fetching pipelining.
3198          */
3199         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3200                 igb_tso_ctx(txr, m_head, &hdrlen);
3201                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3202                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3203                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3204                 txr->tx_nsegs++;
3205                 (*segs_used)++;
3206         } else if (igb_txcsum_ctx(txr, m_head)) {
3207                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3208                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3209                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3210                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3211                 txr->tx_nsegs++;
3212                 (*segs_used)++;
3213         }
3214
3215         *segs_used += nsegs;
3216         txr->tx_nsegs += nsegs;
3217         if (txr->tx_nsegs >= txr->intr_nsegs) {
3218                 /*
3219                  * Report Status (RS) is turned on every intr_nsegs
3220                  * descriptors (roughly).
3221                  */
3222                 txr->tx_nsegs = 0;
3223                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3224         }
3225
3226         /* Calculate payload length */
3227         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3228             << E1000_ADVTXD_PAYLEN_SHIFT);
3229
3230         /* 82575 needs the queue index added */
3231         if (txr->sc->hw.mac.type == e1000_82575)
3232                 olinfo_status |= txr->me << 4;
3233
3234         /* Set up our transmit descriptors */
3235         i = txr->next_avail_desc;
3236         for (j = 0; j < nsegs; j++) {
3237                 bus_size_t seg_len;
3238                 bus_addr_t seg_addr;
3239
3240                 tx_buf = &txr->tx_buf[i];
3241                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3242                 seg_addr = segs[j].ds_addr;
3243                 seg_len = segs[j].ds_len;
3244
3245                 txd->read.buffer_addr = htole64(seg_addr);
3246                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3247                 txd->read.olinfo_status = htole32(olinfo_status);
3248                 last = i;
3249                 if (++i == txr->num_tx_desc)
3250                         i = 0;
3251                 tx_buf->m_head = NULL;
3252         }
3253
3254         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3255         txr->next_avail_desc = i;
3256         txr->tx_avail -= nsegs;
3257
3258         tx_buf->m_head = m_head;
3259         tx_buf_mapped->map = tx_buf->map;
3260         tx_buf->map = map;
3261
3262         /*
3263          * Last Descriptor of Packet needs End Of Packet (EOP)
3264          */
3265         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3266
3267         /*
3268          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3269          * that this frame is available to transmit.
3270          */
3271         *idx = i;
3272         ++txr->tx_packets;
3273
3274         return 0;
3275 }
3276
3277 static void
3278 igb_start(struct ifnet *ifp)
3279 {
3280         struct igb_softc *sc = ifp->if_softc;
3281         struct igb_tx_ring *txr = &sc->tx_rings[0];
3282         struct mbuf *m_head;
3283         int idx = -1, nsegs = 0;
3284
3285         ASSERT_SERIALIZED(&txr->tx_serialize);
3286
3287         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3288                 return;
3289
3290         if (!sc->link_active) {
3291                 ifq_purge(&ifp->if_snd);
3292                 return;
3293         }
3294
3295         if (!IGB_IS_NOT_OACTIVE(txr))
3296                 igb_txeof(txr);
3297
3298         while (!ifq_is_empty(&ifp->if_snd)) {
3299                 if (IGB_IS_OACTIVE(txr)) {
3300                         ifp->if_flags |= IFF_OACTIVE;
3301                         /* Set watchdog on */
3302                         ifp->if_timer = 5;
3303                         break;
3304                 }
3305
3306                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3307                 if (m_head == NULL)
3308                         break;
3309
3310                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3311                         ifp->if_oerrors++;
3312                         continue;
3313                 }
3314
3315                 if (nsegs >= txr->wreg_nsegs) {
3316                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3317                         idx = -1;
3318                         nsegs = 0;
3319                 }
3320
3321                 /* Send a copy of the frame to the BPF listener */
3322                 ETHER_BPF_MTAP(ifp, m_head);
3323         }
3324         if (idx >= 0)
3325                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3326 }
3327
3328 static void
3329 igb_watchdog(struct ifnet *ifp)
3330 {
3331         struct igb_softc *sc = ifp->if_softc;
3332         struct igb_tx_ring *txr = &sc->tx_rings[0];
3333
3334         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3335
3336         /*
3337          * If flow control has paused us since last checking
3338          * it invalidates the watchdog timing, so dont run it.
3339          */
3340         if (sc->pause_frames) {
3341                 sc->pause_frames = 0;
3342                 ifp->if_timer = 5;
3343                 return;
3344         }
3345
3346         if_printf(ifp, "Watchdog timeout -- resetting\n");
3347         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3348             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3349             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3350         if_printf(ifp, "TX(%d) desc avail = %d, "
3351             "Next TX to Clean = %d\n",
3352             txr->me, txr->tx_avail, txr->next_to_clean);
3353
3354         ifp->if_oerrors++;
3355         sc->watchdog_events++;
3356
3357         igb_init(sc);
3358         if (!ifq_is_empty(&ifp->if_snd))
3359                 if_devstart(ifp);
3360 }
3361
3362 static void
3363 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3364 {
3365         uint32_t eitr = 0;
3366
3367         if (rate > 0) {
3368                 if (sc->hw.mac.type == e1000_82575) {
3369                         eitr = 1000000000 / 256 / rate;
3370                         /*
3371                          * NOTE:
3372                          * Document is wrong on the 2 bits left shift
3373                          */
3374                 } else {
3375                         eitr = 1000000 / rate;
3376                         eitr <<= IGB_EITR_INTVL_SHIFT;
3377                 }
3378
3379                 if (eitr == 0) {
3380                         /* Don't disable it */
3381                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3382                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3383                         /* Don't allow it to be too large */
3384                         eitr = IGB_EITR_INTVL_MASK;
3385                 }
3386         }
3387         if (sc->hw.mac.type == e1000_82575)
3388                 eitr |= eitr << 16;
3389         else
3390                 eitr |= E1000_EITR_CNT_IGNR;
3391         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3392 }
3393
3394 static int
3395 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3396 {
3397         struct igb_softc *sc = (void *)arg1;
3398         struct ifnet *ifp = &sc->arpcom.ac_if;
3399         int error, intr_rate;
3400
3401         intr_rate = sc->intr_rate;
3402         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3403         if (error || req->newptr == NULL)
3404                 return error;
3405         if (intr_rate < 0)
3406                 return EINVAL;
3407
3408         ifnet_serialize_all(ifp);
3409
3410         sc->intr_rate = intr_rate;
3411         if (ifp->if_flags & IFF_RUNNING)
3412                 igb_set_eitr(sc, 0, sc->intr_rate);
3413
3414         if (bootverbose)
3415                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3416
3417         ifnet_deserialize_all(ifp);
3418
3419         return 0;
3420 }
3421
3422 static int
3423 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3424 {
3425         struct igb_msix_data *msix = (void *)arg1;
3426         struct igb_softc *sc = msix->msix_sc;
3427         struct ifnet *ifp = &sc->arpcom.ac_if;
3428         int error, msix_rate;
3429
3430         msix_rate = msix->msix_rate;
3431         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3432         if (error || req->newptr == NULL)
3433                 return error;
3434         if (msix_rate < 0)
3435                 return EINVAL;
3436
3437         lwkt_serialize_enter(msix->msix_serialize);
3438
3439         msix->msix_rate = msix_rate;
3440         if (ifp->if_flags & IFF_RUNNING)
3441                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3442
3443         if (bootverbose) {
3444                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3445                     msix->msix_rate);
3446         }
3447
3448         lwkt_serialize_exit(msix->msix_serialize);
3449
3450         return 0;
3451 }
3452
3453 static int
3454 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3455 {
3456         struct igb_softc *sc = (void *)arg1;
3457         struct ifnet *ifp = &sc->arpcom.ac_if;
3458         struct igb_tx_ring *txr = &sc->tx_rings[0];
3459         int error, nsegs;
3460
3461         nsegs = txr->intr_nsegs;
3462         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3463         if (error || req->newptr == NULL)
3464                 return error;
3465         if (nsegs <= 0)
3466                 return EINVAL;
3467
3468         ifnet_serialize_all(ifp);
3469
3470         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3471             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3472                 error = EINVAL;
3473         } else {
3474                 error = 0;
3475                 txr->intr_nsegs = nsegs;
3476         }
3477
3478         ifnet_deserialize_all(ifp);
3479
3480         return error;
3481 }
3482
3483 #ifdef IFPOLL_ENABLE
3484
3485 static int
3486 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3487 {
3488         struct igb_softc *sc = (void *)arg1;
3489         struct ifnet *ifp = &sc->arpcom.ac_if;
3490         int error, off;
3491
3492         off = sc->rx_npoll_off;
3493         error = sysctl_handle_int(oidp, &off, 0, req);
3494         if (error || req->newptr == NULL)
3495                 return error;
3496         if (off < 0)
3497                 return EINVAL;
3498
3499         ifnet_serialize_all(ifp);
3500         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3501                 error = EINVAL;
3502         } else {
3503                 error = 0;
3504                 sc->rx_npoll_off = off;
3505         }
3506         ifnet_deserialize_all(ifp);
3507
3508         return error;
3509 }
3510
3511 static int
3512 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3513 {
3514         struct igb_softc *sc = (void *)arg1;
3515         struct ifnet *ifp = &sc->arpcom.ac_if;
3516         int error, off;
3517
3518         off = sc->tx_npoll_off;
3519         error = sysctl_handle_int(oidp, &off, 0, req);
3520         if (error || req->newptr == NULL)
3521                 return error;
3522         if (off < 0)
3523                 return EINVAL;
3524
3525         ifnet_serialize_all(ifp);
3526         if (off >= ncpus2) {
3527                 error = EINVAL;
3528         } else {
3529                 error = 0;
3530                 sc->tx_npoll_off = off;
3531         }
3532         ifnet_deserialize_all(ifp);
3533
3534         return error;
3535 }
3536
3537 #endif  /* IFPOLL_ENABLE */
3538
3539 static void
3540 igb_init_intr(struct igb_softc *sc)
3541 {
3542         igb_set_intr_mask(sc);
3543
3544         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3545                 igb_init_unshared_intr(sc);
3546
3547         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3548                 igb_set_eitr(sc, 0, sc->intr_rate);
3549         } else {
3550                 int i;
3551
3552                 for (i = 0; i < sc->msix_cnt; ++i)
3553                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3554         }
3555 }
3556
3557 static void
3558 igb_init_unshared_intr(struct igb_softc *sc)
3559 {
3560         struct e1000_hw *hw = &sc->hw;
3561         const struct igb_rx_ring *rxr;
3562         const struct igb_tx_ring *txr;
3563         uint32_t ivar, index;
3564         int i;
3565
3566         /*
3567          * Enable extended mode
3568          */
3569         if (sc->hw.mac.type != e1000_82575) {
3570                 uint32_t gpie;
3571                 int ivar_max;
3572
3573                 gpie = E1000_GPIE_NSICR;
3574                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3575                         gpie |= E1000_GPIE_MSIX_MODE |
3576                             E1000_GPIE_EIAME |
3577                             E1000_GPIE_PBA;
3578                 }
3579                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3580
3581                 /*
3582                  * Clear IVARs
3583                  */
3584                 switch (sc->hw.mac.type) {
3585                 case e1000_82580:
3586                         ivar_max = IGB_MAX_IVAR_82580;
3587                         break;
3588
3589                 case e1000_i350:
3590                         ivar_max = IGB_MAX_IVAR_I350;
3591                         break;
3592
3593                 case e1000_vfadapt:
3594                 case e1000_vfadapt_i350:
3595                         ivar_max = IGB_MAX_IVAR_VF;
3596                         break;
3597
3598                 case e1000_82576:
3599                         ivar_max = IGB_MAX_IVAR_82576;
3600                         break;
3601
3602                 default:
3603                         panic("unknown mac type %d\n", sc->hw.mac.type);
3604                 }
3605                 for (i = 0; i < ivar_max; ++i)
3606                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3607                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3608         } else {
3609                 uint32_t tmp;
3610
3611                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3612                     ("82575 w/ MSI-X"));
3613                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3614                 tmp |= E1000_CTRL_EXT_IRCA;
3615                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3616         }
3617
3618         /*
3619          * Map TX/RX interrupts to EICR
3620          */
3621         switch (sc->hw.mac.type) {
3622         case e1000_82580:
3623         case e1000_i350:
3624         case e1000_vfadapt:
3625         case e1000_vfadapt_i350:
3626                 /* RX entries */
3627                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3628                         rxr = &sc->rx_rings[i];
3629
3630                         index = i >> 1;
3631                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3632
3633                         if (i & 1) {
3634                                 ivar &= 0xff00ffff;
3635                                 ivar |=
3636                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3637                         } else {
3638                                 ivar &= 0xffffff00;
3639                                 ivar |=
3640                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3641                         }
3642                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3643                 }
3644                 /* TX entries */
3645                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3646                         txr = &sc->tx_rings[i];
3647
3648                         index = i >> 1;
3649                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3650
3651                         if (i & 1) {
3652                                 ivar &= 0x00ffffff;
3653                                 ivar |=
3654                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3655                         } else {
3656                                 ivar &= 0xffff00ff;
3657                                 ivar |=
3658                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3659                         }
3660                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3661                 }
3662                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3663                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3664                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3665                 }
3666                 break;
3667
3668         case e1000_82576:
3669                 /* RX entries */
3670                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3671                         rxr = &sc->rx_rings[i];
3672
3673                         index = i & 0x7; /* Each IVAR has two entries */
3674                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3675
3676                         if (i < 8) {
3677                                 ivar &= 0xffffff00;
3678                                 ivar |=
3679                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3680                         } else {
3681                                 ivar &= 0xff00ffff;
3682                                 ivar |=
3683                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3684                         }
3685                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3686                 }
3687                 /* TX entries */
3688                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3689                         txr = &sc->tx_rings[i];
3690
3691                         index = i & 0x7; /* Each IVAR has two entries */
3692                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3693
3694                         if (i < 8) {
3695                                 ivar &= 0xffff00ff;
3696                                 ivar |=
3697                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3698                         } else {
3699                                 ivar &= 0x00ffffff;
3700                                 ivar |=
3701                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3702                         }
3703                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3704                 }
3705                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3706                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3707                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3708                 }
3709                 break;
3710
3711         case e1000_82575:
3712                 /*
3713                  * Enable necessary interrupt bits.
3714                  *
3715                  * The name of the register is confusing; in addition to
3716                  * configuring the first vector of MSI-X, it also configures
3717                  * which bits of EICR could be set by the hardware even when
3718                  * MSI or line interrupt is used; it thus controls interrupt
3719                  * generation.  It MUST be configured explicitly; the default
3720                  * value mentioned in the datasheet is wrong: RX queue0 and
3721                  * TX queue0 are NOT enabled by default.
3722                  */
3723                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3724                 break;
3725
3726         default:
3727                 panic("unknown mac type %d\n", sc->hw.mac.type);
3728         }
3729 }
3730
3731 static int
3732 igb_setup_intr(struct igb_softc *sc)
3733 {
3734         struct ifnet *ifp = &sc->arpcom.ac_if;
3735         int error;
3736
3737         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3738                 return igb_msix_setup(sc);
3739
3740         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3741             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3742             sc, &sc->intr_tag, &sc->main_serialize);
3743         if (error) {
3744                 device_printf(sc->dev, "Failed to register interrupt handler");
3745                 return error;
3746         }
3747
3748         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3749         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3750
3751         return 0;
3752 }
3753
3754 static void
3755 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3756 {
3757         if (txr->sc->hw.mac.type == e1000_82575) {
3758                 txr->tx_intr_bit = 0;   /* unused */
3759                 switch (txr->me) {
3760                 case 0:
3761                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3762                         break;
3763                 case 1:
3764                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3765                         break;
3766                 case 2:
3767                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3768                         break;
3769                 case 3:
3770                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3771                         break;
3772                 default:
3773                         panic("unsupported # of TX ring, %d\n", txr->me);
3774                 }
3775         } else {
3776                 int intr_bit = *intr_bit0;
3777
3778                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3779                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3780
3781                 *intr_bit0 = intr_bit + 1;
3782         }
3783 }
3784
3785 static void
3786 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3787 {
3788         if (rxr->sc->hw.mac.type == e1000_82575) {
3789                 rxr->rx_intr_bit = 0;   /* unused */
3790                 switch (rxr->me) {
3791                 case 0:
3792                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3793                         break;
3794                 case 1:
3795                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3796                         break;
3797                 case 2:
3798                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3799                         break;
3800                 case 3:
3801                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3802                         break;
3803                 default:
3804                         panic("unsupported # of RX ring, %d\n", rxr->me);
3805                 }
3806         } else {
3807                 int intr_bit = *intr_bit0;
3808
3809                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3810                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3811
3812                 *intr_bit0 = intr_bit + 1;
3813         }
3814 }
3815
3816 static void
3817 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3818 {
3819         struct igb_softc *sc = ifp->if_softc;
3820
3821         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3822             sc->tx_serialize, sc->rx_serialize, slz);
3823 }
3824
3825 static void
3826 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3827 {
3828         struct igb_softc *sc = ifp->if_softc;
3829
3830         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3831             sc->tx_serialize, sc->rx_serialize, slz);
3832 }
3833
3834 static int
3835 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3836 {
3837         struct igb_softc *sc = ifp->if_softc;
3838
3839         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3840             sc->tx_serialize, sc->rx_serialize, slz);
3841 }
3842
3843 #ifdef INVARIANTS
3844
3845 static void
3846 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3847     boolean_t serialized)
3848 {
3849         struct igb_softc *sc = ifp->if_softc;
3850
3851         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3852             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3853 }
3854
3855 #endif  /* INVARIANTS */
3856
3857 static void
3858 igb_set_intr_mask(struct igb_softc *sc)
3859 {
3860         int i;
3861
3862         sc->intr_mask = sc->sts_intr_mask;
3863         for (i = 0; i < sc->rx_ring_inuse; ++i)
3864                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3865         for (i = 0; i < sc->tx_ring_cnt; ++i)
3866                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3867         if (bootverbose) {
3868                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3869                     sc->intr_mask);
3870         }
3871 }
3872
3873 static int
3874 igb_alloc_intr(struct igb_softc *sc)
3875 {
3876         int i, intr_bit, intr_bitmax;
3877         u_int intr_flags;
3878
3879         igb_msix_try_alloc(sc);
3880         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3881                 goto done;
3882
3883         /*
3884          * Allocate MSI/legacy interrupt resource
3885          */
3886         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3887             &sc->intr_rid, &intr_flags);
3888
3889         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3890                 int unshared;
3891
3892                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3893                 if (!unshared) {
3894                         sc->flags |= IGB_FLAG_SHARED_INTR;
3895                         if (bootverbose)
3896                                 device_printf(sc->dev, "IRQ shared\n");
3897                 } else {
3898                         intr_flags &= ~RF_SHAREABLE;
3899                         if (bootverbose)
3900                                 device_printf(sc->dev, "IRQ unshared\n");
3901                 }
3902         }
3903
3904         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3905             &sc->intr_rid, intr_flags);
3906         if (sc->intr_res == NULL) {
3907                 device_printf(sc->dev, "Unable to allocate bus resource: "
3908                     "interrupt\n");
3909                 return ENXIO;
3910         }
3911
3912         /*
3913          * Setup MSI/legacy interrupt mask
3914          */
3915         switch (sc->hw.mac.type) {
3916         case e1000_82575:
3917                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3918                 break;
3919         case e1000_82580:
3920                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3921                 break;
3922         case e1000_i350:
3923                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3924                 break;
3925         case e1000_82576:
3926                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3927                 break;
3928         default:
3929                 intr_bitmax = IGB_MIN_TXRXINT;
3930                 break;
3931         }
3932         intr_bit = 0;
3933         for (i = 0; i < sc->tx_ring_cnt; ++i)
3934                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3935         for (i = 0; i < sc->rx_ring_cnt; ++i)
3936                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3937         sc->sts_intr_bit = 0;
3938         sc->sts_intr_mask = E1000_EICR_OTHER;
3939
3940         /* Initialize interrupt rate */
3941         sc->intr_rate = IGB_INTR_RATE;
3942 done:
3943         igb_set_ring_inuse(sc, FALSE);
3944         igb_set_intr_mask(sc);
3945         return 0;
3946 }
3947
3948 static void
3949 igb_free_intr(struct igb_softc *sc)
3950 {
3951         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3952                 if (sc->intr_res != NULL) {
3953                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3954                             sc->intr_res);
3955                 }
3956                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3957                         pci_release_msi(sc->dev);
3958         } else {
3959                 igb_msix_free(sc, TRUE);
3960         }
3961 }
3962
3963 static void
3964 igb_teardown_intr(struct igb_softc *sc)
3965 {
3966         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3967                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3968         else
3969                 igb_msix_teardown(sc, sc->msix_cnt);
3970 }
3971
3972 static void
3973 igb_msix_try_alloc(struct igb_softc *sc)
3974 {
3975         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3976         int i, x, error;
3977         struct igb_msix_data *msix;
3978         boolean_t aggregate, setup = FALSE;
3979
3980         /*
3981          * Don't enable MSI-X on 82575, see:
3982          * 82575 specification update errata #25
3983          */
3984         if (sc->hw.mac.type == e1000_82575)
3985                 return;
3986
3987         /* Don't enable MSI-X on VF */
3988         if (sc->vf_ifp)
3989                 return;
3990
3991         msix_enable = device_getenv_int(sc->dev, "msix.enable",
3992             igb_msix_enable);
3993         if (!msix_enable)
3994                 return;
3995
3996         msix_cnt = pci_msix_count(sc->dev);
3997 #ifdef IGB_MSIX_DEBUG
3998         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3999 #endif
4000         if (msix_cnt <= 1) {
4001                 /* One MSI-X model does not make sense */
4002                 return;
4003         }
4004
4005         i = 0;
4006         while ((1 << (i + 1)) <= msix_cnt)
4007                 ++i;
4008         msix_cnt2 = 1 << i;
4009
4010         if (bootverbose) {
4011                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4012                     msix_cnt2, msix_cnt);
4013         }
4014
4015         KKASSERT(msix_cnt2 <= msix_cnt);
4016         if (msix_cnt == msix_cnt2) {
4017                 /* We need at least one MSI-X for link status */
4018                 msix_cnt2 >>= 1;
4019                 if (msix_cnt2 <= 1) {
4020                         /* One MSI-X for RX/TX does not make sense */
4021                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4022                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4023                         return;
4024                 }
4025                 KKASSERT(msix_cnt > msix_cnt2);
4026
4027                 if (bootverbose) {
4028                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4029                             msix_cnt2, msix_cnt);
4030                 }
4031         }
4032
4033         sc->rx_ring_msix = sc->rx_ring_cnt;
4034         if (sc->rx_ring_msix > msix_cnt2)
4035                 sc->rx_ring_msix = msix_cnt2;
4036
4037         if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
4038                 /*
4039                  * Independent TX/RX MSI-X
4040                  */
4041                 aggregate = FALSE;
4042                 if (bootverbose)
4043                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4044                 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
4045         } else {
4046                 /*
4047                  * Aggregate TX/RX MSI-X
4048                  */
4049                 aggregate = TRUE;
4050                 if (bootverbose)
4051                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4052                 alloc_cnt = msix_cnt2;
4053                 if (alloc_cnt > ncpus2)
4054                         alloc_cnt = ncpus2;
4055                 if (sc->rx_ring_msix > alloc_cnt)
4056                         sc->rx_ring_msix = alloc_cnt;
4057         }
4058         ++alloc_cnt;    /* For link status */
4059
4060         if (bootverbose) {
4061                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4062                     alloc_cnt, sc->rx_ring_msix);
4063         }
4064
4065         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4066         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4067             &sc->msix_mem_rid, RF_ACTIVE);
4068         if (sc->msix_mem_res == NULL) {
4069                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4070                 return;
4071         }
4072
4073         sc->msix_cnt = alloc_cnt;
4074         sc->msix_data = kmalloc_cachealign(
4075             sizeof(struct igb_msix_data) * sc->msix_cnt,
4076             M_DEVBUF, M_WAITOK | M_ZERO);
4077         for (x = 0; x < sc->msix_cnt; ++x) {
4078                 msix = &sc->msix_data[x];
4079
4080                 lwkt_serialize_init(&msix->msix_serialize0);
4081                 msix->msix_sc = sc;
4082                 msix->msix_rid = -1;
4083                 msix->msix_vector = x;
4084                 msix->msix_mask = 1 << msix->msix_vector;
4085                 msix->msix_rate = IGB_INTR_RATE;
4086         }
4087
4088         x = 0;
4089         if (!aggregate) {
4090                 int offset, offset_def;
4091
4092                 if (sc->rx_ring_msix == ncpus2) {
4093                         offset = 0;
4094                 } else {
4095                         offset_def = (sc->rx_ring_msix *
4096                             device_get_unit(sc->dev)) % ncpus2;
4097
4098                         offset = device_getenv_int(sc->dev,
4099                             "msix.rxoff", offset_def);
4100                         if (offset >= ncpus2 ||
4101                             offset % sc->rx_ring_msix != 0) {
4102                                 device_printf(sc->dev,
4103                                     "invalid msix.rxoff %d, use %d\n",
4104                                     offset, offset_def);
4105                                 offset = offset_def;
4106                         }
4107                 }
4108
4109                 /* RX rings */
4110                 for (i = 0; i < sc->rx_ring_msix; ++i) {
4111                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4112
4113                         KKASSERT(x < sc->msix_cnt);
4114                         msix = &sc->msix_data[x++];
4115                         rxr->rx_intr_bit = msix->msix_vector;
4116                         rxr->rx_intr_mask = msix->msix_mask;
4117
4118                         msix->msix_serialize = &rxr->rx_serialize;
4119                         msix->msix_func = igb_msix_rx;
4120                         msix->msix_arg = rxr;
4121                         msix->msix_cpuid = i + offset;
4122                         KKASSERT(msix->msix_cpuid < ncpus2);
4123                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4124                             "%s rx%d", device_get_nameunit(sc->dev), i);
4125                         msix->msix_rate = IGB_MSIX_RX_RATE;
4126                         ksnprintf(msix->msix_rate_desc,
4127                             sizeof(msix->msix_rate_desc),
4128                             "RX%d interrupt rate", i);
4129                 }
4130
4131                 offset_def = device_get_unit(sc->dev) % ncpus2;
4132                 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4133                 if (offset >= ncpus2) {
4134                         device_printf(sc->dev, "invalid msix.txoff %d, "
4135                             "use %d\n", offset, offset_def);
4136                         offset = offset_def;
4137                 }
4138
4139                 /* TX rings */
4140                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4141                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4142
4143                         KKASSERT(x < sc->msix_cnt);
4144                         msix = &sc->msix_data[x++];
4145                         txr->tx_intr_bit = msix->msix_vector;
4146                         txr->tx_intr_mask = msix->msix_mask;
4147
4148                         msix->msix_serialize = &txr->tx_serialize;
4149                         msix->msix_func = igb_msix_tx;
4150                         msix->msix_arg = txr;
4151                         msix->msix_cpuid = i + offset;
4152                         sc->msix_tx_cpuid = msix->msix_cpuid; /* XXX */
4153                         KKASSERT(msix->msix_cpuid < ncpus2);
4154                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4155                             "%s tx%d", device_get_nameunit(sc->dev), i);
4156                         msix->msix_rate = IGB_MSIX_TX_RATE;
4157                         ksnprintf(msix->msix_rate_desc,
4158                             sizeof(msix->msix_rate_desc),
4159                             "TX%d interrupt rate", i);
4160                 }
4161         } else {
4162                 /* TODO */
4163                 error = EOPNOTSUPP;
4164                 goto back;
4165         }
4166
4167         /*
4168          * Link status
4169          */
4170         KKASSERT(x < sc->msix_cnt);
4171         msix = &sc->msix_data[x++];
4172         sc->sts_intr_bit = msix->msix_vector;
4173         sc->sts_intr_mask = msix->msix_mask;
4174
4175         msix->msix_serialize = &sc->main_serialize;
4176         msix->msix_func = igb_msix_status;
4177         msix->msix_arg = sc;
4178         msix->msix_cpuid = 0; /* TODO tunable */
4179         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4180             device_get_nameunit(sc->dev));
4181         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4182             "status interrupt rate");
4183
4184         KKASSERT(x == sc->msix_cnt);
4185
4186         error = pci_setup_msix(sc->dev);
4187         if (error) {
4188                 device_printf(sc->dev, "Setup MSI-X failed\n");
4189                 goto back;
4190         }
4191         setup = TRUE;
4192
4193         for (i = 0; i < sc->msix_cnt; ++i) {
4194                 msix = &sc->msix_data[i];
4195
4196                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4197                     &msix->msix_rid, msix->msix_cpuid);
4198                 if (error) {
4199                         device_printf(sc->dev,
4200                             "Unable to allocate MSI-X %d on cpu%d\n",
4201                             msix->msix_vector, msix->msix_cpuid);
4202                         goto back;
4203                 }
4204
4205                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4206                     &msix->msix_rid, RF_ACTIVE);
4207                 if (msix->msix_res == NULL) {
4208                         device_printf(sc->dev,
4209                             "Unable to allocate MSI-X %d resource\n",
4210                             msix->msix_vector);
4211                         error = ENOMEM;
4212                         goto back;
4213                 }
4214         }
4215
4216         pci_enable_msix(sc->dev);
4217         sc->intr_type = PCI_INTR_TYPE_MSIX;
4218 back:
4219         if (error)
4220                 igb_msix_free(sc, setup);
4221 }
4222
4223 static void
4224 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4225 {
4226         int i;
4227
4228         KKASSERT(sc->msix_cnt > 1);
4229
4230         for (i = 0; i < sc->msix_cnt; ++i) {
4231                 struct igb_msix_data *msix = &sc->msix_data[i];
4232
4233                 if (msix->msix_res != NULL) {
4234                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4235                             msix->msix_rid, msix->msix_res);
4236                 }
4237                 if (msix->msix_rid >= 0)
4238                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4239         }
4240         if (setup)
4241                 pci_teardown_msix(sc->dev);
4242
4243         sc->msix_cnt = 0;
4244         kfree(sc->msix_data, M_DEVBUF);
4245         sc->msix_data = NULL;
4246 }
4247
4248 static int
4249 igb_msix_setup(struct igb_softc *sc)
4250 {
4251         struct ifnet *ifp = &sc->arpcom.ac_if;
4252         int i;
4253
4254         for (i = 0; i < sc->msix_cnt; ++i) {
4255                 struct igb_msix_data *msix = &sc->msix_data[i];
4256                 int error;
4257
4258                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4259                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4260                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4261                 if (error) {
4262                         device_printf(sc->dev, "could not set up %s "
4263                             "interrupt handler.\n", msix->msix_desc);
4264                         igb_msix_teardown(sc, i);
4265                         return error;
4266                 }
4267         }
4268         ifp->if_cpuid = sc->msix_tx_cpuid;
4269
4270         return 0;
4271 }
4272
4273 static void
4274 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4275 {
4276         int i;
4277
4278         for (i = 0; i < msix_cnt; ++i) {
4279                 struct igb_msix_data *msix = &sc->msix_data[i];
4280
4281                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4282         }
4283 }
4284
4285 static void
4286 igb_msix_rx(void *arg)
4287 {
4288         struct igb_rx_ring *rxr = arg;
4289
4290         ASSERT_SERIALIZED(&rxr->rx_serialize);
4291         igb_rxeof(rxr, -1);
4292
4293         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4294 }
4295
4296 static void
4297 igb_msix_tx(void *arg)
4298 {
4299         struct igb_tx_ring *txr = arg;
4300         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
4301
4302         ASSERT_SERIALIZED(&txr->tx_serialize);
4303
4304         igb_txeof(txr);
4305         if (!ifq_is_empty(&ifp->if_snd))
4306                 if_devstart(ifp);
4307
4308         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4309 }
4310
4311 static void
4312 igb_msix_status(void *arg)
4313 {
4314         struct igb_softc *sc = arg;
4315         uint32_t icr;
4316
4317         ASSERT_SERIALIZED(&sc->main_serialize);
4318
4319         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4320         if (icr & E1000_ICR_LSC) {
4321                 sc->hw.mac.get_link_status = 1;
4322                 igb_update_link_status(sc);
4323         }
4324
4325         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4326 }
4327
4328 static void
4329 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4330 {
4331         if (!IGB_ENABLE_HWRSS(sc))
4332                 return;
4333
4334         if (polling)
4335                 sc->rx_ring_inuse = sc->rx_ring_cnt;
4336         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4337                 sc->rx_ring_inuse = IGB_MIN_RING_RSS;
4338         else
4339                 sc->rx_ring_inuse = sc->rx_ring_msix;
4340         if (bootverbose) {
4341                 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d\n",
4342                     sc->rx_ring_inuse, sc->rx_ring_cnt);
4343         }
4344 }
4345
4346 static int
4347 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4348 {
4349         int hoff, iphlen, thoff;
4350         struct mbuf *m;
4351
4352         m = *mp;
4353         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4354
4355         iphlen = m->m_pkthdr.csum_iphlen;
4356         thoff = m->m_pkthdr.csum_thlen;
4357         hoff = m->m_pkthdr.csum_lhlen;
4358
4359         KASSERT(iphlen > 0, ("invalid ip hlen"));
4360         KASSERT(thoff > 0, ("invalid tcp hlen"));
4361         KASSERT(hoff > 0, ("invalid ether hlen"));
4362
4363         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4364                 m = m_pullup(m, hoff + iphlen + thoff);
4365                 if (m == NULL) {
4366                         *mp = NULL;
4367                         return ENOBUFS;
4368                 }
4369                 *mp = m;
4370         }
4371         if (txr->sc->flags & IGB_FLAG_TSO_IPLEN0) {
4372                 struct ip *ip;
4373
4374                 ip = mtodoff(m, struct ip *, hoff);
4375                 ip->ip_len = 0;
4376         }
4377
4378         return 0;
4379 }
4380
4381 static void
4382 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4383 {
4384         struct e1000_adv_tx_context_desc *TXD;
4385         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4386         int hoff, ctxd, iphlen, thoff;
4387
4388         iphlen = m->m_pkthdr.csum_iphlen;
4389         thoff = m->m_pkthdr.csum_thlen;
4390         hoff = m->m_pkthdr.csum_lhlen;
4391
4392         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4393
4394         ctxd = txr->next_avail_desc;
4395         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4396
4397         if (m->m_flags & M_VLANTAG) {
4398                 uint16_t vlantag;
4399
4400                 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4401                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4402         }
4403
4404         vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4405         vlan_macip_lens |= iphlen;
4406
4407         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4408         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4409         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4410
4411         mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4412         mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4413         /* 82575 needs the queue index added */
4414         if (txr->sc->hw.mac.type == e1000_82575)
4415                 mss_l4len_idx |= txr->me << 4;
4416
4417         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4418         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4419         TXD->seqnum_seed = htole32(0);
4420         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4421
4422         /* We've consumed the first desc, adjust counters */
4423         if (++ctxd == txr->num_tx_desc)
4424                 ctxd = 0;
4425         txr->next_avail_desc = ctxd;
4426         --txr->tx_avail;
4427
4428         *hlen = hoff + iphlen + thoff;
4429 }