2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
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6 * modification, are permitted provided that the following conditions
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16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
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36 * $FreeBSD: src/sys/dev/ath/ah_osdep.h,v 1.1 2006/09/18 16:49:14 sam Exp $
37 * $DragonFly: src/sys/dev/netif/ath/hal/ah_osdep.h,v 1.1 2007/02/22 05:17:09 sephe Exp $
39 #ifndef _ATH_AH_OSDEP_H_
40 #define _ATH_AH_OSDEP_H_
42 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/endian.h>
49 * Delay n microseconds.
51 extern void ath_hal_delay(int);
52 #define OS_DELAY(_n) ath_hal_delay(_n)
54 #define OS_INLINE __inline
55 #define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
56 extern void ath_hal_memzero(void *, size_t);
57 #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
58 extern void *ath_hal_memcpy(void *, const void *, size_t);
60 #define abs(_a) __builtin_abs(_a)
63 extern u_int32_t ath_hal_getuptime(struct ath_hal *);
64 #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
67 * Register read/write operations are either handled through
68 * platform-dependent routines (or when debugging is enabled
69 * with AH_DEBUG); or they are inline expanded using the macros
70 * defined below. For public builds we inline expand only for
71 * platforms where it is certain what the requirements are to
72 * read/write registers--typically they are memory-mapped and
73 * no explicit synchronization or memory invalidation operations
74 * are required (e.g. i386).
76 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
77 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
78 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
80 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
81 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
84 * The hardware registers are native little-endian byte order.
85 * Big-endian hosts are handled by enabling hardware byte-swap
86 * of register reads and writes at reset. But the PCI clock
87 * domain registers are not byte swapped! Thus, on big-endian
88 * platforms we have to explicitly byte-swap those registers.
89 * Most of this code is collapsed at compile time because the
90 * register values are constants.
92 #define AH_LITTLE_ENDIAN 1234
93 #define AH_BIG_ENDIAN 4321
95 #if _BYTE_ORDER == _BIG_ENDIAN
96 #define OS_REG_WRITE(_ah, _reg, _val) do { \
97 if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
98 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
99 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
101 bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \
102 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
104 #define OS_REG_READ(_ah, _reg) \
105 (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
106 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
107 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \
108 bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \
109 (bus_space_handle_t)(_ah)->ah_sh, (_reg)))
110 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */
111 #define OS_REG_WRITE(_ah, _reg, _val) \
112 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
113 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
114 #define OS_REG_READ(_ah, _reg) \
115 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
116 (bus_space_handle_t)(_ah)->ah_sh, (_reg))
117 #endif /* _BYTE_ORDER */
118 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
121 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
123 #define OS_MARK(_ah, _id, _v)
126 #endif /* _ATH_AH_OSDEP_H_ */