2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
27 #ifdef HAVE_KERNEL_OPTION_HEADERS
31 #include <dev/sound/pcm/sound.h>
32 #include <dev/sound/pcm/ac97.h>
33 #include <dev/sound/pci/t4dwave.h>
35 #include <bus/pci/pcireg.h>
36 #include <bus/pci/pcivar.h>
38 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/t4dwave.c 254263 2013-08-12 23:30:01Z scottl $");
40 /* -------------------------------------------------------------------- */
42 #define TDX_PCI_ID 0x20001023
43 #define TNX_PCI_ID 0x20011023
44 #define ALI_PCI_ID 0x545110b9
45 #define SPA_PCI_ID 0x70181039
47 #define TR_DEFAULT_BUFSZ 0x1000
48 /* For ALi M5451 the DMA transfer size appears to be fixed to 64k. */
49 #define ALI_BUFSZ 0x10000
50 #define TR_BUFALGN 0x8
51 #define TR_TIMEOUT_CDC 0xffff
53 #define ALI_MAXHWCH 32
54 #define TR_MAXPLAYCH 4
55 #define ALI_MAXPLAYCH 1
57 * Though, it's not clearly documented in the 4DWAVE datasheet, the
58 * DX and NX chips can't handle DMA addresses located above 1GB as the
59 * LBA (loop begin address) register which holds the DMA base address
60 * is 32-bit, but the two MSBs are used for other purposes.
62 #define TR_MAXADDR ((1U << 30) - 1)
63 #define ALI_MAXADDR ((1U << 31) - 1)
67 /* channel registers */
69 u_int32_t cso, alpha, fms, fmc, ec;
73 u_int32_t gvsel, pan, vol, ctrl;
74 u_int32_t active:1, was_active:1;
76 struct snd_dbuf *buffer;
77 struct pcm_channel *channel;
78 struct tr_info *parent;
83 u_int32_t active:1, was_active:1;
84 struct snd_dbuf *buffer;
85 struct pcm_channel *channel;
86 struct tr_info *parent;
89 /* device private data */
95 bus_space_handle_t sh;
96 bus_dma_tag_t parent_dmat;
98 struct resource *reg, *irq;
99 int regtype, regid, irqid;
108 struct tr_chinfo chinfo[TR_MAXPLAYCH];
109 struct tr_rchinfo recchinfo;
112 /* -------------------------------------------------------------------- */
114 static u_int32_t tr_recfmt[] = {
115 SND_FORMAT(AFMT_U8, 1, 0),
116 SND_FORMAT(AFMT_U8, 2, 0),
117 SND_FORMAT(AFMT_S8, 1, 0),
118 SND_FORMAT(AFMT_S8, 2, 0),
119 SND_FORMAT(AFMT_S16_LE, 1, 0),
120 SND_FORMAT(AFMT_S16_LE, 2, 0),
121 SND_FORMAT(AFMT_U16_LE, 1, 0),
122 SND_FORMAT(AFMT_U16_LE, 2, 0),
125 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0};
127 static u_int32_t tr_playfmt[] = {
128 SND_FORMAT(AFMT_U8, 1, 0),
129 SND_FORMAT(AFMT_U8, 2, 0),
130 SND_FORMAT(AFMT_S8, 1, 0),
131 SND_FORMAT(AFMT_S8, 2, 0),
132 SND_FORMAT(AFMT_S16_LE, 1, 0),
133 SND_FORMAT(AFMT_S16_LE, 2, 0),
134 SND_FORMAT(AFMT_U16_LE, 1, 0),
135 SND_FORMAT(AFMT_U16_LE, 2, 0),
138 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0};
140 /* -------------------------------------------------------------------- */
145 tr_rd(struct tr_info *tr, int regno, int size)
149 return bus_space_read_1(tr->st, tr->sh, regno);
151 return bus_space_read_2(tr->st, tr->sh, regno);
153 return bus_space_read_4(tr->st, tr->sh, regno);
160 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size)
164 bus_space_write_1(tr->st, tr->sh, regno, data);
167 bus_space_write_2(tr->st, tr->sh, regno, data);
170 bus_space_write_4(tr->st, tr->sh, regno, data);
175 /* -------------------------------------------------------------------- */
179 tr_rdcd(kobj_t obj, void *devinfo, int regno)
181 struct tr_info *tr = (struct tr_info *)devinfo;
186 treg=SPA_REG_CODECRD;
191 treg=TDX_REG_CODECWR;
193 treg=TDX_REG_CODECRD;
197 treg=TDX_REG_CODECRD;
201 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD;
205 kprintf("!!! tr_rdcd defaulted !!!\n");
212 snd_mtxlock(tr->lock);
213 if (tr->type == ALI_PCI_ID) {
214 u_int32_t chk1, chk2;
216 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
217 j = tr_rd(tr, treg, 4);
219 chk1 = tr_rd(tr, 0xc8, 4);
220 chk2 = tr_rd(tr, 0xc8, 4);
221 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
223 chk2 = tr_rd(tr, 0xc8, 4);
226 if (tr->type != ALI_PCI_ID || i > 0) {
227 tr_wr(tr, treg, regno | trw, 4);
229 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
230 j=tr_rd(tr, treg, 4);
232 snd_mtxunlock(tr->lock);
233 if (i == 0) kprintf("codec timeout during read of register %x\n", regno);
234 return (j >> TR_CDC_DATA) & 0xffff;
238 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
240 struct tr_info *tr = (struct tr_info *)devinfo;
245 treg=SPA_REG_CODECWR;
250 treg=TDX_REG_CODECWR;
254 treg=TNX_REG_CODECWR;
255 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0);
258 kprintf("!!! tr_wrcd defaulted !!!");
266 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno));
269 snd_mtxlock(tr->lock);
270 if (tr->type == ALI_PCI_ID) {
272 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
273 j = tr_rd(tr, treg, 4);
275 u_int32_t chk1, chk2;
276 chk1 = tr_rd(tr, 0xc8, 4);
277 chk2 = tr_rd(tr, 0xc8, 4);
278 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
280 chk2 = tr_rd(tr, 0xc8, 4);
283 if (tr->type != ALI_PCI_ID || i > 0) {
284 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--)
285 j=tr_rd(tr, treg, 4);
286 if (tr->type == ALI_PCI_ID && tr->rev > 0x01)
288 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4);
291 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno));
293 snd_mtxunlock(tr->lock);
294 if (i==0) kprintf("codec timeout writing %x, data %x\n", regno, data);
295 return (i > 0)? 0 : -1;
298 static kobj_method_t tr_ac97_methods[] = {
299 KOBJMETHOD(ac97_read, tr_rdcd),
300 KOBJMETHOD(ac97_write, tr_wrcd),
303 AC97_DECLARE(tr_ac97);
305 /* -------------------------------------------------------------------- */
306 /* playback channel interrupts */
310 tr_testint(struct tr_chinfo *ch)
312 struct tr_info *tr = ch->parent;
315 bank = (ch->index & 0x20) ? 1 : 0;
316 chan = ch->index & 0x1f;
317 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan);
322 tr_clrint(struct tr_chinfo *ch)
324 struct tr_info *tr = ch->parent;
327 bank = (ch->index & 0x20) ? 1 : 0;
328 chan = ch->index & 0x1f;
329 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4);
333 tr_enaint(struct tr_chinfo *ch, int enable)
335 struct tr_info *tr = ch->parent;
339 snd_mtxlock(tr->lock);
340 bank = (ch->index & 0x20) ? 1 : 0;
341 chan = ch->index & 0x1f;
342 reg = bank? TR_REG_INTENB : TR_REG_INTENA;
344 i = tr_rd(tr, reg, 4);
346 i |= (enable? 1 : 0) << chan;
349 tr_wr(tr, reg, i, 4);
350 snd_mtxunlock(tr->lock);
353 /* playback channels */
356 tr_selch(struct tr_chinfo *ch)
358 struct tr_info *tr = ch->parent;
361 i = tr_rd(tr, TR_REG_CIR, 4);
363 i |= ch->index & 0x3f;
364 tr_wr(tr, TR_REG_CIR, i, 4);
368 tr_startch(struct tr_chinfo *ch)
370 struct tr_info *tr = ch->parent;
373 bank = (ch->index & 0x20) ? 1 : 0;
374 chan = ch->index & 0x1f;
375 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4);
379 tr_stopch(struct tr_chinfo *ch)
381 struct tr_info *tr = ch->parent;
384 bank = (ch->index & 0x20) ? 1 : 0;
385 chan = ch->index & 0x1f;
386 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4);
390 tr_wrch(struct tr_chinfo *ch)
392 struct tr_info *tr = ch->parent;
393 u_int32_t cr[TR_CHN_REGS], i;
395 ch->gvsel &= 0x00000001;
396 ch->fmc &= 0x00000003;
397 ch->fms &= 0x0000000f;
398 ch->ctrl &= 0x0000000f;
399 ch->pan &= 0x0000007f;
400 ch->rvol &= 0x0000007f;
401 ch->cvol &= 0x0000007f;
402 ch->vol &= 0x000000ff;
403 ch->ec &= 0x00000fff;
404 ch->alpha &= 0x00000fff;
405 ch->delta &= 0x0000ffff;
406 if (tr->type == ALI_PCI_ID)
407 ch->lba &= ALI_MAXADDR;
409 ch->lba &= TR_MAXADDR;
412 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol);
413 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec);
419 ch->cso &= 0x0000ffff;
420 ch->eso &= 0x0000ffff;
421 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms);
422 cr[2]=(ch->eso<<16) | (ch->delta);
425 ch->cso &= 0x00ffffff;
426 ch->eso &= 0x00ffffff;
427 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso);
428 cr[2]=((ch->delta>>8)<<24) | (ch->eso);
429 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14);
432 /* shouldn't occur */
433 cr[0] = 0; /* avoid gcc warnings */
434 cr[2] = 0; /* avoid gcc warnings */
437 snd_mtxlock(tr->lock);
439 for (i=0; i<TR_CHN_REGS; i++)
440 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4);
441 snd_mtxunlock(tr->lock);
445 tr_rdch(struct tr_chinfo *ch)
447 struct tr_info *tr = ch->parent;
450 snd_mtxlock(tr->lock);
453 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4);
454 snd_mtxunlock(tr->lock);
457 if (tr->type == ALI_PCI_ID)
458 ch->lba=(cr[1] & ALI_MAXADDR);
460 ch->lba=(cr[1] & TR_MAXADDR);
461 ch->fmc= (cr[3] & 0x0000c000) >> 14;
462 ch->rvol= (cr[3] & 0x00003f80) >> 7;
463 ch->cvol= (cr[3] & 0x0000007f);
464 ch->gvsel= (cr[4] & 0x80000000) >> 31;
465 ch->pan= (cr[4] & 0x7f000000) >> 24;
466 ch->vol= (cr[4] & 0x00ff0000) >> 16;
467 ch->ctrl= (cr[4] & 0x0000f000) >> 12;
468 ch->ec= (cr[4] & 0x00000fff);
473 ch->cso= (cr[0] & 0xffff0000) >> 16;
474 ch->alpha= (cr[0] & 0x0000fff0) >> 4;
475 ch->fms= (cr[0] & 0x0000000f);
476 ch->eso= (cr[2] & 0xffff0000) >> 16;
477 ch->delta= (cr[2] & 0x0000ffff);
480 ch->cso= (cr[0] & 0x00ffffff);
481 ch->eso= (cr[2] & 0x00ffffff);
482 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24);
483 ch->alpha= (cr[3] & 0xfff00000) >> 20;
484 ch->fms= (cr[3] & 0x000f0000) >> 16;
490 tr_fmttobits(u_int32_t fmt)
495 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0;
496 bits |= (AFMT_CHANNEL(fmt) > 1)? 0x4 : 0;
497 bits |= (fmt & AFMT_16BIT)? 0x8 : 0;
502 /* -------------------------------------------------------------------- */
503 /* channel interface */
506 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
508 struct tr_info *tr = devinfo;
509 struct tr_chinfo *ch;
511 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction"));
512 ch = &tr->chinfo[tr->playchns];
513 ch->index = tr->playchns++;
517 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
524 trpchan_setformat(kobj_t obj, void *data, u_int32_t format)
526 struct tr_chinfo *ch = data;
528 ch->ctrl = tr_fmttobits(format) | 0x01;
534 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
536 struct tr_chinfo *ch = data;
538 ch->delta = (speed << 12) / 48000;
539 return (ch->delta * 48000) >> 12;
543 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
545 struct tr_chinfo *ch = data;
547 sndbuf_resize(ch->buffer, 2, blocksize);
552 trpchan_trigger(kobj_t obj, void *data, int go)
554 struct tr_chinfo *ch = data;
556 if (!PCMTRIG_COMMON(go))
559 if (go == PCMTRIG_START) {
564 ch->lba = sndbuf_getbufaddr(ch->buffer);
566 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getalign(ch->buffer)) - 1;
567 ch->rvol = ch->cvol = 0x7f;
585 trpchan_getptr(kobj_t obj, void *data)
587 struct tr_chinfo *ch = data;
590 return ch->cso * sndbuf_getalign(ch->buffer);
593 static struct pcmchan_caps *
594 trpchan_getcaps(kobj_t obj, void *data)
599 static kobj_method_t trpchan_methods[] = {
600 KOBJMETHOD(channel_init, trpchan_init),
601 KOBJMETHOD(channel_setformat, trpchan_setformat),
602 KOBJMETHOD(channel_setspeed, trpchan_setspeed),
603 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize),
604 KOBJMETHOD(channel_trigger, trpchan_trigger),
605 KOBJMETHOD(channel_getptr, trpchan_getptr),
606 KOBJMETHOD(channel_getcaps, trpchan_getcaps),
609 CHANNEL_DECLARE(trpchan);
611 /* -------------------------------------------------------------------- */
612 /* rec channel interface */
615 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
617 struct tr_info *tr = devinfo;
618 struct tr_rchinfo *ch;
620 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction"));
625 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
632 trrchan_setformat(kobj_t obj, void *data, u_int32_t format)
634 struct tr_rchinfo *ch = data;
635 struct tr_info *tr = ch->parent;
638 bits = tr_fmttobits(format);
639 /* set # of samples between interrupts */
640 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1;
641 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4);
642 /* set sample format */
643 i = 0x18 | (bits << 4);
644 tr_wr(tr, TR_REG_SBCTRL, i, 1);
650 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
652 struct tr_rchinfo *ch = data;
653 struct tr_info *tr = ch->parent;
656 ch->delta = (48000 << 12) / speed;
657 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2);
659 /* return closest possible speed */
660 return (48000 << 12) / ch->delta;
664 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
666 struct tr_rchinfo *ch = data;
668 sndbuf_resize(ch->buffer, 2, blocksize);
674 trrchan_trigger(kobj_t obj, void *data, int go)
676 struct tr_rchinfo *ch = data;
677 struct tr_info *tr = ch->parent;
680 if (!PCMTRIG_COMMON(go))
683 if (go == PCMTRIG_START) {
684 /* set up dma mode regs */
685 tr_wr(tr, TR_REG_DMAR15, 0, 1);
686 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03;
687 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1);
688 /* set up base address */
689 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4);
690 /* set up buffer size */
691 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff;
692 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4);
694 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1);
697 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1);
706 trrchan_getptr(kobj_t obj, void *data)
708 struct tr_rchinfo *ch = data;
709 struct tr_info *tr = ch->parent;
711 /* return current byte offset of channel */
712 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer);
715 static struct pcmchan_caps *
716 trrchan_getcaps(kobj_t obj, void *data)
721 static kobj_method_t trrchan_methods[] = {
722 KOBJMETHOD(channel_init, trrchan_init),
723 KOBJMETHOD(channel_setformat, trrchan_setformat),
724 KOBJMETHOD(channel_setspeed, trrchan_setspeed),
725 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize),
726 KOBJMETHOD(channel_trigger, trrchan_trigger),
727 KOBJMETHOD(channel_getptr, trrchan_getptr),
728 KOBJMETHOD(channel_getcaps, trrchan_getcaps),
731 CHANNEL_DECLARE(trrchan);
733 /* -------------------------------------------------------------------- */
734 /* The interrupt handler */
739 struct tr_info *tr = (struct tr_info *)p;
740 struct tr_chinfo *ch;
741 u_int32_t active, mask, bufhalf, chnum, intsrc;
744 intsrc = tr_rd(tr, TR_REG_MISCINT, 4);
745 if (intsrc & TR_INT_ADDR) {
747 while (chnum < tr->hwchns) {
749 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4);
750 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4);
754 tmp = (bufhalf & mask)? 1 : 0;
755 if (chnum < tr->playchns) {
756 ch = &tr->chinfo[chnum];
757 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */
758 if (ch->bufhalf != tmp) {
759 chn_intr(ch->channel);
766 } while (chnum & 31);
770 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4);
773 if (intsrc & TR_INT_SB) {
774 chn_intr(tr->recchinfo.channel);
775 tr_rd(tr, TR_REG_SBR9, 1);
776 tr_rd(tr, TR_REG_SBR10, 1);
780 /* -------------------------------------------------------------------- */
783 * Probe and attach the card
787 tr_init(struct tr_info *tr)
791 tr_wr(tr, SPA_REG_GPIO, 0, 4);
792 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4);
795 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4);
798 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4);
802 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4);
807 tr_pci_probe(device_t dev)
809 switch (pci_get_devid(dev)) {
811 device_set_desc(dev, "SiS 7018");
812 return BUS_PROBE_DEFAULT;
814 device_set_desc(dev, "Acer Labs M5451");
815 return BUS_PROBE_DEFAULT;
817 device_set_desc(dev, "Trident 4DWave DX");
818 return BUS_PROBE_DEFAULT;
820 device_set_desc(dev, "Trident 4DWave NX");
821 return BUS_PROBE_DEFAULT;
828 tr_pci_attach(device_t dev)
831 struct ac97_info *codec = 0;
834 char status[SND_STATUSLEN];
836 tr = kmalloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO);
837 tr->type = pci_get_devid(dev);
838 tr->rev = pci_get_revid(dev);
839 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc");
841 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
845 else if (i > TR_MAXPLAYCH)
852 dacn = ALI_MAXPLAYCH;
860 pci_enable_busmaster(dev);
862 tr->regid = PCIR_BAR(0);
863 tr->regtype = SYS_RES_IOPORT;
864 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid,
867 tr->st = rman_get_bustag(tr->reg);
868 tr->sh = rman_get_bushandle(tr->reg);
870 device_printf(dev, "unable to map register space\n");
874 if (tr_init(tr) == -1) {
875 device_printf(dev, "unable to initialize the card\n");
880 codec = AC97_CREATE(dev, tr, tr_ac97);
881 if (codec == NULL) goto bad;
882 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
885 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid,
886 RF_ACTIVE | RF_SHAREABLE);
887 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) {
888 device_printf(dev, "unable to map interrupt\n");
892 if (tr->type == ALI_PCI_ID) {
894 * The M5451 generates 31 bit of DMA and in order to do
895 * 32-bit DMA, the 31st bit can be set via its accompanying
896 * ISA bridge. Note that we can't predict whether bus_dma(9)
897 * will actually supply us with a 32-bit buffer and even when
898 * using a low address of BUS_SPACE_MAXADDR_32BIT for both
899 * we might end up with the play buffer being in the 32-bit
900 * range while the record buffer isn't or vice versa. So we
901 * do not enable the 31st bit.
903 lowaddr = ALI_MAXADDR;
904 tr->hwchns = ALI_MAXHWCH;
905 tr->bufsz = ALI_BUFSZ;
907 lowaddr = TR_MAXADDR;
908 tr->hwchns = TR_MAXHWCH;
909 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ,
913 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
914 /*alignment*/TR_BUFALGN,
917 /*highaddr*/BUS_SPACE_MAXADDR,
918 /*filter*/NULL, /*filterarg*/NULL,
919 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/tr->bufsz,
921 &tr->parent_dmat) != 0) {
922 device_printf(dev, "unable to create dma tag\n");
926 ksnprintf(status, 64, "at io 0x%lx irq %ld %s",
927 rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave));
929 if (pcm_register(dev, tr, dacn, 1))
931 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr);
932 for (i = 0; i < dacn; i++)
933 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr);
934 pcm_setstatus(dev, status);
939 if (codec) ac97_destroy(codec);
940 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
941 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih);
942 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
943 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat);
944 if (tr->lock) snd_mtxfree(tr->lock);
950 tr_pci_detach(device_t dev)
955 r = pcm_unregister(dev);
959 tr = pcm_getdevinfo(dev);
960 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
961 bus_teardown_intr(dev, tr->irq, tr->ih);
962 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
963 bus_dma_tag_destroy(tr->parent_dmat);
964 snd_mtxfree(tr->lock);
971 tr_pci_suspend(device_t dev)
976 tr = pcm_getdevinfo(dev);
978 for (i = 0; i < tr->playchns; i++) {
979 tr->chinfo[i].was_active = tr->chinfo[i].active;
980 if (tr->chinfo[i].active) {
981 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP);
985 tr->recchinfo.was_active = tr->recchinfo.active;
986 if (tr->recchinfo.active) {
987 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP);
994 tr_pci_resume(device_t dev)
999 tr = pcm_getdevinfo(dev);
1001 if (tr_init(tr) == -1) {
1002 device_printf(dev, "unable to initialize the card\n");
1006 if (mixer_reinit(dev) == -1) {
1007 device_printf(dev, "unable to initialize the mixer\n");
1011 for (i = 0; i < tr->playchns; i++) {
1012 if (tr->chinfo[i].was_active) {
1013 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START);
1017 if (tr->recchinfo.was_active) {
1018 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START);
1024 static device_method_t tr_methods[] = {
1025 /* Device interface */
1026 DEVMETHOD(device_probe, tr_pci_probe),
1027 DEVMETHOD(device_attach, tr_pci_attach),
1028 DEVMETHOD(device_detach, tr_pci_detach),
1029 DEVMETHOD(device_suspend, tr_pci_suspend),
1030 DEVMETHOD(device_resume, tr_pci_resume),
1034 static driver_t tr_driver = {
1040 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, NULL, NULL);
1041 MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1042 MODULE_VERSION(snd_t4dwave, 1);