sys/dev/netif/re/if_re.c

   1 /*
   2  * Copyright (c) 2004
   3  *      Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
   4  *
   5  * Copyright (c) 1997, 1998-2003
   6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Bill Paul.
  19  * 4. Neither the name of the author nor the names of any co-contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  33  * THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
  36  */
  37
  38 /*
  39  * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Networking Software Engineer
  43  * Wind River Systems
  44  */
  45
  46 /*
  47  * This driver is designed to support RealTek's next generation of
  48  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
  49  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
  50  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
  51  *
  52  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
  53  * with the older 8139 family, however it also supports a special
  54  * C+ mode of operation that provides several new performance enhancing
  55  * features. These include:
  56  *
  57  *      o Descriptor based DMA mechanism. Each descriptor represents
  58  *        a single packet fragment. Data buffers may be aligned on
  59  *        any byte boundary.
  60  *
  61  *      o 64-bit DMA
  62  *
  63  *      o TCP/IP checksum offload for both RX and TX
  64  *
  65  *      o High and normal priority transmit DMA rings
  66  *
  67  *      o VLAN tag insertion and extraction
  68  *
  69  *      o TCP large send (segmentation offload)
  70  *
  71  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
  72  * programming API is fairly straightforward. The RX filtering, EEPROM
  73  * access and PHY access is the same as it is on the older 8139 series
  74  * chips.
  75  *
  76  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
  77  * same programming API and feature set as the 8139C+ with the following
  78  * differences and additions:
  79  *
  80  *      o 1000Mbps mode
  81  *
  82  *      o Jumbo frames
  83  *
  84  *      o GMII and TBI ports/registers for interfacing with copper
  85  *        or fiber PHYs
  86  *
  87  *      o RX and TX DMA rings can have up to 1024 descriptors
  88  *        (the 8139C+ allows a maximum of 64)
  89  *
  90  *      o Slight differences in register layout from the 8139C+
  91  *
  92  * The TX start and timer interrupt registers are at different locations
  93  * on the 8169 than they are on the 8139C+. Also, the status word in the
  94  * RX descriptor has a slightly different bit layout. The 8169 does not
  95  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
  96  * copper gigE PHY.
  97  *
  98  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
  99  * (the 'S' stands for 'single-chip'). These devices have the same
 100  * programming API as the older 8169, but also have some vendor-specific
 101  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
 102  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
 103  *
 104  * This driver takes advantage of the RX and TX checksum offload and
 105  * VLAN tag insertion/extraction features. It also implements TX
 106  * interrupt moderation using the timer interrupt registers, which
 107  * significantly reduces TX interrupt load. There is also support
 108  * for jumbo frames, however the 8169/8169S/8110S can not transmit
 109  * jumbo frames larger than 7440, so the max MTU possible with this
 110  * driver is 7422 bytes.
 111  */
 112
 113 #define _IP_VHL
 114
 115 #include "opt_polling.h"
 116
 117 #include <sys/param.h>
 118 #include <sys/bus.h>
 119 #include <sys/endian.h>
 120 #include <sys/kernel.h>
 121 #include <sys/in_cksum.h>
 122 #include <sys/interrupt.h>
 123 #include <sys/malloc.h>
 124 #include <sys/mbuf.h>
 125 #include <sys/rman.h>
 126 #include <sys/serialize.h>
 127 #include <sys/socket.h>
 128 #include <sys/sockio.h>
 129 #include <sys/sysctl.h>
 130
 131 #include <net/bpf.h>
 132 #include <net/ethernet.h>
 133 #include <net/if.h>
 134 #include <net/ifq_var.h>
 135 #include <net/if_arp.h>
 136 #include <net/if_dl.h>
 137 #include <net/if_media.h>
 138 #include <net/if_types.h>
 139 #include <net/vlan/if_vlan_var.h>
 140 #include <net/vlan/if_vlan_ether.h>
 141
 142 #include <netinet/ip.h>
 143
 144 #include <dev/netif/mii_layer/mii.h>
 145 #include <dev/netif/mii_layer/miivar.h>
 146
 147 #include <bus/pci/pcidevs.h>
 148 #include <bus/pci/pcireg.h>
 149 #include <bus/pci/pcivar.h>
 150
 151 /* "device miibus" required.  See GENERIC if you get errors here. */
 152 #include "miibus_if.h"
 153
 154 #include <dev/netif/re/if_rereg.h>
 155 #include <dev/netif/re/if_revar.h>
 156
 157 #define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
 158
 159 /*
 160  * Various supported device vendors/types and their names.
 161  */
 162 static const struct re_type {
 163         uint16_t        re_vid;
 164         uint16_t        re_did;
 165         const char      *re_name;
 166 } re_devs[] = {
 167         { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
 168           "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
 169
 170         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
 171           "RealTek 8139C+ 10/100BaseTX" },
 172
 173         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
 174           "RealTek 810x PCIe 10/100baseTX" },
 175
 176         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
 177           "RealTek 8111/8168 PCIe Gigabit Ethernet" },
 178
 179         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
 180           "RealTek 8110/8169 Gigabit Ethernet" },
 181
 182         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
 183           "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
 184
 185         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
 186           "Corega CG-LAPCIGT Gigabit Ethernet" },
 187
 188         { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
 189           "Linksys EG1032 Gigabit Ethernet" },
 190
 191         { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
 192           "US Robotics 997902 Gigabit Ethernet" },
 193
 194         { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
 195           "TTTech MC322 Gigabit Ethernet" },
 196
 197         { 0, 0, NULL }
 198 };
 199
 200 static const struct re_hwrev re_hwrevs[] = {
 201         { RE_HWREV_8139CPLUS,   RE_MACVER_UNKN,         ETHERMTU,
 202           RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE },
 203
 204         { RE_HWREV_8169,        RE_MACVER_UNKN,         ETHERMTU,
 205           RE_C_HWCSUM | RE_C_8169 },
 206
 207         { RE_HWREV_8110S,       RE_MACVER_03,           RE_MTU_6K,
 208           RE_C_HWCSUM | RE_C_8169 },
 209
 210         { RE_HWREV_8169S,       RE_MACVER_03,           RE_MTU_6K,
 211           RE_C_HWCSUM | RE_C_8169 },
 212
 213         { RE_HWREV_8169SB,      RE_MACVER_04,           RE_MTU_6K,
 214           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 215
 216         { RE_HWREV_8169SC1,     RE_MACVER_05,           RE_MTU_6K,
 217           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 218
 219         { RE_HWREV_8169SC2,     RE_MACVER_06,           RE_MTU_6K,
 220           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 221
 222         { RE_HWREV_8168B1,      RE_MACVER_21,           RE_MTU_6K,
 223           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
 224
 225         { RE_HWREV_8168B2,      RE_MACVER_23,           RE_MTU_6K,
 226           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
 227
 228         { RE_HWREV_8168B3,      RE_MACVER_23,           RE_MTU_6K,
 229           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
 230
 231         { RE_HWREV_8168C,       RE_MACVER_29,           RE_MTU_6K,
 232           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 233           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 234
 235         { RE_HWREV_8168CP,      RE_MACVER_2B,           RE_MTU_6K,
 236           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 237           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 238
 239         { RE_HWREV_8168D,       RE_MACVER_2A,           RE_MTU_9K,
 240           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 241           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 242
 243         { RE_HWREV_8168DP,      RE_MACVER_2D,           RE_MTU_9K,
 244           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 245           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 246
 247         { RE_HWREV_8168E,       RE_MACVER_UNKN,         RE_MTU_9K,
 248           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 249           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 250
 251         { RE_HWREV_8168F,       RE_MACVER_UNKN,         RE_MTU_9K,
 252           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 253           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 254
 255         { RE_HWREV_8100E,       RE_MACVER_UNKN,         ETHERMTU,
 256           RE_C_HWCSUM | RE_C_FASTE },
 257
 258         { RE_HWREV_8101E1,      RE_MACVER_16,           ETHERMTU,
 259           RE_C_HWCSUM | RE_C_FASTE },
 260
 261         { RE_HWREV_8101E2,      RE_MACVER_16,           ETHERMTU,
 262           RE_C_HWCSUM | RE_C_FASTE },
 263
 264         { RE_HWREV_8102E,       RE_MACVER_15,           ETHERMTU,
 265           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
 266           RE_C_FASTE },
 267
 268         { RE_HWREV_8102EL,      RE_MACVER_15,           ETHERMTU,
 269           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
 270           RE_C_FASTE },
 271
 272         { RE_HWREV_NULL, 0, 0, 0 }
 273 };
 274
 275 static int      re_probe(device_t);
 276 static int      re_attach(device_t);
 277 static int      re_detach(device_t);
 278 static int      re_suspend(device_t);
 279 static int      re_resume(device_t);
 280 static void     re_shutdown(device_t);
 281
 282 static int      re_allocmem(device_t);
 283 static void     re_freemem(device_t);
 284 static void     re_freebufmem(struct re_softc *, int, int);
 285 static int      re_encap(struct re_softc *, struct mbuf **, int *);
 286 static int      re_newbuf_std(struct re_softc *, int, int);
 287 static int      re_newbuf_jumbo(struct re_softc *, int, int);
 288 static void     re_setup_rxdesc(struct re_softc *, int);
 289 static int      re_rx_list_init(struct re_softc *);
 290 static int      re_tx_list_init(struct re_softc *);
 291 static int      re_rxeof(struct re_softc *);
 292 static int      re_txeof(struct re_softc *);
 293 static int      re_tx_collect(struct re_softc *);
 294 static void     re_intr(void *);
 295 static void     re_tick(void *);
 296 static void     re_tick_serialized(void *);
 297
 298 static void     re_start(struct ifnet *);
 299 static int      re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 300 static void     re_init(void *);
 301 static void     re_stop(struct re_softc *);
 302 static void     re_watchdog(struct ifnet *);
 303 static int      re_ifmedia_upd(struct ifnet *);
 304 static void     re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 305
 306 static void     re_eeprom_putbyte(struct re_softc *, int);
 307 static void     re_eeprom_getword(struct re_softc *, int, u_int16_t *);
 308 static void     re_read_eeprom(struct re_softc *, caddr_t, int, int);
 309 static void     re_get_eewidth(struct re_softc *);
 310
 311 static int      re_gmii_readreg(device_t, int, int);
 312 static int      re_gmii_writereg(device_t, int, int, int);
 313
 314 static int      re_miibus_readreg(device_t, int, int);
 315 static int      re_miibus_writereg(device_t, int, int, int);
 316 static void     re_miibus_statchg(device_t);
 317
 318 static void     re_setmulti(struct re_softc *);
 319 static void     re_reset(struct re_softc *, int);
 320 static void     re_get_eaddr(struct re_softc *, uint8_t *);
 321
 322 static void     re_setup_hw_im(struct re_softc *);
 323 static void     re_setup_sim_im(struct re_softc *);
 324 static void     re_disable_hw_im(struct re_softc *);
 325 static void     re_disable_sim_im(struct re_softc *);
 326 static void     re_config_imtype(struct re_softc *, int);
 327 static void     re_setup_intr(struct re_softc *, int, int);
 328
 329 static int      re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
 330 static int      re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
 331 static int      re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
 332 static int      re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
 333 static int      re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
 334
 335 static int      re_jpool_alloc(struct re_softc *);
 336 static void     re_jpool_free(struct re_softc *);
 337 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
 338 static void     re_jbuf_free(void *);
 339 static void     re_jbuf_ref(void *);
 340
 341 #ifdef RE_DIAG
 342 static int      re_diag(struct re_softc *);
 343 #endif
 344
 345 #ifdef DEVICE_POLLING
 346 static void     re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 347 #endif
 348
 349 static device_method_t re_methods[] = {
 350         /* Device interface */
 351         DEVMETHOD(device_probe,         re_probe),
 352         DEVMETHOD(device_attach,        re_attach),
 353         DEVMETHOD(device_detach,        re_detach),
 354         DEVMETHOD(device_suspend,       re_suspend),
 355         DEVMETHOD(device_resume,        re_resume),
 356         DEVMETHOD(device_shutdown,      re_shutdown),
 357
 358         /* bus interface */
 359         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 360         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 361
 362         /* MII interface */
 363         DEVMETHOD(miibus_readreg,       re_miibus_readreg),
 364         DEVMETHOD(miibus_writereg,      re_miibus_writereg),
 365         DEVMETHOD(miibus_statchg,       re_miibus_statchg),
 366
 367         { 0, 0 }
 368 };
 369
 370 static driver_t re_driver = {
 371         "re",
 372         re_methods,
 373         sizeof(struct re_softc)
 374 };
 375
 376 static devclass_t re_devclass;
 377
 378 DECLARE_DUMMY_MODULE(if_re);
 379 MODULE_DEPEND(if_re, miibus, 1, 1, 1);
 380 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL);
 381 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL);
 382 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL);
 383
 384 static int      re_rx_desc_count = RE_RX_DESC_CNT_DEF;
 385 static int      re_tx_desc_count = RE_TX_DESC_CNT_DEF;
 386
 387 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
 388 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
 389
 390 #define EE_SET(x)       \
 391         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
 392
 393 #define EE_CLR(x)       \
 394         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
 395
 396 static __inline void
 397 re_free_rxchain(struct re_softc *sc)
 398 {
 399         if (sc->re_head != NULL) {
 400                 m_freem(sc->re_head);
 401                 sc->re_head = sc->re_tail = NULL;
 402         }
 403 }
 404
 405 /*
 406  * Send a read command and address to the EEPROM, check for ACK.
 407  */
 408 static void
 409 re_eeprom_putbyte(struct re_softc *sc, int addr)
 410 {
 411         int d, i;
 412
 413         d = addr | (RE_9346_READ << sc->re_eewidth);
 414
 415         /*
 416          * Feed in each bit and strobe the clock.
 417          */
 418         for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
 419                 if (d & i)
 420                         EE_SET(RE_EE_DATAIN);
 421                 else
 422                         EE_CLR(RE_EE_DATAIN);
 423                 DELAY(100);
 424                 EE_SET(RE_EE_CLK);
 425                 DELAY(150);
 426                 EE_CLR(RE_EE_CLK);
 427                 DELAY(100);
 428         }
 429 }
 430
 431 /*
 432  * Read a word of data stored in the EEPROM at address 'addr.'
 433  */
 434 static void
 435 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
 436 {
 437         int i;
 438         uint16_t word = 0;
 439
 440         /*
 441          * Send address of word we want to read.
 442          */
 443         re_eeprom_putbyte(sc, addr);
 444
 445         /*
 446          * Start reading bits from EEPROM.
 447          */
 448         for (i = 0x8000; i != 0; i >>= 1) {
 449                 EE_SET(RE_EE_CLK);
 450                 DELAY(100);
 451                 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
 452                         word |= i;
 453                 EE_CLR(RE_EE_CLK);
 454                 DELAY(100);
 455         }
 456
 457         *dest = word;
 458 }
 459
 460 /*
 461  * Read a sequence of words from the EEPROM.
 462  */
 463 static void
 464 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
 465 {
 466         int i;
 467         uint16_t word = 0, *ptr;
 468
 469         CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
 470         DELAY(100);
 471
 472         for (i = 0; i < cnt; i++) {
 473                 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
 474                 re_eeprom_getword(sc, off + i, &word);
 475                 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
 476                 ptr = (uint16_t *)(dest + (i * 2));
 477                 *ptr = word;
 478         }
 479
 480         CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
 481 }
 482
 483 static void
 484 re_get_eewidth(struct re_softc *sc)
 485 {
 486         uint16_t re_did = 0;
 487
 488         sc->re_eewidth = 6;
 489         re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
 490         if (re_did != 0x8129)
 491                 sc->re_eewidth = 8;
 492 }
 493
 494 static int
 495 re_gmii_readreg(device_t dev, int phy, int reg)
 496 {
 497         struct re_softc *sc = device_get_softc(dev);
 498         u_int32_t rval;
 499         int i;
 500
 501         if (phy != 1)
 502                 return(0);
 503
 504         /* Let the rgephy driver read the GMEDIASTAT register */
 505
 506         if (reg == RE_GMEDIASTAT)
 507                 return(CSR_READ_1(sc, RE_GMEDIASTAT));
 508
 509         CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
 510         DELAY(1000);
 511
 512         for (i = 0; i < RE_TIMEOUT; i++) {
 513                 rval = CSR_READ_4(sc, RE_PHYAR);
 514                 if (rval & RE_PHYAR_BUSY)
 515                         break;
 516                 DELAY(100);
 517         }
 518
 519         if (i == RE_TIMEOUT) {
 520                 device_printf(dev, "PHY read failed\n");
 521                 return(0);
 522         }
 523
 524         return(rval & RE_PHYAR_PHYDATA);
 525 }
 526
 527 static int
 528 re_gmii_writereg(device_t dev, int phy, int reg, int data)
 529 {
 530         struct re_softc *sc = device_get_softc(dev);
 531         uint32_t rval;
 532         int i;
 533
 534         CSR_WRITE_4(sc, RE_PHYAR,
 535                     (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
 536         DELAY(1000);
 537
 538         for (i = 0; i < RE_TIMEOUT; i++) {
 539                 rval = CSR_READ_4(sc, RE_PHYAR);
 540                 if ((rval & RE_PHYAR_BUSY) == 0)
 541                         break;
 542                 DELAY(100);
 543         }
 544
 545         if (i == RE_TIMEOUT)
 546                 device_printf(dev, "PHY write failed\n");
 547
 548         return(0);
 549 }
 550
 551 static int
 552 re_miibus_readreg(device_t dev, int phy, int reg)
 553 {
 554         struct re_softc *sc = device_get_softc(dev);
 555         uint16_t rval = 0;
 556         uint16_t re8139_reg = 0;
 557
 558         if (!RE_IS_8139CP(sc)) {
 559                 rval = re_gmii_readreg(dev, phy, reg);
 560                 return(rval);
 561         }
 562
 563         /* Pretend the internal PHY is only at address 0 */
 564         if (phy)
 565                 return(0);
 566
 567         switch(reg) {
 568         case MII_BMCR:
 569                 re8139_reg = RE_BMCR;
 570                 break;
 571         case MII_BMSR:
 572                 re8139_reg = RE_BMSR;
 573                 break;
 574         case MII_ANAR:
 575                 re8139_reg = RE_ANAR;
 576                 break;
 577         case MII_ANER:
 578                 re8139_reg = RE_ANER;
 579                 break;
 580         case MII_ANLPAR:
 581                 re8139_reg = RE_LPAR;
 582                 break;
 583         case MII_PHYIDR1:
 584         case MII_PHYIDR2:
 585                 return(0);
 586         /*
 587          * Allow the rlphy driver to read the media status
 588          * register. If we have a link partner which does not
 589          * support NWAY, this is the register which will tell
 590          * us the results of parallel detection.
 591          */
 592         case RE_MEDIASTAT:
 593                 return(CSR_READ_1(sc, RE_MEDIASTAT));
 594         default:
 595                 device_printf(dev, "bad phy register\n");
 596                 return(0);
 597         }
 598         rval = CSR_READ_2(sc, re8139_reg);
 599         if (re8139_reg == RE_BMCR) {
 600                 /* 8139C+ has different bit layout. */
 601                 rval &= ~(BMCR_LOOP | BMCR_ISO);
 602         }
 603         return(rval);
 604 }
 605
 606 static int
 607 re_miibus_writereg(device_t dev, int phy, int reg, int data)
 608 {
 609         struct re_softc *sc= device_get_softc(dev);
 610         u_int16_t re8139_reg = 0;
 611
 612         if (!RE_IS_8139CP(sc))
 613                 return(re_gmii_writereg(dev, phy, reg, data));
 614
 615         /* Pretend the internal PHY is only at address 0 */
 616         if (phy)
 617                 return(0);
 618
 619         switch(reg) {
 620         case MII_BMCR:
 621                 re8139_reg = RE_BMCR;
 622                 /* 8139C+ has different bit layout. */
 623                 data &= ~(BMCR_LOOP | BMCR_ISO);
 624                 break;
 625         case MII_BMSR:
 626                 re8139_reg = RE_BMSR;
 627                 break;
 628         case MII_ANAR:
 629                 re8139_reg = RE_ANAR;
 630                 break;
 631         case MII_ANER:
 632                 re8139_reg = RE_ANER;
 633                 break;
 634         case MII_ANLPAR:
 635                 re8139_reg = RE_LPAR;
 636                 break;
 637         case MII_PHYIDR1:
 638         case MII_PHYIDR2:
 639                 return(0);
 640         default:
 641                 device_printf(dev, "bad phy register\n");
 642                 return(0);
 643         }
 644         CSR_WRITE_2(sc, re8139_reg, data);
 645         return(0);
 646 }
 647
 648 static void
 649 re_miibus_statchg(device_t dev)
 650 {
 651 }
 652
 653 /*
 654  * Program the 64-bit multicast hash filter.
 655  */
 656 static void
 657 re_setmulti(struct re_softc *sc)
 658 {
 659         struct ifnet *ifp = &sc->arpcom.ac_if;
 660         int h = 0;
 661         uint32_t hashes[2] = { 0, 0 };
 662         struct ifmultiaddr *ifma;
 663         uint32_t rxfilt;
 664         int mcnt = 0;
 665
 666         rxfilt = CSR_READ_4(sc, RE_RXCFG);
 667
 668         /* Set the individual bit to receive frames for this host only. */
 669         rxfilt |= RE_RXCFG_RX_INDIV;
 670         /* Set capture broadcast bit to capture broadcast frames. */
 671         rxfilt |= RE_RXCFG_RX_BROAD;
 672
 673         rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
 674         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
 675                 rxfilt |= RE_RXCFG_RX_MULTI;
 676
 677                 /* If we want promiscuous mode, set the allframes bit. */
 678                 if (ifp->if_flags & IFF_PROMISC)
 679                         rxfilt |= RE_RXCFG_RX_ALLPHYS;
 680
 681                 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
 682                 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
 683                 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
 684                 return;
 685         }
 686
 687         /* first, zot all the existing hash bits */
 688         CSR_WRITE_4(sc, RE_MAR0, 0);
 689         CSR_WRITE_4(sc, RE_MAR4, 0);
 690
 691         /* now program new ones */
 692         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 693                 if (ifma->ifma_addr->sa_family != AF_LINK)
 694                         continue;
 695                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 696                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 697                 if (h < 32)
 698                         hashes[0] |= (1 << h);
 699                 else
 700                         hashes[1] |= (1 << (h - 32));
 701                 mcnt++;
 702         }
 703
 704         if (mcnt)
 705                 rxfilt |= RE_RXCFG_RX_MULTI;
 706         else
 707                 rxfilt &= ~RE_RXCFG_RX_MULTI;
 708
 709         CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
 710
 711         /*
 712          * For some unfathomable reason, RealTek decided to reverse
 713          * the order of the multicast hash registers in the PCI Express
 714          * parts. This means we have to write the hash pattern in reverse
 715          * order for those devices.
 716          */
 717         if (sc->re_caps & RE_C_PCIE) {
 718                 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1]));
 719                 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0]));
 720         } else {
 721                 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
 722                 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
 723         }
 724 }
 725
 726 static void
 727 re_reset(struct re_softc *sc, int running)
 728 {
 729         int i;
 730
 731         if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
 732                 CSR_WRITE_1(sc, RE_COMMAND,
 733                             RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
 734                 DELAY(100);
 735         }
 736
 737         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
 738
 739         for (i = 0; i < RE_TIMEOUT; i++) {
 740                 DELAY(10);
 741                 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
 742                         break;
 743         }
 744         if (i == RE_TIMEOUT)
 745                 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
 746 }
 747
 748 #ifdef RE_DIAG
 749 /*
 750  * The following routine is designed to test for a defect on some
 751  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
 752  * lines connected to the bus, however for a 32-bit only card, they
 753  * should be pulled high. The result of this defect is that the
 754  * NIC will not work right if you plug it into a 64-bit slot: DMA
 755  * operations will be done with 64-bit transfers, which will fail
 756  * because the 64-bit data lines aren't connected.
 757  *
 758  * There's no way to work around this (short of talking a soldering
 759  * iron to the board), however we can detect it. The method we use
 760  * here is to put the NIC into digital loopback mode, set the receiver
 761  * to promiscuous mode, and then try to send a frame. We then compare
 762  * the frame data we sent to what was received. If the data matches,
 763  * then the NIC is working correctly, otherwise we know the user has
 764  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
 765  * slot. In the latter case, there's no way the NIC can work correctly,
 766  * so we print out a message on the console and abort the device attach.
 767  */
 768
 769 static int
 770 re_diag(struct re_softc *sc)
 771 {
 772         struct ifnet *ifp = &sc->arpcom.ac_if;
 773         struct mbuf *m0;
 774         struct ether_header *eh;
 775         struct re_desc *cur_rx;
 776         uint16_t status;
 777         uint32_t rxstat;
 778         int total_len, i, error = 0, phyaddr;
 779         uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
 780         uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
 781
 782         /* Allocate a single mbuf */
 783
 784         MGETHDR(m0, MB_DONTWAIT, MT_DATA);
 785         if (m0 == NULL)
 786                 return(ENOBUFS);
 787
 788         /*
 789          * Initialize the NIC in test mode. This sets the chip up
 790          * so that it can send and receive frames, but performs the
 791          * following special functions:
 792          * - Puts receiver in promiscuous mode
 793          * - Enables digital loopback mode
 794          * - Leaves interrupts turned off
 795          */
 796
 797         ifp->if_flags |= IFF_PROMISC;
 798         sc->re_flags |= RE_F_TESTMODE;
 799         re_init(sc);
 800         sc->re_flags |= RE_F_LINKED;
 801         if (!RE_IS_8139CP(sc))
 802                 phyaddr = 1;
 803         else
 804                 phyaddr = 0;
 805
 806         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
 807         for (i = 0; i < RE_TIMEOUT; i++) {
 808                 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
 809                 if (!(status & BMCR_RESET))
 810                         break;
 811         }
 812
 813         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
 814         CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
 815
 816         DELAY(100000);
 817
 818         /* Put some data in the mbuf */
 819
 820         eh = mtod(m0, struct ether_header *);
 821         bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
 822         bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
 823         eh->ether_type = htons(ETHERTYPE_IP);
 824         m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
 825
 826         /*
 827          * Queue the packet, start transmission.
 828          * Note: ifq_handoff() ultimately calls re_start() for us.
 829          */
 830
 831         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
 832         error = ifq_handoff(ifp, m0, NULL);
 833         if (error) {
 834                 m0 = NULL;
 835                 goto done;
 836         }
 837         m0 = NULL;
 838
 839         /* Wait for it to propagate through the chip */
 840
 841         DELAY(100000);
 842         for (i = 0; i < RE_TIMEOUT; i++) {
 843                 status = CSR_READ_2(sc, RE_ISR);
 844                 CSR_WRITE_2(sc, RE_ISR, status);
 845                 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
 846                     (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
 847                         break;
 848                 DELAY(10);
 849         }
 850
 851         if (i == RE_TIMEOUT) {
 852                 if_printf(ifp, "diagnostic failed to receive packet "
 853                           "in loopback mode\n");
 854                 error = EIO;
 855                 goto done;
 856         }
 857
 858         /*
 859          * The packet should have been dumped into the first
 860          * entry in the RX DMA ring. Grab it from there.
 861          */
 862
 863         bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0],
 864                         BUS_DMASYNC_POSTREAD);
 865         bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
 866                           sc->re_ldata.re_rx_dmamap[0]);
 867
 868         m0 = sc->re_ldata.re_rx_mbuf[0];
 869         sc->re_ldata.re_rx_mbuf[0] = NULL;
 870         eh = mtod(m0, struct ether_header *);
 871
 872         cur_rx = &sc->re_ldata.re_rx_list[0];
 873         total_len = RE_RXBYTES(cur_rx);
 874         rxstat = le32toh(cur_rx->re_cmdstat);
 875
 876         if (total_len != ETHER_MIN_LEN) {
 877                 if_printf(ifp, "diagnostic failed, received short packet\n");
 878                 error = EIO;
 879                 goto done;
 880         }
 881
 882         /* Test that the received packet data matches what we sent. */
 883
 884         if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
 885             bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
 886             be16toh(eh->ether_type) != ETHERTYPE_IP) {
 887                 if_printf(ifp, "WARNING, DMA FAILURE!\n");
 888                 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
 889                     dst, ":", src, ":", ETHERTYPE_IP);
 890                 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
 891                     eh->ether_dhost, ":",  eh->ether_shost, ":",
 892                     ntohs(eh->ether_type));
 893                 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
 894                     "into a 64-bit PCI slot.\n");
 895                 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
 896                     "for proper operation.\n");
 897                 if_printf(ifp, "Read the re(4) man page for more details.\n");
 898                 error = EIO;
 899         }
 900
 901 done:
 902         /* Turn interface off, release resources */
 903
 904         sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
 905         ifp->if_flags &= ~IFF_PROMISC;
 906         re_stop(sc);
 907         if (m0 != NULL)
 908                 m_freem(m0);
 909
 910         return (error);
 911 }
 912 #endif  /* RE_DIAG */
 913
 914 /*
 915  * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
 916  * IDs against our list and return a device name if we find a match.
 917  */
 918 static int
 919 re_probe(device_t dev)
 920 {
 921         const struct re_type *t;
 922         const struct re_hwrev *hw_rev;
 923         struct re_softc *sc;
 924         int rid;
 925         uint32_t hwrev, macmode, txcfg;
 926         uint16_t vendor, product;
 927
 928         vendor = pci_get_vendor(dev);
 929         product = pci_get_device(dev);
 930
 931         /*
 932          * Only attach to rev.3 of the Linksys EG1032 adapter.
 933          * Rev.2 is supported by sk(4).
 934          */
 935         if (vendor == PCI_VENDOR_LINKSYS &&
 936             product == PCI_PRODUCT_LINKSYS_EG1032 &&
 937             pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
 938                 return ENXIO;
 939
 940         if (vendor == PCI_VENDOR_REALTEK &&
 941             product == PCI_PRODUCT_REALTEK_RT8139 &&
 942             pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) {
 943                 /* Poor 8139 */
 944                 return ENXIO;
 945         }
 946
 947         for (t = re_devs; t->re_name != NULL; t++) {
 948                 if (product == t->re_did && vendor == t->re_vid)
 949                         break;
 950         }
 951
 952         /*
 953          * Check if we found a RealTek device.
 954          */
 955         if (t->re_name == NULL)
 956                 return ENXIO;
 957
 958         /*
 959          * Temporarily map the I/O space so we can read the chip ID register.
 960          */
 961         sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
 962         rid = RE_PCI_LOIO;
 963         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
 964                                             RF_ACTIVE);
 965         if (sc->re_res == NULL) {
 966                 device_printf(dev, "couldn't map ports/memory\n");
 967                 kfree(sc, M_TEMP);
 968                 return ENXIO;
 969         }
 970
 971         sc->re_btag = rman_get_bustag(sc->re_res);
 972         sc->re_bhandle = rman_get_bushandle(sc->re_res);
 973
 974         txcfg = CSR_READ_4(sc, RE_TXCFG);
 975         hwrev = txcfg & RE_TXCFG_HWREV;
 976         macmode = txcfg & RE_TXCFG_MACMODE;
 977         bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
 978         kfree(sc, M_TEMP);
 979
 980         /*
 981          * and continue matching for the specific chip...
 982          */
 983         for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
 984                 if (hw_rev->re_hwrev == hwrev) {
 985                         sc = device_get_softc(dev);
 986
 987                         sc->re_hwrev = hw_rev->re_hwrev;
 988                         sc->re_macver = hw_rev->re_macver;
 989                         sc->re_caps = hw_rev->re_caps;
 990                         sc->re_maxmtu = hw_rev->re_maxmtu;
 991
 992                         /*
 993                          * Apply chip property fixup
 994                          */
 995                         switch (sc->re_hwrev) {
 996                         case RE_HWREV_8101E1:
 997                         case RE_HWREV_8101E2:
 998                                 if (macmode == 0)
 999                                         sc->re_macver = RE_MACVER_11;
1000                                 else if (macmode == 0x200000)
1001                                         sc->re_macver = RE_MACVER_12;
1002                                 break;
1003                         case RE_HWREV_8102E:
1004                         case RE_HWREV_8102EL:
1005                                 if (macmode == 0)
1006                                         sc->re_macver = RE_MACVER_13;
1007                                 else if (macmode == 0x100000)
1008                                         sc->re_macver = RE_MACVER_14;
1009                                 break;
1010                         case RE_HWREV_8168B2:
1011                         case RE_HWREV_8168B3:
1012                                 if (macmode == 0)
1013                                         sc->re_macver = RE_MACVER_22;
1014                                 break;
1015                         case RE_HWREV_8168C:
1016                                 if (macmode == 0)
1017                                         sc->re_macver = RE_MACVER_24;
1018                                 else if (macmode == 0x200000)
1019                                         sc->re_macver = RE_MACVER_25;
1020                                 else if (macmode == 0x300000)
1021                                         sc->re_macver = RE_MACVER_27;
1022                                 break;
1023                         case RE_HWREV_8168CP:
1024                                 if (macmode == 0)
1025                                         sc->re_macver = RE_MACVER_26;
1026                                 else if (macmode == 0x100000)
1027                                         sc->re_macver = RE_MACVER_28;
1028                                 break;
1029                         case RE_HWREV_8168DP:
1030                                 if (macmode == 0)
1031                                         sc->re_macver = RE_MACVER_2B;
1032                                 else if (macmode == 0x200000)
1033                                         sc->re_macver = RE_MACVER_2C;
1034                                 break;
1035                         case RE_HWREV_8168E:
1036                                 if (macmode == 0x100000)
1037                                         sc->re_macver = RE_MACVER_2E;
1038                                 else if (macmode == 0x200000)
1039                                         sc->re_macver = RE_MACVER_2F;
1040                                 break;
1041                         case RE_HWREV_8168F:
1042                                 if (macmode == 0x000000)
1043                                         sc->re_macver = RE_MACVER_30;
1044                                 else if (macmode == 0x100000)
1045                                         sc->re_macver = RE_MACVER_31;
1046                                 break;
1047                         }
1048                         if (pci_is_pcie(dev))
1049                                 sc->re_caps |= RE_C_PCIE;
1050
1051                         device_set_desc(dev, t->re_name);
1052                         return 0;
1053                 }
1054         }
1055
1056         if (bootverbose) {
1057                 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1058                               hwrev, macmode);
1059         }
1060         return ENXIO;
1061 }
1062
1063 static int
1064 re_allocmem(device_t dev)
1065 {
1066         struct re_softc *sc = device_get_softc(dev);
1067         bus_dmamem_t dmem;
1068         int error, i;
1069
1070         /*
1071          * Allocate list data
1072          */
1073         sc->re_ldata.re_tx_mbuf =
1074         kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1075                 M_DEVBUF, M_ZERO | M_WAITOK);
1076
1077         sc->re_ldata.re_rx_mbuf =
1078         kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1079                 M_DEVBUF, M_ZERO | M_WAITOK);
1080
1081         sc->re_ldata.re_rx_paddr =
1082         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1083                 M_DEVBUF, M_ZERO | M_WAITOK);
1084
1085         sc->re_ldata.re_tx_dmamap =
1086         kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1087                 M_DEVBUF, M_ZERO | M_WAITOK);
1088
1089         sc->re_ldata.re_rx_dmamap =
1090         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1091                 M_DEVBUF, M_ZERO | M_WAITOK);
1092
1093         /*
1094          * Allocate the parent bus DMA tag appropriate for PCI.
1095          */
1096         error = bus_dma_tag_create(NULL,        /* parent */
1097                         1, 0,                   /* alignment, boundary */
1098                         BUS_SPACE_MAXADDR,      /* lowaddr */
1099                         BUS_SPACE_MAXADDR,      /* highaddr */
1100                         NULL, NULL,             /* filter, filterarg */
1101                         BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1102                         0,                      /* nsegments */
1103                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1104                         0,                      /* flags */
1105                         &sc->re_parent_tag);
1106         if (error) {
1107                 device_printf(dev, "could not allocate parent dma tag\n");
1108                 return error;
1109         }
1110
1111         /* Allocate TX descriptor list. */
1112         error = bus_dmamem_coherent(sc->re_parent_tag,
1113                         RE_RING_ALIGN, 0,
1114                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1115                         RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1116                         &dmem);
1117         if (error) {
1118                 device_printf(dev, "could not allocate TX ring\n");
1119                 return error;
1120         }
1121         sc->re_ldata.re_tx_list_tag = dmem.dmem_tag;
1122         sc->re_ldata.re_tx_list_map = dmem.dmem_map;
1123         sc->re_ldata.re_tx_list = dmem.dmem_addr;
1124         sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr;
1125
1126         /* Allocate RX descriptor list. */
1127         error = bus_dmamem_coherent(sc->re_parent_tag,
1128                         RE_RING_ALIGN, 0,
1129                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1130                         RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1131                         &dmem);
1132         if (error) {
1133                 device_printf(dev, "could not allocate RX ring\n");
1134                 return error;
1135         }
1136         sc->re_ldata.re_rx_list_tag = dmem.dmem_tag;
1137         sc->re_ldata.re_rx_list_map = dmem.dmem_map;
1138         sc->re_ldata.re_rx_list = dmem.dmem_addr;
1139         sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr;
1140
1141         /* Allocate maps for TX mbufs. */
1142         error = bus_dma_tag_create(sc->re_parent_tag,
1143                         1, 0,
1144                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1145                         NULL, NULL,
1146                         RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1147                         BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1148                         &sc->re_ldata.re_tx_mtag);
1149         if (error) {
1150                 device_printf(dev, "could not allocate TX buf dma tag\n");
1151                 return(error);
1152         }
1153
1154         /* Create DMA maps for TX buffers */
1155         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1156                 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag,
1157                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1158                                 &sc->re_ldata.re_tx_dmamap[i]);
1159                 if (error) {
1160                         device_printf(dev, "can't create DMA map for TX buf\n");
1161                         re_freebufmem(sc, i, 0);
1162                         return(error);
1163                 }
1164         }
1165
1166         /* Allocate maps for RX mbufs. */
1167         error = bus_dma_tag_create(sc->re_parent_tag,
1168                         RE_RXBUF_ALIGN, 0,
1169                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1170                         NULL, NULL,
1171                         MCLBYTES, 1, MCLBYTES,
1172                         BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,
1173                         &sc->re_ldata.re_rx_mtag);
1174         if (error) {
1175                 device_printf(dev, "could not allocate RX buf dma tag\n");
1176                 return(error);
1177         }
1178
1179         /* Create spare DMA map for RX */
1180         error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK,
1181                         &sc->re_ldata.re_rx_spare);
1182         if (error) {
1183                 device_printf(dev, "can't create spare DMA map for RX\n");
1184                 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1185                 sc->re_ldata.re_rx_mtag = NULL;
1186                 return error;
1187         }
1188
1189         /* Create DMA maps for RX buffers */
1190         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1191                 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag,
1192                                 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]);
1193                 if (error) {
1194                         device_printf(dev, "can't create DMA map for RX buf\n");
1195                         re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1196                         return(error);
1197                 }
1198         }
1199
1200         /* Create jumbo buffer pool for RX if required */
1201         if (sc->re_caps & RE_C_CONTIGRX) {
1202                 error = re_jpool_alloc(sc);
1203                 if (error) {
1204                         re_jpool_free(sc);
1205                         /* Disable jumbo frame support */
1206                         sc->re_maxmtu = ETHERMTU;
1207                 }
1208         }
1209         return(0);
1210 }
1211
1212 static void
1213 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1214 {
1215         int i;
1216
1217         /* Destroy all the RX and TX buffer maps */
1218         if (sc->re_ldata.re_tx_mtag) {
1219                 for (i = 0; i < tx_cnt; i++) {
1220                         bus_dmamap_destroy(sc->re_ldata.re_tx_mtag,
1221                                            sc->re_ldata.re_tx_dmamap[i]);
1222                 }
1223                 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag);
1224                 sc->re_ldata.re_tx_mtag = NULL;
1225         }
1226
1227         if (sc->re_ldata.re_rx_mtag) {
1228                 for (i = 0; i < rx_cnt; i++) {
1229                         bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1230                                            sc->re_ldata.re_rx_dmamap[i]);
1231                 }
1232                 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1233                                    sc->re_ldata.re_rx_spare);
1234                 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1235                 sc->re_ldata.re_rx_mtag = NULL;
1236         }
1237 }
1238
1239 static void
1240 re_freemem(device_t dev)
1241 {
1242         struct re_softc *sc = device_get_softc(dev);
1243
1244         /* Unload and free the RX DMA ring memory and map */
1245         if (sc->re_ldata.re_rx_list_tag) {
1246                 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1247                                   sc->re_ldata.re_rx_list_map);
1248                 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1249                                 sc->re_ldata.re_rx_list,
1250                                 sc->re_ldata.re_rx_list_map);
1251                 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1252         }
1253
1254         /* Unload and free the TX DMA ring memory and map */
1255         if (sc->re_ldata.re_tx_list_tag) {
1256                 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1257                                   sc->re_ldata.re_tx_list_map);
1258                 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1259                                 sc->re_ldata.re_tx_list,
1260                                 sc->re_ldata.re_tx_list_map);
1261                 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1262         }
1263
1264         /* Free RX/TX buf DMA stuffs */
1265         re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1266
1267         /* Unload and free the stats buffer and map */
1268         if (sc->re_ldata.re_stag) {
1269                 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap);
1270                 bus_dmamem_free(sc->re_ldata.re_stag,
1271                                 sc->re_ldata.re_stats,
1272                                 sc->re_ldata.re_smap);
1273                 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1274         }
1275
1276         if (sc->re_caps & RE_C_CONTIGRX)
1277                 re_jpool_free(sc);
1278
1279         if (sc->re_parent_tag)
1280                 bus_dma_tag_destroy(sc->re_parent_tag);
1281
1282         if (sc->re_ldata.re_tx_mbuf != NULL)
1283                 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1284         if (sc->re_ldata.re_rx_mbuf != NULL)
1285                 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1286         if (sc->re_ldata.re_rx_paddr != NULL)
1287                 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1288         if (sc->re_ldata.re_tx_dmamap != NULL)
1289                 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1290         if (sc->re_ldata.re_rx_dmamap != NULL)
1291                 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1292 }
1293
1294 /*
1295  * Attach the interface. Allocate softc structures, do ifmedia
1296  * setup and ethernet/BPF attach.
1297  */
1298 static int
1299 re_attach(device_t dev)
1300 {
1301         struct re_softc *sc = device_get_softc(dev);
1302         struct ifnet *ifp;
1303         uint8_t eaddr[ETHER_ADDR_LEN];
1304         int error = 0, rid, qlen;
1305
1306         callout_init(&sc->re_timer);
1307         sc->re_dev = dev;
1308
1309         if (RE_IS_8139CP(sc)) {
1310                 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1311                 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1312         } else {
1313                 sc->re_rx_desc_cnt = re_rx_desc_count;
1314                 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1315                         sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1316
1317                 sc->re_tx_desc_cnt = re_tx_desc_count;
1318                 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1319                         sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1320         }
1321
1322         qlen = RE_IFQ_MAXLEN;
1323         if (sc->re_tx_desc_cnt > qlen)
1324                 qlen = sc->re_tx_desc_cnt;
1325
1326         sc->re_rxbuf_size = MCLBYTES;
1327         sc->re_newbuf = re_newbuf_std;
1328
1329         sc->re_tx_time = 5;             /* 125us */
1330         sc->re_rx_time = 2;             /* 50us */
1331         if (sc->re_caps & RE_C_PCIE)
1332                 sc->re_sim_time = 75;   /* 75us */
1333         else
1334                 sc->re_sim_time = 125;  /* 125us */
1335         if (!RE_IS_8139CP(sc)) {
1336                 /* simulated interrupt moderation */
1337                 sc->re_imtype = RE_IMTYPE_SIM;
1338         } else {
1339                 sc->re_imtype = RE_IMTYPE_NONE;
1340         }
1341         re_config_imtype(sc, sc->re_imtype);
1342
1343         sysctl_ctx_init(&sc->re_sysctl_ctx);
1344         sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1345                                              SYSCTL_STATIC_CHILDREN(_hw),
1346                                              OID_AUTO,
1347                                              device_get_nameunit(dev),
1348                                              CTLFLAG_RD, 0, "");
1349         if (sc->re_sysctl_tree == NULL) {
1350                 device_printf(dev, "can't add sysctl node\n");
1351                 error = ENXIO;
1352                 goto fail;
1353         }
1354         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1355                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1356                        "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1357                        0, "RX desc count");
1358         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1359                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1360                        "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1361                        0, "TX desc count");
1362         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1363                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1364                         OID_AUTO, "sim_time",
1365                         CTLTYPE_INT | CTLFLAG_RW,
1366                         sc, 0, re_sysctl_simtime, "I",
1367                         "Simulated interrupt moderation time (usec).");
1368         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1369                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1370                         OID_AUTO, "imtype",
1371                         CTLTYPE_INT | CTLFLAG_RW,
1372                         sc, 0, re_sysctl_imtype, "I",
1373                         "Interrupt moderation type -- "
1374                         "0:disable, 1:simulated, "
1375                         "2:hardware(if supported)");
1376         if (sc->re_caps & RE_C_HWIM) {
1377                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1378                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1379                                 OID_AUTO, "hw_rxtime",
1380                                 CTLTYPE_INT | CTLFLAG_RW,
1381                                 sc, 0, re_sysctl_rxtime, "I",
1382                                 "Hardware interrupt moderation time "
1383                                 "(unit: 25usec).");
1384                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1385                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1386                                 OID_AUTO, "hw_txtime",
1387                                 CTLTYPE_INT | CTLFLAG_RW,
1388                                 sc, 0, re_sysctl_txtime, "I",
1389                                 "Hardware interrupt moderation time "
1390                                 "(unit: 25usec).");
1391         }
1392
1393 #ifndef BURN_BRIDGES
1394         /*
1395          * Handle power management nonsense.
1396          */
1397
1398         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1399                 uint32_t membase, irq;
1400
1401                 /* Save important PCI config data. */
1402                 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1403                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1404
1405                 /* Reset the power state. */
1406                 device_printf(dev, "chip is in D%d power mode "
1407                     "-- setting to D0\n", pci_get_powerstate(dev));
1408
1409                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1410
1411                 /* Restore PCI config data. */
1412                 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1413                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1414         }
1415 #endif
1416         /*
1417          * Map control/status registers.
1418          */
1419         pci_enable_busmaster(dev);
1420
1421         rid = RE_PCI_LOIO;
1422         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1423                                             RF_ACTIVE);
1424
1425         if (sc->re_res == NULL) {
1426                 device_printf(dev, "couldn't map ports\n");
1427                 error = ENXIO;
1428                 goto fail;
1429         }
1430
1431         sc->re_btag = rman_get_bustag(sc->re_res);
1432         sc->re_bhandle = rman_get_bushandle(sc->re_res);
1433
1434         /* Allocate interrupt */
1435         rid = 0;
1436         sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1437                                             RF_SHAREABLE | RF_ACTIVE);
1438
1439         if (sc->re_irq == NULL) {
1440                 device_printf(dev, "couldn't map interrupt\n");
1441                 error = ENXIO;
1442                 goto fail;
1443         }
1444
1445         /* Reset the adapter. */
1446         re_reset(sc, 0);
1447
1448         if (RE_IS_8139CP(sc)) {
1449                 sc->re_bus_speed = 33; /* XXX */
1450         } else if (sc->re_caps & RE_C_PCIE) {
1451                 sc->re_bus_speed = 125;
1452         } else {
1453                 uint8_t cfg2;
1454
1455                 cfg2 = CSR_READ_1(sc, RE_CFG2);
1456                 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1457                 case RE_CFG2_PCICLK_33MHZ:
1458                         sc->re_bus_speed = 33;
1459                         break;
1460                 case RE_CFG2_PCICLK_66MHZ:
1461                         sc->re_bus_speed = 66;
1462                         break;
1463                 default:
1464                         device_printf(dev, "unknown bus speed, assume 33MHz\n");
1465                         sc->re_bus_speed = 33;
1466                         break;
1467                 }
1468                 if (cfg2 & RE_CFG2_PCI64)
1469                         sc->re_caps |= RE_C_PCI64;
1470         }
1471         device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1472                       "PCI%s %dMHz\n",
1473                       sc->re_hwrev, sc->re_macver,
1474                       (sc->re_caps & RE_C_PCIE) ?
1475                       "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1476                       sc->re_bus_speed);
1477
1478         /*
1479          * NOTE:
1480          * DO NOT try to adjust config1 and config5 which was spotted in
1481          * Realtek's Linux drivers.  It will _permanently_ damage certain
1482          * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1483          */
1484
1485         re_get_eaddr(sc, eaddr);
1486
1487         if (!RE_IS_8139CP(sc)) {
1488                 /* Set RX length mask */
1489                 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1490                 sc->re_txstart = RE_GTXSTART;
1491         } else {
1492                 /* Set RX length mask */
1493                 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1494                 sc->re_txstart = RE_TXSTART;
1495         }
1496
1497         /* Allocate DMA stuffs */
1498         error = re_allocmem(dev);
1499         if (error)
1500                 goto fail;
1501
1502         /*
1503          * Apply some magic PCI settings from Realtek ...
1504          */
1505         if (RE_IS_8169(sc)) {
1506                 CSR_WRITE_1(sc, 0x82, 1);
1507                 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1508         }
1509         pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1510
1511         if (sc->re_caps & RE_C_MAC2) {
1512                 /*
1513                  * Following part is extracted from Realtek BSD driver v176.
1514                  * However, this does _not_ make much/any sense:
1515                  * 8168C's PCI Express device control is located at 0x78,
1516                  * so the reading from 0x79 (higher part of 0x78) and setting
1517                  * the 4~6bits intend to enlarge the "max read request size"
1518                  * (we will do it).  The content of the rest part of this
1519                  * register is not meaningful to other PCI registers, so
1520                  * writing the value to 0x54 could be completely wrong.
1521                  * 0x80 is the lower part of PCI Express device status, non-
1522                  * reserved bits are RW1C, writing 0 to them will not have
1523                  * any effect at all.
1524                  */
1525 #ifdef foo
1526                 uint8_t val;
1527
1528                 val = pci_read_config(dev, 0x79, 1);
1529                 val = (val & ~0x70) | 0x50;
1530                 pci_write_config(dev, 0x54, val, 1);
1531                 pci_write_config(dev, 0x80, 0, 1);
1532 #endif
1533         }
1534
1535         /*
1536          * Apply some PHY fixup from Realtek ...
1537          */
1538         if (sc->re_hwrev == RE_HWREV_8110S) {
1539                 CSR_WRITE_1(sc, 0x82, 1);
1540                 re_miibus_writereg(dev, 1, 0xb, 0);
1541         }
1542         if (sc->re_caps & RE_C_PHYPMGT) {
1543                 /* Power up PHY */
1544                 re_miibus_writereg(dev, 1, 0x1f, 0);
1545                 re_miibus_writereg(dev, 1, 0xe, 0);
1546         }
1547
1548         /* Do MII setup */
1549         if (mii_phy_probe(dev, &sc->re_miibus,
1550             re_ifmedia_upd, re_ifmedia_sts)) {
1551                 device_printf(dev, "MII without any phy!\n");
1552                 error = ENXIO;
1553                 goto fail;
1554         }
1555
1556         ifp = &sc->arpcom.ac_if;
1557         ifp->if_softc = sc;
1558         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1559         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1560         ifp->if_ioctl = re_ioctl;
1561         ifp->if_start = re_start;
1562 #ifdef DEVICE_POLLING
1563         ifp->if_poll = re_poll;
1564 #endif
1565         ifp->if_watchdog = re_watchdog;
1566         ifp->if_init = re_init;
1567         if (!RE_IS_8139CP(sc)) /* XXX */
1568                 ifp->if_baudrate = 1000000000;
1569         else
1570                 ifp->if_baudrate = 100000000;
1571         ifq_set_maxlen(&ifp->if_snd, qlen);
1572         ifq_set_ready(&ifp->if_snd);
1573
1574         ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1575         if (sc->re_caps & RE_C_HWCSUM)
1576                 ifp->if_capabilities |= IFCAP_HWCSUM;
1577
1578         ifp->if_capenable = ifp->if_capabilities;
1579         if (ifp->if_capabilities & IFCAP_HWCSUM)
1580                 ifp->if_hwassist = RE_CSUM_FEATURES;
1581         else
1582                 ifp->if_hwassist = 0;
1583
1584         /*
1585          * Call MI attach routine.
1586          */
1587         ether_ifattach(ifp, eaddr, NULL);
1588
1589 #ifdef RE_DIAG
1590         /*
1591          * Perform hardware diagnostic on the original RTL8169.
1592          * Some 32-bit cards were incorrectly wired and would
1593          * malfunction if plugged into a 64-bit slot.
1594          */
1595         if (sc->re_hwrev == RE_HWREV_8169) {
1596                 lwkt_serialize_enter(ifp->if_serializer);
1597                 error = re_diag(sc);
1598                 lwkt_serialize_exit(ifp->if_serializer);
1599
1600                 if (error) {
1601                         device_printf(dev, "hardware diagnostic failure\n");
1602                         ether_ifdetach(ifp);
1603                         goto fail;
1604                 }
1605         }
1606 #endif  /* RE_DIAG */
1607
1608         /* Hook interrupt last to avoid having to lock softc */
1609         error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1610                                &sc->re_intrhand, ifp->if_serializer);
1611
1612         if (error) {
1613                 device_printf(dev, "couldn't set up irq\n");
1614                 ether_ifdetach(ifp);
1615                 goto fail;
1616         }
1617
1618         ifp->if_cpuid = rman_get_cpuid(sc->re_irq);
1619         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1620
1621 fail:
1622         if (error)
1623                 re_detach(dev);
1624
1625         return (error);
1626 }
1627
1628 /*
1629  * Shutdown hardware and free up resources. This can be called any
1630  * time after the mutex has been initialized. It is called in both
1631  * the error case in attach and the normal detach case so it needs
1632  * to be careful about only freeing resources that have actually been
1633  * allocated.
1634  */
1635 static int
1636 re_detach(device_t dev)
1637 {
1638         struct re_softc *sc = device_get_softc(dev);
1639         struct ifnet *ifp = &sc->arpcom.ac_if;
1640
1641         /* These should only be active if attach succeeded */
1642         if (device_is_attached(dev)) {
1643                 lwkt_serialize_enter(ifp->if_serializer);
1644                 re_stop(sc);
1645                 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1646                 lwkt_serialize_exit(ifp->if_serializer);
1647
1648                 ether_ifdetach(ifp);
1649         }
1650         if (sc->re_miibus)
1651                 device_delete_child(dev, sc->re_miibus);
1652         bus_generic_detach(dev);
1653
1654         if (sc->re_sysctl_tree != NULL)
1655                 sysctl_ctx_free(&sc->re_sysctl_ctx);
1656
1657         if (sc->re_irq)
1658                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1659         if (sc->re_res) {
1660                 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1661                                      sc->re_res);
1662         }
1663
1664         /* Free DMA stuffs */
1665         re_freemem(dev);
1666
1667         return(0);
1668 }
1669
1670 static void
1671 re_setup_rxdesc(struct re_softc *sc, int idx)
1672 {
1673         bus_addr_t paddr;
1674         uint32_t cmdstat;
1675         struct re_desc *d;
1676
1677         paddr = sc->re_ldata.re_rx_paddr[idx];
1678         d = &sc->re_ldata.re_rx_list[idx];
1679
1680         d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1681         d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1682
1683         cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1684         if (idx == (sc->re_rx_desc_cnt - 1))
1685                 cmdstat |= RE_RDESC_CMD_EOR;
1686         d->re_cmdstat = htole32(cmdstat);
1687 }
1688
1689 static int
1690 re_newbuf_std(struct re_softc *sc, int idx, int init)
1691 {
1692         bus_dma_segment_t seg;
1693         bus_dmamap_t map;
1694         struct mbuf *m;
1695         int error, nsegs;
1696
1697         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1698         if (m == NULL) {
1699                 error = ENOBUFS;
1700
1701                 if (init) {
1702                         if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1703                         return error;
1704                 } else {
1705                         goto back;
1706                 }
1707         }
1708         m->m_len = m->m_pkthdr.len = MCLBYTES;
1709
1710         /*
1711          * NOTE:
1712          * re(4) chips need address of the receive buffer to be 8-byte
1713          * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1714          */
1715
1716         error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag,
1717                         sc->re_ldata.re_rx_spare, m,
1718                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1719         if (error) {
1720                 m_freem(m);
1721                 if (init) {
1722                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1723                         return error;
1724                 } else {
1725                         goto back;
1726                 }
1727         }
1728
1729         if (!init) {
1730                 bus_dmamap_sync(sc->re_ldata.re_rx_mtag,
1731                                 sc->re_ldata.re_rx_dmamap[idx],
1732                                 BUS_DMASYNC_POSTREAD);
1733                 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1734                                   sc->re_ldata.re_rx_dmamap[idx]);
1735         }
1736         sc->re_ldata.re_rx_mbuf[idx] = m;
1737         sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1738
1739         map = sc->re_ldata.re_rx_dmamap[idx];
1740         sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1741         sc->re_ldata.re_rx_spare = map;
1742 back:
1743         re_setup_rxdesc(sc, idx);
1744         return error;
1745 }
1746
1747 static int
1748 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1749 {
1750         struct mbuf *m;
1751         struct re_jbuf *jbuf;
1752         int error = 0;
1753
1754         MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1755         if (m == NULL) {
1756                 error = ENOBUFS;
1757                 if (init) {
1758                         if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1759                         return error;
1760                 } else {
1761                         goto back;
1762                 }
1763         }
1764
1765         jbuf = re_jbuf_alloc(sc);
1766         if (jbuf == NULL) {
1767                 m_freem(m);
1768
1769                 error = ENOBUFS;
1770                 if (init) {
1771                         if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1772                         return error;
1773                 } else {
1774                         goto back;
1775                 }
1776         }
1777
1778         m->m_ext.ext_arg = jbuf;
1779         m->m_ext.ext_buf = jbuf->re_buf;
1780         m->m_ext.ext_free = re_jbuf_free;
1781         m->m_ext.ext_ref = re_jbuf_ref;
1782         m->m_ext.ext_size = sc->re_rxbuf_size;
1783
1784         m->m_data = m->m_ext.ext_buf;
1785         m->m_flags |= M_EXT;
1786         m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1787
1788         /*
1789          * NOTE:
1790          * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1791          * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1792          */
1793
1794         sc->re_ldata.re_rx_mbuf[idx] = m;
1795         sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1796 back:
1797         re_setup_rxdesc(sc, idx);
1798         return error;
1799 }
1800
1801 static int
1802 re_tx_list_init(struct re_softc *sc)
1803 {
1804         bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1805
1806         sc->re_ldata.re_tx_prodidx = 0;
1807         sc->re_ldata.re_tx_considx = 0;
1808         sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1809
1810         return(0);
1811 }
1812
1813 static int
1814 re_rx_list_init(struct re_softc *sc)
1815 {
1816         int i, error;
1817
1818         bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1819
1820         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1821                 error = sc->re_newbuf(sc, i, 1);
1822                 if (error)
1823                         return(error);
1824         }
1825
1826         sc->re_ldata.re_rx_prodidx = 0;
1827         sc->re_head = sc->re_tail = NULL;
1828
1829         return(0);
1830 }
1831
1832 #define RE_IP4_PACKET   0x1
1833 #define RE_TCP_PACKET   0x2
1834 #define RE_UDP_PACKET   0x4
1835
1836 static __inline uint8_t
1837 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1838 {
1839         uint8_t packet_type = 0;
1840
1841         if (sc->re_caps & RE_C_MAC2) {
1842                 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1843                         packet_type |= RE_IP4_PACKET;
1844         } else {
1845                 if (rxstat & RE_RDESC_STAT_PROTOID)
1846                         packet_type |= RE_IP4_PACKET;
1847         }
1848         if (RE_TCPPKT(rxstat))
1849                 packet_type |= RE_TCP_PACKET;
1850         else if (RE_UDPPKT(rxstat))
1851                 packet_type |= RE_UDP_PACKET;
1852         return packet_type;
1853 }
1854
1855 /*
1856  * RX handler for C+ and 8169. For the gigE chips, we support
1857  * the reception of jumbo frames that have been fragmented
1858  * across multiple 2K mbuf cluster buffers.
1859  */
1860 static int
1861 re_rxeof(struct re_softc *sc)
1862 {
1863         struct ifnet *ifp = &sc->arpcom.ac_if;
1864         struct mbuf *m;
1865         struct re_desc  *cur_rx;
1866         uint32_t rxstat, rxctrl;
1867         int i, total_len, rx = 0;
1868
1869         for (i = sc->re_ldata.re_rx_prodidx;
1870              RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1871                 cur_rx = &sc->re_ldata.re_rx_list[i];
1872                 m = sc->re_ldata.re_rx_mbuf[i];
1873                 total_len = RE_RXBYTES(cur_rx);
1874                 rxstat = le32toh(cur_rx->re_cmdstat);
1875                 rxctrl = le32toh(cur_rx->re_control);
1876
1877                 rx = 1;
1878
1879 #ifdef INVARIANTS
1880                 if (sc->re_flags & RE_F_USE_JPOOL)
1881                         KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1882 #endif
1883
1884                 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1885                         if (sc->re_flags & RE_F_DROP_RXFRAG) {
1886                                 re_setup_rxdesc(sc, i);
1887                                 continue;
1888                         }
1889
1890                         if (sc->re_newbuf(sc, i, 0)) {
1891                                 /* Drop upcoming fragments */
1892                                 sc->re_flags |= RE_F_DROP_RXFRAG;
1893                                 continue;
1894                         }
1895
1896                         m->m_len = MCLBYTES;
1897                         if (sc->re_head == NULL) {
1898                                 sc->re_head = sc->re_tail = m;
1899                         } else {
1900                                 sc->re_tail->m_next = m;
1901                                 sc->re_tail = m;
1902                         }
1903                         continue;
1904                 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1905                         /*
1906                          * Last fragment of a multi-fragment packet.
1907                          *
1908                          * Since error already happened, this fragment
1909                          * must be dropped as well as the fragment chain.
1910                          */
1911                         re_setup_rxdesc(sc, i);
1912                         re_free_rxchain(sc);
1913                         sc->re_flags &= ~RE_F_DROP_RXFRAG;
1914                         continue;
1915                 }
1916
1917                 /*
1918                  * NOTE: for the 8139C+, the frame length field
1919                  * is always 12 bits in size, but for the gigE chips,
1920                  * it is 13 bits (since the max RX frame length is 16K).
1921                  * Unfortunately, all 32 bits in the status word
1922                  * were already used, so to make room for the extra
1923                  * length bit, RealTek took out the 'frame alignment
1924                  * error' bit and shifted the other status bits
1925                  * over one slot. The OWN, EOR, FS and LS bits are
1926                  * still in the same places. We have already extracted
1927                  * the frame length and checked the OWN bit, so rather
1928                  * than using an alternate bit mapping, we shift the
1929                  * status bits one space to the right so we can evaluate
1930                  * them using the 8169 status as though it was in the
1931                  * same format as that of the 8139C+.
1932                  */
1933                 if (!RE_IS_8139CP(sc))
1934                         rxstat >>= 1;
1935
1936                 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1937                         ifp->if_ierrors++;
1938                         /*
1939                          * If this is part of a multi-fragment packet,
1940                          * discard all the pieces.
1941                          */
1942                         re_free_rxchain(sc);
1943                         re_setup_rxdesc(sc, i);
1944                         continue;
1945                 }
1946
1947                 /*
1948                  * If allocating a replacement mbuf fails,
1949                  * reload the current one.
1950                  */
1951
1952                 if (sc->re_newbuf(sc, i, 0)) {
1953                         ifp->if_ierrors++;
1954                         continue;
1955                 }
1956
1957                 if (sc->re_head != NULL) {
1958                         m->m_len = total_len % MCLBYTES;
1959                         /*
1960                          * Special case: if there's 4 bytes or less
1961                          * in this buffer, the mbuf can be discarded:
1962                          * the last 4 bytes is the CRC, which we don't
1963                          * care about anyway.
1964                          */
1965                         if (m->m_len <= ETHER_CRC_LEN) {
1966                                 sc->re_tail->m_len -=
1967                                     (ETHER_CRC_LEN - m->m_len);
1968                                 m_freem(m);
1969                         } else {
1970                                 m->m_len -= ETHER_CRC_LEN;
1971                                 sc->re_tail->m_next = m;
1972                         }
1973                         m = sc->re_head;
1974                         sc->re_head = sc->re_tail = NULL;
1975                         m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1976                 } else {
1977                         m->m_pkthdr.len = m->m_len =
1978                             (total_len - ETHER_CRC_LEN);
1979                 }
1980
1981                 ifp->if_ipackets++;
1982                 m->m_pkthdr.rcvif = ifp;
1983
1984                 /* Do RX checksumming if enabled */
1985
1986                 if (ifp->if_capenable & IFCAP_RXCSUM) {
1987                         uint8_t packet_type;
1988
1989                         packet_type = re_packet_type(sc, rxstat, rxctrl);
1990
1991                         /* Check IP header checksum */
1992                         if (packet_type & RE_IP4_PACKET) {
1993                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1994                                 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1995                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1996                         }
1997
1998                         /* Check TCP/UDP checksum */
1999                         if (((packet_type & RE_TCP_PACKET) &&
2000                              (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
2001                             ((packet_type & RE_UDP_PACKET) &&
2002                              (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
2003                                 m->m_pkthdr.csum_flags |=
2004                                     CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2005                                     CSUM_FRAG_NOT_CHECKED;
2006                                 m->m_pkthdr.csum_data = 0xffff;
2007                         }
2008                 }
2009
2010                 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2011                         m->m_flags |= M_VLANTAG;
2012                         m->m_pkthdr.ether_vlantag =
2013                                 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2014                 }
2015                 ifp->if_input(ifp, m);
2016         }
2017
2018         sc->re_ldata.re_rx_prodidx = i;
2019
2020         return rx;
2021 }
2022
2023 #undef RE_IP4_PACKET
2024 #undef RE_TCP_PACKET
2025 #undef RE_UDP_PACKET
2026
2027 static int
2028 re_tx_collect(struct re_softc *sc)
2029 {
2030         struct ifnet *ifp = &sc->arpcom.ac_if;
2031         uint32_t txstat;
2032         int idx, tx = 0;
2033
2034         for (idx = sc->re_ldata.re_tx_considx;
2035              sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2036              RE_TXDESC_INC(sc, idx)) {
2037                 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2038                 if (txstat & RE_TDESC_CMD_OWN)
2039                         break;
2040
2041                 tx = 1;
2042
2043                 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2044
2045                 /*
2046                  * We only stash mbufs in the last descriptor
2047                  * in a fragment chain, which also happens to
2048                  * be the only place where the TX status bits
2049                  * are valid.
2050                  */
2051                 if (txstat & RE_TDESC_CMD_EOF) {
2052                         bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2053                             sc->re_ldata.re_tx_dmamap[idx]);
2054                         m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2055                         sc->re_ldata.re_tx_mbuf[idx] = NULL;
2056                         if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2057                             RE_TDESC_STAT_COLCNT))
2058                                 ifp->if_collisions++;
2059                         if (txstat & RE_TDESC_STAT_TXERRSUM)
2060                                 ifp->if_oerrors++;
2061                         else
2062                                 ifp->if_opackets++;
2063                 }
2064                 sc->re_ldata.re_tx_free++;
2065         }
2066         sc->re_ldata.re_tx_considx = idx;
2067
2068         return tx;
2069 }
2070
2071 static int
2072 re_txeof(struct re_softc *sc)
2073 {
2074         struct ifnet *ifp = &sc->arpcom.ac_if;
2075         int tx;
2076
2077         tx = re_tx_collect(sc);
2078
2079         /* There is enough free TX descs */
2080         if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2081                 ifp->if_flags &= ~IFF_OACTIVE;
2082
2083         /*
2084          * Some chips will ignore a second TX request issued while an
2085          * existing transmission is in progress. If the transmitter goes
2086          * idle but there are still packets waiting to be sent, we need
2087          * to restart the channel here to flush them out. This only seems
2088          * to be required with the PCIe devices.
2089          */
2090         if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2091                 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2092         else
2093                 ifp->if_timer = 0;
2094
2095         return tx;
2096 }
2097
2098 static void
2099 re_tick(void *xsc)
2100 {
2101         struct re_softc *sc = xsc;
2102
2103         lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2104         re_tick_serialized(xsc);
2105         lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2106 }
2107
2108 static void
2109 re_tick_serialized(void *xsc)
2110 {
2111         struct re_softc *sc = xsc;
2112         struct ifnet *ifp = &sc->arpcom.ac_if;
2113         struct mii_data *mii;
2114
2115         ASSERT_SERIALIZED(ifp->if_serializer);
2116
2117         mii = device_get_softc(sc->re_miibus);
2118         mii_tick(mii);
2119         if (sc->re_flags & RE_F_LINKED) {
2120                 if (!(mii->mii_media_status & IFM_ACTIVE))
2121                         sc->re_flags &= ~RE_F_LINKED;
2122         } else {
2123                 if (mii->mii_media_status & IFM_ACTIVE &&
2124                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2125                         sc->re_flags |= RE_F_LINKED;
2126                         if (!ifq_is_empty(&ifp->if_snd))
2127                                 if_devstart(ifp);
2128                 }
2129         }
2130
2131         callout_reset(&sc->re_timer, hz, re_tick, sc);
2132 }
2133
2134 #ifdef DEVICE_POLLING
2135
2136 static void
2137 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2138 {
2139         struct re_softc *sc = ifp->if_softc;
2140
2141         ASSERT_SERIALIZED(ifp->if_serializer);
2142
2143         switch(cmd) {
2144         case POLL_REGISTER:
2145                 /* disable interrupts */
2146                 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2147                 break;
2148
2149         case POLL_DEREGISTER:
2150                 /* enable interrupts */
2151                 re_setup_intr(sc, 1, sc->re_imtype);
2152                 break;
2153
2154         default:
2155                 sc->rxcycles = count;
2156                 re_rxeof(sc);
2157                 re_txeof(sc);
2158
2159                 if (!ifq_is_empty(&ifp->if_snd))
2160                         if_devstart(ifp);
2161
2162                 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2163                         uint16_t       status;
2164
2165                         status = CSR_READ_2(sc, RE_ISR);
2166                         if (status == 0xffff)
2167                                 return;
2168                         if (status)
2169                                 CSR_WRITE_2(sc, RE_ISR, status);
2170
2171                         /*
2172                          * XXX check behaviour on receiver stalls.
2173                          */
2174
2175                         if (status & RE_ISR_SYSTEM_ERR)
2176                                 re_init(sc);
2177                 }
2178                 break;
2179         }
2180 }
2181 #endif /* DEVICE_POLLING */
2182
2183 static void
2184 re_intr(void *arg)
2185 {
2186         struct re_softc *sc = arg;
2187         struct ifnet *ifp = &sc->arpcom.ac_if;
2188         uint16_t status;
2189         int rx, tx;
2190
2191         ASSERT_SERIALIZED(ifp->if_serializer);
2192
2193         if ((sc->re_flags & RE_F_SUSPENDED) ||
2194             (ifp->if_flags & IFF_RUNNING) == 0)
2195                 return;
2196
2197         rx = tx = 0;
2198         for (;;) {
2199                 status = CSR_READ_2(sc, RE_ISR);
2200                 /* If the card has gone away the read returns 0xffff. */
2201                 if (status == 0xffff)
2202                         break;
2203                 if (status)
2204                         CSR_WRITE_2(sc, RE_ISR, status);
2205
2206                 if ((status & sc->re_intrs) == 0)
2207                         break;
2208
2209                 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2210                         rx |= re_rxeof(sc);
2211
2212                 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2213                         tx |= re_txeof(sc);
2214
2215                 if (status & RE_ISR_SYSTEM_ERR)
2216                         re_init(sc);
2217
2218                 if (status & RE_ISR_LINKCHG) {
2219                         callout_stop(&sc->re_timer);
2220                         re_tick_serialized(sc);
2221                 }
2222         }
2223
2224         if (sc->re_imtype == RE_IMTYPE_SIM) {
2225                 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2226                         if ((tx | rx) == 0) {
2227                                 /*
2228                                  * Nothing needs to be processed, fallback
2229                                  * to use TX/RX interrupts.
2230                                  */
2231                                 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2232
2233                                 /*
2234                                  * Recollect, mainly to avoid the possible
2235                                  * race introduced by changing interrupt
2236                                  * masks.
2237                                  */
2238                                 re_rxeof(sc);
2239                                 tx = re_txeof(sc);
2240                         } else {
2241                                 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2242                         }
2243                 } else if (tx | rx) {
2244                         /*
2245                          * Assume that using simulated interrupt moderation
2246                          * (hardware timer based) could reduce the interript
2247                          * rate.
2248                          */
2249                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2250                 }
2251         }
2252
2253         if (tx && !ifq_is_empty(&ifp->if_snd))
2254                 if_devstart(ifp);
2255 }
2256
2257 static int
2258 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2259 {
2260         struct mbuf *m = *m_head;
2261         bus_dma_segment_t segs[RE_MAXSEGS];
2262         bus_dmamap_t map;
2263         int error, maxsegs, idx, i, nsegs;
2264         struct re_desc *d, *tx_ring;
2265         uint32_t cmd_csum, ctl_csum, vlantag;
2266
2267         KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2268                 ("not enough free TX desc"));
2269
2270         map = sc->re_ldata.re_tx_dmamap[*idx0];
2271
2272         /*
2273          * Set up checksum offload. Note: checksum offload bits must
2274          * appear in all descriptors of a multi-descriptor transmit
2275          * attempt. (This is according to testing done with an 8169
2276          * chip. I'm not sure if this is a requirement or a bug.)
2277          */
2278         cmd_csum = ctl_csum = 0;
2279         if (m->m_pkthdr.csum_flags & CSUM_IP) {
2280                 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2281                 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2282         }
2283         if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2284                 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2285                 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2286         }
2287         if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2288                 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2289                 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2290         }
2291
2292         /* For MAC2 chips, csum flags are set on re_control */
2293         if (sc->re_caps & RE_C_MAC2)
2294                 cmd_csum = 0;
2295         else
2296                 ctl_csum = 0;
2297
2298         if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2299                 /*
2300                  * With some of the RealTek chips, using the checksum offload
2301                  * support in conjunction with the autopadding feature results
2302                  * in the transmission of corrupt frames. For example, if we
2303                  * need to send a really small IP fragment that's less than 60
2304                  * bytes in size, and IP header checksumming is enabled, the
2305                  * resulting ethernet frame that appears on the wire will
2306                  * have garbled payload. To work around this, if TX checksum
2307                  * offload is enabled, we always manually pad short frames out
2308                  * to the minimum ethernet frame size.
2309                  *
2310                  * Note: this appears unnecessary for TCP, and doing it for TCP
2311                  * with PCIe adapters seems to result in bad checksums.
2312                  */
2313                 if ((m->m_pkthdr.csum_flags &
2314                      (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2315                     (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2316                     m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2317                         error = m_devpad(m, RE_MIN_FRAMELEN);
2318                         if (error)
2319                                 goto back;
2320                 }
2321         }
2322
2323         vlantag = 0;
2324         if (m->m_flags & M_VLANTAG) {
2325                 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2326                           RE_TDESC_CTL_INSTAG;
2327         }
2328
2329         maxsegs = sc->re_ldata.re_tx_free;
2330         if (maxsegs > RE_MAXSEGS)
2331                 maxsegs = RE_MAXSEGS;
2332
2333         error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map,
2334                         m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2335         if (error)
2336                 goto back;
2337
2338         m = *m_head;
2339         bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2340
2341         /*
2342          * Map the segment array into descriptors.  We also keep track
2343          * of the end of the ring and set the end-of-ring bits as needed,
2344          * and we set the ownership bits in all except the very first
2345          * descriptor, whose ownership bits will be turned on later.
2346          */
2347         tx_ring = sc->re_ldata.re_tx_list;
2348         idx = *idx0;
2349         i = 0;
2350         for (;;) {
2351                 uint32_t cmdstat;
2352
2353                 d = &tx_ring[idx];
2354
2355                 cmdstat = segs[i].ds_len;
2356                 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2357                 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2358                 if (i == 0)
2359                         cmdstat |= RE_TDESC_CMD_SOF;
2360                 else
2361                         cmdstat |= RE_TDESC_CMD_OWN;
2362                 if (idx == (sc->re_tx_desc_cnt - 1))
2363                         cmdstat |= RE_TDESC_CMD_EOR;
2364                 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2365                 d->re_control = htole32(ctl_csum | vlantag);
2366
2367                 i++;
2368                 if (i == nsegs)
2369                         break;
2370                 RE_TXDESC_INC(sc, idx);
2371         }
2372         d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2373
2374         /* Transfer ownership of packet to the chip. */
2375         d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2376         if (*idx0 != idx)
2377                 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2378
2379         /*
2380          * Insure that the map for this transmission
2381          * is placed at the array index of the last descriptor
2382          * in this chain.
2383          */
2384         sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2385         sc->re_ldata.re_tx_dmamap[idx] = map;
2386
2387         sc->re_ldata.re_tx_mbuf[idx] = m;
2388         sc->re_ldata.re_tx_free -= nsegs;
2389
2390         RE_TXDESC_INC(sc, idx);
2391         *idx0 = idx;
2392 back:
2393         if (error) {
2394                 m_freem(*m_head);
2395                 *m_head = NULL;
2396         }
2397         return error;
2398 }
2399
2400 /*
2401  * Main transmit routine for C+ and gigE NICs.
2402  */
2403
2404 static void
2405 re_start(struct ifnet *ifp)
2406 {
2407         struct re_softc *sc = ifp->if_softc;
2408         struct mbuf *m_head;
2409         int idx, need_trans, oactive, error;
2410
2411         ASSERT_SERIALIZED(ifp->if_serializer);
2412
2413         if ((sc->re_flags & RE_F_LINKED) == 0) {
2414                 ifq_purge(&ifp->if_snd);
2415                 return;
2416         }
2417
2418         if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2419                 return;
2420
2421         idx = sc->re_ldata.re_tx_prodidx;
2422
2423         need_trans = 0;
2424         oactive = 0;
2425         while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2426                 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2427                         if (!oactive) {
2428                                 if (re_tx_collect(sc)) {
2429                                         oactive = 1;
2430                                         continue;
2431                                 }
2432                         }
2433                         ifp->if_flags |= IFF_OACTIVE;
2434                         break;
2435                 }
2436
2437                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2438                 if (m_head == NULL)
2439                         break;
2440
2441                 error = re_encap(sc, &m_head, &idx);
2442                 if (error) {
2443                         /* m_head is freed by re_encap(), if we reach here */
2444                         ifp->if_oerrors++;
2445
2446                         if (error == EFBIG && !oactive) {
2447                                 if (re_tx_collect(sc)) {
2448                                         oactive = 1;
2449                                         continue;
2450                                 }
2451                         }
2452                         ifp->if_flags |= IFF_OACTIVE;
2453                         break;
2454                 }
2455
2456                 oactive = 0;
2457                 need_trans = 1;
2458
2459                 /*
2460                  * If there's a BPF listener, bounce a copy of this frame
2461                  * to him.
2462                  */
2463                 ETHER_BPF_MTAP(ifp, m_head);
2464         }
2465
2466         /*
2467          * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible
2468          * for IFF_OACTIVE to not be properly set when we also do not
2469          * have sufficient free tx descriptors, leaving packet in
2470          * ifp->if_send.  This can cause if_start_dispatch() to loop
2471          * infinitely so make sure IFF_OACTIVE is set properly.
2472          */
2473         if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2474                 if ((ifp->if_flags & IFF_OACTIVE) == 0) {
2475                         device_printf(sc->re_dev,
2476                                       "Debug: IFF_OACTIVE was not set when"
2477                                       " re_tx_free was below minimum!\n");
2478                         ifp->if_flags |= IFF_OACTIVE;
2479                 }
2480         }
2481         if (!need_trans)
2482                 return;
2483
2484         sc->re_ldata.re_tx_prodidx = idx;
2485
2486         /*
2487          * RealTek put the TX poll request register in a different
2488          * location on the 8169 gigE chip. I don't know why.
2489          */
2490         CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2491
2492         /*
2493          * Set a timeout in case the chip goes out to lunch.
2494          */
2495         ifp->if_timer = 5;
2496 }
2497
2498 static void
2499 re_init(void *xsc)
2500 {
2501         struct re_softc *sc = xsc;
2502         struct ifnet *ifp = &sc->arpcom.ac_if;
2503         struct mii_data *mii;
2504         int error, framelen;
2505
2506         ASSERT_SERIALIZED(ifp->if_serializer);
2507
2508         mii = device_get_softc(sc->re_miibus);
2509
2510         /*
2511          * Cancel pending I/O and free all RX/TX buffers.
2512          */
2513         re_stop(sc);
2514
2515         if (sc->re_caps & RE_C_CONTIGRX) {
2516                 if (ifp->if_mtu > ETHERMTU) {
2517                         KKASSERT(sc->re_ldata.re_jbuf != NULL);
2518                         sc->re_flags |= RE_F_USE_JPOOL;
2519                         sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2520                         sc->re_newbuf = re_newbuf_jumbo;
2521                 } else {
2522                         sc->re_flags &= ~RE_F_USE_JPOOL;
2523                         sc->re_rxbuf_size = MCLBYTES;
2524                         sc->re_newbuf = re_newbuf_std;
2525                 }
2526         }
2527
2528         /*
2529          * Adjust max read request size according to MTU; mainly to
2530          * improve TX performance for common case (ETHERMTU) on GigE
2531          * NICs.  However, this could _not_ be done on 10/100 only
2532          * NICs; their DMA engines will malfunction using non-default
2533          * max read request size.
2534          */
2535         if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) {
2536                 if (ifp->if_mtu > ETHERMTU) {
2537                         /*
2538                          * 512 seems to be the only value that works
2539                          * reliably with jumbo frame
2540                          */
2541                         pcie_set_max_readrq(sc->re_dev,
2542                                 PCIEM_DEVCTL_MAX_READRQ_512);
2543                 } else {
2544                         pcie_set_max_readrq(sc->re_dev,
2545                                 PCIEM_DEVCTL_MAX_READRQ_4096);
2546                 }
2547         }
2548
2549         /*
2550          * Enable C+ RX and TX mode, as well as VLAN stripping and
2551          * RX checksum offload. We must configure the C+ register
2552          * before all others.
2553          */
2554         CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2555                     RE_CPLUSCMD_PCI_MRW |
2556                     (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2557                      RE_CPLUSCMD_VLANSTRIP : 0) |
2558                     (ifp->if_capenable & IFCAP_RXCSUM ?
2559                      RE_CPLUSCMD_RXCSUM_ENB : 0));
2560
2561         /*
2562          * Init our MAC address.  Even though the chipset
2563          * documentation doesn't mention it, we need to enter "Config
2564          * register write enable" mode to modify the ID registers.
2565          */
2566         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2567         CSR_WRITE_4(sc, RE_IDR0,
2568             htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2569         CSR_WRITE_2(sc, RE_IDR4,
2570             htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2571         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2572
2573         /*
2574          * For C+ mode, initialize the RX descriptors and mbufs.
2575          */
2576         error = re_rx_list_init(sc);
2577         if (error) {
2578                 re_stop(sc);
2579                 return;
2580         }
2581         error = re_tx_list_init(sc);
2582         if (error) {
2583                 re_stop(sc);
2584                 return;
2585         }
2586
2587         /*
2588          * Load the addresses of the RX and TX lists into the chip.
2589          */
2590         CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2591             RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2592         CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2593             RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2594
2595         CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2596             RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2597         CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2598             RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2599
2600         /*
2601          * Enable transmit and receive.
2602          */
2603         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2604
2605         /*
2606          * Set the initial TX and RX configuration.
2607          */
2608         if (sc->re_flags & RE_F_TESTMODE) {
2609                 if (!RE_IS_8139CP(sc))
2610                         CSR_WRITE_4(sc, RE_TXCFG,
2611                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2612                 else
2613                         CSR_WRITE_4(sc, RE_TXCFG,
2614                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2615         } else
2616                 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2617
2618         framelen = RE_FRAMELEN(ifp->if_mtu);
2619         if (framelen < MCLBYTES)
2620                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2621         else
2622                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2623
2624         CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2625
2626         /*
2627          * Program the multicast filter, if necessary.
2628          */
2629         re_setmulti(sc);
2630
2631 #ifdef DEVICE_POLLING
2632         /*
2633          * Disable interrupts if we are polling.
2634          */
2635         if (ifp->if_flags & IFF_POLLING)
2636                 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2637         else    /* otherwise ... */
2638 #endif /* DEVICE_POLLING */
2639         /*
2640          * Enable interrupts.
2641          */
2642         if (sc->re_flags & RE_F_TESTMODE)
2643                 CSR_WRITE_2(sc, RE_IMR, 0);
2644         else
2645                 re_setup_intr(sc, 1, sc->re_imtype);
2646         CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2647
2648         /* Start RX/TX process. */
2649         CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2650
2651 #ifdef notdef
2652         /* Enable receiver and transmitter. */
2653         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2654 #endif
2655
2656         /*
2657          * For 8169 gigE NICs, set the max allowed RX packet
2658          * size so we can receive jumbo frames.
2659          */
2660         if (!RE_IS_8139CP(sc)) {
2661                 if (sc->re_caps & RE_C_CONTIGRX)
2662                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2663                 else
2664                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2665         }
2666
2667         if (sc->re_flags & RE_F_TESTMODE)
2668                 return;
2669
2670         mii_mediachg(mii);
2671
2672         CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2673
2674         ifp->if_flags |= IFF_RUNNING;
2675         ifp->if_flags &= ~IFF_OACTIVE;
2676
2677         callout_reset(&sc->re_timer, hz, re_tick, sc);
2678 }
2679
2680 /*
2681  * Set media options.
2682  */
2683 static int
2684 re_ifmedia_upd(struct ifnet *ifp)
2685 {
2686         struct re_softc *sc = ifp->if_softc;
2687         struct mii_data *mii;
2688
2689         ASSERT_SERIALIZED(ifp->if_serializer);
2690
2691         mii = device_get_softc(sc->re_miibus);
2692         mii_mediachg(mii);
2693
2694         return(0);
2695 }
2696
2697 /*
2698  * Report current media status.
2699  */
2700 static void
2701 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2702 {
2703         struct re_softc *sc = ifp->if_softc;
2704         struct mii_data *mii;
2705
2706         ASSERT_SERIALIZED(ifp->if_serializer);
2707
2708         mii = device_get_softc(sc->re_miibus);
2709
2710         mii_pollstat(mii);
2711         ifmr->ifm_active = mii->mii_media_active;
2712         ifmr->ifm_status = mii->mii_media_status;
2713 }
2714
2715 static int
2716 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2717 {
2718         struct re_softc *sc = ifp->if_softc;
2719         struct ifreq *ifr = (struct ifreq *) data;
2720         struct mii_data *mii;
2721         int error = 0, mask;
2722
2723         ASSERT_SERIALIZED(ifp->if_serializer);
2724
2725         switch(command) {
2726         case SIOCSIFMTU:
2727                 if (ifr->ifr_mtu > sc->re_maxmtu) {
2728                         error = EINVAL;
2729                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2730                         ifp->if_mtu = ifr->ifr_mtu;
2731                         if (ifp->if_flags & IFF_RUNNING)
2732                                 ifp->if_init(sc);
2733                 }
2734                 break;
2735
2736         case SIOCSIFFLAGS:
2737                 if (ifp->if_flags & IFF_UP) {
2738                         if (ifp->if_flags & IFF_RUNNING) {
2739                                 if ((ifp->if_flags ^ sc->re_if_flags) &
2740                                     (IFF_PROMISC | IFF_ALLMULTI))
2741                                         re_setmulti(sc);
2742                         } else {
2743                                 re_init(sc);
2744                         }
2745                 } else if (ifp->if_flags & IFF_RUNNING) {
2746                         re_stop(sc);
2747                 }
2748                 sc->re_if_flags = ifp->if_flags;
2749                 break;
2750
2751         case SIOCADDMULTI:
2752         case SIOCDELMULTI:
2753                 re_setmulti(sc);
2754                 break;
2755
2756         case SIOCGIFMEDIA:
2757         case SIOCSIFMEDIA:
2758                 mii = device_get_softc(sc->re_miibus);
2759                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2760                 break;
2761
2762         case SIOCSIFCAP:
2763                 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2764                        ifp->if_capabilities;
2765                 ifp->if_capenable ^= mask;
2766
2767                 if (mask & IFCAP_HWCSUM) {
2768                         if (ifp->if_capenable & IFCAP_TXCSUM)
2769                                 ifp->if_hwassist = RE_CSUM_FEATURES;
2770                         else
2771                                 ifp->if_hwassist = 0;
2772                 }
2773                 if (mask && (ifp->if_flags & IFF_RUNNING))
2774                         re_init(sc);
2775                 break;
2776
2777         default:
2778                 error = ether_ioctl(ifp, command, data);
2779                 break;
2780         }
2781         return(error);
2782 }
2783
2784 static void
2785 re_watchdog(struct ifnet *ifp)
2786 {
2787         struct re_softc *sc = ifp->if_softc;
2788
2789         ASSERT_SERIALIZED(ifp->if_serializer);
2790
2791         if_printf(ifp, "watchdog timeout\n");
2792
2793         ifp->if_oerrors++;
2794
2795         re_txeof(sc);
2796         re_rxeof(sc);
2797
2798         re_init(sc);
2799
2800         if (!ifq_is_empty(&ifp->if_snd))
2801                 if_devstart(ifp);
2802 }
2803
2804 /*
2805  * Stop the adapter and free any mbufs allocated to the
2806  * RX and TX lists.
2807  */
2808 static void
2809 re_stop(struct re_softc *sc)
2810 {
2811         struct ifnet *ifp = &sc->arpcom.ac_if;
2812         int i;
2813
2814         ASSERT_SERIALIZED(ifp->if_serializer);
2815
2816         /* Reset the adapter. */
2817         re_reset(sc, ifp->if_flags & IFF_RUNNING);
2818
2819         ifp->if_timer = 0;
2820         callout_stop(&sc->re_timer);
2821
2822         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2823         sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2824
2825         CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2826         CSR_WRITE_2(sc, RE_IMR, 0x0000);
2827         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2828
2829         re_free_rxchain(sc);
2830
2831         /* Free the TX list buffers. */
2832         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2833                 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2834                         bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2835                                           sc->re_ldata.re_tx_dmamap[i]);
2836                         m_freem(sc->re_ldata.re_tx_mbuf[i]);
2837                         sc->re_ldata.re_tx_mbuf[i] = NULL;
2838                 }
2839         }
2840
2841         /* Free the RX list buffers. */
2842         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2843                 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2844                         if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2845                                 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
2846                                                   sc->re_ldata.re_rx_dmamap[i]);
2847                         }
2848                         m_freem(sc->re_ldata.re_rx_mbuf[i]);
2849                         sc->re_ldata.re_rx_mbuf[i] = NULL;
2850                 }
2851         }
2852 }
2853
2854 /*
2855  * Device suspend routine.  Stop the interface and save some PCI
2856  * settings in case the BIOS doesn't restore them properly on
2857  * resume.
2858  */
2859 static int
2860 re_suspend(device_t dev)
2861 {
2862 #ifndef BURN_BRIDGES
2863         int i;
2864 #endif
2865         struct re_softc *sc = device_get_softc(dev);
2866         struct ifnet *ifp = &sc->arpcom.ac_if;
2867
2868         lwkt_serialize_enter(ifp->if_serializer);
2869
2870         re_stop(sc);
2871
2872 #ifndef BURN_BRIDGES
2873         for (i = 0; i < 5; i++)
2874                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2875         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2876         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2877         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2878         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2879 #endif
2880
2881         sc->re_flags |= RE_F_SUSPENDED;
2882
2883         lwkt_serialize_exit(ifp->if_serializer);
2884
2885         return (0);
2886 }
2887
2888 /*
2889  * Device resume routine.  Restore some PCI settings in case the BIOS
2890  * doesn't, re-enable busmastering, and restart the interface if
2891  * appropriate.
2892  */
2893 static int
2894 re_resume(device_t dev)
2895 {
2896         struct re_softc *sc = device_get_softc(dev);
2897         struct ifnet *ifp = &sc->arpcom.ac_if;
2898 #ifndef BURN_BRIDGES
2899         int i;
2900 #endif
2901
2902         lwkt_serialize_enter(ifp->if_serializer);
2903
2904 #ifndef BURN_BRIDGES
2905         /* better way to do this? */
2906         for (i = 0; i < 5; i++)
2907                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2908         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2909         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2910         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2911         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2912
2913         /* reenable busmastering */
2914         pci_enable_busmaster(dev);
2915         pci_enable_io(dev, SYS_RES_IOPORT);
2916 #endif
2917
2918         /* reinitialize interface if necessary */
2919         if (ifp->if_flags & IFF_UP)
2920                 re_init(sc);
2921
2922         sc->re_flags &= ~RE_F_SUSPENDED;
2923
2924         lwkt_serialize_exit(ifp->if_serializer);
2925
2926         return (0);
2927 }
2928
2929 /*
2930  * Stop all chip I/O so that the kernel's probe routines don't
2931  * get confused by errant DMAs when rebooting.
2932  */
2933 static void
2934 re_shutdown(device_t dev)
2935 {
2936         struct re_softc *sc = device_get_softc(dev);
2937         struct ifnet *ifp = &sc->arpcom.ac_if;
2938
2939         lwkt_serialize_enter(ifp->if_serializer);
2940         re_stop(sc);
2941         lwkt_serialize_exit(ifp->if_serializer);
2942 }
2943
2944 static int
2945 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
2946 {
2947         struct re_softc *sc = arg1;
2948
2949         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
2950 }
2951
2952 static int
2953 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
2954 {
2955         struct re_softc *sc = arg1;
2956
2957         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
2958 }
2959
2960 static int
2961 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
2962 {
2963         struct re_softc *sc = arg1;
2964         struct ifnet *ifp = &sc->arpcom.ac_if;
2965         int error, v;
2966
2967         lwkt_serialize_enter(ifp->if_serializer);
2968
2969         v = *hwtime;
2970         error = sysctl_handle_int(oidp, &v, 0, req);
2971         if (error || req->newptr == NULL)
2972                 goto back;
2973
2974         if (v <= 0) {
2975                 error = EINVAL;
2976                 goto back;
2977         }
2978
2979         if (v != *hwtime) {
2980                 *hwtime = v;
2981
2982                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
2983                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
2984                         re_setup_hw_im(sc);
2985         }
2986 back:
2987         lwkt_serialize_exit(ifp->if_serializer);
2988         return error;
2989 }
2990
2991 static int
2992 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
2993 {
2994         struct re_softc *sc = arg1;
2995         struct ifnet *ifp = &sc->arpcom.ac_if;
2996         int error, v;
2997
2998         lwkt_serialize_enter(ifp->if_serializer);
2999
3000         v = sc->re_sim_time;
3001         error = sysctl_handle_int(oidp, &v, 0, req);
3002         if (error || req->newptr == NULL)
3003                 goto back;
3004
3005         if (v <= 0) {
3006                 error = EINVAL;
3007                 goto back;
3008         }
3009
3010         if (v != sc->re_sim_time) {
3011                 sc->re_sim_time = v;
3012
3013                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3014                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3015 #ifdef foo
3016                         int reg;
3017
3018                         /*
3019                          * Following code causes various strange
3020                          * performance problems.  Hmm ...
3021                          */
3022                         CSR_WRITE_2(sc, RE_IMR, 0);
3023                         if (!RE_IS_8139CP(sc))
3024                                 reg = RE_TIMERINT_8169;
3025                         else
3026                                 reg = RE_TIMERINT;
3027                         CSR_WRITE_4(sc, reg, 0);
3028                         CSR_READ_4(sc, reg); /* flush */
3029
3030                         CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3031                         re_setup_sim_im(sc);
3032 #else
3033                         re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3034                         DELAY(10);
3035                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3036 #endif
3037                 }
3038         }
3039 back:
3040         lwkt_serialize_exit(ifp->if_serializer);
3041         return error;
3042 }
3043
3044 static int
3045 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3046 {
3047         struct re_softc *sc = arg1;
3048         struct ifnet *ifp = &sc->arpcom.ac_if;
3049         int error, v;
3050
3051         lwkt_serialize_enter(ifp->if_serializer);
3052
3053         v = sc->re_imtype;
3054         error = sysctl_handle_int(oidp, &v, 0, req);
3055         if (error || req->newptr == NULL)
3056                 goto back;
3057
3058         if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3059                 error = EINVAL;
3060                 goto back;
3061         }
3062         if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3063                 /* Can't do hardware interrupt moderation */
3064                 error = EOPNOTSUPP;
3065                 goto back;
3066         }
3067
3068         if (v != sc->re_imtype) {
3069                 sc->re_imtype = v;
3070                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3071                     IFF_RUNNING)
3072                         re_setup_intr(sc, 1, sc->re_imtype);
3073         }
3074 back:
3075         lwkt_serialize_exit(ifp->if_serializer);
3076         return error;
3077 }
3078
3079 static void
3080 re_setup_hw_im(struct re_softc *sc)
3081 {
3082         KKASSERT(sc->re_caps & RE_C_HWIM);
3083
3084         /*
3085          * Interrupt moderation
3086          *
3087          * 0xABCD
3088          * A - unknown (maybe TX related)
3089          * B - TX timer (unit: 25us)
3090          * C - unknown (maybe RX related)
3091          * D - RX timer (unit: 25us)
3092          *
3093          *
3094          * re(4)'s interrupt moderation is actually controlled by
3095          * two variables, like most other NICs (bge, bce etc.)
3096          * o  timer
3097          * o  number of packets [P]
3098          *
3099          * The logic relationship between these two variables is
3100          * similar to other NICs too:
3101          * if (timer expire || packets > [P])
3102          *     Interrupt is delivered
3103          *
3104          * Currently we only know how to set 'timer', but not
3105          * 'number of packets', which should be ~30, as far as I
3106          * tested (sink ~900Kpps, interrupt rate is 30KHz)
3107          */
3108         CSR_WRITE_2(sc, RE_IM,
3109                     RE_IM_RXTIME(sc->re_rx_time) |
3110                     RE_IM_TXTIME(sc->re_tx_time) |
3111                     RE_IM_MAGIC);
3112 }
3113
3114 static void
3115 re_disable_hw_im(struct re_softc *sc)
3116 {
3117         if (sc->re_caps & RE_C_HWIM)
3118                 CSR_WRITE_2(sc, RE_IM, 0);
3119 }
3120
3121 static void
3122 re_setup_sim_im(struct re_softc *sc)
3123 {
3124         if (!RE_IS_8139CP(sc)) {
3125                 uint32_t ticks;
3126
3127                 /*
3128                  * Datasheet says tick decreases at bus speed,
3129                  * but it seems the clock runs a little bit
3130                  * faster, so we do some compensation here.
3131                  */
3132                 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3133                 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3134         } else {
3135                 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3136         }
3137         CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3138         sc->re_flags |= RE_F_TIMER_INTR;
3139 }
3140
3141 static void
3142 re_disable_sim_im(struct re_softc *sc)
3143 {
3144         if (!RE_IS_8139CP(sc))
3145                 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3146         else
3147                 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3148         sc->re_flags &= ~RE_F_TIMER_INTR;
3149 }
3150
3151 static void
3152 re_config_imtype(struct re_softc *sc, int imtype)
3153 {
3154         switch (imtype) {
3155         case RE_IMTYPE_HW:
3156                 KKASSERT(sc->re_caps & RE_C_HWIM);
3157                 /* FALL THROUGH */
3158         case RE_IMTYPE_NONE:
3159                 sc->re_intrs = RE_INTRS;
3160                 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3161                                 RE_ISR_RX_OVERRUN;
3162                 sc->re_tx_ack = RE_ISR_TX_OK;
3163                 break;
3164
3165         case RE_IMTYPE_SIM:
3166                 sc->re_intrs = RE_INTRS_TIMER;
3167                 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3168                 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3169                 break;
3170
3171         default:
3172                 panic("%s: unknown imtype %d",
3173                       sc->arpcom.ac_if.if_xname, imtype);
3174         }
3175 }
3176
3177 static void
3178 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3179 {
3180         re_config_imtype(sc, imtype);
3181
3182         if (enable_intrs)
3183                 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3184         else
3185                 CSR_WRITE_2(sc, RE_IMR, 0);
3186
3187         switch (imtype) {
3188         case RE_IMTYPE_NONE:
3189                 re_disable_sim_im(sc);
3190                 re_disable_hw_im(sc);
3191                 break;
3192
3193         case RE_IMTYPE_HW:
3194                 KKASSERT(sc->re_caps & RE_C_HWIM);
3195                 re_disable_sim_im(sc);
3196                 re_setup_hw_im(sc);
3197                 break;
3198
3199         case RE_IMTYPE_SIM:
3200                 re_disable_hw_im(sc);
3201                 re_setup_sim_im(sc);
3202                 break;
3203
3204         default:
3205                 panic("%s: unknown imtype %d",
3206                       sc->arpcom.ac_if.if_xname, imtype);
3207         }
3208 }
3209
3210 static void
3211 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3212 {
3213         int i;
3214
3215         if (sc->re_macver == RE_MACVER_11 ||
3216             sc->re_macver == RE_MACVER_12 ||
3217             sc->re_macver == RE_MACVER_30 ||
3218             sc->re_macver == RE_MACVER_31) {
3219                 uint16_t re_did;
3220
3221                 re_get_eewidth(sc);
3222                 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3223                 if (re_did == 0x8128) {
3224                         uint16_t as[ETHER_ADDR_LEN / 2];
3225                         int eaddr_off;
3226
3227                         if (sc->re_macver == RE_MACVER_30 ||
3228                             sc->re_macver == RE_MACVER_31)
3229                                 eaddr_off = RE_EE_EADDR1;
3230                         else
3231                                 eaddr_off = RE_EE_EADDR0;
3232
3233                         /*
3234                          * Get station address from the EEPROM.
3235                          */
3236                         re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3);
3237                         for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3238                                 as[i] = le16toh(as[i]);
3239                         bcopy(as, eaddr, sizeof(eaddr));
3240                         return;
3241                 }
3242         }
3243
3244         /*
3245          * Get station address from IDRx.
3246          */
3247         for (i = 0; i < ETHER_ADDR_LEN; ++i)
3248                 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3249 }
3250
3251 static int
3252 re_jpool_alloc(struct re_softc *sc)
3253 {
3254         struct re_list_data *ldata = &sc->re_ldata;
3255         struct re_jbuf *jbuf;
3256         bus_addr_t paddr;
3257         bus_size_t jpool_size;
3258         bus_dmamem_t dmem;
3259         caddr_t buf;
3260         int i, error;
3261
3262         lwkt_serialize_init(&ldata->re_jbuf_serializer);
3263
3264         ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3265                                  M_DEVBUF, M_WAITOK | M_ZERO);
3266
3267         jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3268
3269         error = bus_dmamem_coherent(sc->re_parent_tag,
3270                         RE_RXBUF_ALIGN, 0,
3271                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3272                         jpool_size, BUS_DMA_WAITOK, &dmem);
3273         if (error) {
3274                 device_printf(sc->re_dev, "could not allocate jumbo memory\n");
3275                 return error;
3276         }
3277         ldata->re_jpool_tag = dmem.dmem_tag;
3278         ldata->re_jpool_map = dmem.dmem_map;
3279         ldata->re_jpool = dmem.dmem_addr;
3280         paddr = dmem.dmem_busaddr;
3281
3282         /* ..and split it into 9KB chunks */
3283         SLIST_INIT(&ldata->re_jbuf_free);
3284
3285         buf = ldata->re_jpool;
3286         for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3287                 jbuf = &ldata->re_jbuf[i];
3288
3289                 jbuf->re_sc = sc;
3290                 jbuf->re_inuse = 0;
3291                 jbuf->re_slot = i;
3292                 jbuf->re_buf = buf;
3293                 jbuf->re_paddr = paddr;
3294
3295                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3296
3297                 buf += RE_JBUF_SIZE;
3298                 paddr += RE_JBUF_SIZE;
3299         }
3300         return 0;
3301 }
3302
3303 static void
3304 re_jpool_free(struct re_softc *sc)
3305 {
3306         struct re_list_data *ldata = &sc->re_ldata;
3307
3308         if (ldata->re_jpool_tag != NULL) {
3309                 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3310                 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3311                                 ldata->re_jpool_map);
3312                 bus_dma_tag_destroy(ldata->re_jpool_tag);
3313                 ldata->re_jpool_tag = NULL;
3314         }
3315
3316         if (ldata->re_jbuf != NULL) {
3317                 kfree(ldata->re_jbuf, M_DEVBUF);
3318                 ldata->re_jbuf = NULL;
3319         }
3320 }
3321
3322 static struct re_jbuf *
3323 re_jbuf_alloc(struct re_softc *sc)
3324 {
3325         struct re_list_data *ldata = &sc->re_ldata;
3326         struct re_jbuf *jbuf;
3327
3328         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3329
3330         jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3331         if (jbuf != NULL) {
3332                 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3333                 jbuf->re_inuse = 1;
3334         }
3335
3336         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3337
3338         return jbuf;
3339 }
3340
3341 static void
3342 re_jbuf_free(void *arg)
3343 {
3344         struct re_jbuf *jbuf = arg;
3345         struct re_softc *sc = jbuf->re_sc;
3346         struct re_list_data *ldata = &sc->re_ldata;
3347
3348         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3349                 panic("%s: free wrong jumbo buffer",
3350                       sc->arpcom.ac_if.if_xname);
3351         } else if (jbuf->re_inuse == 0) {
3352                 panic("%s: jumbo buffer already freed",
3353                       sc->arpcom.ac_if.if_xname);
3354         }
3355
3356         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3357         atomic_subtract_int(&jbuf->re_inuse, 1);
3358         if (jbuf->re_inuse == 0)
3359                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3360         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3361 }
3362
3363 static void
3364 re_jbuf_ref(void *arg)
3365 {
3366         struct re_jbuf *jbuf = arg;
3367         struct re_softc *sc = jbuf->re_sc;
3368         struct re_list_data *ldata = &sc->re_ldata;
3369
3370         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3371                 panic("%s: ref wrong jumbo buffer",
3372                       sc->arpcom.ac_if.if_xname);
3373         } else if (jbuf->re_inuse == 0) {
3374                 panic("%s: jumbo buffer already freed",
3375                       sc->arpcom.ac_if.if_xname);
3376         }
3377         atomic_add_int(&jbuf->re_inuse, 1);
3378 }