sys/platform/pc32/apic/apic_vector.s

   1 /*
   2  *      from: vector.s, 386BSD 0.1 unknown origin
   3  * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $
   4  * $DragonFly: src/sys/platform/pc32/apic/apic_vector.s,v 1.37 2008/01/14 15:27:16 dillon Exp $
   5  */
   6
   7 #include "use_npx.h"
   8 #include "opt_auto_eoi.h"
   9
  10 #include <machine/asmacros.h>
  11 #include <machine/lock.h>
  12 #include <machine/psl.h>
  13 #include <machine/trap.h>
  14
  15 #include <machine_base/icu/icu.h>
  16 #include <bus/isa/i386/isa.h>
  17
  18 #include "assym.s"
  19
  20 #include "apicreg.h"
  21 #include "apic_ipl.h"
  22 #include <machine/smp.h>
  23 #include <machine_base/isa/intr_machdep.h>
  24
  25 /* convert an absolute IRQ# into a bitmask */
  26 #define IRQ_LBIT(irq_num)       (1 << (irq_num))
  27
  28 /* make an index into the IO APIC from the IRQ# */
  29 #define REDTBL_IDX(irq_num)     (0x10 + ((irq_num) * 2))
  30
  31 #ifdef SMP
  32 #define MPLOCKED     lock ;
  33 #else
  34 #define MPLOCKED
  35 #endif
  36
  37 /*
  38  * Push an interrupt frame in a format acceptable to doreti, reload
  39  * the segment registers for the kernel.
  40  */
  41 #define PUSH_FRAME                                                      \
  42         pushl   $0 ;            /* dummy error code */                  \
  43         pushl   $0 ;            /* dummy trap type */                   \
  44         pushl   $0 ;            /* dummy xflags type */                 \
  45         pushal ;                                                        \
  46         pushl   %ds ;           /* save data and extra segments ... */  \
  47         pushl   %es ;                                                   \
  48         pushl   %fs ;                                                   \
  49         pushl   %gs ;                                                   \
  50         mov     $KDSEL,%ax ;                                            \
  51         mov     %ax,%ds ;                                               \
  52         mov     %ax,%es ;                                               \
  53         mov     %ax,%gs ;                                               \
  54         mov     $KPSEL,%ax ;                                            \
  55         mov     %ax,%fs ;                                               \
  56
  57 #define PUSH_DUMMY                                                      \
  58         pushfl ;                /* phys int frame / flags */            \
  59         pushl %cs ;             /* phys int frame / cs */               \
  60         pushl   12(%esp) ;      /* original caller eip */               \
  61         pushl   $0 ;            /* dummy error code */                  \
  62         pushl   $0 ;            /* dummy trap type */                   \
  63         pushl   $0 ;            /* dummy xflags type */                 \
  64         subl    $13*4,%esp ;    /* pushal + 4 seg regs (dummy) + CPL */ \
  65
  66 /*
  67  * Warning: POP_FRAME can only be used if there is no chance of a
  68  * segment register being changed (e.g. by procfs), which is why syscalls
  69  * have to use doreti.
  70  */
  71 #define POP_FRAME                                                       \
  72         popl    %gs ;                                                   \
  73         popl    %fs ;                                                   \
  74         popl    %es ;                                                   \
  75         popl    %ds ;                                                   \
  76         popal ;                                                         \
  77         addl    $3*4,%esp ;     /* dummy xflags, trap & error codes */  \
  78
  79 #define POP_DUMMY                                                       \
  80         addl    $19*4,%esp ;                                            \
  81
  82 #define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
  83 #define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
  84
  85 #define MASK_IRQ(irq_num)                                               \
  86         APIC_IMASK_LOCK ;                       /* into critical reg */ \
  87         testl   $IRQ_LBIT(irq_num), apic_imen ;                         \
  88         jne     7f ;                    /* masked, don't mask */        \
  89         orl     $IRQ_LBIT(irq_num), apic_imen ; /* set the mask bit */  \
  90         movl    IOAPICADDR(irq_num), %ecx ;     /* ioapic addr */       \
  91         movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
  92         movl    %eax, (%ecx) ;                  /* write the index */   \
  93         movl    IOAPIC_WINDOW(%ecx), %eax ;     /* current value */     \
  94         orl     $IOART_INTMASK, %eax ;          /* set the mask */      \
  95         movl    %eax, IOAPIC_WINDOW(%ecx) ;     /* new value */         \
  96 7: ;                                            /* already masked */    \
  97         APIC_IMASK_UNLOCK ;                                             \
  98
  99 /*
 100  * Test to see whether we are handling an edge or level triggered INT.
 101  *  Level-triggered INTs must still be masked as we don't clear the source,
 102  *  and the EOI cycle would cause redundant INTs to occur.
 103  */
 104 #define MASK_LEVEL_IRQ(irq_num)                                         \
 105         testl   $IRQ_LBIT(irq_num), apic_pin_trigger ;                  \
 106         jz      9f ;                            /* edge, don't mask */  \
 107         MASK_IRQ(irq_num) ;                                             \
 108 9: ;                                                                    \
 109
 110 /*
 111  * Test to see if the source is currntly masked, clear if so.
 112  */
 113 #define UNMASK_IRQ(irq_num)                                     \
 114         cmpl    $0,%eax ;                                               \
 115         jnz     8f ;                                                    \
 116         APIC_IMASK_LOCK ;                       /* into critical reg */ \
 117         testl   $IRQ_LBIT(irq_num), apic_imen ;                         \
 118         je      7f ;                    /* bit clear, not masked */     \
 119         andl    $~IRQ_LBIT(irq_num), apic_imen ;/* clear mask bit */    \
 120         movl    IOAPICADDR(irq_num),%ecx ;      /* ioapic addr */       \
 121         movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
 122         movl    %eax,(%ecx) ;                   /* write the index */   \
 123         movl    IOAPIC_WINDOW(%ecx),%eax ;      /* current value */     \
 124         andl    $~IOART_INTMASK,%eax ;          /* clear the mask */    \
 125         movl    %eax,IOAPIC_WINDOW(%ecx) ;      /* new value */         \
 126 7: ;                                                                    \
 127         APIC_IMASK_UNLOCK ;                                             \
 128 8: ;                                                                    \
 129
 130 #ifdef APIC_IO
 131
 132 /*
 133  * Fast interrupt call handlers run in the following sequence:
 134  *
 135  *      - Push the trap frame required by doreti
 136  *      - Mask the interrupt and reenable its source
 137  *      - If we cannot take the interrupt set its fpending bit and
 138  *        doreti.  Note that we cannot mess with mp_lock at all
 139  *        if we entered from a critical section!
 140  *      - If we can take the interrupt clear its fpending bit,
 141  *        call the handler, then unmask and doreti.
 142  *
 143  * YYY can cache gd base opitner instead of using hidden %fs prefixes.
 144  */
 145
 146 #define FAST_INTR(irq_num, vec_name)                                    \
 147         .text ;                                                         \
 148         SUPERALIGN_TEXT ;                                               \
 149 IDTVEC(vec_name) ;                                                      \
 150         PUSH_FRAME ;                                                    \
 151         FAKE_MCOUNT(15*4(%esp)) ;                                       \
 152         MASK_LEVEL_IRQ(irq_num) ;                                       \
 153         movl    $0, lapic_eoi ;                                         \
 154         movl    PCPU(curthread),%ebx ;                                  \
 155         movl    $0,%eax ;       /* CURRENT CPL IN FRAME (REMOVED) */    \
 156         pushl   %eax ;                                                  \
 157         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 158         jne     1f ;                                                    \
 159         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 160         jl      2f ;                                                    \
 161 1: ;                                                                    \
 162         /* in critical section, make interrupt pending */               \
 163         /* set the pending bit and return, leave interrupt masked */    \
 164         orl     $IRQ_LBIT(irq_num),PCPU(fpending) ;                     \
 165         orl     $RQF_INTPEND,PCPU(reqflags) ;                           \
 166         jmp     5f ;                                                    \
 167 2: ;                                                                    \
 168         /* clear pending bit, run handler */                            \
 169         andl    $~IRQ_LBIT(irq_num),PCPU(fpending) ;                    \
 170         pushl   $irq_num ;                                              \
 171         pushl   %esp ;                   /* pass frame by reference */  \
 172         call    ithread_fast_handler ;   /* returns 0 to unmask */      \
 173         addl    $8, %esp ;                                              \
 174         UNMASK_IRQ(irq_num) ;                                           \
 175 5: ;                                                                    \
 176         MEXITCOUNT ;                                                    \
 177         jmp     doreti ;                                                \
 178
 179 /*
 180  * Slow interrupt call handlers run in the following sequence:
 181  *
 182  *      - Push the trap frame required by doreti.
 183  *      - Mask the interrupt and reenable its source.
 184  *      - If we cannot take the interrupt set its ipending bit and
 185  *        doreti.  In addition to checking for a critical section
 186  *        and cpl mask we also check to see if the thread is still
 187  *        running.  Note that we cannot mess with mp_lock at all
 188  *        if we entered from a critical section!
 189  *      - If we can take the interrupt clear its ipending bit
 190  *        and schedule the thread.  Leave interrupts masked and doreti.
 191  *
 192  *      Note that calls to sched_ithd() are made with interrupts enabled
 193  *      and outside a critical section.  YYY sched_ithd may preempt us
 194  *      synchronously (fix interrupt stacking).
 195  *
 196  *      YYY can cache gd base pointer instead of using hidden %fs
 197  *      prefixes.
 198  */
 199
 200 #define SLOW_INTR(irq_num, vec_name, maybe_extra_ipending)              \
 201         .text ;                                                         \
 202         SUPERALIGN_TEXT ;                                               \
 203 IDTVEC(vec_name) ;                                                      \
 204         PUSH_FRAME ;                                                    \
 205         maybe_extra_ipending ;                                          \
 206 ;                                                                       \
 207         MASK_LEVEL_IRQ(irq_num) ;                                       \
 208         incl    PCPU(cnt) + V_INTR ;                                    \
 209         movl    $0, lapic_eoi ;                                         \
 210         movl    PCPU(curthread),%ebx ;                                  \
 211         movl    $0,%eax ;       /* CURRENT CPL IN FRAME (REMOVED) */    \
 212         pushl   %eax ;          /* cpl do restore */                    \
 213         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 214         jne     1f ;                                                    \
 215         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 216         jl      2f ;                                                    \
 217 1: ;                                                                    \
 218         /* set the pending bit and return, leave the interrupt masked */ \
 219         orl     $IRQ_LBIT(irq_num), PCPU(ipending) ;                    \
 220         orl     $RQF_INTPEND,PCPU(reqflags) ;                           \
 221         jmp     5f ;                                                    \
 222 2: ;                                                                    \
 223         /* set running bit, clear pending bit, run handler */           \
 224         andl    $~IRQ_LBIT(irq_num), PCPU(ipending) ;                   \
 225         incl    TD_NEST_COUNT(%ebx) ;                                   \
 226         sti ;                                                           \
 227         pushl   $irq_num ;                                              \
 228         call    sched_ithd ;                                            \
 229         addl    $4,%esp ;                                               \
 230         cli ;                                                           \
 231         decl    TD_NEST_COUNT(%ebx) ;                                   \
 232 5: ;                                                                    \
 233         MEXITCOUNT ;                                                    \
 234         jmp     doreti ;                                                \
 235
 236 /*
 237  * Wrong interrupt call handlers.  We program these into APIC vectors
 238  * that should otherwise never occur.  For example, we program the SLOW
 239  * vector for irq N with this when we program the FAST vector with the
 240  * real interrupt.
 241  *
 242  * XXX for now all we can do is EOI it.  We can't call do_wrongintr
 243  * (yet) because we could be in a critical section.
 244  */
 245 #define WRONGINTR(irq_num,vec_name)                                     \
 246         .text ;                                                         \
 247         SUPERALIGN_TEXT  ;                                              \
 248 IDTVEC(vec_name) ;                                                      \
 249         PUSH_FRAME ;                                                    \
 250         movl    $0, lapic_eoi ; /* End Of Interrupt to APIC */          \
 251         /*pushl $irq_num ;*/                                            \
 252         /*call  do_wrongintr ;*/                                        \
 253         /*addl  $4,%esp ;*/                                             \
 254         POP_FRAME ;                                                     \
 255         iret  ;                                                         \
 256
 257 #endif
 258
 259 /*
 260  * Handle "spurious INTerrupts".
 261  * Notes:
 262  *  This is different than the "spurious INTerrupt" generated by an
 263  *   8259 PIC for missing INTs.  See the APIC documentation for details.
 264  *  This routine should NOT do an 'EOI' cycle.
 265  */
 266         .text
 267         SUPERALIGN_TEXT
 268         .globl Xspuriousint
 269 Xspuriousint:
 270
 271         /* No EOI cycle used here */
 272
 273         iret
 274
 275
 276 /*
 277  * Handle TLB shootdowns.
 278  */
 279         .text
 280         SUPERALIGN_TEXT
 281         .globl  Xinvltlb
 282 Xinvltlb:
 283         pushl   %eax
 284
 285         movl    %cr3, %eax              /* invalidate the TLB */
 286         movl    %eax, %cr3
 287
 288         ss                              /* stack segment, avoid %ds load */
 289         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 290
 291         popl    %eax
 292         iret
 293
 294
 295 /*
 296  * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
 297  *
 298  *  - Signals its receipt.
 299  *  - Waits for permission to restart.
 300  *  - Processing pending IPIQ events while waiting.
 301  *  - Signals its restart.
 302  */
 303
 304         .text
 305         SUPERALIGN_TEXT
 306         .globl Xcpustop
 307 Xcpustop:
 308         pushl   %ebp
 309         movl    %esp, %ebp
 310         pushl   %eax
 311         pushl   %ecx
 312         pushl   %edx
 313         pushl   %ds                     /* save current data segment */
 314         pushl   %fs
 315
 316         movl    $KDSEL, %eax
 317         mov     %ax, %ds                /* use KERNEL data segment */
 318         movl    $KPSEL, %eax
 319         mov     %ax, %fs
 320
 321         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 322
 323         movl    PCPU(cpuid), %eax
 324         imull   $PCB_SIZE, %eax
 325         leal    CNAME(stoppcbs)(%eax), %eax
 326         pushl   %eax
 327         call    CNAME(savectx)          /* Save process context */
 328         addl    $4, %esp
 329
 330
 331         movl    PCPU(cpuid), %eax
 332
 333         /*
 334          * Indicate that we have stopped and loop waiting for permission
 335          * to start again.  We must still process IPI events while in a
 336          * stopped state.
 337          */
 338         MPLOCKED
 339         btsl    %eax, stopped_cpus      /* stopped_cpus |= (1<<id) */
 340 1:
 341         andl    $~RQF_IPIQ,PCPU(reqflags)
 342         pushl   %eax
 343         call    lwkt_smp_stopped
 344         popl    %eax
 345         btl     %eax, started_cpus      /* while (!(started_cpus & (1<<id))) */
 346         jnc     1b
 347
 348         MPLOCKED
 349         btrl    %eax, started_cpus      /* started_cpus &= ~(1<<id) */
 350         MPLOCKED
 351         btrl    %eax, stopped_cpus      /* stopped_cpus &= ~(1<<id) */
 352
 353         test    %eax, %eax
 354         jnz     2f
 355
 356         movl    CNAME(cpustop_restartfunc), %eax
 357         test    %eax, %eax
 358         jz      2f
 359         movl    $0, CNAME(cpustop_restartfunc)  /* One-shot */
 360
 361         call    *%eax
 362 2:
 363         popl    %fs
 364         popl    %ds                     /* restore previous data segment */
 365         popl    %edx
 366         popl    %ecx
 367         popl    %eax
 368         movl    %ebp, %esp
 369         popl    %ebp
 370         iret
 371
 372         /*
 373          * For now just have one ipiq IPI, but what we really want is
 374          * to have one for each source cpu to the APICs don't get stalled
 375          * backlogging the requests.
 376          */
 377         .text
 378         SUPERALIGN_TEXT
 379         .globl Xipiq
 380 Xipiq:
 381         PUSH_FRAME
 382         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 383         FAKE_MCOUNT(15*4(%esp))
 384
 385         movl    PCPU(curthread),%ebx
 386         cmpl    $TDPRI_CRIT,TD_PRI(%ebx)
 387         jge     1f
 388         subl    $8,%esp                 /* make same as interrupt frame */
 389         pushl   %esp                    /* pass frame by reference */
 390         incl    PCPU(intr_nesting_level)
 391         addl    $TDPRI_CRIT,TD_PRI(%ebx)
 392         call    lwkt_process_ipiq_frame
 393         subl    $TDPRI_CRIT,TD_PRI(%ebx)
 394         decl    PCPU(intr_nesting_level)
 395         addl    $12,%esp
 396         pushl   $0                      /* CPL for frame (REMOVED) */
 397         MEXITCOUNT
 398         jmp     doreti
 399 1:
 400         orl     $RQF_IPIQ,PCPU(reqflags)
 401         MEXITCOUNT
 402         POP_FRAME
 403         iret
 404
 405 #ifdef APIC_IO
 406
 407 MCOUNT_LABEL(bintr)
 408         FAST_INTR(0,apic_fastintr0)
 409         FAST_INTR(1,apic_fastintr1)
 410         FAST_INTR(2,apic_fastintr2)
 411         FAST_INTR(3,apic_fastintr3)
 412         FAST_INTR(4,apic_fastintr4)
 413         FAST_INTR(5,apic_fastintr5)
 414         FAST_INTR(6,apic_fastintr6)
 415         FAST_INTR(7,apic_fastintr7)
 416         FAST_INTR(8,apic_fastintr8)
 417         FAST_INTR(9,apic_fastintr9)
 418         FAST_INTR(10,apic_fastintr10)
 419         FAST_INTR(11,apic_fastintr11)
 420         FAST_INTR(12,apic_fastintr12)
 421         FAST_INTR(13,apic_fastintr13)
 422         FAST_INTR(14,apic_fastintr14)
 423         FAST_INTR(15,apic_fastintr15)
 424         FAST_INTR(16,apic_fastintr16)
 425         FAST_INTR(17,apic_fastintr17)
 426         FAST_INTR(18,apic_fastintr18)
 427         FAST_INTR(19,apic_fastintr19)
 428         FAST_INTR(20,apic_fastintr20)
 429         FAST_INTR(21,apic_fastintr21)
 430         FAST_INTR(22,apic_fastintr22)
 431         FAST_INTR(23,apic_fastintr23)
 432
 433         /* YYY what is this garbage? */
 434
 435         SLOW_INTR(0,apic_slowintr0,)
 436         SLOW_INTR(1,apic_slowintr1,)
 437         SLOW_INTR(2,apic_slowintr2,)
 438         SLOW_INTR(3,apic_slowintr3,)
 439         SLOW_INTR(4,apic_slowintr4,)
 440         SLOW_INTR(5,apic_slowintr5,)
 441         SLOW_INTR(6,apic_slowintr6,)
 442         SLOW_INTR(7,apic_slowintr7,)
 443         SLOW_INTR(8,apic_slowintr8,)
 444         SLOW_INTR(9,apic_slowintr9,)
 445         SLOW_INTR(10,apic_slowintr10,)
 446         SLOW_INTR(11,apic_slowintr11,)
 447         SLOW_INTR(12,apic_slowintr12,)
 448         SLOW_INTR(13,apic_slowintr13,)
 449         SLOW_INTR(14,apic_slowintr14,)
 450         SLOW_INTR(15,apic_slowintr15,)
 451         SLOW_INTR(16,apic_slowintr16,)
 452         SLOW_INTR(17,apic_slowintr17,)
 453         SLOW_INTR(18,apic_slowintr18,)
 454         SLOW_INTR(19,apic_slowintr19,)
 455         SLOW_INTR(20,apic_slowintr20,)
 456         SLOW_INTR(21,apic_slowintr21,)
 457         SLOW_INTR(22,apic_slowintr22,)
 458         SLOW_INTR(23,apic_slowintr23,)
 459
 460         WRONGINTR(0,apic_wrongintr0)
 461         WRONGINTR(1,apic_wrongintr1)
 462         WRONGINTR(2,apic_wrongintr2)
 463         WRONGINTR(3,apic_wrongintr3)
 464         WRONGINTR(4,apic_wrongintr4)
 465         WRONGINTR(5,apic_wrongintr5)
 466         WRONGINTR(6,apic_wrongintr6)
 467         WRONGINTR(7,apic_wrongintr7)
 468         WRONGINTR(8,apic_wrongintr8)
 469         WRONGINTR(9,apic_wrongintr9)
 470         WRONGINTR(10,apic_wrongintr10)
 471         WRONGINTR(11,apic_wrongintr11)
 472         WRONGINTR(12,apic_wrongintr12)
 473         WRONGINTR(13,apic_wrongintr13)
 474         WRONGINTR(14,apic_wrongintr14)
 475         WRONGINTR(15,apic_wrongintr15)
 476         WRONGINTR(16,apic_wrongintr16)
 477         WRONGINTR(17,apic_wrongintr17)
 478         WRONGINTR(18,apic_wrongintr18)
 479         WRONGINTR(19,apic_wrongintr19)
 480         WRONGINTR(20,apic_wrongintr20)
 481         WRONGINTR(21,apic_wrongintr21)
 482         WRONGINTR(22,apic_wrongintr22)
 483         WRONGINTR(23,apic_wrongintr23)
 484 MCOUNT_LABEL(eintr)
 485
 486 #endif
 487
 488         .data
 489
 490 /* variables used by stop_cpus()/restart_cpus()/Xcpustop */
 491         .globl stopped_cpus, started_cpus
 492 stopped_cpus:
 493         .long   0
 494 started_cpus:
 495         .long   0
 496
 497         .globl CNAME(cpustop_restartfunc)
 498 CNAME(cpustop_restartfunc):
 499         .long 0
 500
 501         .globl  apic_pin_trigger
 502 apic_pin_trigger:
 503         .long   0
 504
 505         .text
 506