sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id: i4b_ifpi_pci.c,v 1.4 2000/06/02 11:58:56 hm Exp $
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6.2.1 2001/08/10 14:08:37 obrien Exp $
  39  *
  40  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  41  *
  42  *---------------------------------------------------------------------------*/
  43
  44 #include "ifpi.h"
  45 #include "opt_i4b.h"
  46 #include "pci.h"
  47
  48 #if (NIFPI > 0) && (NPCI > 0)
  49
  50 #include <sys/param.h>
  51 #include <sys/kernel.h>
  52 #include <sys/systm.h>
  53 #include <sys/mbuf.h>
  54
  55 #include <machine/bus.h>
  56 #include <sys/bus.h>
  57 #include <sys/rman.h>
  58
  59 #include <pci/pcireg.h>
  60 #include <pci/pcivar.h>
  61
  62 #include <sys/socket.h>
  63 #include <net/if.h>
  64
  65 #include <machine/i4b_debug.h>
  66 #include <machine/i4b_ioctl.h>
  67 #include <machine/i4b_trace.h>
  68
  69 #include <i4b/include/i4b_global.h>
  70 #include <i4b/include/i4b_mbuf.h>
  71
  72 #include <i4b/layer1/i4b_l1.h>
  73 #include <i4b/layer1/isic/i4b_isic.h>
  74 #include <i4b/layer1/isic/i4b_isac.h>
  75 #include <i4b/layer1/isic/i4b_hscx.h>
  76
  77 #include <i4b/layer1/ifpi/i4b_ifpi_ext.h>
  78
  79 #define PCI_AVMA1_VID 0x1244
  80 #define PCI_AVMA1_DID 0x0a00
  81
  82 /* prototypes */
  83 static void avma1pp_disable(device_t);
  84
  85 static void avma1pp_intr(void *);
  86 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
  87 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
  88 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
  89 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  90 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  91 static void avma1pp_hscx_int_handler(struct l1_softc *);
  92 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
  93 static void avma1pp_init_linktab(struct l1_softc *);
  94 static void avma1pp_bchannel_setup(int, int, int, int);
  95 static void avma1pp_bchannel_start(int, int);
  96 static void avma1pp_hscx_init(struct l1_softc *, int, int);
  97 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
  98 static void avma1pp_set_linktab(int, int, drvr_link_t *);
  99 static isdn_link_t * avma1pp_ret_linktab(int, int);
 100 static int avma1pp_pci_probe(device_t);
 101 static int avma1pp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 102 int avma1pp_attach_avma1pp(device_t);
 103 static void ifpi_isac_intr(struct l1_softc *sc);
 104
 105 static device_method_t avma1pp_pci_methods[] = {
 106         /* Device interface */
 107         DEVMETHOD(device_probe,         avma1pp_pci_probe),
 108         DEVMETHOD(device_attach,        avma1pp_attach_avma1pp),
 109         DEVMETHOD(device_shutdown,      avma1pp_disable),
 110
 111         /* bus interface */
 112         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 113         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 114
 115         { 0, 0 }
 116 };
 117
 118 #if 0 /* use what's in l1_softc */
 119 /* a minimal softc for the Fritz!Card PCI */
 120 struct avma1pp_softc
 121 {
 122         bus_space_handle_t      avma1pp_bhandle;
 123         bus_space_tag_t         avma1pp_btag;
 124         void                    *avma1pp_intrhand;
 125         struct resource         *avma1pp_irq;
 126         struct resource         *avma1pp_res;
 127         /* pointer to ifpi_sc */
 128         struct l1_softc *avma1pp_isc;
 129 };
 130 #endif
 131
 132 static driver_t avma1pp_pci_driver = {
 133         "ifpi",
 134         avma1pp_pci_methods,
 135         sizeof(struct l1_softc)
 136 };
 137
 138 static devclass_t avma1pp_pci_devclass;
 139
 140 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, 0, 0);
 141
 142 /* jump table for multiplex routines */
 143
 144 struct i4b_l1mux_func avma1pp_l1mux_func = {
 145         avma1pp_ret_linktab,
 146         avma1pp_set_linktab,
 147         ifpi_mph_command_req,
 148         ifpi_ph_data_req,
 149         ifpi_ph_activate_req,
 150 };
 151
 152 struct l1_softc *ifpi_scp[IFPI_MAXUNIT];
 153
 154 /*---------------------------------------------------------------------------*
 155  *      AVM PCI Fritz!Card special registers
 156  *---------------------------------------------------------------------------*/
 157
 158 /*
 159  *      register offsets from i/o base
 160  */
 161 #define STAT0_OFFSET            0x02
 162 #define STAT1_OFFSET            0x03
 163 #define ADDR_REG_OFFSET         0x04
 164 /*#define MODREG_OFFSET         0x06
 165 #define VERREG_OFFSET           0x07*/
 166
 167 /* these 2 are used to select an ISAC register set */
 168 #define ISAC_LO_REG_OFFSET      0x04
 169 #define ISAC_HI_REG_OFFSET      0x06
 170
 171 /* offset higher than this goes to the HI register set */
 172 #define MAX_LO_REG_OFFSET       0x2f
 173
 174 /* mask for the offset */
 175 #define ISAC_REGSET_MASK        0x0f
 176
 177 /* the offset from the base to the ISAC registers */
 178 #define ISAC_REG_OFFSET         0x10
 179
 180 /* the offset from the base to the ISAC FIFO */
 181 #define ISAC_FIFO               0x02
 182
 183 /* not really the HSCX, but sort of */
 184 #define HSCX_FIFO               0x00
 185 #define HSCX_STAT               0x04
 186
 187 /*
 188  *      AVM PCI Status Latch 0 read only bits
 189  */
 190 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 191 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 192 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 193 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 194 /* actually active LOW */
 195 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 196
 197 /*
 198  *      AVM Status Latch 0 write only bits
 199  */
 200 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 201 #define ASL_TIMERDISABLE        0x02  /* active high */
 202 #define ASL_TIMERRESET          0x04  /* active high */
 203 #define ASL_ENABLE_INT          0x08  /* active high */
 204 #define ASL_TESTBIT             0x10  /* active high */
 205
 206 /*
 207  *      AVM Status Latch 1 write only bits
 208  */
 209 #define ASL1_INTSEL              0x0f  /* active high */
 210 #define ASL1_ENABLE_IOM          0x80  /* active high */
 211
 212 /*
 213  * "HSCX" mode bits
 214  */
 215 #define  HSCX_MODE_ITF_FLG      0x01
 216 #define  HSCX_MODE_TRANS        0x02
 217 #define  HSCX_MODE_CCR_7        0x04
 218 #define  HSCX_MODE_CCR_16       0x08
 219 #define  HSCX_MODE_TESTLOOP     0x80
 220
 221 /*
 222  * "HSCX" status bits
 223  */
 224 #define  HSCX_STAT_RME          0x01
 225 #define  HSCX_STAT_RDO          0x10
 226 #define  HSCX_STAT_CRCVFRRAB    0x0E
 227 #define  HSCX_STAT_CRCVFR       0x06
 228 #define  HSCX_STAT_RML_MASK     0x3f00
 229
 230 /*
 231  * "HSCX" interrupt bits
 232  */
 233 #define  HSCX_INT_XPR           0x80
 234 #define  HSCX_INT_XDU           0x40
 235 #define  HSCX_INT_RPR           0x20
 236 #define  HSCX_INT_MASK          0xE0
 237
 238 /*
 239  * "HSCX" command bits
 240  */
 241 #define  HSCX_CMD_XRS           0x80
 242 #define  HSCX_CMD_XME           0x01
 243 #define  HSCX_CMD_RRS           0x20
 244 #define  HSCX_CMD_XML_MASK      0x3f00
 245
 246 /*
 247  * Commands and parameters are sent to the "HSCX" as a long, but the
 248  * fields are handled as bytes.
 249  *
 250  * The long contains:
 251  *      (prot << 16)|(txl << 8)|cmd
 252  *
 253  * where:
 254  *      prot = protocol to use
 255  *      txl = transmit length
 256  *      cmd = the command to be executed
 257  *
 258  * The fields are defined as u_char in struct l1_softc.
 259  *
 260  * Macro to coalesce the byte fields into a u_int
 261  */
 262 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 263                                         | (sc->avma1pp_prot << 16))
 264
 265 /*
 266  * to prevent deactivating the "HSCX" when both channels are active we
 267  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 268  * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
 269  * It is set high to allow room for new flags.
 270  */
 271 #define HSCX_AVMA1PP_ACTIVE     0x1000
 272
 273 /*---------------------------------------------------------------------------*
 274  *      AVM read fifo routines
 275  *---------------------------------------------------------------------------*/
 276
 277 static void
 278 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 279 {
 280         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 281         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 282
 283         switch (what) {
 284                 case ISIC_WHAT_ISAC:
 285                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 286                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 287                         break;
 288                 case ISIC_WHAT_HSCXA:
 289                         hscx_read_fifo(0, buf, size, sc);
 290                         break;
 291                 case ISIC_WHAT_HSCXB:
 292                         hscx_read_fifo(1, buf, size, sc);
 293                         break;
 294         }
 295 }
 296
 297 static void
 298 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 299 {
 300         u_int32_t *ip;
 301         size_t cnt;
 302         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 303         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 304
 305         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 306         ip = (u_int32_t *)buf;
 307         cnt = 0;
 308         /* what if len isn't a multiple of sizeof(int) and buf is */
 309         /* too small ???? */
 310         while (cnt < len)
 311         {
 312                 *ip++ = bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET);
 313                 cnt += 4;
 314         }
 315 }
 316
 317 /*---------------------------------------------------------------------------*
 318  *      AVM write fifo routines
 319  *---------------------------------------------------------------------------*/
 320 static void
 321 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 322 {
 323         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 324         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 325
 326         switch (what) {
 327                 case ISIC_WHAT_ISAC:
 328                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 329                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 330                         break;
 331                 case ISIC_WHAT_HSCXA:
 332                         hscx_write_fifo(0, buf, size, sc);
 333                         break;
 334                 case ISIC_WHAT_HSCXB:
 335                         hscx_write_fifo(1, buf, size, sc);
 336                         break;
 337         }
 338 }
 339
 340 static void
 341 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 342 {
 343         u_int32_t *ip;
 344         size_t cnt;
 345         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 346         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 347         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 348
 349
 350         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 351         sc->avma1pp_txl = 0;
 352         if (Bchan->out_mbuf_cur == NULL)
 353         {
 354           if (Bchan->bprot != BPROT_NONE)
 355                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 356         }
 357         if (len != sc->sc_bfifolen)
 358                 sc->avma1pp_txl = len;
 359
 360         cnt = 0; /* borrow cnt */
 361         AVMA1PPSETCMDLONG(cnt);
 362         hscx_write_reg(chan, HSCX_STAT, cnt, sc);
 363
 364         ip = (u_int32_t *)buf;
 365         cnt = 0;
 366         while (cnt < len)
 367         {
 368                 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET, *ip);
 369                 ip++;
 370                 cnt += 4;
 371         }
 372 }
 373
 374 /*---------------------------------------------------------------------------*
 375  *      AVM write register routines
 376  *---------------------------------------------------------------------------*/
 377
 378 static void
 379 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 380 {
 381         u_char reg_bank;
 382         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 383         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 384
 385         switch (what) {
 386                 case ISIC_WHAT_ISAC:
 387                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 388 #ifdef AVMA1PCI_DEBUG
 389                         printf("write_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 390 #endif
 391                         /* set the register bank */
 392                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 393                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 394                         break;
 395                 case ISIC_WHAT_HSCXA:
 396                         hscx_write_reg(0, offs, data, sc);
 397                         break;
 398                 case ISIC_WHAT_HSCXB:
 399                         hscx_write_reg(1, offs, data, sc);
 400                         break;
 401         }
 402 }
 403
 404 static void
 405 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
 406 {
 407         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 408         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 409
 410         /* point at the correct channel */
 411         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 412         bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET + off, val);
 413 }
 414
 415 /*---------------------------------------------------------------------------*
 416  *      AVM read register routines
 417  *---------------------------------------------------------------------------*/
 418 static u_int8_t
 419 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 420 {
 421         u_char reg_bank;
 422         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 423         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 424
 425         switch (what) {
 426                 case ISIC_WHAT_ISAC:
 427                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 428 #ifdef AVMA1PCI_DEBUG
 429                         printf("read_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 430 #endif
 431                         /* set the register bank */
 432                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 433                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 434                                 (offs & ISAC_REGSET_MASK)));
 435                 case ISIC_WHAT_HSCXA:
 436                         return hscx_read_reg(0, offs, sc);
 437                 case ISIC_WHAT_HSCXB:
 438                         return hscx_read_reg(1, offs, sc);
 439         }
 440         return 0;
 441 }
 442
 443 static u_char
 444 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 445 {
 446         return(hscx_read_reg_int(chan, off, sc) & 0xff);
 447 }
 448
 449 /*
 450  * need to be able to return an int because the RBCH is in the 2nd
 451  * byte.
 452  */
 453 static u_int
 454 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
 455 {
 456         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 457         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 458
 459         /* point at the correct channel */
 460         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 461         return(bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET + off));
 462 }
 463
 464 /*---------------------------------------------------------------------------*
 465  *      avma1pp_probe - probe for a card
 466  *---------------------------------------------------------------------------*/
 467 static int
 468 avma1pp_pci_probe(dev)
 469         device_t                dev;
 470 {
 471         u_int16_t               did, vid;
 472
 473         vid = pci_get_vendor(dev);
 474         did = pci_get_device(dev);
 475
 476         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
 477                 device_set_desc(dev, "AVM Fritz!Card PCI");
 478                 return(0);
 479         }
 480
 481         return(ENXIO);
 482 }
 483
 484 /*---------------------------------------------------------------------------*
 485  *      avma1pp_attach_avma1pp - attach Fritz!Card PCI
 486  *---------------------------------------------------------------------------*/
 487 int
 488 avma1pp_attach_avma1pp(device_t dev)
 489 {
 490         struct l1_softc *sc;
 491         u_int v;
 492         int unit, error = 0;
 493         int s;
 494         u_int16_t did, vid;
 495         void *ih = 0;
 496         bus_space_handle_t bhandle;
 497         bus_space_tag_t btag;
 498         l1_bchan_state_t *chan;
 499
 500         s = splimp();
 501
 502         vid = pci_get_vendor(dev);
 503         did = pci_get_device(dev);
 504         sc = device_get_softc(dev);
 505         unit = device_get_unit(dev);
 506         bzero(sc, sizeof(struct l1_softc));
 507
 508         /* probably not really required */
 509         if(unit > IFPI_MAXUNIT) {
 510                 printf("avma1pp%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 511                 splx(s);
 512                 return(ENXIO);
 513         }
 514
 515         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
 516                 printf("avma1pp%d: unknown device!?\n", unit);
 517                 goto fail;
 518         }
 519
 520         ifpi_scp[unit] = sc;
 521
 522         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 523         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 524                 &sc->sc_resources.io_rid[0],
 525                 0, ~0, 1, RF_ACTIVE);
 526
 527         if (sc->sc_resources.io_base[0] == NULL) {
 528                 printf("avma1pp%d: couldn't map IO port\n", unit);
 529                 error = ENXIO;
 530                 goto fail;
 531         }
 532
 533         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 534         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 535
 536         /* Allocate interrupt */
 537         sc->sc_resources.irq_rid = 0;
 538         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 539                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 540
 541         if (sc->sc_resources.irq == NULL) {
 542                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 543                 printf("avma1pp%d: couldn't map interrupt\n", unit);
 544                 error = ENXIO;
 545                 goto fail;
 546         }
 547
 548         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET, avma1pp_intr, sc, &ih);
 549
 550         if (error) {
 551                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 552                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 553                 printf("avma1pp%d: couldn't set up irq\n", unit);
 554                 goto fail;
 555         }
 556
 557         sc->sc_unit = unit;
 558
 559         /* end of new-bus stuff */
 560
 561         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 562
 563         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 564         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 565
 566         /* setup access routines */
 567
 568         sc->clearirq = NULL;
 569         sc->readreg = avma1pp_read_reg;
 570         sc->writereg = avma1pp_write_reg;
 571
 572         sc->readfifo = avma1pp_read_fifo;
 573         sc->writefifo = avma1pp_write_fifo;
 574
 575         /* setup card type */
 576
 577         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
 578
 579         /* setup IOM bus type */
 580
 581         sc->sc_bustyp = BUS_TYPE_IOM2;
 582
 583         /* set up some other miscellaneous things */
 584         sc->sc_ipac = 0;
 585         sc->sc_bfifolen = HSCX_FIFO_LEN;
 586
 587         /* reset the card */
 588         /* the Linux driver does this to clear any pending ISAC interrupts */
 589         v = 0;
 590         v = ISAC_READ(I_STAR);
 591 #ifdef AVMA1PCI_DEBUG
 592         printf("avma1pp_attach: I_STAR %x...", v);
 593 #endif
 594         v = ISAC_READ(I_MODE);
 595 #ifdef AVMA1PCI_DEBUG
 596         printf("avma1pp_attach: I_MODE %x...", v);
 597 #endif
 598         v = ISAC_READ(I_ADF2);
 599 #ifdef AVMA1PCI_DEBUG
 600         printf("avma1pp_attach: I_ADF2 %x...", v);
 601 #endif
 602         v = ISAC_READ(I_ISTA);
 603 #ifdef AVMA1PCI_DEBUG
 604         printf("avma1pp_attach: I_ISTA %x...", v);
 605 #endif
 606         if (v & ISAC_ISTA_EXI)
 607         {
 608                  v = ISAC_READ(I_EXIR);
 609 #ifdef AVMA1PCI_DEBUG
 610                  printf("avma1pp_attach: I_EXIR %x...", v);
 611 #endif
 612         }
 613         v = ISAC_READ(I_CIRR);
 614 #ifdef AVMA1PCI_DEBUG
 615         printf("avma1pp_attach: I_CIRR %x...", v);
 616 #endif
 617         ISAC_WRITE(I_MASK, 0xff);
 618         /* the Linux driver does this to clear any pending HSCX interrupts */
 619         v = hscx_read_reg_int(0, HSCX_STAT, sc);
 620 #ifdef AVMA1PCI_DEBUG
 621         printf("avma1pp_attach: 0 HSCX_STAT %x...", v);
 622 #endif
 623         v = hscx_read_reg_int(1, HSCX_STAT, sc);
 624 #ifdef AVMA1PCI_DEBUG
 625         printf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
 626 #endif
 627
 628         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 629         DELAY(SEC_DELAY/100); /* 10 ms */
 630         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 631         DELAY(SEC_DELAY/100); /* 10 ms */
 632 #ifdef AVMA1PCI_DEBUG
 633         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 634         DELAY(SEC_DELAY/100); /* 10 ms */
 635         v = bus_space_read_1(btag, bhandle, STAT1_OFFSET);
 636         printf("after reset: S1 %#x\n", v);
 637
 638         v = bus_space_read_4(btag, bhandle, 0);
 639         printf("avma1pp_attach_avma1pp: v %#x\n", v);
 640 #endif
 641
 642    /* from here to the end would normally be done in isic_pciattach */
 643
 644          printf("ifpi%d: ISAC %s (IOM-%c)\n", unit,
 645                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 646                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 647
 648         /* init the ISAC */
 649         ifpi_isac_init(sc);
 650
 651 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 652         /* Init the channel mutexes */
 653         chan = &sc->sc_chan[HSCX_CH_A];
 654         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", MTX_DEF);
 655         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", MTX_DEF);
 656         chan = &sc->sc_chan[HSCX_CH_B];
 657         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", MTX_DEF);
 658         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", MTX_DEF);
 659 #endif
 660
 661         /* init the "HSCX" */
 662         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 663
 664         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 665
 666         /* can't use the normal B-Channel stuff */
 667         avma1pp_init_linktab(sc);
 668
 669         /* set trace level */
 670
 671         sc->sc_trace = TRACE_OFF;
 672
 673         sc->sc_state = ISAC_IDLE;
 674
 675         sc->sc_ibuf = NULL;
 676         sc->sc_ib = NULL;
 677         sc->sc_ilen = 0;
 678
 679         sc->sc_obuf = NULL;
 680         sc->sc_op = NULL;
 681         sc->sc_ol = 0;
 682         sc->sc_freeflag = 0;
 683
 684         sc->sc_obuf2 = NULL;
 685         sc->sc_freeflag2 = 0;
 686
 687 #if defined(__FreeBSD__) && __FreeBSD__ >=3
 688         callout_handle_init(&sc->sc_T3_callout);
 689         callout_handle_init(&sc->sc_T4_callout);
 690 #endif
 691
 692         /* init higher protocol layers */
 693
 694         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp_l1mux_func);
 695
 696   fail:
 697         splx(s);
 698         return(error);
 699 }
 700
 701 /*
 702  * this is the real interrupt routine
 703  */
 704 static void
 705 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 706 {
 707         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 708         int activity = -1;
 709         u_int param = 0;
 710
 711         NDBGL1(L1_H_IRQ, "%#x", stat);
 712
 713         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 714         {
 715                 chan->stat_XDU++;
 716                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 717                 /* abort the transmission */
 718                 sc->avma1pp_txl = 0;
 719                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 720                 AVMA1PPSETCMDLONG(param);
 721                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 722                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 723                 AVMA1PPSETCMDLONG(param);
 724                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 725
 726                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 727                 {
 728                         i4b_Bfreembuf(chan->out_mbuf_head);
 729                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 730                 }
 731         }
 732
 733         /*
 734          * The following is based on examination of the Linux driver.
 735          *
 736          * The logic here is different than with a "real" HSCX; all kinds
 737          * of information (interrupt/status bits) are in stat.
 738          *              HSCX_INT_RPR indicates a receive interrupt
 739          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 740          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 741          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 742          *                      CRC/framing errors are only reported in this state.
 743          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 744          *                                      CRC/framing error
 745          */
 746
 747         if(stat & HSCX_INT_RPR)
 748         {
 749                 register int fifo_data_len;
 750                 int error = 0;
 751                 /* always have to read the FIFO, so use a scratch buffer */
 752                 u_char scrbuf[HSCX_FIFO_LEN];
 753
 754                 if(stat & HSCX_STAT_RDO)
 755                 {
 756                         chan->stat_RDO++;
 757                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 758                         error++;
 759                 }
 760
 761                 /*
 762                  * check whether we're receiving data for an inactive B-channel
 763                  * and discard it. This appears to happen for telephony when
 764                  * both B-channels are active and one is deactivated. Since
 765                  * it is not really possible to deactivate the channel in that
 766                  * case (the ASIC seems to deactivate _both_ channels), the
 767                  * "deactivated" channel keeps receiving data which can lead
 768                  * to exhaustion of mbufs and a kernel panic.
 769                  *
 770                  * This is a hack, but it's the only solution I can think of
 771                  * without having the documentation for the ASIC.
 772                  * GJ - 28 Nov 1999
 773                  */
 774                  if (chan->state == HSCX_IDLE)
 775                  {
 776                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 777                         error++;
 778                  }
 779
 780                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 781
 782                 if(fifo_data_len == 0)
 783                         fifo_data_len = sc->sc_bfifolen;
 784
 785                 /* ALWAYS read data from HSCX fifo */
 786
 787                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 788                 chan->rxcount += fifo_data_len;
 789
 790                 /* all error conditions checked, now decide and take action */
 791
 792                 if(error == 0)
 793                 {
 794                         if(chan->in_mbuf == NULL)
 795                         {
 796                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 797                                         panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
 798                                 chan->in_cbptr = chan->in_mbuf->m_data;
 799                                 chan->in_len = 0;
 800                         }
 801
 802                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 803                         {
 804                                 /* OK to copy the data */
 805                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 806                                 chan->in_cbptr += fifo_data_len;
 807                                 chan->in_len += fifo_data_len;
 808
 809                                 /* setup mbuf data length */
 810
 811                                 chan->in_mbuf->m_len = chan->in_len;
 812                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 813
 814                                 if(sc->sc_trace & TRACE_B_RX)
 815                                 {
 816                                         i4b_trace_hdr_t hdr;
 817                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 818                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 819                                         hdr.dir = FROM_NT;
 820                                         hdr.count = ++sc->sc_trace_bcount;
 821                                         MICROTIME(hdr.time);
 822                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 823                                 }
 824
 825                                 if (stat & HSCX_STAT_RME)
 826                                 {
 827                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 828                                   {
 829                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 830                                          activity = ACT_RX;
 831
 832                                          /* mark buffer ptr as unused */
 833
 834                                          chan->in_mbuf = NULL;
 835                                          chan->in_cbptr = NULL;
 836                                          chan->in_len = 0;
 837                                   }
 838                                   else
 839                                   {
 840                                                 chan->stat_CRC++;
 841                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 842                                           if (chan->in_mbuf != NULL)
 843                                           {
 844                                                   i4b_Bfreembuf(chan->in_mbuf);
 845                                                   chan->in_mbuf = NULL;
 846                                                   chan->in_cbptr = NULL;
 847                                                   chan->in_len = 0;
 848                                           }
 849                                   }
 850                                 }
 851                         } /* END enough space in mbuf */
 852                         else
 853                         {
 854                                  if(chan->bprot == BPROT_NONE)
 855                                  {
 856                                           /* setup mbuf data length */
 857
 858                                           chan->in_mbuf->m_len = chan->in_len;
 859                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 860
 861                                           if(sc->sc_trace & TRACE_B_RX)
 862                                           {
 863                                                         i4b_trace_hdr_t hdr;
 864                                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 865                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 866                                                         hdr.dir = FROM_NT;
 867                                                         hdr.count = ++sc->sc_trace_bcount;
 868                                                         MICROTIME(hdr.time);
 869                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 870                                                 }
 871
 872                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 873                                                  activity = ACT_RX;
 874
 875                                           /* move rx'd data to rx queue */
 876
 877 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 878                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 879 #else
 880                                           if(!(IF_QFULL(&chan->rx_queue)))
 881                                           {
 882                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 883                                           }
 884                                           else
 885                                           {
 886                                                 i4b_Bfreembuf(chan->in_mbuf);
 887                                           }
 888 #endif
 889                                           /* signal upper layer that data are available */
 890                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 891
 892                                           /* alloc new buffer */
 893
 894                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 895                                                  panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 896
 897                                           /* setup new data ptr */
 898
 899                                           chan->in_cbptr = chan->in_mbuf->m_data;
 900
 901                                           /* OK to copy the data */
 902                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 903
 904                                           chan->in_cbptr += fifo_data_len;
 905                                           chan->in_len = fifo_data_len;
 906
 907                                           chan->rxcount += fifo_data_len;
 908                                         }
 909                                  else
 910                                         {
 911                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 912                                           chan->in_cbptr = chan->in_mbuf->m_data;
 913                                           chan->in_len = 0;
 914                                         }
 915                           }
 916                 } /* if(error == 0) */
 917                 else
 918                 {
 919                         /* land here for RDO */
 920                         if (chan->in_mbuf != NULL)
 921                         {
 922                                 i4b_Bfreembuf(chan->in_mbuf);
 923                                 chan->in_mbuf = NULL;
 924                                 chan->in_cbptr = NULL;
 925                                 chan->in_len = 0;
 926                         }
 927                         sc->avma1pp_txl = 0;
 928                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 929                         AVMA1PPSETCMDLONG(param);
 930                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 931                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 932                         AVMA1PPSETCMDLONG(param);
 933                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 934                 }
 935         }
 936
 937
 938         /* transmit fifo empty, new data can be written to fifo */
 939
 940         if(stat & HSCX_INT_XPR)
 941         {
 942                 /*
 943                  * for a description what is going on here, please have
 944                  * a look at isic_bchannel_start() in i4b_bchan.c !
 945                  */
 946
 947                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 948
 949                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 950                 {
 951                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 952
 953                         if(chan->out_mbuf_head == NULL)
 954                         {
 955                                 chan->state &= ~HSCX_TX_ACTIVE;
 956                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 957                         }
 958                         else
 959                         {
 960                                 chan->state |= HSCX_TX_ACTIVE;
 961                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 962                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 963                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 964
 965                                 if(sc->sc_trace & TRACE_B_TX)
 966                                 {
 967                                         i4b_trace_hdr_t hdr;
 968                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 969                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 970                                         hdr.dir = FROM_TE;
 971                                         hdr.count = ++sc->sc_trace_bcount;
 972                                         MICROTIME(hdr.time);
 973                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 974                                 }
 975
 976                                 if(chan->bprot == BPROT_NONE)
 977                                 {
 978                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 979                                                 activity = ACT_TX;
 980                                 }
 981                                 else
 982                                 {
 983                                         activity = ACT_TX;
 984                                 }
 985                         }
 986                 }
 987
 988                 avma1pp_hscx_fifo(chan, sc);
 989         }
 990
 991         /* call timeout handling routine */
 992
 993         if(activity == ACT_RX || activity == ACT_TX)
 994                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 995 }
 996
 997 /*
 998  * this is the main routine which checks each channel and then calls
 999  * the real interrupt routine as appropriate
1000  */
1001 static void
1002 avma1pp_hscx_int_handler(struct l1_softc *sc)
1003 {
1004         u_int stat;
1005
1006         /* has to be a u_int because the byte count is in the 2nd byte */
1007         stat = hscx_read_reg_int(0, HSCX_STAT, sc);
1008         if (stat & HSCX_INT_MASK)
1009           avma1pp_hscx_intr(0, stat, sc);
1010         stat = hscx_read_reg_int(1, HSCX_STAT, sc);
1011         if (stat & HSCX_INT_MASK)
1012           avma1pp_hscx_intr(1, stat, sc);
1013 }
1014
1015 static void
1016 avma1pp_disable(device_t dev)
1017 {
1018         struct l1_softc *sc = device_get_softc(dev);
1019         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1020         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1021
1022         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1023 }
1024
1025 static void
1026 avma1pp_intr(void *xsc)
1027 {
1028         u_char stat;
1029         struct l1_softc *sc;
1030         bus_space_handle_t bhandle;
1031         bus_space_tag_t btag;
1032
1033         sc = xsc;
1034         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1035         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1036
1037         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
1038         NDBGL1(L1_H_IRQ, "stat %x", stat);
1039         /* was there an interrupt from this card ? */
1040         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1041                 return; /* no */
1042         /* interrupts are low active */
1043         if (!(stat & ASL_IRQ_TIMER))
1044           NDBGL1(L1_H_IRQ, "timer interrupt ???");
1045         if (!(stat & ASL_IRQ_HSCX))
1046         {
1047           NDBGL1(L1_H_IRQ, "HSCX");
1048                 avma1pp_hscx_int_handler(sc);
1049         }
1050         if (!(stat & ASL_IRQ_ISAC))
1051         {
1052           NDBGL1(L1_H_IRQ, "ISAC");
1053                 ifpi_isac_intr(sc);
1054         }
1055 }
1056
1057 static void
1058 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1059 {
1060         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1061         u_int param = 0;
1062
1063         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1064                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1065
1066         if (activate == 0)
1067         {
1068                 /* only deactivate if both channels are idle */
1069                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1070                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1071                 {
1072                         return;
1073                 }
1074                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1075                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1076                 AVMA1PPSETCMDLONG(param);
1077                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1078                 return;
1079         }
1080         if(chan->bprot == BPROT_RHDLC)
1081         {
1082                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1083
1084                 /* HDLC Frames, transparent mode 0 */
1085                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1086                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1087                 AVMA1PPSETCMDLONG(param);
1088                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1089                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1090                 AVMA1PPSETCMDLONG(param);
1091                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1092                 sc->avma1pp_cmd = 0;
1093         }
1094         else
1095         {
1096                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1097
1098                 /* Raw Telephony, extended transparent mode 1 */
1099                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1100                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1101                 AVMA1PPSETCMDLONG(param);
1102                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1103                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1104                 AVMA1PPSETCMDLONG(param);
1105                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1106                 sc->avma1pp_cmd = 0;
1107         }
1108 }
1109
1110 static void
1111 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1112 {
1113 #ifdef __FreeBSD__
1114         struct l1_softc *sc = ifpi_scp[unit];
1115 #else
1116         struct l1_softc *sc = isic_find_sc(unit);
1117 #endif
1118         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1119
1120         int s = SPLI4B();
1121
1122         if(activate == 0)
1123         {
1124                 /* deactivation */
1125                 chan->state = HSCX_IDLE;
1126                 avma1pp_hscx_init(sc, h_chan, activate);
1127         }
1128
1129         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1130                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1131
1132         /* general part */
1133
1134         chan->unit = sc->sc_unit;       /* unit number */
1135         chan->channel = h_chan;         /* B channel */
1136         chan->bprot = bprot;            /* B channel protocol */
1137         chan->state = HSCX_IDLE;        /* B channel state */
1138
1139         /* receiver part */
1140
1141         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1142
1143         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1144
1145         chan->rxcount = 0;              /* reset rx counter */
1146
1147         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1148
1149         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1150         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1151         chan->in_len = 0;               /* reset mbuf data len */
1152
1153         /* transmitter part */
1154
1155         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1156
1157         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1158
1159         chan->txcount = 0;              /* reset tx counter */
1160
1161         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1162
1163         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1164         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1165         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1166         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1167
1168         if(activate != 0)
1169         {
1170                 /* activation */
1171                 avma1pp_hscx_init(sc, h_chan, activate);
1172                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1173         }
1174
1175         splx(s);
1176 }
1177
1178 static void
1179 avma1pp_bchannel_start(int unit, int h_chan)
1180 {
1181 #ifdef __FreeBSD__
1182         struct l1_softc *sc = ifpi_scp[unit];
1183 #else
1184         struct l1_softc *sc = isic_find_sc(unit);
1185 #endif
1186         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1187         int s;
1188         int activity = -1;
1189
1190         s = SPLI4B();                           /* enter critical section */
1191         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1192         {
1193                 splx(s);
1194                 return;                         /* yes, leave */
1195         }
1196
1197         /* get next mbuf from queue */
1198
1199         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1200
1201         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1202         {
1203                 splx(s);                        /* leave critical section */
1204                 return;                         /* yes, exit */
1205         }
1206
1207         /* init current mbuf values */
1208
1209         chan->out_mbuf_cur = chan->out_mbuf_head;
1210         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1211         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1212
1213         /* activity indicator for timeout handling */
1214
1215         if(chan->bprot == BPROT_NONE)
1216         {
1217                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1218                         activity = ACT_TX;
1219         }
1220         else
1221         {
1222                 activity = ACT_TX;
1223         }
1224
1225         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1226
1227         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1228         {
1229                 i4b_trace_hdr_t hdr;
1230                 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1231                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1232                 hdr.dir = FROM_TE;
1233                 hdr.count = ++sc->sc_trace_bcount;
1234                 MICROTIME(hdr.time);
1235                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1236         }
1237
1238         avma1pp_hscx_fifo(chan, sc);
1239
1240         /* call timeout handling routine */
1241
1242         if(activity == ACT_RX || activity == ACT_TX)
1243                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1244
1245         splx(s);
1246 }
1247
1248 /*---------------------------------------------------------------------------*
1249  *      return the address of isic drivers linktab
1250  *---------------------------------------------------------------------------*/
1251 static isdn_link_t *
1252 avma1pp_ret_linktab(int unit, int channel)
1253 {
1254 #ifdef __FreeBSD__
1255         struct l1_softc *sc = ifpi_scp[unit];
1256 #else
1257         struct l1_softc *sc = isic_find_sc(unit);
1258 #endif
1259         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1260
1261         return(&chan->isic_isdn_linktab);
1262 }
1263
1264 /*---------------------------------------------------------------------------*
1265  *      set the driver linktab in the b channel softc
1266  *---------------------------------------------------------------------------*/
1267 static void
1268 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1269 {
1270 #ifdef __FreeBSD__
1271         struct l1_softc *sc = ifpi_scp[unit];
1272 #else
1273         struct l1_softc *sc = isic_find_sc(unit);
1274 #endif
1275         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1276
1277         chan->isic_drvr_linktab = dlt;
1278 }
1279
1280
1281 /*---------------------------------------------------------------------------*
1282  *      initialize our local linktab
1283  *---------------------------------------------------------------------------*/
1284 static void
1285 avma1pp_init_linktab(struct l1_softc *sc)
1286 {
1287         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1288         isdn_link_t *lt = &chan->isic_isdn_linktab;
1289
1290         /* make sure the hardware driver is known to layer 4 */
1291         /* avoid overwriting if already set */
1292         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1293         {
1294                 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1295                 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1296         }
1297
1298         /* local setup */
1299         lt->unit = sc->sc_unit;
1300         lt->channel = HSCX_CH_A;
1301         lt->bch_config = avma1pp_bchannel_setup;
1302         lt->bch_tx_start = avma1pp_bchannel_start;
1303         lt->bch_stat = avma1pp_bchannel_stat;
1304         lt->tx_queue = &chan->tx_queue;
1305
1306         /* used by non-HDLC data transfers, i.e. telephony drivers */
1307         lt->rx_queue = &chan->rx_queue;
1308
1309         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1310         lt->rx_mbuf = &chan->in_mbuf;
1311
1312         chan = &sc->sc_chan[HSCX_CH_B];
1313         lt = &chan->isic_isdn_linktab;
1314
1315         lt->unit = sc->sc_unit;
1316         lt->channel = HSCX_CH_B;
1317         lt->bch_config = avma1pp_bchannel_setup;
1318         lt->bch_tx_start = avma1pp_bchannel_start;
1319         lt->bch_stat = avma1pp_bchannel_stat;
1320         lt->tx_queue = &chan->tx_queue;
1321
1322         /* used by non-HDLC data transfers, i.e. telephony drivers */
1323         lt->rx_queue = &chan->rx_queue;
1324
1325         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1326         lt->rx_mbuf = &chan->in_mbuf;
1327 }
1328
1329 /*
1330  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1331  */
1332 static void
1333 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1334 {
1335 #ifdef __FreeBSD__
1336         struct l1_softc *sc = ifpi_scp[unit];
1337 #else
1338         struct l1_softc *sc = isic_find_sc(unit);
1339 #endif
1340         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1341         int s;
1342
1343         s = SPLI4B();
1344
1345         bsp->outbytes = chan->txcount;
1346         bsp->inbytes = chan->rxcount;
1347
1348         chan->txcount = 0;
1349         chan->rxcount = 0;
1350
1351         splx(s);
1352 }
1353
1354 /*---------------------------------------------------------------------------*
1355  *      fill HSCX fifo with data from the current mbuf
1356  *      Put this here until it can go into i4b_hscx.c
1357  *---------------------------------------------------------------------------*/
1358 static int
1359 avma1pp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1360 {
1361         int len;
1362         int nextlen;
1363         int i;
1364         int cmd = 0;
1365         /* using a scratch buffer simplifies writing to the FIFO */
1366         u_char scrbuf[HSCX_FIFO_LEN];
1367
1368         len = 0;
1369
1370         /*
1371          * fill the HSCX tx fifo with data from the current mbuf. if
1372          * current mbuf holds less data than HSCX fifo length, try to
1373          * get the next mbuf from (a possible) mbuf chain. if there is
1374          * not enough data in a single mbuf or in a chain, then this
1375          * is the last mbuf and we tell the HSCX that it has to send
1376          * CRC and closing flag
1377          */
1378
1379         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1380         {
1381                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1382
1383 #ifdef NOTDEF
1384                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1385                         chan->out_mbuf_head,
1386                         chan->out_mbuf_cur,
1387                         chan->out_mbuf_cur_ptr,
1388                         chan->out_mbuf_cur_len,
1389                         len,
1390                         nextlen);
1391 #endif
1392
1393                 cmd |= HSCX_CMDR_XTF;
1394                 /* collect the data in the scratch buffer */
1395                 for (i = 0; i < nextlen; i++)
1396                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1397
1398                 len += nextlen;
1399                 chan->txcount += nextlen;
1400
1401                 chan->out_mbuf_cur_ptr += nextlen;
1402                 chan->out_mbuf_cur_len -= nextlen;
1403
1404                 if(chan->out_mbuf_cur_len == 0)
1405                 {
1406                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1407                         {
1408                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1409                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1410
1411                                 if(sc->sc_trace & TRACE_B_TX)
1412                                 {
1413                                         i4b_trace_hdr_t hdr;
1414                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
1415                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1416                                         hdr.dir = FROM_TE;
1417                                         hdr.count = ++sc->sc_trace_bcount;
1418                                         MICROTIME(hdr.time);
1419                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1420                                 }
1421                         }
1422                         else
1423                         {
1424                                 if (chan->bprot != BPROT_NONE)
1425                                         cmd |= HSCX_CMDR_XME;
1426                                 i4b_Bfreembuf(chan->out_mbuf_head);
1427                                 chan->out_mbuf_head = NULL;
1428                         }
1429                 }
1430         }
1431         /* write what we have from the scratch buf to the HSCX fifo */
1432         if (len != 0)
1433                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1434         return(cmd);
1435 }
1436
1437 /*---------------------------------------------------------------------------*
1438  *      ifpi - ISAC interrupt routine
1439  *---------------------------------------------------------------------------*/
1440 static void
1441 ifpi_isac_intr(struct l1_softc *sc)
1442 {
1443         register u_char isac_irq_stat;
1444
1445         for(;;)
1446         {
1447                 /* get isac irq status */
1448                 isac_irq_stat = ISAC_READ(I_ISTA);
1449
1450                 if(isac_irq_stat)
1451                         ifpi_isac_irq(sc, isac_irq_stat); /* isac handler */
1452                 else
1453                         break;
1454         }
1455
1456         ISAC_WRITE(I_MASK, 0xff);
1457
1458         DELAY(100);
1459
1460         ISAC_WRITE(I_MASK, ISAC_IMASK);
1461 }
1462
1463 /*---------------------------------------------------------------------------*
1464  *      ifpi_recover - try to recover from irq lockup
1465  *---------------------------------------------------------------------------*/
1466 void
1467 ifpi_recover(struct l1_softc *sc)
1468 {
1469         u_char byte;
1470
1471         /* get isac irq status */
1472
1473         byte = ISAC_READ(I_ISTA);
1474
1475         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1476
1477         if(byte & ISAC_ISTA_EXI)
1478                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1479
1480         if(byte & ISAC_ISTA_CISQ)
1481         {
1482                 byte = ISAC_READ(I_CIRR);
1483
1484                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1485
1486                 if(byte & ISAC_CIRR_SQC)
1487                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1488         }
1489
1490         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1491
1492         ISAC_WRITE(I_MASK, 0xff);
1493         DELAY(100);
1494         ISAC_WRITE(I_MASK, ISAC_IMASK);
1495 }
1496
1497
1498 #endif /* NIFPI > 0 */