sys/dev/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/export.h>
  30 #include <drm/drmP.h>
  31 #include <linux/slab.h>
  32 #include <linux/string.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  41
  42 struct dp_link_dpll {
  43         int link_bw;
  44         struct dpll dpll;
  45 };
  46
  47 static const struct dp_link_dpll gen4_dpll[] = {
  48         { DP_LINK_BW_1_62,
  49                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  50         { DP_LINK_BW_2_7,
  51                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  52 };
  53
  54 static const struct dp_link_dpll pch_dpll[] = {
  55         { DP_LINK_BW_1_62,
  56                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  57         { DP_LINK_BW_2_7,
  58                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  59 };
  60
  61 static const struct dp_link_dpll vlv_dpll[] = {
  62         { DP_LINK_BW_1_62,
  63                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  64         { DP_LINK_BW_2_7,
  65                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  66 };
  67
  68 /**
  69  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  70  * @intel_dp: DP struct
  71  *
  72  * If a CPU or PCH DP output is attached to an eDP panel, this function
  73  * will return true, and false otherwise.
  74  */
  75 static bool is_edp(struct intel_dp *intel_dp)
  76 {
  77         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  78
  79         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  80 }
  81
  82 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  83 {
  84         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  85
  86         return intel_dig_port->base.base.dev;
  87 }
  88
  89 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  90 {
  91         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  92 }
  93
  94 static void intel_dp_link_down(struct intel_dp *intel_dp);
  95
  96 static int
  97 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  98 {
  99         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 100
 101         switch (max_link_bw) {
 102         case DP_LINK_BW_1_62:
 103         case DP_LINK_BW_2_7:
 104                 break;
 105         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 106                 max_link_bw = DP_LINK_BW_2_7;
 107                 break;
 108         default:
 109                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 110                      max_link_bw);
 111                 max_link_bw = DP_LINK_BW_1_62;
 112                 break;
 113         }
 114         return max_link_bw;
 115 }
 116
 117 /*
 118  * The units on the numbers in the next two are... bizarre.  Examples will
 119  * make it clearer; this one parallels an example in the eDP spec.
 120  *
 121  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 122  *
 123  *     270000 * 1 * 8 / 10 == 216000
 124  *
 125  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 126  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 127  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 128  * 119000.  At 18bpp that's 2142000 kilobits per second.
 129  *
 130  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 131  * get the result in decakilobits instead of kilobits.
 132  */
 133
 134 static int
 135 intel_dp_link_required(int pixel_clock, int bpp)
 136 {
 137         return (pixel_clock * bpp + 9) / 10;
 138 }
 139
 140 static int
 141 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 142 {
 143         return (max_link_clock * max_lanes * 8) / 10;
 144 }
 145
 146 static enum drm_mode_status
 147 intel_dp_mode_valid(struct drm_connector *connector,
 148                     struct drm_display_mode *mode)
 149 {
 150         struct intel_dp *intel_dp = intel_attached_dp(connector);
 151         struct intel_connector *intel_connector = to_intel_connector(connector);
 152         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 153         int target_clock = mode->clock;
 154         int max_rate, mode_rate, max_lanes, max_link_clock;
 155
 156         if (is_edp(intel_dp) && fixed_mode) {
 157                 if (mode->hdisplay > fixed_mode->hdisplay)
 158                         return MODE_PANEL;
 159
 160                 if (mode->vdisplay > fixed_mode->vdisplay)
 161                         return MODE_PANEL;
 162
 163                 target_clock = fixed_mode->clock;
 164         }
 165
 166         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 167         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 168
 169         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 170         mode_rate = intel_dp_link_required(target_clock, 18);
 171
 172         if (mode_rate > max_rate)
 173                 return MODE_CLOCK_HIGH;
 174
 175         if (mode->clock < 10000)
 176                 return MODE_CLOCK_LOW;
 177
 178         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 179                 return MODE_H_ILLEGAL;
 180
 181         return MODE_OK;
 182 }
 183
 184 static uint32_t
 185 pack_aux(uint8_t *src, int src_bytes)
 186 {
 187         int     i;
 188         uint32_t v = 0;
 189
 190         if (src_bytes > 4)
 191                 src_bytes = 4;
 192         for (i = 0; i < src_bytes; i++)
 193                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 194         return v;
 195 }
 196
 197 static void
 198 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 199 {
 200         int i;
 201         if (dst_bytes > 4)
 202                 dst_bytes = 4;
 203         for (i = 0; i < dst_bytes; i++)
 204                 dst[i] = src >> ((3-i) * 8);
 205 }
 206
 207 /* hrawclock is 1/4 the FSB frequency */
 208 static int
 209 intel_hrawclk(struct drm_device *dev)
 210 {
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         uint32_t clkcfg;
 213
 214         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 215         if (IS_VALLEYVIEW(dev))
 216                 return 200;
 217
 218         clkcfg = I915_READ(CLKCFG);
 219         switch (clkcfg & CLKCFG_FSB_MASK) {
 220         case CLKCFG_FSB_400:
 221                 return 100;
 222         case CLKCFG_FSB_533:
 223                 return 133;
 224         case CLKCFG_FSB_667:
 225                 return 166;
 226         case CLKCFG_FSB_800:
 227                 return 200;
 228         case CLKCFG_FSB_1067:
 229                 return 266;
 230         case CLKCFG_FSB_1333:
 231                 return 333;
 232         /* these two are just a guess; one of them might be right */
 233         case CLKCFG_FSB_1600:
 234         case CLKCFG_FSB_1600_ALT:
 235                 return 400;
 236         default:
 237                 return 133;
 238         }
 239 }
 240
 241 static void
 242 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 243                                     struct intel_dp *intel_dp,
 244                                     struct edp_power_seq *out);
 245 static void
 246 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 247                                               struct intel_dp *intel_dp,
 248                                               struct edp_power_seq *out);
 249
 250 static enum i915_pipe
 251 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 252 {
 253         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 254         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 255         struct drm_device *dev = intel_dig_port->base.base.dev;
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         enum port port = intel_dig_port->port;
 258         enum i915_pipe pipe;
 259
 260         /* modeset should have pipe */
 261         if (crtc)
 262                 return to_intel_crtc(crtc)->pipe;
 263
 264         /* init time, try to find a pipe with this port selected */
 265         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 266                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 267                         PANEL_PORT_SELECT_MASK;
 268                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 269                         return pipe;
 270                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 271                         return pipe;
 272         }
 273
 274         /* shrug */
 275         return PIPE_A;
 276 }
 277
 278 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 279 {
 280         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 281
 282         if (HAS_PCH_SPLIT(dev))
 283                 return PCH_PP_CONTROL;
 284         else
 285                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 286 }
 287
 288 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 289 {
 290         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 291
 292         if (HAS_PCH_SPLIT(dev))
 293                 return PCH_PP_STATUS;
 294         else
 295                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 296 }
 297
 298 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 299 {
 300         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 301         struct drm_i915_private *dev_priv = dev->dev_private;
 302
 303         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 304 }
 305
 306 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 307 {
 308         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 309         struct drm_i915_private *dev_priv = dev->dev_private;
 310
 311         return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 312 }
 313
 314 static void
 315 intel_dp_check_edp(struct intel_dp *intel_dp)
 316 {
 317         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         if (!is_edp(intel_dp))
 321                 return;
 322
 323         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 324                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 325                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 326                               I915_READ(_pp_stat_reg(intel_dp)),
 327                               I915_READ(_pp_ctrl_reg(intel_dp)));
 328         }
 329 }
 330
 331 static uint32_t
 332 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 333 {
 334         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 335         struct drm_device *dev = intel_dig_port->base.base.dev;
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 338         uint32_t status;
 339         bool done;
 340
 341 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 342         if (has_aux_irq)
 343                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 344                                           msecs_to_jiffies_timeout(10));
 345         else
 346                 done = wait_for_atomic(C, 10) == 0;
 347         if (!done)
 348                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 349                           has_aux_irq);
 350 #undef C
 351
 352         return status;
 353 }
 354
 355 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
 356                                       int index)
 357 {
 358         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 359         struct drm_device *dev = intel_dig_port->base.base.dev;
 360         struct drm_i915_private *dev_priv = dev->dev_private;
 361
 362         /* The clock divider is based off the hrawclk,
 363          * and would like to run at 2MHz. So, take the
 364          * hrawclk value and divide by 2 and use that
 365          *
 366          * Note that PCH attached eDP panels should use a 125MHz input
 367          * clock divider.
 368          */
 369         if (IS_VALLEYVIEW(dev)) {
 370                 return index ? 0 : 100;
 371         } else if (intel_dig_port->port == PORT_A) {
 372                 if (index)
 373                         return 0;
 374                 if (HAS_DDI(dev))
 375                         return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 376                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 377                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 378                 else
 379                         return 225; /* eDP input clock at 450Mhz */
 380         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 381                 /* Workaround for non-ULT HSW */
 382                 switch (index) {
 383                 case 0: return 63;
 384                 case 1: return 72;
 385                 default: return 0;
 386                 }
 387         } else if (HAS_PCH_SPLIT(dev)) {
 388                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 389         } else {
 390                 return index ? 0 :intel_hrawclk(dev) / 2;
 391         }
 392 }
 393
 394 static int
 395 intel_dp_aux_ch(struct intel_dp *intel_dp,
 396                 uint8_t *send, int send_bytes,
 397                 uint8_t *recv, int recv_size)
 398 {
 399         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 400         struct drm_device *dev = intel_dig_port->base.base.dev;
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 403         uint32_t ch_data = ch_ctl + 4;
 404         uint32_t aux_clock_divider;
 405         int i, ret, recv_bytes;
 406         uint32_t status;
 407         int try, precharge, clock = 0;
 408         bool has_aux_irq = HAS_AUX_IRQ(dev);
 409         uint32_t timeout;
 410
 411         /* dp aux is extremely sensitive to irq latency, hence request the
 412          * lowest possible wakeup latency and so prevent the cpu from going into
 413          * deep sleep states.
 414          */
 415         pm_qos_update_request(&dev_priv->pm_qos, 0);
 416
 417         intel_dp_check_edp(intel_dp);
 418
 419         if (IS_GEN6(dev))
 420                 precharge = 3;
 421         else
 422                 precharge = 5;
 423
 424         if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
 425                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 426         else
 427                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 428
 429         intel_aux_display_runtime_get(dev_priv);
 430
 431         /* Try to wait for any previous AUX channel activity */
 432         for (try = 0; try < 3; try++) {
 433                 status = I915_READ_NOTRACE(ch_ctl);
 434                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 435                         break;
 436                 msleep(1);
 437         }
 438
 439         if (try == 3) {
 440                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 441                      I915_READ(ch_ctl));
 442                 ret = -EBUSY;
 443                 goto out;
 444         }
 445
 446         /* Only 5 data registers! */
 447         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 448                 ret = -E2BIG;
 449                 goto out;
 450         }
 451
 452         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
 453                 /* Must try at least 3 times according to DP spec */
 454                 for (try = 0; try < 5; try++) {
 455                         /* Load the send data into the aux channel data registers */
 456                         for (i = 0; i < send_bytes; i += 4)
 457                                 I915_WRITE(ch_data + i,
 458                                            pack_aux(send + i, send_bytes - i));
 459
 460                         /* Send the command and wait for it to complete */
 461                         I915_WRITE(ch_ctl,
 462                                    DP_AUX_CH_CTL_SEND_BUSY |
 463                                    (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 464                                    timeout |
 465                                    (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 466                                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 467                                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 468                                    DP_AUX_CH_CTL_DONE |
 469                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 470                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 471
 472                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 473
 474                         /* Clear done status and any errors */
 475                         I915_WRITE(ch_ctl,
 476                                    status |
 477                                    DP_AUX_CH_CTL_DONE |
 478                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 479                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 480
 481                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 482                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 483                                 continue;
 484                         if (status & DP_AUX_CH_CTL_DONE)
 485                                 break;
 486                 }
 487                 if (status & DP_AUX_CH_CTL_DONE)
 488                         break;
 489         }
 490
 491         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 492                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 493                 ret = -EBUSY;
 494                 goto out;
 495         }
 496
 497         /* Check for timeout or receive error.
 498          * Timeouts occur when the sink is not connected
 499          */
 500         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 501                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 502                 ret = -EIO;
 503                 goto out;
 504         }
 505
 506         /* Timeouts occur when the device isn't connected, so they're
 507          * "normal" -- don't fill the kernel log with these */
 508         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 509                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 510                 ret = -ETIMEDOUT;
 511                 goto out;
 512         }
 513
 514         /* Unload any bytes sent back from the other side */
 515         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 516                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 517         if (recv_bytes > recv_size)
 518                 recv_bytes = recv_size;
 519
 520         for (i = 0; i < recv_bytes; i += 4)
 521                 unpack_aux(I915_READ(ch_data + i),
 522                            recv + i, recv_bytes - i);
 523
 524         ret = recv_bytes;
 525 out:
 526         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 527         intel_aux_display_runtime_put(dev_priv);
 528
 529         return ret;
 530 }
 531
 532 /* Write data to the aux channel in native mode */
 533 static int
 534 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 535                           uint16_t address, uint8_t *send, int send_bytes)
 536 {
 537         int ret;
 538         uint8_t msg[20];
 539         int msg_bytes;
 540         uint8_t ack;
 541         int retry;
 542
 543         if (WARN_ON(send_bytes > 16))
 544                 return -E2BIG;
 545
 546         intel_dp_check_edp(intel_dp);
 547         msg[0] = DP_AUX_NATIVE_WRITE << 4;
 548         msg[1] = address >> 8;
 549         msg[2] = address & 0xff;
 550         msg[3] = send_bytes - 1;
 551         memcpy(&msg[4], send, send_bytes);
 552         msg_bytes = send_bytes + 4;
 553         for (retry = 0; retry < 7; retry++) {
 554                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 555                 if (ret < 0)
 556                         return ret;
 557                 ack >>= 4;
 558                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 559                         return send_bytes;
 560                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 561                         usleep_range(400, 500);
 562                 else
 563                         return -EIO;
 564         }
 565
 566         DRM_ERROR("too many retries, giving up\n");
 567         return -EIO;
 568 }
 569
 570 /* Write a single byte to the aux channel in native mode */
 571 static int
 572 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 573                             uint16_t address, uint8_t byte)
 574 {
 575         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 576 }
 577
 578 /* read bytes from a native aux channel */
 579 static int
 580 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 581                          uint16_t address, uint8_t *recv, int recv_bytes)
 582 {
 583         uint8_t msg[4];
 584         int msg_bytes;
 585         uint8_t reply[20];
 586         int reply_bytes;
 587         uint8_t ack;
 588         int ret;
 589         int retry;
 590
 591         if (WARN_ON(recv_bytes > 19))
 592                 return -E2BIG;
 593
 594         intel_dp_check_edp(intel_dp);
 595         msg[0] = DP_AUX_NATIVE_READ << 4;
 596         msg[1] = address >> 8;
 597         msg[2] = address & 0xff;
 598         msg[3] = recv_bytes - 1;
 599
 600         msg_bytes = 4;
 601         reply_bytes = recv_bytes + 1;
 602
 603         for (retry = 0; retry < 7; retry++) {
 604                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 605                                       reply, reply_bytes);
 606                 if (ret == 0)
 607                         return -EPROTO;
 608                 if (ret < 0)
 609                         return ret;
 610                 ack = reply[0] >> 4;
 611                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
 612                         memcpy(recv, reply + 1, ret - 1);
 613                         return ret - 1;
 614                 }
 615                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 616                         usleep_range(400, 500);
 617                 else
 618                         return -EIO;
 619         }
 620
 621         DRM_ERROR("too many retries, giving up\n");
 622         return -EIO;
 623 }
 624
 625 static int
 626 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
 627                     uint8_t write_byte, uint8_t *read_byte)
 628 {
 629         struct i2c_algo_dp_aux_data *data = device_get_softc(adapter);
 630         struct intel_dp *intel_dp = data->priv;
 631         uint16_t address = data->address;
 632         uint8_t msg[5];
 633         uint8_t reply[2];
 634         unsigned retry;
 635         int msg_bytes;
 636         int reply_bytes;
 637         int ret;
 638
 639         ironlake_edp_panel_vdd_on(intel_dp);
 640         intel_dp_check_edp(intel_dp);
 641         /* Set up the command byte */
 642         if (mode & MODE_I2C_READ)
 643                 msg[0] = DP_AUX_I2C_READ << 4;
 644         else
 645                 msg[0] = DP_AUX_I2C_WRITE << 4;
 646
 647         if (!(mode & MODE_I2C_STOP))
 648                 msg[0] |= DP_AUX_I2C_MOT << 4;
 649
 650         msg[1] = address >> 8;
 651         msg[2] = address;
 652
 653         switch (mode) {
 654         case MODE_I2C_WRITE:
 655                 msg[3] = 0;
 656                 msg[4] = write_byte;
 657                 msg_bytes = 5;
 658                 reply_bytes = 1;
 659                 break;
 660         case MODE_I2C_READ:
 661                 msg[3] = 0;
 662                 msg_bytes = 4;
 663                 reply_bytes = 2;
 664                 break;
 665         default:
 666                 msg_bytes = 3;
 667                 reply_bytes = 1;
 668                 break;
 669         }
 670
 671         /*
 672          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
 673          * required to retry at least seven times upon receiving AUX_DEFER
 674          * before giving up the AUX transaction.
 675          */
 676         for (retry = 0; retry < 7; retry++) {
 677                 ret = intel_dp_aux_ch(intel_dp,
 678                                       msg, msg_bytes,
 679                                       reply, reply_bytes);
 680                 if (ret < 0) {
 681                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 682                         goto out;
 683                 }
 684
 685                 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 686                 case DP_AUX_NATIVE_REPLY_ACK:
 687                         /* I2C-over-AUX Reply field is only valid
 688                          * when paired with AUX ACK.
 689                          */
 690                         break;
 691                 case DP_AUX_NATIVE_REPLY_NACK:
 692                         DRM_DEBUG_KMS("aux_ch native nack\n");
 693                         ret = -EREMOTEIO;
 694                         goto out;
 695                 case DP_AUX_NATIVE_REPLY_DEFER:
 696                         /*
 697                          * For now, just give more slack to branch devices. We
 698                          * could check the DPCD for I2C bit rate capabilities,
 699                          * and if available, adjust the interval. We could also
 700                          * be more careful with DP-to-Legacy adapters where a
 701                          * long legacy cable may force very low I2C bit rates.
 702                          */
 703                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 704                             DP_DWN_STRM_PORT_PRESENT)
 705                                 usleep_range(500, 600);
 706                         else
 707                                 usleep_range(300, 400);
 708                         continue;
 709                 default:
 710                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 711                                   reply[0]);
 712                         ret = -EREMOTEIO;
 713                         goto out;
 714                 }
 715
 716                 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
 717                 case DP_AUX_I2C_REPLY_ACK:
 718                         if (mode == MODE_I2C_READ) {
 719                                 *read_byte = reply[1];
 720                         }
 721                         ret = 0;        /* reply_bytes - 1 */
 722                         goto out;
 723                 case DP_AUX_I2C_REPLY_NACK:
 724                         DRM_DEBUG_KMS("aux_i2c nack\n");
 725                         ret = -EREMOTEIO;
 726                         goto out;
 727                 case DP_AUX_I2C_REPLY_DEFER:
 728                         DRM_DEBUG_KMS("aux_i2c defer\n");
 729                         udelay(100);
 730                         break;
 731                 default:
 732                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 733                         ret = -EREMOTEIO;
 734                         goto out;
 735                 }
 736         }
 737
 738         DRM_ERROR("too many retries, giving up\n");
 739         ret = -EREMOTEIO;
 740
 741 out:
 742         ironlake_edp_panel_vdd_off(intel_dp, false);
 743         return ret;
 744 }
 745
 746 static int
 747 intel_dp_i2c_init(struct intel_dp *intel_dp,
 748                   struct intel_connector *intel_connector, const char *name)
 749 {
 750         int     ret;
 751
 752         DRM_DEBUG_KMS("i2c_init %s\n", name);
 753
 754         ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
 755             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
 756             &intel_dp->adapter);
 757         return ret;
 758 }
 759
 760 static void
 761 intel_dp_set_clock(struct intel_encoder *encoder,
 762                    struct intel_crtc_config *pipe_config, int link_bw)
 763 {
 764         struct drm_device *dev = encoder->base.dev;
 765         const struct dp_link_dpll *divisor = NULL;
 766         int i, count = 0;
 767
 768         if (IS_G4X(dev)) {
 769                 divisor = gen4_dpll;
 770                 count = ARRAY_SIZE(gen4_dpll);
 771         } else if (IS_HASWELL(dev)) {
 772                 /* Haswell has special-purpose DP DDI clocks. */
 773         } else if (HAS_PCH_SPLIT(dev)) {
 774                 divisor = pch_dpll;
 775                 count = ARRAY_SIZE(pch_dpll);
 776         } else if (IS_VALLEYVIEW(dev)) {
 777                 divisor = vlv_dpll;
 778                 count = ARRAY_SIZE(vlv_dpll);
 779         }
 780
 781         if (divisor && count) {
 782                 for (i = 0; i < count; i++) {
 783                         if (link_bw == divisor[i].link_bw) {
 784                                 pipe_config->dpll = divisor[i].dpll;
 785                                 pipe_config->clock_set = true;
 786                                 break;
 787                         }
 788                 }
 789         }
 790 }
 791
 792 bool
 793 intel_dp_compute_config(struct intel_encoder *encoder,
 794                         struct intel_crtc_config *pipe_config)
 795 {
 796         struct drm_device *dev = encoder->base.dev;
 797         struct drm_i915_private *dev_priv = dev->dev_private;
 798         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 799         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 800         enum port port = dp_to_dig_port(intel_dp)->port;
 801         struct intel_crtc *intel_crtc = encoder->new_crtc;
 802         struct intel_connector *intel_connector = intel_dp->attached_connector;
 803         int lane_count, clock;
 804         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 805         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 806         int bpp, mode_rate;
 807         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 808         int link_avail, link_clock;
 809
 810         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 811                 pipe_config->has_pch_encoder = true;
 812
 813         pipe_config->has_dp_encoder = true;
 814
 815         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 816                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 817                                        adjusted_mode);
 818                 if (!HAS_PCH_SPLIT(dev))
 819                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 820                                                  intel_connector->panel.fitting_mode);
 821                 else
 822                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 823                                                 intel_connector->panel.fitting_mode);
 824         }
 825
 826         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 827                 return false;
 828
 829         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 830                       "max bw %02x pixel clock %iKHz\n",
 831                       max_lane_count, bws[max_clock],
 832                       adjusted_mode->crtc_clock);
 833
 834         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 835          * bpc in between. */
 836         bpp = pipe_config->pipe_bpp;
 837         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 838             dev_priv->vbt.edp_bpp < bpp) {
 839                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 840                               dev_priv->vbt.edp_bpp);
 841                 bpp = dev_priv->vbt.edp_bpp;
 842         }
 843
 844         for (; bpp >= 6*3; bpp -= 2*3) {
 845                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 846                                                    bpp);
 847
 848                 for (clock = 0; clock <= max_clock; clock++) {
 849                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 850                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 851                                 link_avail = intel_dp_max_data_rate(link_clock,
 852                                                                     lane_count);
 853
 854                                 if (mode_rate <= link_avail) {
 855                                         goto found;
 856                                 }
 857                         }
 858                 }
 859         }
 860
 861         return false;
 862
 863 found:
 864         if (intel_dp->color_range_auto) {
 865                 /*
 866                  * See:
 867                  * CEA-861-E - 5.1 Default Encoding Parameters
 868                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 869                  */
 870                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 871                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 872                 else
 873                         intel_dp->color_range = 0;
 874         }
 875
 876         if (intel_dp->color_range)
 877                 pipe_config->limited_color_range = true;
 878
 879         intel_dp->link_bw = bws[clock];
 880         intel_dp->lane_count = lane_count;
 881         pipe_config->pipe_bpp = bpp;
 882         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 883
 884         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 885                       intel_dp->link_bw, intel_dp->lane_count,
 886                       pipe_config->port_clock, bpp);
 887         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 888                       mode_rate, link_avail);
 889
 890         intel_link_compute_m_n(bpp, lane_count,
 891                                adjusted_mode->crtc_clock,
 892                                pipe_config->port_clock,
 893                                &pipe_config->dp_m_n);
 894
 895         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 896
 897         return true;
 898 }
 899
 900 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 901 {
 902         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 903         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 904         struct drm_device *dev = crtc->base.dev;
 905         struct drm_i915_private *dev_priv = dev->dev_private;
 906         u32 dpa_ctl;
 907
 908         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 909         dpa_ctl = I915_READ(DP_A);
 910         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 911
 912         if (crtc->config.port_clock == 162000) {
 913                 /* For a long time we've carried around a ILK-DevA w/a for the
 914                  * 160MHz clock. If we're really unlucky, it's still required.
 915                  */
 916                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 917                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 918                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 919         } else {
 920                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 921                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 922         }
 923
 924         I915_WRITE(DP_A, dpa_ctl);
 925
 926         POSTING_READ(DP_A);
 927         udelay(500);
 928 }
 929
 930 static void intel_dp_mode_set(struct intel_encoder *encoder)
 931 {
 932         struct drm_device *dev = encoder->base.dev;
 933         struct drm_i915_private *dev_priv = dev->dev_private;
 934         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 935         enum port port = dp_to_dig_port(intel_dp)->port;
 936         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 937         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 938
 939         /*
 940          * There are four kinds of DP registers:
 941          *
 942          *      IBX PCH
 943          *      SNB CPU
 944          *      IVB CPU
 945          *      CPT PCH
 946          *
 947          * IBX PCH and CPU are the same for almost everything,
 948          * except that the CPU DP PLL is configured in this
 949          * register
 950          *
 951          * CPT PCH is quite different, having many bits moved
 952          * to the TRANS_DP_CTL register instead. That
 953          * configuration happens (oddly) in ironlake_pch_enable
 954          */
 955
 956         /* Preserve the BIOS-computed detected bit. This is
 957          * supposed to be read-only.
 958          */
 959         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 960
 961         /* Handle DP bits in common between all three register formats */
 962         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 963         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 964
 965         if (intel_dp->has_audio) {
 966                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 967                                  pipe_name(crtc->pipe));
 968                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 969                 intel_write_eld(&encoder->base, adjusted_mode);
 970         }
 971
 972         /* Split out the IBX/CPU vs CPT settings */
 973
 974         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 975                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 976                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 977                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 978                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 979                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 980
 981                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 982                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 983
 984                 intel_dp->DP |= crtc->pipe << 29;
 985         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 986                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 987                         intel_dp->DP |= intel_dp->color_range;
 988
 989                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 990                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 991                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 992                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 993                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 994
 995                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 996                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 997
 998                 if (crtc->pipe == 1)
 999                         intel_dp->DP |= DP_PIPEB_SELECT;
1000         } else {
1001                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1002         }
1003
1004         if (port == PORT_A && !IS_VALLEYVIEW(dev))
1005                 ironlake_set_pll_cpu_edp(intel_dp);
1006 }
1007
1008 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1009 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1010
1011 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1012 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1013
1014 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1015 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1016
1017 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1018                                        u32 mask,
1019                                        u32 value)
1020 {
1021         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1022         struct drm_i915_private *dev_priv = dev->dev_private;
1023         u32 pp_stat_reg, pp_ctrl_reg;
1024
1025         pp_stat_reg = _pp_stat_reg(intel_dp);
1026         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1027
1028         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1029                         mask, value,
1030                         I915_READ(pp_stat_reg),
1031                         I915_READ(pp_ctrl_reg));
1032
1033         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1034                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1035                                 I915_READ(pp_stat_reg),
1036                                 I915_READ(pp_ctrl_reg));
1037         }
1038
1039         DRM_DEBUG_KMS("Wait complete\n");
1040 }
1041
1042 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1043 {
1044         DRM_DEBUG_KMS("Wait for panel power on\n");
1045         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1046 }
1047
1048 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1049 {
1050         DRM_DEBUG_KMS("Wait for panel power off time\n");
1051         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1052 }
1053
1054 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1055 {
1056         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1057         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1058 }
1059
1060
1061 /* Read the current pp_control value, unlocking the register if it
1062  * is locked
1063  */
1064
1065 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1066 {
1067         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1068         struct drm_i915_private *dev_priv = dev->dev_private;
1069         u32 control;
1070
1071         control = I915_READ(_pp_ctrl_reg(intel_dp));
1072         control &= ~PANEL_UNLOCK_MASK;
1073         control |= PANEL_UNLOCK_REGS;
1074         return control;
1075 }
1076
1077 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1078 {
1079         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081         u32 pp;
1082         u32 pp_stat_reg, pp_ctrl_reg;
1083
1084         if (!is_edp(intel_dp))
1085                 return;
1086
1087         WARN(intel_dp->want_panel_vdd,
1088              "eDP VDD already requested on\n");
1089
1090         intel_dp->want_panel_vdd = true;
1091
1092         if (ironlake_edp_have_panel_vdd(intel_dp))
1093                 return;
1094
1095         intel_runtime_pm_get(dev_priv);
1096
1097         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1098
1099         if (!ironlake_edp_have_panel_power(intel_dp))
1100                 ironlake_wait_panel_power_cycle(intel_dp);
1101
1102         pp = ironlake_get_pp_control(intel_dp);
1103         pp |= EDP_FORCE_VDD;
1104
1105         pp_stat_reg = _pp_stat_reg(intel_dp);
1106         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1107
1108         I915_WRITE(pp_ctrl_reg, pp);
1109         POSTING_READ(pp_ctrl_reg);
1110         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1111                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1112         /*
1113          * If the panel wasn't on, delay before accessing aux channel
1114          */
1115         if (!ironlake_edp_have_panel_power(intel_dp)) {
1116                 DRM_DEBUG_KMS("eDP was not running\n");
1117                 msleep(intel_dp->panel_power_up_delay);
1118         }
1119 }
1120
1121 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1122 {
1123         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125         u32 pp;
1126         u32 pp_stat_reg, pp_ctrl_reg;
1127
1128         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1129
1130         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1131                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1132
1133                 pp = ironlake_get_pp_control(intel_dp);
1134                 pp &= ~EDP_FORCE_VDD;
1135
1136                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1137                 pp_stat_reg = _pp_stat_reg(intel_dp);
1138
1139                 I915_WRITE(pp_ctrl_reg, pp);
1140                 POSTING_READ(pp_ctrl_reg);
1141
1142                 /* Make sure sequencer is idle before allowing subsequent activity */
1143                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1144                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1145
1146                 if ((pp & POWER_TARGET_ON) == 0)
1147                         msleep(intel_dp->panel_power_cycle_delay);
1148
1149                 intel_runtime_pm_put(dev_priv);
1150         }
1151 }
1152
1153 static void ironlake_panel_vdd_work(struct work_struct *__work)
1154 {
1155         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1156                                                  struct intel_dp, panel_vdd_work);
1157         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1158
1159         mutex_lock(&dev->mode_config.mutex);
1160         ironlake_panel_vdd_off_sync(intel_dp);
1161         mutex_unlock(&dev->mode_config.mutex);
1162 }
1163
1164 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1165 {
1166         if (!is_edp(intel_dp))
1167                 return;
1168
1169         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1170
1171         intel_dp->want_panel_vdd = false;
1172
1173         if (sync) {
1174                 ironlake_panel_vdd_off_sync(intel_dp);
1175         } else {
1176                 /*
1177                  * Queue the timer to fire a long
1178                  * time from now (relative to the power down delay)
1179                  * to keep the panel power up across a sequence of operations
1180                  */
1181                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1182                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1183         }
1184 }
1185
1186 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1187 {
1188         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1189         struct drm_i915_private *dev_priv = dev->dev_private;
1190         u32 pp;
1191         u32 pp_ctrl_reg;
1192
1193         if (!is_edp(intel_dp))
1194                 return;
1195
1196         DRM_DEBUG_KMS("Turn eDP power on\n");
1197
1198         if (ironlake_edp_have_panel_power(intel_dp)) {
1199                 DRM_DEBUG_KMS("eDP power already on\n");
1200                 return;
1201         }
1202
1203         ironlake_wait_panel_power_cycle(intel_dp);
1204
1205         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1206         pp = ironlake_get_pp_control(intel_dp);
1207         if (IS_GEN5(dev)) {
1208                 /* ILK workaround: disable reset around power sequence */
1209                 pp &= ~PANEL_POWER_RESET;
1210                 I915_WRITE(pp_ctrl_reg, pp);
1211                 POSTING_READ(pp_ctrl_reg);
1212         }
1213
1214         pp |= POWER_TARGET_ON;
1215         if (!IS_GEN5(dev))
1216                 pp |= PANEL_POWER_RESET;
1217
1218         I915_WRITE(pp_ctrl_reg, pp);
1219         POSTING_READ(pp_ctrl_reg);
1220
1221         ironlake_wait_panel_on(intel_dp);
1222
1223         if (IS_GEN5(dev)) {
1224                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1225                 I915_WRITE(pp_ctrl_reg, pp);
1226                 POSTING_READ(pp_ctrl_reg);
1227         }
1228 }
1229
1230 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1231 {
1232         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1233         struct drm_i915_private *dev_priv = dev->dev_private;
1234         u32 pp;
1235         u32 pp_ctrl_reg;
1236
1237         if (!is_edp(intel_dp))
1238                 return;
1239
1240         DRM_DEBUG_KMS("Turn eDP power off\n");
1241
1242         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1243
1244         pp = ironlake_get_pp_control(intel_dp);
1245         /* We need to switch off panel power _and_ force vdd, for otherwise some
1246          * panels get very unhappy and cease to work. */
1247         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1248
1249         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1250
1251         I915_WRITE(pp_ctrl_reg, pp);
1252         POSTING_READ(pp_ctrl_reg);
1253
1254         intel_dp->want_panel_vdd = false;
1255
1256         ironlake_wait_panel_off(intel_dp);
1257
1258         /* We got a reference when we enabled the VDD. */
1259         intel_runtime_pm_put(dev_priv);
1260 }
1261
1262 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1263 {
1264         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1265         struct drm_device *dev = intel_dig_port->base.base.dev;
1266         struct drm_i915_private *dev_priv = dev->dev_private;
1267         u32 pp;
1268         u32 pp_ctrl_reg;
1269
1270         if (!is_edp(intel_dp))
1271                 return;
1272
1273         DRM_DEBUG_KMS("\n");
1274         /*
1275          * If we enable the backlight right away following a panel power
1276          * on, we may see slight flicker as the panel syncs with the eDP
1277          * link.  So delay a bit to make sure the image is solid before
1278          * allowing it to appear.
1279          */
1280         msleep(intel_dp->backlight_on_delay);
1281         pp = ironlake_get_pp_control(intel_dp);
1282         pp |= EDP_BLC_ENABLE;
1283
1284         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1285
1286         I915_WRITE(pp_ctrl_reg, pp);
1287         POSTING_READ(pp_ctrl_reg);
1288
1289         intel_panel_enable_backlight(intel_dp->attached_connector);
1290 }
1291
1292 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1293 {
1294         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         u32 pp;
1297         u32 pp_ctrl_reg;
1298
1299         if (!is_edp(intel_dp))
1300                 return;
1301
1302         intel_panel_disable_backlight(intel_dp->attached_connector);
1303
1304         DRM_DEBUG_KMS("\n");
1305         pp = ironlake_get_pp_control(intel_dp);
1306         pp &= ~EDP_BLC_ENABLE;
1307
1308         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1309
1310         I915_WRITE(pp_ctrl_reg, pp);
1311         POSTING_READ(pp_ctrl_reg);
1312         msleep(intel_dp->backlight_off_delay);
1313 }
1314
1315 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1316 {
1317         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1318         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1319         struct drm_device *dev = crtc->dev;
1320         struct drm_i915_private *dev_priv = dev->dev_private;
1321         u32 dpa_ctl;
1322
1323         assert_pipe_disabled(dev_priv,
1324                              to_intel_crtc(crtc)->pipe);
1325
1326         DRM_DEBUG_KMS("\n");
1327         dpa_ctl = I915_READ(DP_A);
1328         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1329         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1330
1331         /* We don't adjust intel_dp->DP while tearing down the link, to
1332          * facilitate link retraining (e.g. after hotplug). Hence clear all
1333          * enable bits here to ensure that we don't enable too much. */
1334         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1335         intel_dp->DP |= DP_PLL_ENABLE;
1336         I915_WRITE(DP_A, intel_dp->DP);
1337         POSTING_READ(DP_A);
1338         udelay(200);
1339 }
1340
1341 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1342 {
1343         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1344         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1345         struct drm_device *dev = crtc->dev;
1346         struct drm_i915_private *dev_priv = dev->dev_private;
1347         u32 dpa_ctl;
1348
1349         assert_pipe_disabled(dev_priv,
1350                              to_intel_crtc(crtc)->pipe);
1351
1352         dpa_ctl = I915_READ(DP_A);
1353         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1354              "dp pll off, should be on\n");
1355         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1356
1357         /* We can't rely on the value tracked for the DP register in
1358          * intel_dp->DP because link_down must not change that (otherwise link
1359          * re-training will fail. */
1360         dpa_ctl &= ~DP_PLL_ENABLE;
1361         I915_WRITE(DP_A, dpa_ctl);
1362         POSTING_READ(DP_A);
1363         udelay(200);
1364 }
1365
1366 /* If the sink supports it, try to set the power state appropriately */
1367 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1368 {
1369         int ret, i;
1370
1371         /* Should have a valid DPCD by this point */
1372         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1373                 return;
1374
1375         if (mode != DRM_MODE_DPMS_ON) {
1376                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1377                                                   DP_SET_POWER_D3);
1378                 if (ret != 1)
1379                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1380         } else {
1381                 /*
1382                  * When turning on, we need to retry for 1ms to give the sink
1383                  * time to wake up.
1384                  */
1385                 for (i = 0; i < 3; i++) {
1386                         ret = intel_dp_aux_native_write_1(intel_dp,
1387                                                           DP_SET_POWER,
1388                                                           DP_SET_POWER_D0);
1389                         if (ret == 1)
1390                                 break;
1391                         msleep(1);
1392                 }
1393         }
1394 }
1395
1396 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1397                                   enum i915_pipe *pipe)
1398 {
1399         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1400         enum port port = dp_to_dig_port(intel_dp)->port;
1401         struct drm_device *dev = encoder->base.dev;
1402         struct drm_i915_private *dev_priv = dev->dev_private;
1403         u32 tmp = I915_READ(intel_dp->output_reg);
1404
1405         if (!(tmp & DP_PORT_EN))
1406                 return false;
1407
1408         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1409                 *pipe = PORT_TO_PIPE_CPT(tmp);
1410         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1411                 *pipe = PORT_TO_PIPE(tmp);
1412         } else {
1413                 u32 trans_sel;
1414                 u32 trans_dp;
1415                 int i;
1416
1417                 switch (intel_dp->output_reg) {
1418                 case PCH_DP_B:
1419                         trans_sel = TRANS_DP_PORT_SEL_B;
1420                         break;
1421                 case PCH_DP_C:
1422                         trans_sel = TRANS_DP_PORT_SEL_C;
1423                         break;
1424                 case PCH_DP_D:
1425                         trans_sel = TRANS_DP_PORT_SEL_D;
1426                         break;
1427                 default:
1428                         return true;
1429                 }
1430
1431                 for_each_pipe(i) {
1432                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1433                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1434                                 *pipe = i;
1435                                 return true;
1436                         }
1437                 }
1438
1439                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1440                               intel_dp->output_reg);
1441         }
1442
1443         return true;
1444 }
1445
1446 static void intel_dp_get_config(struct intel_encoder *encoder,
1447                                 struct intel_crtc_config *pipe_config)
1448 {
1449         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1450         u32 tmp, flags = 0;
1451         struct drm_device *dev = encoder->base.dev;
1452         struct drm_i915_private *dev_priv = dev->dev_private;
1453         enum port port = dp_to_dig_port(intel_dp)->port;
1454         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1455         int dotclock;
1456
1457         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1458                 tmp = I915_READ(intel_dp->output_reg);
1459                 if (tmp & DP_SYNC_HS_HIGH)
1460                         flags |= DRM_MODE_FLAG_PHSYNC;
1461                 else
1462                         flags |= DRM_MODE_FLAG_NHSYNC;
1463
1464                 if (tmp & DP_SYNC_VS_HIGH)
1465                         flags |= DRM_MODE_FLAG_PVSYNC;
1466                 else
1467                         flags |= DRM_MODE_FLAG_NVSYNC;
1468         } else {
1469                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1470                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1471                         flags |= DRM_MODE_FLAG_PHSYNC;
1472                 else
1473                         flags |= DRM_MODE_FLAG_NHSYNC;
1474
1475                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1476                         flags |= DRM_MODE_FLAG_PVSYNC;
1477                 else
1478                         flags |= DRM_MODE_FLAG_NVSYNC;
1479         }
1480
1481         pipe_config->adjusted_mode.flags |= flags;
1482
1483         pipe_config->has_dp_encoder = true;
1484
1485         intel_dp_get_m_n(crtc, pipe_config);
1486
1487         if (port == PORT_A) {
1488                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1489                         pipe_config->port_clock = 162000;
1490                 else
1491                         pipe_config->port_clock = 270000;
1492         }
1493
1494         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1495                                             &pipe_config->dp_m_n);
1496
1497         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1498                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1499
1500         pipe_config->adjusted_mode.crtc_clock = dotclock;
1501
1502         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1503             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1504                 /*
1505                  * This is a big fat ugly hack.
1506                  *
1507                  * Some machines in UEFI boot mode provide us a VBT that has 18
1508                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1509                  * unknown we fail to light up. Yet the same BIOS boots up with
1510                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1511                  * max, not what it tells us to use.
1512                  *
1513                  * Note: This will still be broken if the eDP panel is not lit
1514                  * up by the BIOS, and thus we can't get the mode at module
1515                  * load.
1516                  */
1517                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1518                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1519                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1520         }
1521 }
1522
1523 static bool is_edp_psr(struct drm_device *dev)
1524 {
1525         struct drm_i915_private *dev_priv = dev->dev_private;
1526
1527         return dev_priv->psr.sink_support;
1528 }
1529
1530 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1531 {
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533
1534         if (!HAS_PSR(dev))
1535                 return false;
1536
1537         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1538 }
1539
1540 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1541                                     struct edp_vsc_psr *vsc_psr)
1542 {
1543         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1544         struct drm_device *dev = dig_port->base.base.dev;
1545         struct drm_i915_private *dev_priv = dev->dev_private;
1546         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1547         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1548         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1549         uint32_t *data = (uint32_t *) vsc_psr;
1550         unsigned int i;
1551
1552         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1553            the video DIP being updated before program video DIP data buffer
1554            registers for DIP being updated. */
1555         I915_WRITE(ctl_reg, 0);
1556         POSTING_READ(ctl_reg);
1557
1558         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1559                 if (i < sizeof(struct edp_vsc_psr))
1560                         I915_WRITE(data_reg + i, *data++);
1561                 else
1562                         I915_WRITE(data_reg + i, 0);
1563         }
1564
1565         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1566         POSTING_READ(ctl_reg);
1567 }
1568
1569 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1570 {
1571         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1572         struct drm_i915_private *dev_priv = dev->dev_private;
1573         struct edp_vsc_psr psr_vsc;
1574
1575         if (intel_dp->psr_setup_done)
1576                 return;
1577
1578         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1579         memset(&psr_vsc, 0, sizeof(psr_vsc));
1580         psr_vsc.sdp_header.HB0 = 0;
1581         psr_vsc.sdp_header.HB1 = 0x7;
1582         psr_vsc.sdp_header.HB2 = 0x2;
1583         psr_vsc.sdp_header.HB3 = 0x8;
1584         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1585
1586         /* Avoid continuous PSR exit by masking memup and hpd */
1587         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1588                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1589
1590         intel_dp->psr_setup_done = true;
1591 }
1592
1593 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1594 {
1595         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1598         int precharge = 0x3;
1599         int msg_size = 5;       /* Header(4) + Message(1) */
1600
1601         /* Enable PSR in sink */
1602         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1603                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1604                                             DP_PSR_ENABLE &
1605                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1606         else
1607                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1608                                             DP_PSR_ENABLE |
1609                                             DP_PSR_MAIN_LINK_ACTIVE);
1610
1611         /* Setup AUX registers */
1612         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1613         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1614         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1615                    DP_AUX_CH_CTL_TIME_OUT_400us |
1616                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1617                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1618                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1619 }
1620
1621 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1622 {
1623         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1624         struct drm_i915_private *dev_priv = dev->dev_private;
1625         uint32_t max_sleep_time = 0x1f;
1626         uint32_t idle_frames = 1;
1627         uint32_t val = 0x0;
1628         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1629
1630         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1631                 val |= EDP_PSR_LINK_STANDBY;
1632                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1633                 val |= EDP_PSR_TP1_TIME_0us;
1634                 val |= EDP_PSR_SKIP_AUX_EXIT;
1635         } else
1636                 val |= EDP_PSR_LINK_DISABLE;
1637
1638         I915_WRITE(EDP_PSR_CTL(dev), val |
1639                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1640                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1641                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1642                    EDP_PSR_ENABLE);
1643 }
1644
1645 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1646 {
1647         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1648         struct drm_device *dev = dig_port->base.base.dev;
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650         struct drm_crtc *crtc = dig_port->base.base.crtc;
1651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1652         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1653         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1654
1655         dev_priv->psr.source_ok = false;
1656
1657         if (!HAS_PSR(dev)) {
1658                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1659                 return false;
1660         }
1661
1662         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1663             (dig_port->port != PORT_A)) {
1664                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1665                 return false;
1666         }
1667
1668         if (!i915_enable_psr) {
1669                 DRM_DEBUG_KMS("PSR disable by flag\n");
1670                 return false;
1671         }
1672
1673         crtc = dig_port->base.base.crtc;
1674         if (crtc == NULL) {
1675                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1676                 return false;
1677         }
1678
1679         intel_crtc = to_intel_crtc(crtc);
1680         if (!intel_crtc_active(crtc)) {
1681                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1682                 return false;
1683         }
1684
1685         obj = to_intel_framebuffer(crtc->fb)->obj;
1686         if (obj->tiling_mode != I915_TILING_X ||
1687             obj->fence_reg == I915_FENCE_REG_NONE) {
1688                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1689                 return false;
1690         }
1691
1692         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1693                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1694                 return false;
1695         }
1696
1697         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1698             S3D_ENABLE) {
1699                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1700                 return false;
1701         }
1702
1703         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1704                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1705                 return false;
1706         }
1707
1708         dev_priv->psr.source_ok = true;
1709         return true;
1710 }
1711
1712 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1713 {
1714         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1715
1716         if (!intel_edp_psr_match_conditions(intel_dp) ||
1717             intel_edp_is_psr_enabled(dev))
1718                 return;
1719
1720         /* Setup PSR once */
1721         intel_edp_psr_setup(intel_dp);
1722
1723         /* Enable PSR on the panel */
1724         intel_edp_psr_enable_sink(intel_dp);
1725
1726         /* Enable PSR on the host */
1727         intel_edp_psr_enable_source(intel_dp);
1728 }
1729
1730 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1731 {
1732         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1733
1734         if (intel_edp_psr_match_conditions(intel_dp) &&
1735             !intel_edp_is_psr_enabled(dev))
1736                 intel_edp_psr_do_enable(intel_dp);
1737 }
1738
1739 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1740 {
1741         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1742         struct drm_i915_private *dev_priv = dev->dev_private;
1743
1744         if (!intel_edp_is_psr_enabled(dev))
1745                 return;
1746
1747         I915_WRITE(EDP_PSR_CTL(dev),
1748                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1749
1750         /* Wait till PSR is idle */
1751         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1752                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1753                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1754 }
1755
1756 void intel_edp_psr_update(struct drm_device *dev)
1757 {
1758         struct intel_encoder *encoder;
1759         struct intel_dp *intel_dp = NULL;
1760
1761         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1762                 if (encoder->type == INTEL_OUTPUT_EDP) {
1763                         intel_dp = enc_to_intel_dp(&encoder->base);
1764
1765                         if (!is_edp_psr(dev))
1766                                 return;
1767
1768                         if (!intel_edp_psr_match_conditions(intel_dp))
1769                                 intel_edp_psr_disable(intel_dp);
1770                         else
1771                                 if (!intel_edp_is_psr_enabled(dev))
1772                                         intel_edp_psr_do_enable(intel_dp);
1773                 }
1774 }
1775
1776 static void intel_disable_dp(struct intel_encoder *encoder)
1777 {
1778         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1779         enum port port = dp_to_dig_port(intel_dp)->port;
1780         struct drm_device *dev = encoder->base.dev;
1781
1782         /* Make sure the panel is off before trying to change the mode. But also
1783          * ensure that we have vdd while we switch off the panel. */
1784         ironlake_edp_panel_vdd_on(intel_dp);
1785         ironlake_edp_backlight_off(intel_dp);
1786         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1787         ironlake_edp_panel_off(intel_dp);
1788
1789         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1790         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1791                 intel_dp_link_down(intel_dp);
1792 }
1793
1794 static void intel_post_disable_dp(struct intel_encoder *encoder)
1795 {
1796         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1797         enum port port = dp_to_dig_port(intel_dp)->port;
1798         struct drm_device *dev = encoder->base.dev;
1799
1800         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1801                 intel_dp_link_down(intel_dp);
1802                 if (!IS_VALLEYVIEW(dev))
1803                         ironlake_edp_pll_off(intel_dp);
1804         }
1805 }
1806
1807 static void intel_enable_dp(struct intel_encoder *encoder)
1808 {
1809         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1810         struct drm_device *dev = encoder->base.dev;
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1813
1814         if (WARN_ON(dp_reg & DP_PORT_EN))
1815                 return;
1816
1817         ironlake_edp_panel_vdd_on(intel_dp);
1818         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1819         intel_dp_start_link_train(intel_dp);
1820         ironlake_edp_panel_on(intel_dp);
1821         ironlake_edp_panel_vdd_off(intel_dp, true);
1822         intel_dp_complete_link_train(intel_dp);
1823         intel_dp_stop_link_train(intel_dp);
1824 }
1825
1826 static void g4x_enable_dp(struct intel_encoder *encoder)
1827 {
1828         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829
1830         intel_enable_dp(encoder);
1831         ironlake_edp_backlight_on(intel_dp);
1832 }
1833
1834 static void vlv_enable_dp(struct intel_encoder *encoder)
1835 {
1836         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1837
1838         ironlake_edp_backlight_on(intel_dp);
1839 }
1840
1841 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1842 {
1843         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1844         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1845
1846         if (dport->port == PORT_A)
1847                 ironlake_edp_pll_on(intel_dp);
1848 }
1849
1850 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1851 {
1852         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1853         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1854         struct drm_device *dev = encoder->base.dev;
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1857         enum dpio_channel port = vlv_dport_to_channel(dport);
1858         int pipe = intel_crtc->pipe;
1859         struct edp_power_seq power_seq;
1860         u32 val;
1861
1862         mutex_lock(&dev_priv->dpio_lock);
1863
1864         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1865         val = 0;
1866         if (pipe)
1867                 val |= (1<<21);
1868         else
1869                 val &= ~(1<<21);
1870         val |= 0x001000c4;
1871         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1872         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1873         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1874
1875         mutex_unlock(&dev_priv->dpio_lock);
1876
1877         if (is_edp(intel_dp)) {
1878                 /* init power sequencer on this pipe and port */
1879                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1880                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1881                                                               &power_seq);
1882         }
1883
1884         intel_enable_dp(encoder);
1885
1886         vlv_wait_port_ready(dev_priv, dport);
1887 }
1888
1889 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1890 {
1891         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1892         struct drm_device *dev = encoder->base.dev;
1893         struct drm_i915_private *dev_priv = dev->dev_private;
1894         struct intel_crtc *intel_crtc =
1895                 to_intel_crtc(encoder->base.crtc);
1896         enum dpio_channel port = vlv_dport_to_channel(dport);
1897         int pipe = intel_crtc->pipe;
1898
1899         /* Program Tx lane resets to default */
1900         mutex_lock(&dev_priv->dpio_lock);
1901         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1902                          DPIO_PCS_TX_LANE2_RESET |
1903                          DPIO_PCS_TX_LANE1_RESET);
1904         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1905                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1906                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1907                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1908                                  DPIO_PCS_CLK_SOFT_RESET);
1909
1910         /* Fix up inter-pair skew failure */
1911         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1912         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1913         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1914         mutex_unlock(&dev_priv->dpio_lock);
1915 }
1916
1917 /*
1918  * Native read with retry for link status and receiver capability reads for
1919  * cases where the sink may still be asleep.
1920  */
1921 static bool
1922 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1923                                uint8_t *recv, int recv_bytes)
1924 {
1925         int ret, i;
1926
1927         /*
1928          * Sinks are *supposed* to come up within 1ms from an off state,
1929          * but we're also supposed to retry 3 times per the spec.
1930          */
1931         for (i = 0; i < 3; i++) {
1932                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1933                                                recv_bytes);
1934                 if (ret == recv_bytes)
1935                         return true;
1936                 msleep(1);
1937         }
1938
1939         return false;
1940 }
1941
1942 /*
1943  * Fetch AUX CH registers 0x202 - 0x207 which contain
1944  * link status information
1945  */
1946 static bool
1947 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1948 {
1949         return intel_dp_aux_native_read_retry(intel_dp,
1950                                               DP_LANE0_1_STATUS,
1951                                               link_status,
1952                                               DP_LINK_STATUS_SIZE);
1953 }
1954
1955 /*
1956  * These are source-specific values; current Intel hardware supports
1957  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1958  */
1959
1960 static uint8_t
1961 intel_dp_voltage_max(struct intel_dp *intel_dp)
1962 {
1963         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1964         enum port port = dp_to_dig_port(intel_dp)->port;
1965
1966         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1967                 return DP_TRAIN_VOLTAGE_SWING_1200;
1968         else if (IS_GEN7(dev) && port == PORT_A)
1969                 return DP_TRAIN_VOLTAGE_SWING_800;
1970         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1971                 return DP_TRAIN_VOLTAGE_SWING_1200;
1972         else
1973                 return DP_TRAIN_VOLTAGE_SWING_800;
1974 }
1975
1976 static uint8_t
1977 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1978 {
1979         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1980         enum port port = dp_to_dig_port(intel_dp)->port;
1981
1982         if (IS_BROADWELL(dev)) {
1983                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1984                 case DP_TRAIN_VOLTAGE_SWING_400:
1985                 case DP_TRAIN_VOLTAGE_SWING_600:
1986                         return DP_TRAIN_PRE_EMPHASIS_6;
1987                 case DP_TRAIN_VOLTAGE_SWING_800:
1988                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1989                 case DP_TRAIN_VOLTAGE_SWING_1200:
1990                 default:
1991                         return DP_TRAIN_PRE_EMPHASIS_0;
1992                 }
1993         } else if (IS_HASWELL(dev)) {
1994                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1995                 case DP_TRAIN_VOLTAGE_SWING_400:
1996                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1997                 case DP_TRAIN_VOLTAGE_SWING_600:
1998                         return DP_TRAIN_PRE_EMPHASIS_6;
1999                 case DP_TRAIN_VOLTAGE_SWING_800:
2000                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2001                 case DP_TRAIN_VOLTAGE_SWING_1200:
2002                 default:
2003                         return DP_TRAIN_PRE_EMPHASIS_0;
2004                 }
2005         } else if (IS_VALLEYVIEW(dev)) {
2006                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2007                 case DP_TRAIN_VOLTAGE_SWING_400:
2008                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2009                 case DP_TRAIN_VOLTAGE_SWING_600:
2010                         return DP_TRAIN_PRE_EMPHASIS_6;
2011                 case DP_TRAIN_VOLTAGE_SWING_800:
2012                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2013                 case DP_TRAIN_VOLTAGE_SWING_1200:
2014                 default:
2015                         return DP_TRAIN_PRE_EMPHASIS_0;
2016                 }
2017         } else if (IS_GEN7(dev) && port == PORT_A) {
2018                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2019                 case DP_TRAIN_VOLTAGE_SWING_400:
2020                         return DP_TRAIN_PRE_EMPHASIS_6;
2021                 case DP_TRAIN_VOLTAGE_SWING_600:
2022                 case DP_TRAIN_VOLTAGE_SWING_800:
2023                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2024                 default:
2025                         return DP_TRAIN_PRE_EMPHASIS_0;
2026                 }
2027         } else {
2028                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2029                 case DP_TRAIN_VOLTAGE_SWING_400:
2030                         return DP_TRAIN_PRE_EMPHASIS_6;
2031                 case DP_TRAIN_VOLTAGE_SWING_600:
2032                         return DP_TRAIN_PRE_EMPHASIS_6;
2033                 case DP_TRAIN_VOLTAGE_SWING_800:
2034                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2035                 case DP_TRAIN_VOLTAGE_SWING_1200:
2036                 default:
2037                         return DP_TRAIN_PRE_EMPHASIS_0;
2038                 }
2039         }
2040 }
2041
2042 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2043 {
2044         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2045         struct drm_i915_private *dev_priv = dev->dev_private;
2046         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2047         struct intel_crtc *intel_crtc =
2048                 to_intel_crtc(dport->base.base.crtc);
2049         unsigned long demph_reg_value, preemph_reg_value,
2050                 uniqtranscale_reg_value;
2051         uint8_t train_set = intel_dp->train_set[0];
2052         enum dpio_channel port = vlv_dport_to_channel(dport);
2053         int pipe = intel_crtc->pipe;
2054
2055         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2056         case DP_TRAIN_PRE_EMPHASIS_0:
2057                 preemph_reg_value = 0x0004000;
2058                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2059                 case DP_TRAIN_VOLTAGE_SWING_400:
2060                         demph_reg_value = 0x2B405555;
2061                         uniqtranscale_reg_value = 0x552AB83A;
2062                         break;
2063                 case DP_TRAIN_VOLTAGE_SWING_600:
2064                         demph_reg_value = 0x2B404040;
2065                         uniqtranscale_reg_value = 0x5548B83A;
2066                         break;
2067                 case DP_TRAIN_VOLTAGE_SWING_800:
2068                         demph_reg_value = 0x2B245555;
2069                         uniqtranscale_reg_value = 0x5560B83A;
2070                         break;
2071                 case DP_TRAIN_VOLTAGE_SWING_1200:
2072                         demph_reg_value = 0x2B405555;
2073                         uniqtranscale_reg_value = 0x5598DA3A;
2074                         break;
2075                 default:
2076                         return 0;
2077                 }
2078                 break;
2079         case DP_TRAIN_PRE_EMPHASIS_3_5:
2080                 preemph_reg_value = 0x0002000;
2081                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2082                 case DP_TRAIN_VOLTAGE_SWING_400:
2083                         demph_reg_value = 0x2B404040;
2084                         uniqtranscale_reg_value = 0x5552B83A;
2085                         break;
2086                 case DP_TRAIN_VOLTAGE_SWING_600:
2087                         demph_reg_value = 0x2B404848;
2088                         uniqtranscale_reg_value = 0x5580B83A;
2089                         break;
2090                 case DP_TRAIN_VOLTAGE_SWING_800:
2091                         demph_reg_value = 0x2B404040;
2092                         uniqtranscale_reg_value = 0x55ADDA3A;
2093                         break;
2094                 default:
2095                         return 0;
2096                 }
2097                 break;
2098         case DP_TRAIN_PRE_EMPHASIS_6:
2099                 preemph_reg_value = 0x0000000;
2100                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2101                 case DP_TRAIN_VOLTAGE_SWING_400:
2102                         demph_reg_value = 0x2B305555;
2103                         uniqtranscale_reg_value = 0x5570B83A;
2104                         break;
2105                 case DP_TRAIN_VOLTAGE_SWING_600:
2106                         demph_reg_value = 0x2B2B4040;
2107                         uniqtranscale_reg_value = 0x55ADDA3A;
2108                         break;
2109                 default:
2110                         return 0;
2111                 }
2112                 break;
2113         case DP_TRAIN_PRE_EMPHASIS_9_5:
2114                 preemph_reg_value = 0x0006000;
2115                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2116                 case DP_TRAIN_VOLTAGE_SWING_400:
2117                         demph_reg_value = 0x1B405555;
2118                         uniqtranscale_reg_value = 0x55ADDA3A;
2119                         break;
2120                 default:
2121                         return 0;
2122                 }
2123                 break;
2124         default:
2125                 return 0;
2126         }
2127
2128         mutex_lock(&dev_priv->dpio_lock);
2129         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2130         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2131         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2132                          uniqtranscale_reg_value);
2133         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2134         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2135         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2136         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2137         mutex_unlock(&dev_priv->dpio_lock);
2138
2139         return 0;
2140 }
2141
2142 static void
2143 intel_get_adjust_train(struct intel_dp *intel_dp,
2144                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2145 {
2146         uint8_t v = 0;
2147         uint8_t p = 0;
2148         int lane;
2149         uint8_t voltage_max;
2150         uint8_t preemph_max;
2151
2152         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2153                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2154                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2155
2156                 if (this_v > v)
2157                         v = this_v;
2158                 if (this_p > p)
2159                         p = this_p;
2160         }
2161
2162         voltage_max = intel_dp_voltage_max(intel_dp);
2163         if (v >= voltage_max)
2164                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2165
2166         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2167         if (p >= preemph_max)
2168                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2169
2170         for (lane = 0; lane < 4; lane++)
2171                 intel_dp->train_set[lane] = v | p;
2172 }
2173
2174 static uint32_t
2175 intel_gen4_signal_levels(uint8_t train_set)
2176 {
2177         uint32_t        signal_levels = 0;
2178
2179         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2180         case DP_TRAIN_VOLTAGE_SWING_400:
2181         default:
2182                 signal_levels |= DP_VOLTAGE_0_4;
2183                 break;
2184         case DP_TRAIN_VOLTAGE_SWING_600:
2185                 signal_levels |= DP_VOLTAGE_0_6;
2186                 break;
2187         case DP_TRAIN_VOLTAGE_SWING_800:
2188                 signal_levels |= DP_VOLTAGE_0_8;
2189                 break;
2190         case DP_TRAIN_VOLTAGE_SWING_1200:
2191                 signal_levels |= DP_VOLTAGE_1_2;
2192                 break;
2193         }
2194         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2195         case DP_TRAIN_PRE_EMPHASIS_0:
2196         default:
2197                 signal_levels |= DP_PRE_EMPHASIS_0;
2198                 break;
2199         case DP_TRAIN_PRE_EMPHASIS_3_5:
2200                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2201                 break;
2202         case DP_TRAIN_PRE_EMPHASIS_6:
2203                 signal_levels |= DP_PRE_EMPHASIS_6;
2204                 break;
2205         case DP_TRAIN_PRE_EMPHASIS_9_5:
2206                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2207                 break;
2208         }
2209         return signal_levels;
2210 }
2211
2212 /* Gen6's DP voltage swing and pre-emphasis control */
2213 static uint32_t
2214 intel_gen6_edp_signal_levels(uint8_t train_set)
2215 {
2216         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2217                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2218         switch (signal_levels) {
2219         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2220         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2221                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2222         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2223                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2224         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2225         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2226                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2227         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2228         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2229                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2230         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2231         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2232                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2233         default:
2234                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2235                               "0x%x\n", signal_levels);
2236                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2237         }
2238 }
2239
2240 /* Gen7's DP voltage swing and pre-emphasis control */
2241 static uint32_t
2242 intel_gen7_edp_signal_levels(uint8_t train_set)
2243 {
2244         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2245                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2246         switch (signal_levels) {
2247         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2248                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2249         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2250                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2251         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2252                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2253
2254         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2255                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2256         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2257                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2258
2259         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2260                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2261         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2262                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2263
2264         default:
2265                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2266                               "0x%x\n", signal_levels);
2267                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2268         }
2269 }
2270
2271 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2272 static uint32_t
2273 intel_hsw_signal_levels(uint8_t train_set)
2274 {
2275         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2276                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2277         switch (signal_levels) {
2278         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2279                 return DDI_BUF_EMP_400MV_0DB_HSW;
2280         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2282         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2283                 return DDI_BUF_EMP_400MV_6DB_HSW;
2284         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2285                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2286
2287         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2288                 return DDI_BUF_EMP_600MV_0DB_HSW;
2289         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2290                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2291         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2292                 return DDI_BUF_EMP_600MV_6DB_HSW;
2293
2294         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2295                 return DDI_BUF_EMP_800MV_0DB_HSW;
2296         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2297                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2298         default:
2299                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2300                               "0x%x\n", signal_levels);
2301                 return DDI_BUF_EMP_400MV_0DB_HSW;
2302         }
2303 }
2304
2305 static uint32_t
2306 intel_bdw_signal_levels(uint8_t train_set)
2307 {
2308         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2309                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2310         switch (signal_levels) {
2311         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2312                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2313         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2315         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2316                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2317
2318         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2319                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2320         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2321                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2322         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2323                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2324
2325         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2326                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2327         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2328                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2329
2330         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2331                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2332
2333         default:
2334                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2335                               "0x%x\n", signal_levels);
2336                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2337         }
2338 }
2339
2340 /* Properly updates "DP" with the correct signal levels. */
2341 static void
2342 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2343 {
2344         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2345         enum port port = intel_dig_port->port;
2346         struct drm_device *dev = intel_dig_port->base.base.dev;
2347         uint32_t signal_levels, mask;
2348         uint8_t train_set = intel_dp->train_set[0];
2349
2350         if (IS_BROADWELL(dev)) {
2351                 signal_levels = intel_bdw_signal_levels(train_set);
2352                 mask = DDI_BUF_EMP_MASK;
2353         } else if (IS_HASWELL(dev)) {
2354                 signal_levels = intel_hsw_signal_levels(train_set);
2355                 mask = DDI_BUF_EMP_MASK;
2356         } else if (IS_VALLEYVIEW(dev)) {
2357                 signal_levels = intel_vlv_signal_levels(intel_dp);
2358                 mask = 0;
2359         } else if (IS_GEN7(dev) && port == PORT_A) {
2360                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2361                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2362         } else if (IS_GEN6(dev) && port == PORT_A) {
2363                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2364                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2365         } else {
2366                 signal_levels = intel_gen4_signal_levels(train_set);
2367                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2368         }
2369
2370         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2371
2372         *DP = (*DP & ~mask) | signal_levels;
2373 }
2374
2375 static bool
2376 intel_dp_set_link_train(struct intel_dp *intel_dp,
2377                         uint32_t *DP,
2378                         uint8_t dp_train_pat)
2379 {
2380         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2381         struct drm_device *dev = intel_dig_port->base.base.dev;
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383         enum port port = intel_dig_port->port;
2384         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2385         int ret, len;
2386
2387         if (HAS_DDI(dev)) {
2388                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2389
2390                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2391                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2392                 else
2393                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2394
2395                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2396                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2397                 case DP_TRAINING_PATTERN_DISABLE:
2398                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2399
2400                         break;
2401                 case DP_TRAINING_PATTERN_1:
2402                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2403                         break;
2404                 case DP_TRAINING_PATTERN_2:
2405                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2406                         break;
2407                 case DP_TRAINING_PATTERN_3:
2408                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2409                         break;
2410                 }
2411                 I915_WRITE(DP_TP_CTL(port), temp);
2412
2413         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2414                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2415
2416                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2417                 case DP_TRAINING_PATTERN_DISABLE:
2418                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2419                         break;
2420                 case DP_TRAINING_PATTERN_1:
2421                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2422                         break;
2423                 case DP_TRAINING_PATTERN_2:
2424                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2425                         break;
2426                 case DP_TRAINING_PATTERN_3:
2427                         DRM_ERROR("DP training pattern 3 not supported\n");
2428                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2429                         break;
2430                 }
2431
2432         } else {
2433                 *DP &= ~DP_LINK_TRAIN_MASK;
2434
2435                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2436                 case DP_TRAINING_PATTERN_DISABLE:
2437                         *DP |= DP_LINK_TRAIN_OFF;
2438                         break;
2439                 case DP_TRAINING_PATTERN_1:
2440                         *DP |= DP_LINK_TRAIN_PAT_1;
2441                         break;
2442                 case DP_TRAINING_PATTERN_2:
2443                         *DP |= DP_LINK_TRAIN_PAT_2;
2444                         break;
2445                 case DP_TRAINING_PATTERN_3:
2446                         DRM_ERROR("DP training pattern 3 not supported\n");
2447                         *DP |= DP_LINK_TRAIN_PAT_2;
2448                         break;
2449                 }
2450         }
2451
2452         I915_WRITE(intel_dp->output_reg, *DP);
2453         POSTING_READ(intel_dp->output_reg);
2454
2455         buf[0] = dp_train_pat;
2456         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2457             DP_TRAINING_PATTERN_DISABLE) {
2458                 /* don't write DP_TRAINING_LANEx_SET on disable */
2459                 len = 1;
2460         } else {
2461                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2462                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2463                 len = intel_dp->lane_count + 1;
2464         }
2465
2466         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2467                                         buf, len);
2468
2469         return ret == len;
2470 }
2471
2472 static bool
2473 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2474                         uint8_t dp_train_pat)
2475 {
2476         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2477         intel_dp_set_signal_levels(intel_dp, DP);
2478         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2479 }
2480
2481 static bool
2482 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2483                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2484 {
2485         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2486         struct drm_device *dev = intel_dig_port->base.base.dev;
2487         struct drm_i915_private *dev_priv = dev->dev_private;
2488         int ret;
2489
2490         intel_get_adjust_train(intel_dp, link_status);
2491         intel_dp_set_signal_levels(intel_dp, DP);
2492
2493         I915_WRITE(intel_dp->output_reg, *DP);
2494         POSTING_READ(intel_dp->output_reg);
2495
2496         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2497                                         intel_dp->train_set,
2498                                         intel_dp->lane_count);
2499
2500         return ret == intel_dp->lane_count;
2501 }
2502
2503 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2504 {
2505         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2506         struct drm_device *dev = intel_dig_port->base.base.dev;
2507         struct drm_i915_private *dev_priv = dev->dev_private;
2508         enum port port = intel_dig_port->port;
2509         uint32_t val;
2510
2511         if (!HAS_DDI(dev))
2512                 return;
2513
2514         val = I915_READ(DP_TP_CTL(port));
2515         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2516         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2517         I915_WRITE(DP_TP_CTL(port), val);
2518
2519         /*
2520          * On PORT_A we can have only eDP in SST mode. There the only reason
2521          * we need to set idle transmission mode is to work around a HW issue
2522          * where we enable the pipe while not in idle link-training mode.
2523          * In this case there is requirement to wait for a minimum number of
2524          * idle patterns to be sent.
2525          */
2526         if (port == PORT_A)
2527                 return;
2528
2529         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2530                      1))
2531                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2532 }
2533
2534 /* Enable corresponding port and start training pattern 1 */
2535 void
2536 intel_dp_start_link_train(struct intel_dp *intel_dp)
2537 {
2538         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2539         struct drm_device *dev = encoder->dev;
2540         int i;
2541         uint8_t voltage;
2542         int voltage_tries, loop_tries;
2543         uint32_t DP = intel_dp->DP;
2544         uint8_t link_config[2];
2545
2546         if (HAS_DDI(dev))
2547                 intel_ddi_prepare_link_retrain(encoder);
2548
2549         /* Write the link configuration data */
2550         link_config[0] = intel_dp->link_bw;
2551         link_config[1] = intel_dp->lane_count;
2552         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2553                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2554         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2555
2556         link_config[0] = 0;
2557         link_config[1] = DP_SET_ANSI_8B10B;
2558         intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2559
2560         DP |= DP_PORT_EN;
2561
2562         /* clock recovery */
2563         if (!intel_dp_reset_link_train(intel_dp, &DP,
2564                                        DP_TRAINING_PATTERN_1 |
2565                                        DP_LINK_SCRAMBLING_DISABLE)) {
2566                 DRM_ERROR("failed to enable link training\n");
2567                 return;
2568         }
2569
2570         voltage = 0xff;
2571         voltage_tries = 0;
2572         loop_tries = 0;
2573         for (;;) {
2574                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2575
2576                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2577                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2578                         DRM_ERROR("failed to get link status\n");
2579                         break;
2580                 }
2581
2582                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2583                         DRM_DEBUG_KMS("clock recovery OK\n");
2584                         break;
2585                 }
2586
2587                 /* Check to see if we've tried the max voltage */
2588                 for (i = 0; i < intel_dp->lane_count; i++)
2589                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2590                                 break;
2591                 if (i == intel_dp->lane_count) {
2592                         ++loop_tries;
2593                         if (loop_tries == 5) {
2594                                 DRM_ERROR("too many full retries, give up\n");
2595                                 break;
2596                         }
2597                         intel_dp_reset_link_train(intel_dp, &DP,
2598                                                   DP_TRAINING_PATTERN_1 |
2599                                                   DP_LINK_SCRAMBLING_DISABLE);
2600                         voltage_tries = 0;
2601                         continue;
2602                 }
2603
2604                 /* Check to see if we've tried the same voltage 5 times */
2605                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2606                         ++voltage_tries;
2607                         if (voltage_tries == 5) {
2608                                 DRM_ERROR("too many voltage retries, give up\n");
2609                                 break;
2610                         }
2611                 } else
2612                         voltage_tries = 0;
2613                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2614
2615                 /* Update training set as requested by target */
2616                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2617                         DRM_ERROR("failed to update link training\n");
2618                         break;
2619                 }
2620         }
2621
2622         intel_dp->DP = DP;
2623 }
2624
2625 void
2626 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2627 {
2628         bool channel_eq = false;
2629         int tries, cr_tries;
2630         uint32_t DP = intel_dp->DP;
2631
2632         /* channel equalization */
2633         if (!intel_dp_set_link_train(intel_dp, &DP,
2634                                      DP_TRAINING_PATTERN_2 |
2635                                      DP_LINK_SCRAMBLING_DISABLE)) {
2636                 DRM_ERROR("failed to start channel equalization\n");
2637                 return;
2638         }
2639
2640         tries = 0;
2641         cr_tries = 0;
2642         channel_eq = false;
2643         for (;;) {
2644                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2645
2646                 if (cr_tries > 5) {
2647                         DRM_ERROR("failed to train DP, aborting\n");
2648                         break;
2649                 }
2650
2651                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2652                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2653                         DRM_ERROR("failed to get link status\n");
2654                         break;
2655                 }
2656
2657                 /* Make sure clock is still ok */
2658                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2659                         intel_dp_start_link_train(intel_dp);
2660                         intel_dp_set_link_train(intel_dp, &DP,
2661                                                 DP_TRAINING_PATTERN_2 |
2662                                                 DP_LINK_SCRAMBLING_DISABLE);
2663                         cr_tries++;
2664                         continue;
2665                 }
2666
2667                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2668                         channel_eq = true;
2669                         break;
2670                 }
2671
2672                 /* Try 5 times, then try clock recovery if that fails */
2673                 if (tries > 5) {
2674                         intel_dp_link_down(intel_dp);
2675                         intel_dp_start_link_train(intel_dp);
2676                         intel_dp_set_link_train(intel_dp, &DP,
2677                                                 DP_TRAINING_PATTERN_2 |
2678                                                 DP_LINK_SCRAMBLING_DISABLE);
2679                         tries = 0;
2680                         cr_tries++;
2681                         continue;
2682                 }
2683
2684                 /* Update training set as requested by target */
2685                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2686                         DRM_ERROR("failed to update link training\n");
2687                         break;
2688                 }
2689                 ++tries;
2690         }
2691
2692         intel_dp_set_idle_link_train(intel_dp);
2693
2694         intel_dp->DP = DP;
2695
2696         if (channel_eq)
2697                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2698
2699 }
2700
2701 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2702 {
2703         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2704                                 DP_TRAINING_PATTERN_DISABLE);
2705 }
2706
2707 static void
2708 intel_dp_link_down(struct intel_dp *intel_dp)
2709 {
2710         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2711         enum port port = intel_dig_port->port;
2712         struct drm_device *dev = intel_dig_port->base.base.dev;
2713         struct drm_i915_private *dev_priv = dev->dev_private;
2714         struct intel_crtc *intel_crtc =
2715                 to_intel_crtc(intel_dig_port->base.base.crtc);
2716         uint32_t DP = intel_dp->DP;
2717
2718         /*
2719          * DDI code has a strict mode set sequence and we should try to respect
2720          * it, otherwise we might hang the machine in many different ways. So we
2721          * really should be disabling the port only on a complete crtc_disable
2722          * sequence. This function is just called under two conditions on DDI
2723          * code:
2724          * - Link train failed while doing crtc_enable, and on this case we
2725          *   really should respect the mode set sequence and wait for a
2726          *   crtc_disable.
2727          * - Someone turned the monitor off and intel_dp_check_link_status
2728          *   called us. We don't need to disable the whole port on this case, so
2729          *   when someone turns the monitor on again,
2730          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2731          *   train.
2732          */
2733         if (HAS_DDI(dev))
2734                 return;
2735
2736         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2737                 return;
2738
2739         DRM_DEBUG_KMS("\n");
2740
2741         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2742                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2743                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2744         } else {
2745                 DP &= ~DP_LINK_TRAIN_MASK;
2746                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2747         }
2748         POSTING_READ(intel_dp->output_reg);
2749
2750         /* We don't really know why we're doing this */
2751         intel_wait_for_vblank(dev, intel_crtc->pipe);
2752
2753         if (HAS_PCH_IBX(dev) &&
2754             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2755                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2756
2757                 /* Hardware workaround: leaving our transcoder select
2758                  * set to transcoder B while it's off will prevent the
2759                  * corresponding HDMI output on transcoder A.
2760                  *
2761                  * Combine this with another hardware workaround:
2762                  * transcoder select bit can only be cleared while the
2763                  * port is enabled.
2764                  */
2765                 DP &= ~DP_PIPEB_SELECT;
2766                 I915_WRITE(intel_dp->output_reg, DP);
2767
2768                 /* Changes to enable or select take place the vblank
2769                  * after being written.
2770                  */
2771                 if (WARN_ON(crtc == NULL)) {
2772                         /* We should never try to disable a port without a crtc
2773                          * attached. For paranoia keep the code around for a
2774                          * bit. */
2775                         POSTING_READ(intel_dp->output_reg);
2776                         msleep(50);
2777                 } else
2778                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2779         }
2780
2781         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2782         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2783         POSTING_READ(intel_dp->output_reg);
2784         msleep(intel_dp->panel_power_down_delay);
2785 }
2786
2787 static bool
2788 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2789 {
2790         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2791         struct drm_device *dev = dig_port->base.base.dev;
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793
2794         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2795
2796         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2797                                            sizeof(intel_dp->dpcd)) == 0)
2798                 return false; /* aux transfer failed */
2799
2800         ksnprintf(dpcd_hex_dump,
2801                   sizeof(dpcd_hex_dump),
2802                   "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2803                   intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2804                   intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2805                   intel_dp->dpcd[6], intel_dp->dpcd[7]);
2806
2807         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2808
2809         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2810                 return false; /* DPCD not present */
2811
2812         /* Check if the panel supports PSR */
2813         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2814         if (is_edp(intel_dp)) {
2815                 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2816                                                intel_dp->psr_dpcd,
2817                                                sizeof(intel_dp->psr_dpcd));
2818                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2819                         dev_priv->psr.sink_support = true;
2820                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2821                 }
2822         }
2823
2824         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2825               DP_DWN_STRM_PORT_PRESENT))
2826                 return true; /* native DP sink */
2827
2828         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2829                 return true; /* no per-port downstream info */
2830
2831         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2832                                            intel_dp->downstream_ports,
2833                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2834                 return false; /* downstream port status fetch failed */
2835
2836         return true;
2837 }
2838
2839 static void
2840 intel_dp_probe_oui(struct intel_dp *intel_dp)
2841 {
2842         u8 buf[3];
2843
2844         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2845                 return;
2846
2847         ironlake_edp_panel_vdd_on(intel_dp);
2848
2849         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2850                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2851                               buf[0], buf[1], buf[2]);
2852
2853         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2854                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2855                               buf[0], buf[1], buf[2]);
2856
2857         ironlake_edp_panel_vdd_off(intel_dp, false);
2858 }
2859
2860 static bool
2861 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2862 {
2863         int ret;
2864
2865         ret = intel_dp_aux_native_read_retry(intel_dp,
2866                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2867                                              sink_irq_vector, 1);
2868         if (!ret)
2869                 return false;
2870
2871         return true;
2872 }
2873
2874 static void
2875 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2876 {
2877         /* NAK by default */
2878         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2879 }
2880
2881 /*
2882  * According to DP spec
2883  * 5.1.2:
2884  *  1. Read DPCD
2885  *  2. Configure link according to Receiver Capabilities
2886  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2887  *  4. Check link status on receipt of hot-plug interrupt
2888  */
2889
2890 void
2891 intel_dp_check_link_status(struct intel_dp *intel_dp)
2892 {
2893         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2894         u8 sink_irq_vector;
2895         u8 link_status[DP_LINK_STATUS_SIZE];
2896
2897         if (!intel_encoder->connectors_active)
2898                 return;
2899
2900         if (WARN_ON(!intel_encoder->base.crtc))
2901                 return;
2902
2903         /* Try to read receiver status if the link appears to be up */
2904         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2905                 return;
2906         }
2907
2908         /* Now read the DPCD to see if it's actually running */
2909         if (!intel_dp_get_dpcd(intel_dp)) {
2910                 return;
2911         }
2912
2913         /* Try to read the source of the interrupt */
2914         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2915             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2916                 /* Clear interrupt source */
2917                 intel_dp_aux_native_write_1(intel_dp,
2918                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2919                                             sink_irq_vector);
2920
2921                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2922                         intel_dp_handle_test_request(intel_dp);
2923                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2924                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2925         }
2926
2927         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2928                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2929                               drm_get_encoder_name(&intel_encoder->base));
2930                 intel_dp_start_link_train(intel_dp);
2931                 intel_dp_complete_link_train(intel_dp);
2932                 intel_dp_stop_link_train(intel_dp);
2933         }
2934 }
2935
2936 /* XXX this is probably wrong for multiple downstream ports */
2937 static enum drm_connector_status
2938 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2939 {
2940         uint8_t *dpcd = intel_dp->dpcd;
2941         uint8_t type;
2942
2943         if (!intel_dp_get_dpcd(intel_dp))
2944                 return connector_status_disconnected;
2945
2946         /* if there's no downstream port, we're done */
2947         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2948                 return connector_status_connected;
2949
2950         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2951         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2952             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2953                 uint8_t reg;
2954                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2955                                                     &reg, 1))
2956                         return connector_status_unknown;
2957                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2958                                               : connector_status_disconnected;
2959         }
2960
2961         /* If no HPD, poke DDC gently */
2962         if (drm_probe_ddc(intel_dp->adapter))
2963                 return connector_status_connected;
2964
2965         /* Well we tried, say unknown for unreliable port types */
2966         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2967                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2968                 if (type == DP_DS_PORT_TYPE_VGA ||
2969                     type == DP_DS_PORT_TYPE_NON_EDID)
2970                         return connector_status_unknown;
2971         } else {
2972                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2973                         DP_DWN_STRM_PORT_TYPE_MASK;
2974                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2975                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
2976                         return connector_status_unknown;
2977         }
2978
2979         /* Anything else is out of spec, warn and ignore */
2980         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2981         return connector_status_disconnected;
2982 }
2983
2984 static enum drm_connector_status
2985 ironlake_dp_detect(struct intel_dp *intel_dp)
2986 {
2987         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2988         struct drm_i915_private *dev_priv = dev->dev_private;
2989         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2990         enum drm_connector_status status;
2991
2992         /* Can't disconnect eDP, but you can close the lid... */
2993         if (is_edp(intel_dp)) {
2994                 status = intel_panel_detect(dev);
2995                 if (status == connector_status_unknown)
2996                         status = connector_status_connected;
2997                 return status;
2998         }
2999
3000         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3001                 return connector_status_disconnected;
3002
3003         return intel_dp_detect_dpcd(intel_dp);
3004 }
3005
3006 static enum drm_connector_status
3007 g4x_dp_detect(struct intel_dp *intel_dp)
3008 {
3009         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3012         uint32_t bit;
3013
3014         /* Can't disconnect eDP, but you can close the lid... */
3015         if (is_edp(intel_dp)) {
3016                 enum drm_connector_status status;
3017
3018                 status = intel_panel_detect(dev);
3019                 if (status == connector_status_unknown)
3020                         status = connector_status_connected;
3021                 return status;
3022         }
3023
3024         if (IS_VALLEYVIEW(dev)) {
3025                 switch (intel_dig_port->port) {
3026                 case PORT_B:
3027                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3028                         break;
3029                 case PORT_C:
3030                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3031                         break;
3032                 case PORT_D:
3033                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3034                         break;
3035                 default:
3036                         return connector_status_unknown;
3037                 }
3038         } else {
3039                 switch (intel_dig_port->port) {
3040                 case PORT_B:
3041                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3042                         break;
3043                 case PORT_C:
3044                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3045                         break;
3046                 case PORT_D:
3047                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3048                         break;
3049                 default:
3050                         return connector_status_unknown;
3051                 }
3052         }
3053
3054         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3055                 return connector_status_disconnected;
3056
3057         return intel_dp_detect_dpcd(intel_dp);
3058 }
3059
3060 static struct edid *
3061 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
3062 {
3063         struct intel_connector *intel_connector = to_intel_connector(connector);
3064
3065         /* use cached edid if we have one */
3066         if (intel_connector->edid) {
3067                 /* invalid edid */
3068                 if (IS_ERR(intel_connector->edid))
3069                         return NULL;
3070
3071                 return drm_edid_duplicate(intel_connector->edid);
3072         }
3073
3074         return drm_get_edid(connector, adapter);
3075 }
3076
3077 static int
3078 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
3079 {
3080         struct intel_connector *intel_connector = to_intel_connector(connector);
3081
3082         /* use cached edid if we have one */
3083         if (intel_connector->edid) {
3084                 /* invalid edid */
3085                 if (IS_ERR(intel_connector->edid))
3086                         return 0;
3087
3088                 return intel_connector_update_modes(connector,
3089                                                     intel_connector->edid);
3090         }
3091
3092         return intel_ddc_get_modes(connector, adapter);
3093 }
3094
3095 static enum drm_connector_status
3096 intel_dp_detect(struct drm_connector *connector, bool force)
3097 {
3098         struct intel_dp *intel_dp = intel_attached_dp(connector);
3099         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3100         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3101         struct drm_device *dev = connector->dev;
3102         struct drm_i915_private *dev_priv = dev->dev_private;
3103         enum drm_connector_status status;
3104         struct edid *edid = NULL;
3105
3106         intel_runtime_pm_get(dev_priv);
3107
3108         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3109                       connector->base.id, drm_get_connector_name(connector));
3110
3111         intel_dp->has_audio = false;
3112
3113         if (HAS_PCH_SPLIT(dev))
3114                 status = ironlake_dp_detect(intel_dp);
3115         else
3116                 status = g4x_dp_detect(intel_dp);
3117
3118         if (status != connector_status_connected)
3119                 goto out;
3120
3121         intel_dp_probe_oui(intel_dp);
3122
3123         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3124                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3125         } else {
3126                 edid = intel_dp_get_edid(connector, intel_dp->adapter);
3127                 if (edid) {
3128                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3129                         kfree(edid);
3130                 }
3131         }
3132
3133         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3134                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3135         status = connector_status_connected;
3136
3137 out:
3138         intel_runtime_pm_put(dev_priv);
3139         return status;
3140 }
3141
3142 static int intel_dp_get_modes(struct drm_connector *connector)
3143 {
3144         struct intel_dp *intel_dp = intel_attached_dp(connector);
3145         struct intel_connector *intel_connector = to_intel_connector(connector);
3146         struct drm_device *dev = connector->dev;
3147         int ret;
3148
3149         /* We should parse the EDID data and find out if it has an audio sink
3150          */
3151
3152         ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
3153         if (ret)
3154                 return ret;
3155
3156         /* if eDP has no EDID, fall back to fixed mode */
3157         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3158                 struct drm_display_mode *mode;
3159                 mode = drm_mode_duplicate(dev,
3160                                           intel_connector->panel.fixed_mode);
3161                 if (mode) {
3162                         drm_mode_probed_add(connector, mode);
3163                         return 1;
3164                 }
3165         }
3166         return 0;
3167 }
3168
3169 static bool
3170 intel_dp_detect_audio(struct drm_connector *connector)
3171 {
3172         struct intel_dp *intel_dp = intel_attached_dp(connector);
3173         struct edid *edid;
3174         bool has_audio = false;
3175
3176         edid = intel_dp_get_edid(connector, intel_dp->adapter);
3177         if (edid) {
3178                 has_audio = drm_detect_monitor_audio(edid);
3179                 kfree(edid);
3180         }
3181
3182         return has_audio;
3183 }
3184
3185 static int
3186 intel_dp_set_property(struct drm_connector *connector,
3187                       struct drm_property *property,
3188                       uint64_t val)
3189 {
3190         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3191         struct intel_connector *intel_connector = to_intel_connector(connector);
3192         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3193         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3194         int ret;
3195
3196         ret = drm_object_property_set_value(&connector->base, property, val);
3197         if (ret)
3198                 return ret;
3199
3200         if (property == dev_priv->force_audio_property) {
3201                 int i = val;
3202                 bool has_audio;
3203
3204                 if (i == intel_dp->force_audio)
3205                         return 0;
3206
3207                 intel_dp->force_audio = i;
3208
3209                 if (i == HDMI_AUDIO_AUTO)
3210                         has_audio = intel_dp_detect_audio(connector);
3211                 else
3212                         has_audio = (i == HDMI_AUDIO_ON);
3213
3214                 if (has_audio == intel_dp->has_audio)
3215                         return 0;
3216
3217                 intel_dp->has_audio = has_audio;
3218                 goto done;
3219         }
3220
3221         if (property == dev_priv->broadcast_rgb_property) {
3222                 bool old_auto = intel_dp->color_range_auto;
3223                 uint32_t old_range = intel_dp->color_range;
3224
3225                 switch (val) {
3226                 case INTEL_BROADCAST_RGB_AUTO:
3227                         intel_dp->color_range_auto = true;
3228                         break;
3229                 case INTEL_BROADCAST_RGB_FULL:
3230                         intel_dp->color_range_auto = false;
3231                         intel_dp->color_range = 0;
3232                         break;
3233                 case INTEL_BROADCAST_RGB_LIMITED:
3234                         intel_dp->color_range_auto = false;
3235                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3236                         break;
3237                 default:
3238                         return -EINVAL;
3239                 }
3240
3241                 if (old_auto == intel_dp->color_range_auto &&
3242                     old_range == intel_dp->color_range)
3243                         return 0;
3244
3245                 goto done;
3246         }
3247
3248         if (is_edp(intel_dp) &&
3249             property == connector->dev->mode_config.scaling_mode_property) {
3250                 if (val == DRM_MODE_SCALE_NONE) {
3251                         DRM_DEBUG_KMS("no scaling not supported\n");
3252                         return -EINVAL;
3253                 }
3254
3255                 if (intel_connector->panel.fitting_mode == val) {
3256                         /* the eDP scaling property is not changed */
3257                         return 0;
3258                 }
3259                 intel_connector->panel.fitting_mode = val;
3260
3261                 goto done;
3262         }
3263
3264         return -EINVAL;
3265
3266 done:
3267         if (intel_encoder->base.crtc)
3268                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3269
3270         return 0;
3271 }
3272
3273 static void
3274 intel_dp_connector_destroy(struct drm_connector *connector)
3275 {
3276         struct intel_connector *intel_connector = to_intel_connector(connector);
3277
3278         if (!IS_ERR_OR_NULL(intel_connector->edid))
3279                 kfree(intel_connector->edid);
3280
3281         /* Can't call is_edp() since the encoder may have been destroyed
3282          * already. */
3283         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3284                 intel_panel_fini(&intel_connector->panel);
3285
3286         drm_connector_cleanup(connector);
3287         kfree(connector);
3288 }
3289
3290 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3291 {
3292         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3293         struct intel_dp *intel_dp = &intel_dig_port->dp;
3294         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3295
3296         if (intel_dp->dp_iic_bus != NULL) {
3297                 if (intel_dp->adapter != NULL) {
3298                         device_delete_child(intel_dp->dp_iic_bus,
3299                         intel_dp->adapter);
3300                 }
3301                 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
3302         }
3303         drm_encoder_cleanup(encoder);
3304         if (is_edp(intel_dp)) {
3305                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3306                 mutex_lock(&dev->mode_config.mutex);
3307                 ironlake_panel_vdd_off_sync(intel_dp);
3308                 mutex_unlock(&dev->mode_config.mutex);
3309         }
3310         kfree(intel_dig_port);
3311 }
3312
3313 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3314         .dpms = intel_connector_dpms,
3315         .detect = intel_dp_detect,
3316         .fill_modes = drm_helper_probe_single_connector_modes,
3317         .set_property = intel_dp_set_property,
3318         .destroy = intel_dp_connector_destroy,
3319 };
3320
3321 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3322         .get_modes = intel_dp_get_modes,
3323         .mode_valid = intel_dp_mode_valid,
3324         .best_encoder = intel_best_encoder,
3325 };
3326
3327 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3328         .destroy = intel_dp_encoder_destroy,
3329 };
3330
3331 static void
3332 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3333 {
3334         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3335
3336         intel_dp_check_link_status(intel_dp);
3337 }
3338
3339 /* Return which DP Port should be selected for Transcoder DP control */
3340 int
3341 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct intel_encoder *intel_encoder;
3345         struct intel_dp *intel_dp;
3346
3347         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3348                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3349
3350                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3351                     intel_encoder->type == INTEL_OUTPUT_EDP)
3352                         return intel_dp->output_reg;
3353         }
3354
3355         return -1;
3356 }
3357
3358 /* check the VBT to see whether the eDP is on DP-D port */
3359 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3360 {
3361         struct drm_i915_private *dev_priv = dev->dev_private;
3362         union child_device_config *p_child;
3363         int i;
3364         static const short port_mapping[] = {
3365                 [PORT_B] = PORT_IDPB,
3366                 [PORT_C] = PORT_IDPC,
3367                 [PORT_D] = PORT_IDPD,
3368         };
3369
3370         if (port == PORT_A)
3371                 return true;
3372
3373         if (!dev_priv->vbt.child_dev_num)
3374                 return false;
3375
3376         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3377                 p_child = dev_priv->vbt.child_dev + i;
3378
3379                 if (p_child->common.dvo_port == port_mapping[port] &&
3380                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3381                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3382                         return true;
3383         }
3384         return false;
3385 }
3386
3387 static void
3388 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3389 {
3390         struct intel_connector *intel_connector = to_intel_connector(connector);
3391
3392         intel_attach_force_audio_property(connector);
3393         intel_attach_broadcast_rgb_property(connector);
3394         intel_dp->color_range_auto = true;
3395
3396         if (is_edp(intel_dp)) {
3397                 drm_mode_create_scaling_mode_property(connector->dev);
3398                 drm_object_attach_property(
3399                         &connector->base,
3400                         connector->dev->mode_config.scaling_mode_property,
3401                         DRM_MODE_SCALE_ASPECT);
3402                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3403         }
3404 }
3405
3406 static void
3407 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3408                                     struct intel_dp *intel_dp,
3409                                     struct edp_power_seq *out)
3410 {
3411         struct drm_i915_private *dev_priv = dev->dev_private;
3412         struct edp_power_seq cur, vbt, spec, final;
3413         u32 pp_on, pp_off, pp_div, pp;
3414         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3415
3416         if (HAS_PCH_SPLIT(dev)) {
3417                 pp_ctrl_reg = PCH_PP_CONTROL;
3418                 pp_on_reg = PCH_PP_ON_DELAYS;
3419                 pp_off_reg = PCH_PP_OFF_DELAYS;
3420                 pp_div_reg = PCH_PP_DIVISOR;
3421         } else {
3422                 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3423
3424                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3425                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3426                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3427                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3428         }
3429
3430         /* Workaround: Need to write PP_CONTROL with the unlock key as
3431          * the very first thing. */
3432         pp = ironlake_get_pp_control(intel_dp);
3433         I915_WRITE(pp_ctrl_reg, pp);
3434
3435         pp_on = I915_READ(pp_on_reg);
3436         pp_off = I915_READ(pp_off_reg);
3437         pp_div = I915_READ(pp_div_reg);
3438
3439         /* Pull timing values out of registers */
3440         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3441                 PANEL_POWER_UP_DELAY_SHIFT;
3442
3443         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3444                 PANEL_LIGHT_ON_DELAY_SHIFT;
3445
3446         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3447                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3448
3449         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3450                 PANEL_POWER_DOWN_DELAY_SHIFT;
3451
3452         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3453                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3454
3455         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3456                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3457
3458         vbt = dev_priv->vbt.edp_pps;
3459
3460         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3461          * our hw here, which are all in 100usec. */
3462         spec.t1_t3 = 210 * 10;
3463         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3464         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3465         spec.t10 = 500 * 10;
3466         /* This one is special and actually in units of 100ms, but zero
3467          * based in the hw (so we need to add 100 ms). But the sw vbt
3468          * table multiplies it with 1000 to make it in units of 100usec,
3469          * too. */
3470         spec.t11_t12 = (510 + 100) * 10;
3471
3472         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3473                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3474
3475         /* Use the max of the register settings and vbt. If both are
3476          * unset, fall back to the spec limits. */
3477 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3478                                        spec.field : \
3479                                        max(cur.field, vbt.field))
3480         assign_final(t1_t3);
3481         assign_final(t8);
3482         assign_final(t9);
3483         assign_final(t10);
3484         assign_final(t11_t12);
3485 #undef assign_final
3486
3487 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3488         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3489         intel_dp->backlight_on_delay = get_delay(t8);
3490         intel_dp->backlight_off_delay = get_delay(t9);
3491         intel_dp->panel_power_down_delay = get_delay(t10);
3492         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3493 #undef get_delay
3494
3495         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3496                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3497                       intel_dp->panel_power_cycle_delay);
3498
3499         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3500                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3501
3502         if (out)
3503                 *out = final;
3504 }
3505
3506 static void
3507 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3508                                               struct intel_dp *intel_dp,
3509                                               struct edp_power_seq *seq)
3510 {
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         u32 pp_on, pp_off, pp_div, port_sel = 0;
3513         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3514         int pp_on_reg, pp_off_reg, pp_div_reg;
3515
3516         if (HAS_PCH_SPLIT(dev)) {
3517                 pp_on_reg = PCH_PP_ON_DELAYS;
3518                 pp_off_reg = PCH_PP_OFF_DELAYS;
3519                 pp_div_reg = PCH_PP_DIVISOR;
3520         } else {
3521                 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3522
3523                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3524                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3525                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3526         }
3527
3528         /* And finally store the new values in the power sequencer. */
3529         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3530                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3531         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3532                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3533         /* Compute the divisor for the pp clock, simply match the Bspec
3534          * formula. */
3535         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3536         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3537                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3538
3539         /* Haswell doesn't have any port selection bits for the panel
3540          * power sequencer any more. */
3541         if (IS_VALLEYVIEW(dev)) {
3542                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3543                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3544                 else
3545                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3546         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3547                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3548                         port_sel = PANEL_PORT_SELECT_DPA;
3549                 else
3550                         port_sel = PANEL_PORT_SELECT_DPD;
3551         }
3552
3553         pp_on |= port_sel;
3554
3555         I915_WRITE(pp_on_reg, pp_on);
3556         I915_WRITE(pp_off_reg, pp_off);
3557         I915_WRITE(pp_div_reg, pp_div);
3558
3559         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3560                       I915_READ(pp_on_reg),
3561                       I915_READ(pp_off_reg),
3562                       I915_READ(pp_div_reg));
3563 }
3564
3565 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3566                                      struct intel_connector *intel_connector)
3567 {
3568         struct drm_connector *connector = &intel_connector->base;
3569         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3570         struct drm_device *dev = intel_dig_port->base.base.dev;
3571         struct drm_i915_private *dev_priv = dev->dev_private;
3572         struct drm_display_mode *fixed_mode = NULL;
3573         struct edp_power_seq power_seq = { 0 };
3574         bool has_dpcd;
3575         struct drm_display_mode *scan;
3576         struct edid *edid;
3577
3578         if (!is_edp(intel_dp))
3579                 return true;
3580
3581         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3582
3583         /* Cache DPCD and EDID for edp. */
3584         ironlake_edp_panel_vdd_on(intel_dp);
3585         has_dpcd = intel_dp_get_dpcd(intel_dp);
3586         ironlake_edp_panel_vdd_off(intel_dp, false);
3587
3588         if (has_dpcd) {
3589                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3590                         dev_priv->no_aux_handshake =
3591                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3592                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3593         } else {
3594                 /* if this fails, presume the device is a ghost */
3595                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3596                 return false;
3597         }
3598
3599         /* We now know it's not a ghost, init power sequence regs. */
3600         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3601                                                       &power_seq);
3602
3603         edid = drm_get_edid(connector, intel_dp->adapter);
3604         if (edid) {
3605                 if (drm_add_edid_modes(connector, edid)) {
3606                         drm_mode_connector_update_edid_property(connector,
3607                                                                 edid);
3608                         drm_edid_to_eld(connector, edid);
3609                 } else {
3610                         kfree(edid);
3611                         edid = ERR_PTR(-EINVAL);
3612                 }
3613         } else {
3614                 edid = ERR_PTR(-ENOENT);
3615         }
3616         intel_connector->edid = edid;
3617
3618         /* prefer fixed mode from EDID if available */
3619         list_for_each_entry(scan, &connector->probed_modes, head) {
3620                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3621                         fixed_mode = drm_mode_duplicate(dev, scan);
3622                         break;
3623                 }
3624         }
3625
3626         /* fallback to VBT if available for eDP */
3627         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3628                 fixed_mode = drm_mode_duplicate(dev,
3629                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3630                 if (fixed_mode)
3631                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3632         }
3633
3634         intel_panel_init(&intel_connector->panel, fixed_mode);
3635         intel_panel_setup_backlight(connector);
3636
3637         return true;
3638 }
3639
3640 bool
3641 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3642                         struct intel_connector *intel_connector)
3643 {
3644         struct drm_connector *connector = &intel_connector->base;
3645         struct intel_dp *intel_dp = &intel_dig_port->dp;
3646         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3647         struct drm_device *dev = intel_encoder->base.dev;
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649         enum port port = intel_dig_port->port;
3650         const char *name = NULL;
3651         int type, error;
3652
3653         /* Preserve the current hw state. */
3654         intel_dp->DP = I915_READ(intel_dp->output_reg);
3655         intel_dp->attached_connector = intel_connector;
3656
3657         if (intel_dp_is_edp(dev, port))
3658                 type = DRM_MODE_CONNECTOR_eDP;
3659         else
3660                 type = DRM_MODE_CONNECTOR_DisplayPort;
3661
3662         /*
3663          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3664          * for DP the encoder type can be set by the caller to
3665          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3666          */
3667         if (type == DRM_MODE_CONNECTOR_eDP)
3668                 intel_encoder->type = INTEL_OUTPUT_EDP;
3669
3670         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3671                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3672                         port_name(port));
3673
3674         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3675         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3676
3677         connector->interlace_allowed = true;
3678         connector->doublescan_allowed = 0;
3679
3680         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3681                           ironlake_panel_vdd_work);
3682
3683         intel_connector_attach_encoder(intel_connector, intel_encoder);
3684         drm_sysfs_connector_add(connector);
3685
3686         if (HAS_DDI(dev))
3687                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3688         else
3689                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3690
3691         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3692         if (HAS_DDI(dev)) {
3693                 switch (intel_dig_port->port) {
3694                 case PORT_A:
3695                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3696                         break;
3697                 case PORT_B:
3698                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3699                         break;
3700                 case PORT_C:
3701                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3702                         break;
3703                 case PORT_D:
3704                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3705                         break;
3706                 default:
3707                         BUG();
3708                 }
3709         }
3710
3711         /* Set up the DDC bus. */
3712         switch (port) {
3713         case PORT_A:
3714                 intel_encoder->hpd_pin = HPD_PORT_A;
3715                 name = "DPDDC-A";
3716                 break;
3717         case PORT_B:
3718                 intel_encoder->hpd_pin = HPD_PORT_B;
3719                 name = "DPDDC-B";
3720                 break;
3721         case PORT_C:
3722                 intel_encoder->hpd_pin = HPD_PORT_C;
3723                 name = "DPDDC-C";
3724                 break;
3725         case PORT_D:
3726                 intel_encoder->hpd_pin = HPD_PORT_D;
3727                 name = "DPDDC-D";
3728                 break;
3729         default:
3730                 BUG();
3731         }
3732
3733         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3734         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3735              error, port_name(port));
3736
3737         intel_dp->psr_setup_done = false;
3738
3739         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3740 #if 0
3741                 i2c_del_adapter(&intel_dp->adapter);
3742 #endif
3743                 if (is_edp(intel_dp)) {
3744                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3745                         mutex_lock(&dev->mode_config.mutex);
3746                         ironlake_panel_vdd_off_sync(intel_dp);
3747                         mutex_unlock(&dev->mode_config.mutex);
3748                 }
3749                 drm_sysfs_connector_remove(connector);
3750                 drm_connector_cleanup(connector);
3751                 return false;
3752         }
3753
3754         intel_dp_add_properties(intel_dp, connector);
3755
3756         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3757          * 0xd.  Failure to do so will result in spurious interrupts being
3758          * generated on the port when a cable is not attached.
3759          */
3760         if (IS_G4X(dev) && !IS_GM45(dev)) {
3761                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3762                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3763         }
3764
3765         return true;
3766 }
3767
3768 void
3769 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3770 {
3771         struct intel_digital_port *intel_dig_port;
3772         struct intel_encoder *intel_encoder;
3773         struct drm_encoder *encoder;
3774         struct intel_connector *intel_connector;
3775
3776         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3777         if (!intel_dig_port)
3778                 return;
3779
3780         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3781         if (!intel_connector) {
3782                 kfree(intel_dig_port);
3783                 return;
3784         }
3785
3786         intel_encoder = &intel_dig_port->base;
3787         encoder = &intel_encoder->base;
3788
3789         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3790                          DRM_MODE_ENCODER_TMDS);
3791
3792         intel_encoder->compute_config = intel_dp_compute_config;
3793         intel_encoder->mode_set = intel_dp_mode_set;
3794         intel_encoder->disable = intel_disable_dp;
3795         intel_encoder->post_disable = intel_post_disable_dp;
3796         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3797         intel_encoder->get_config = intel_dp_get_config;
3798         if (IS_VALLEYVIEW(dev)) {
3799                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3800                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3801                 intel_encoder->enable = vlv_enable_dp;
3802         } else {
3803                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3804                 intel_encoder->enable = g4x_enable_dp;
3805         }
3806
3807         intel_dig_port->port = port;
3808         intel_dig_port->dp.output_reg = output_reg;
3809
3810         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3811         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3812         intel_encoder->cloneable = false;
3813         intel_encoder->hot_plug = intel_dp_hot_plug;
3814
3815         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3816                 drm_encoder_cleanup(encoder);
3817                 kfree(intel_dig_port);
3818                 kfree(intel_connector);
3819         }
3820 }