sys/dev/sound/pci/hda/hdac.c

   1 /*-
   2  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
   3  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
   4  * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * Intel High Definition Audio (Controller) driver for FreeBSD.
  31  */
  32
  33 #ifdef HAVE_KERNEL_OPTION_HEADERS
  34 #include "opt_snd.h"
  35 #endif
  36
  37 #include <dev/sound/pcm/sound.h>
  38 #include <bus/pci/pcireg.h>
  39 #include <bus/pci/pcivar.h>
  40
  41 #include <sys/ctype.h>
  42 #include <sys/taskqueue.h>
  43
  44 #include <dev/sound/pci/hda/hdac_private.h>
  45 #include <dev/sound/pci/hda/hdac_reg.h>
  46 #include <dev/sound/pci/hda/hda_reg.h>
  47 #include <dev/sound/pci/hda/hdac.h>
  48
  49 #define HDA_DRV_TEST_REV        "20120126_0002"
  50
  51 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 275101 2014-11-26 04:23:21Z mav $");
  52
  53 #define hdac_lock(sc)           snd_mtxlock((sc)->lock)
  54 #define hdac_unlock(sc)         snd_mtxunlock((sc)->lock)
  55 #define hdac_lockassert(sc)     snd_mtxassert((sc)->lock)
  56 #define hdac_lockowned(sc)      (lockstatus((sc)->lock, curthread) == LK_EXCLUSIVE)
  57
  58 #define HDAC_QUIRK_64BIT        (1 << 0)
  59 #define HDAC_QUIRK_DMAPOS       (1 << 1)
  60 #define HDAC_QUIRK_MSI          (1 << 2)
  61
  62 static const struct {
  63         const char *key;
  64         uint32_t value;
  65 } hdac_quirks_tab[] = {
  66         { "64bit", HDAC_QUIRK_DMAPOS },
  67         { "dmapos", HDAC_QUIRK_DMAPOS },
  68         { "msi", HDAC_QUIRK_MSI },
  69 };
  70
  71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
  72
  73 static const struct {
  74         uint32_t        model;
  75         const char      *desc;
  76         char            quirks_on;
  77         char            quirks_off;
  78 } hdac_devices[] = {
  79         { HDA_INTEL_OAK,     "Intel Oaktrail",  0, 0 },
  80         { HDA_INTEL_BAY,     "Intel BayTrail",  0, 0 },
  81         { HDA_INTEL_HSW1,    "Intel Haswell",   0, 0 },
  82         { HDA_INTEL_HSW2,    "Intel Haswell",   0, 0 },
  83         { HDA_INTEL_HSW3,    "Intel Haswell",   0, 0 },
  84         { HDA_INTEL_CPT,     "Intel Cougar Point",      0, 0 },
  85         { HDA_INTEL_PATSBURG,"Intel Patsburg",  0, 0 },
  86         { HDA_INTEL_PPT1,    "Intel Panther Point",     0, 0 },
  87         { HDA_INTEL_LPT1,    "Intel Lynx Point",        0, 0 },
  88         { HDA_INTEL_LPT2,    "Intel Lynx Point",        0, 0 },
  89         { HDA_INTEL_WCPT,    "Intel Wildcat Point",     0, 0 },
  90         { HDA_INTEL_WELLS1,  "Intel Wellsburg", 0, 0 },
  91         { HDA_INTEL_WELLS2,  "Intel Wellsburg", 0, 0 },
  92         { HDA_INTEL_LPTLP1,  "Intel Lynx Point-LP",     0, 0 },
  93         { HDA_INTEL_LPTLP2,  "Intel Lynx Point-LP",     0, 0 },
  94         { HDA_INTEL_82801F,  "Intel 82801F",    0, 0 },
  95         { HDA_INTEL_63XXESB, "Intel 631x/632xESB",      0, 0 },
  96         { HDA_INTEL_82801G,  "Intel 82801G",    0, 0 },
  97         { HDA_INTEL_82801H,  "Intel 82801H",    0, 0 },
  98         { HDA_INTEL_82801I,  "Intel 82801I",    0, 0 },
  99         { HDA_INTEL_82801JI, "Intel 82801JI",   0, 0 },
 100         { HDA_INTEL_82801JD, "Intel 82801JD",   0, 0 },
 101         { HDA_INTEL_PCH,     "Intel 5 Series/3400 Series",      0, 0 },
 102         { HDA_INTEL_PCH2,    "Intel 5 Series/3400 Series",      0, 0 },
 103         { HDA_INTEL_SCH,     "Intel SCH",       0, 0 },
 104         { HDA_NVIDIA_MCP51,  "NVIDIA MCP51",    0, HDAC_QUIRK_MSI },
 105         { HDA_NVIDIA_MCP55,  "NVIDIA MCP55",    0, HDAC_QUIRK_MSI },
 106         { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61",   0, 0 },
 107         { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61",   0, 0 },
 108         { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65",   0, 0 },
 109         { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65",   0, 0 },
 110         { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67",   0, 0 },
 111         { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67",   0, 0 },
 112         { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73",   0, 0 },
 113         { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73",   0, 0 },
 114         { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 115         { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 116         { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 117         { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 118         { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79",   0, 0 },
 119         { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79",   0, 0 },
 120         { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79",   0, 0 },
 121         { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79",   0, 0 },
 122         { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89",   0, 0 },
 123         { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89",   0, 0 },
 124         { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89",   0, 0 },
 125         { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89",   0, 0 },
 126         { HDA_NVIDIA_0BE2,   "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
 127         { HDA_NVIDIA_0BE3,   "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
 128         { HDA_NVIDIA_0BE4,   "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
 129         { HDA_NVIDIA_GT100,  "NVIDIA GT100",    0, HDAC_QUIRK_MSI },
 130         { HDA_NVIDIA_GT104,  "NVIDIA GT104",    0, HDAC_QUIRK_MSI },
 131         { HDA_NVIDIA_GT106,  "NVIDIA GT106",    0, HDAC_QUIRK_MSI },
 132         { HDA_NVIDIA_GT108,  "NVIDIA GT108",    0, HDAC_QUIRK_MSI },
 133         { HDA_NVIDIA_GT116,  "NVIDIA GT116",    0, HDAC_QUIRK_MSI },
 134         { HDA_NVIDIA_GF119,  "NVIDIA GF119",    0, 0 },
 135         { HDA_NVIDIA_GF110_1, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 136         { HDA_NVIDIA_GF110_2, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 137         { HDA_ATI_SB450,     "ATI SB450",       0, 0 },
 138         { HDA_ATI_SB600,     "ATI SB600",       0, 0 },
 139         { HDA_ATI_RS600,     "ATI RS600",       0, 0 },
 140         { HDA_ATI_RS690,     "ATI RS690",       0, 0 },
 141         { HDA_ATI_RS780,     "ATI RS780",       0, 0 },
 142         { HDA_ATI_R600,      "ATI R600",        0, 0 },
 143         { HDA_ATI_RV610,     "ATI RV610",       0, 0 },
 144         { HDA_ATI_RV620,     "ATI RV620",       0, 0 },
 145         { HDA_ATI_RV630,     "ATI RV630",       0, 0 },
 146         { HDA_ATI_RV635,     "ATI RV635",       0, 0 },
 147         { HDA_ATI_RV710,     "ATI RV710",       0, 0 },
 148         { HDA_ATI_RV730,     "ATI RV730",       0, 0 },
 149         { HDA_ATI_RV740,     "ATI RV740",       0, 0 },
 150         { HDA_ATI_RV770,     "ATI RV770",       0, 0 },
 151         { HDA_ATI_RV810,     "ATI RV810",       0, 0 },
 152         { HDA_ATI_RV830,     "ATI RV830",       0, 0 },
 153         { HDA_ATI_RV840,     "ATI RV840",       0, 0 },
 154         { HDA_ATI_RV870,     "ATI RV870",       0, 0 },
 155         { HDA_ATI_RV910,     "ATI RV910",       0, 0 },
 156         { HDA_ATI_RV930,     "ATI RV930",       0, 0 },
 157         { HDA_ATI_RV940,     "ATI RV940",       0, 0 },
 158         { HDA_ATI_RV970,     "ATI RV970",       0, 0 },
 159         { HDA_ATI_R1000,     "ATI R1000",       0, 0 },
 160         { HDA_RDC_M3010,     "RDC M3010",       0, 0 },
 161         { HDA_VIA_VT82XX,    "VIA VT8251/8237A",0, 0 },
 162         { HDA_SIS_966,       "SiS 966",         0, 0 },
 163         { HDA_ULI_M5461,     "ULI M5461",       0, 0 },
 164         /* Unknown */
 165         { HDA_INTEL_ALL,  "Intel",              0, 0 },
 166         { HDA_NVIDIA_ALL, "NVIDIA",             0, 0 },
 167         { HDA_ATI_ALL,    "ATI",                0, 0 },
 168         { HDA_VIA_ALL,    "VIA",                0, 0 },
 169         { HDA_SIS_ALL,    "SiS",                0, 0 },
 170         { HDA_ULI_ALL,    "ULI",                0, 0 },
 171 };
 172
 173 static const struct {
 174         uint16_t vendor;
 175         uint8_t reg;
 176         uint8_t mask;
 177         uint8_t enable;
 178 } hdac_pcie_snoop[] = {
 179         {  INTEL_VENDORID, 0x00, 0x00, 0x00 },
 180         {    ATI_VENDORID, 0x42, 0xf8, 0x02 },
 181         { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
 182 };
 183
 184 /****************************************************************************
 185  * Function prototypes
 186  ****************************************************************************/
 187 static void     hdac_intr_handler(void *);
 188 static int      hdac_reset(struct hdac_softc *, int);
 189 static int      hdac_get_capabilities(struct hdac_softc *);
 190 static void     hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
 191 static int      hdac_dma_alloc(struct hdac_softc *,
 192                                         struct hdac_dma *, bus_size_t);
 193 static void     hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
 194 static int      hdac_mem_alloc(struct hdac_softc *);
 195 static void     hdac_mem_free(struct hdac_softc *);
 196 static int      hdac_irq_alloc(struct hdac_softc *);
 197 static void     hdac_irq_free(struct hdac_softc *);
 198 static void     hdac_corb_init(struct hdac_softc *);
 199 static void     hdac_rirb_init(struct hdac_softc *);
 200 static void     hdac_corb_start(struct hdac_softc *);
 201 static void     hdac_rirb_start(struct hdac_softc *);
 202
 203 static void     hdac_attach2(void *);
 204
 205 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
 206
 207 static int      hdac_probe(device_t);
 208 static int      hdac_attach(device_t);
 209 static int      hdac_detach(device_t);
 210 static int      hdac_suspend(device_t);
 211 static int      hdac_resume(device_t);
 212
 213 static int      hdac_rirb_flush(struct hdac_softc *sc);
 214 static int      hdac_unsolq_flush(struct hdac_softc *sc);
 215
 216 #define hdac_command(a1, a2, a3)        \
 217                 hdac_send_command(a1, a3, a2)
 218
 219 /* This function surely going to make its way into upper level someday. */
 220 static void
 221 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
 222 {
 223         const char *res = NULL;
 224         int i = 0, j, k, len, inv;
 225
 226         if (resource_string_value(device_get_name(sc->dev),
 227             device_get_unit(sc->dev), "config", &res) != 0)
 228                 return;
 229         if (!(res != NULL && strlen(res) > 0))
 230                 return;
 231         HDA_BOOTVERBOSE(
 232                 device_printf(sc->dev, "Config options:");
 233         );
 234         for (;;) {
 235                 while (res[i] != '\0' &&
 236                     (res[i] == ',' || isspace(res[i]) != 0))
 237                         i++;
 238                 if (res[i] == '\0') {
 239                         HDA_BOOTVERBOSE(
 240                                 kprintf("\n");
 241                         );
 242                         return;
 243                 }
 244                 j = i;
 245                 while (res[j] != '\0' &&
 246                     !(res[j] == ',' || isspace(res[j]) != 0))
 247                         j++;
 248                 len = j - i;
 249                 if (len > 2 && strncmp(res + i, "no", 2) == 0)
 250                         inv = 2;
 251                 else
 252                         inv = 0;
 253                 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) {
 254                         if (strncmp(res + i + inv,
 255                             hdac_quirks_tab[k].key, len - inv) != 0)
 256                                 continue;
 257                         if (len - inv != strlen(hdac_quirks_tab[k].key))
 258                                 continue;
 259                         HDA_BOOTVERBOSE(
 260                                 kprintf(" %s%s", (inv != 0) ? "no" : "",
 261                                     hdac_quirks_tab[k].key);
 262                         );
 263                         if (inv == 0) {
 264                                 *on |= hdac_quirks_tab[k].value;
 265                                 *on &= ~hdac_quirks_tab[k].value;
 266                         } else if (inv != 0) {
 267                                 *off |= hdac_quirks_tab[k].value;
 268                                 *off &= ~hdac_quirks_tab[k].value;
 269                         }
 270                         break;
 271                 }
 272                 i = j;
 273         }
 274 }
 275
 276 /****************************************************************************
 277  * void hdac_intr_handler(void *)
 278  *
 279  * Interrupt handler. Processes interrupts received from the hdac.
 280  ****************************************************************************/
 281 static void
 282 hdac_intr_handler(void *context)
 283 {
 284         struct hdac_softc *sc;
 285         device_t dev;
 286         uint32_t intsts;
 287         uint8_t rirbsts;
 288         int i;
 289
 290         sc = (struct hdac_softc *)context;
 291         hdac_lock(sc);
 292
 293         /* Do we have anything to do? */
 294         intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
 295         if ((intsts & HDAC_INTSTS_GIS) == 0) {
 296                 hdac_unlock(sc);
 297                 return;
 298         }
 299
 300         /* Was this a controller interrupt? */
 301         if (intsts & HDAC_INTSTS_CIS) {
 302                 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 303                 /* Get as many responses that we can */
 304                 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
 305                         HDAC_WRITE_1(&sc->mem,
 306                             HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
 307                         hdac_rirb_flush(sc);
 308                         rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 309                 }
 310                 if (sc->unsolq_rp != sc->unsolq_wp)
 311                         taskqueue_enqueue(taskqueue_thread[mycpuid], &sc->unsolq_task);
 312         }
 313
 314         if (intsts & HDAC_INTSTS_SIS_MASK) {
 315                 for (i = 0; i < sc->num_ss; i++) {
 316                         if ((intsts & (1 << i)) == 0)
 317                                 continue;
 318                         HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
 319                             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
 320                         if ((dev = sc->streams[i].dev) != NULL) {
 321                                 HDAC_STREAM_INTR(dev,
 322                                     sc->streams[i].dir, sc->streams[i].stream);
 323                         }
 324                 }
 325         }
 326
 327         HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
 328         hdac_unlock(sc);
 329 }
 330
 331 static void
 332 hdac_poll_callback(void *arg)
 333 {
 334         struct hdac_softc *sc = arg;
 335
 336         if (sc == NULL)
 337                 return;
 338
 339         hdac_lock(sc);
 340         if (sc->polling == 0) {
 341                 hdac_unlock(sc);
 342                 return;
 343         }
 344         callout_reset(&sc->poll_callout, sc->poll_ival,
 345             hdac_poll_callback, sc);
 346         hdac_unlock(sc);
 347
 348         hdac_intr_handler(sc);
 349 }
 350
 351 /****************************************************************************
 352  * int hdac_reset(hdac_softc *, int)
 353  *
 354  * Reset the hdac to a quiescent and known state.
 355  ****************************************************************************/
 356 static int
 357 hdac_reset(struct hdac_softc *sc, int wakeup)
 358 {
 359         uint32_t gctl;
 360         uint32_t wee;
 361         int count, i;
 362
 363         /*
 364          * Stop all Streams DMA engine
 365          */
 366         for (i = 0; i < sc->num_iss; i++)
 367                 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
 368         for (i = 0; i < sc->num_oss; i++)
 369                 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
 370         for (i = 0; i < sc->num_bss; i++)
 371                 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
 372
 373         /*
 374          * Stop Control DMA engines.
 375          */
 376         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
 377         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
 378
 379         /*
 380          * Reset DMA position buffer.
 381          */
 382         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
 383         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
 384
 385         /*
 386          * Reset the controller. The reset must remain asserted for
 387          * a minimum of 100us.
 388          */
 389         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 390         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
 391         count = 10000;
 392         do {
 393                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 394                 if (!(gctl & HDAC_GCTL_CRST))
 395                         break;
 396                 DELAY(10);
 397         } while (--count);
 398         if (gctl & HDAC_GCTL_CRST) {
 399                 device_printf(sc->dev, "Unable to put hdac in reset\n");
 400                 return (ENXIO);
 401         }
 402
 403         /* If wakeup is not requested - leave the controller in reset state. */
 404         if (!wakeup)
 405                 return (0);
 406
 407         DELAY(100);
 408         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 409         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
 410         count = 10000;
 411         do {
 412                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 413                 if (gctl & HDAC_GCTL_CRST)
 414                         break;
 415                 DELAY(10);
 416         } while (--count);
 417         if (!(gctl & HDAC_GCTL_CRST)) {
 418                 device_printf(sc->dev, "Device stuck in reset\n");
 419                 return (ENXIO);
 420         }
 421
 422         /*
 423          * Wait for codecs to finish their own reset sequence. The delay here
 424          * should be of 250us but for some reasons, on it's not enough on my
 425          * computer. Let's use twice as much as necessary to make sure that
 426          * it's reset properly.
 427          */
 428         DELAY(1000);
 429
 430         /*
 431          * BIOS May have left some wake bits enabled / pending, which can
 432          *      force a continuous interrupt.  Make sure it is turned off.
 433          */
 434         wee = HDAC_READ_2(&sc->mem, HDAC_WAKEEN);
 435         HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, wee & ~HDAC_WAKEEN_SDIWEN_MASK);
 436         /*HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, HDAC_STATESTS_SDIWAKE_MASK);*/
 437
 438         return (0);
 439 }
 440
 441
 442 /****************************************************************************
 443  * int hdac_get_capabilities(struct hdac_softc *);
 444  *
 445  * Retreive the general capabilities of the hdac;
 446  *      Number of Input Streams
 447  *      Number of Output Streams
 448  *      Number of bidirectional Streams
 449  *      64bit ready
 450  *      CORB and RIRB sizes
 451  ****************************************************************************/
 452 static int
 453 hdac_get_capabilities(struct hdac_softc *sc)
 454 {
 455         uint16_t gcap;
 456         uint8_t corbsize, rirbsize;
 457
 458         gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
 459         sc->num_iss = HDAC_GCAP_ISS(gcap);
 460         sc->num_oss = HDAC_GCAP_OSS(gcap);
 461         sc->num_bss = HDAC_GCAP_BSS(gcap);
 462         sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
 463         sc->num_sdo = HDAC_GCAP_NSDO(gcap);
 464         sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
 465         if (sc->quirks_on & HDAC_QUIRK_64BIT)
 466                 sc->support_64bit = 1;
 467         else if (sc->quirks_off & HDAC_QUIRK_64BIT)
 468                 sc->support_64bit = 0;
 469
 470         corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
 471         if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
 472             HDAC_CORBSIZE_CORBSZCAP_256)
 473                 sc->corb_size = 256;
 474         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
 475             HDAC_CORBSIZE_CORBSZCAP_16)
 476                 sc->corb_size = 16;
 477         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
 478             HDAC_CORBSIZE_CORBSZCAP_2)
 479                 sc->corb_size = 2;
 480         else {
 481                 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
 482                     __func__, corbsize);
 483                 return (ENXIO);
 484         }
 485
 486         rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
 487         if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
 488             HDAC_RIRBSIZE_RIRBSZCAP_256)
 489                 sc->rirb_size = 256;
 490         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
 491             HDAC_RIRBSIZE_RIRBSZCAP_16)
 492                 sc->rirb_size = 16;
 493         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
 494             HDAC_RIRBSIZE_RIRBSZCAP_2)
 495                 sc->rirb_size = 2;
 496         else {
 497                 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
 498                     __func__, rirbsize);
 499                 return (ENXIO);
 500         }
 501
 502         HDA_BOOTVERBOSE(
 503                 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
 504                     "NSDO %d%s, CORB %d, RIRB %d\n",
 505                     sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
 506                     sc->support_64bit ? ", 64bit" : "",
 507                     sc->corb_size, sc->rirb_size);
 508         );
 509
 510         return (0);
 511 }
 512
 513
 514 /****************************************************************************
 515  * void hdac_dma_cb
 516  *
 517  * This function is called by bus_dmamap_load when the mapping has been
 518  * established. We just record the physical address of the mapping into
 519  * the struct hdac_dma passed in.
 520  ****************************************************************************/
 521 static void
 522 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
 523 {
 524         struct hdac_dma *dma;
 525
 526         if (error == 0) {
 527                 dma = (struct hdac_dma *)callback_arg;
 528                 dma->dma_paddr = segs[0].ds_addr;
 529         }
 530 }
 531
 532
 533 /****************************************************************************
 534  * int hdac_dma_alloc
 535  *
 536  * This function allocate and setup a dma region (struct hdac_dma).
 537  * It must be freed by a corresponding hdac_dma_free.
 538  ****************************************************************************/
 539 static int
 540 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
 541 {
 542         bus_size_t alignment, roundsz;
 543         int result;
 544
 545         if (sc->flags & HDAC_F_DMA_NOCACHE)
 546                 alignment = roundup2(HDA_DMA_ALIGNMENT, PAGE_SIZE);
 547         else
 548                 alignment = HDA_DMA_ALIGNMENT;
 549
 550         roundsz = roundup2(size, alignment);
 551         bzero(dma, sizeof(*dma));
 552
 553         /*
 554          * Create a DMA tag
 555          */
 556         result = bus_dma_tag_create(
 557             bus_get_dma_tag(sc->dev),           /* parent */
 558             alignment,                          /* alignment */
 559             0,                                  /* boundary */
 560             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
 561                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
 562             BUS_SPACE_MAXADDR,                  /* highaddr */
 563             NULL,                               /* filtfunc */
 564             NULL,                               /* fistfuncarg */
 565             roundsz,                            /* maxsize */
 566             1,                                  /* nsegments */
 567             roundsz,                            /* maxsegsz */
 568             0,                                  /* flags */
 569             &dma->dma_tag);                     /* dmat */
 570         if (result != 0) {
 571                 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
 572                     __func__, result);
 573                 goto hdac_dma_alloc_fail;
 574         }
 575
 576         /*
 577          * Allocate DMA memory
 578          */
 579         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
 580             BUS_DMA_NOWAIT | BUS_DMA_ZERO |
 581             ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
 582             &dma->dma_map);
 583         if (result != 0) {
 584                 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
 585                     __func__, result);
 586                 goto hdac_dma_alloc_fail;
 587         }
 588
 589         dma->dma_size = roundsz;
 590
 591         /*
 592          * Map the memory
 593          */
 594         result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
 595             (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
 596         if (result != 0 || dma->dma_paddr == 0) {
 597                 if (result == 0)
 598                         result = ENOMEM;
 599                 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
 600                     __func__, result);
 601                 goto hdac_dma_alloc_fail;
 602         }
 603
 604         HDA_BOOTHVERBOSE(
 605                 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
 606                     __func__, (uintmax_t)size, (uintmax_t)roundsz);
 607         );
 608
 609         return (0);
 610
 611 hdac_dma_alloc_fail:
 612         hdac_dma_free(sc, dma);
 613
 614         return (result);
 615 }
 616
 617
 618 /****************************************************************************
 619  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
 620  *
 621  * Free a struct dhac_dma that has been previously allocated via the
 622  * hdac_dma_alloc function.
 623  ****************************************************************************/
 624 static void
 625 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
 626 {
 627         if (dma->dma_paddr != 0) {
 628 #if 0
 629                 /* Flush caches */
 630                 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
 631                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 632 #endif
 633                 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
 634                 dma->dma_paddr = 0;
 635         }
 636         if (dma->dma_vaddr != NULL) {
 637                 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
 638                 dma->dma_vaddr = NULL;
 639         }
 640         if (dma->dma_tag != NULL) {
 641                 bus_dma_tag_destroy(dma->dma_tag);
 642                 dma->dma_tag = NULL;
 643         }
 644         dma->dma_size = 0;
 645 }
 646
 647 /****************************************************************************
 648  * int hdac_mem_alloc(struct hdac_softc *)
 649  *
 650  * Allocate all the bus resources necessary to speak with the physical
 651  * controller.
 652  ****************************************************************************/
 653 static int
 654 hdac_mem_alloc(struct hdac_softc *sc)
 655 {
 656         struct hdac_mem *mem;
 657
 658         mem = &sc->mem;
 659         mem->mem_rid = PCIR_BAR(0);
 660         mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
 661             &mem->mem_rid, RF_ACTIVE);
 662         if (mem->mem_res == NULL) {
 663                 device_printf(sc->dev,
 664                     "%s: Unable to allocate memory resource\n", __func__);
 665                 return (ENOMEM);
 666         }
 667         mem->mem_tag = rman_get_bustag(mem->mem_res);
 668         mem->mem_handle = rman_get_bushandle(mem->mem_res);
 669
 670         return (0);
 671 }
 672
 673 /****************************************************************************
 674  * void hdac_mem_free(struct hdac_softc *)
 675  *
 676  * Free up resources previously allocated by hdac_mem_alloc.
 677  ****************************************************************************/
 678 static void
 679 hdac_mem_free(struct hdac_softc *sc)
 680 {
 681         struct hdac_mem *mem;
 682
 683         mem = &sc->mem;
 684         if (mem->mem_res != NULL)
 685                 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
 686                     mem->mem_res);
 687         mem->mem_res = NULL;
 688 }
 689
 690 /****************************************************************************
 691  * int hdac_irq_alloc(struct hdac_softc *)
 692  *
 693  * Allocate and setup the resources necessary for interrupt handling.
 694  ****************************************************************************/
 695 static int
 696 hdac_irq_alloc(struct hdac_softc *sc)
 697 {
 698         struct hdac_irq *irq;
 699         int result;
 700
 701         irq = &sc->irq;
 702         irq->irq_rid = 0x0;
 703
 704         if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
 705             (result = pci_msi_count(sc->dev)) == 1 &&
 706             pci_alloc_msi(sc->dev, &result, 1, -1) == 0)
 707                 irq->irq_rid = 0x1;
 708
 709         irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
 710             &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
 711         if (irq->irq_res == NULL) {
 712                 device_printf(sc->dev, "%s: Unable to allocate irq\n",
 713                     __func__);
 714                 goto hdac_irq_alloc_fail;
 715         }
 716         result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
 717             hdac_intr_handler, sc, &irq->irq_handle, NULL);
 718         if (result != 0) {
 719                 device_printf(sc->dev,
 720                     "%s: Unable to setup interrupt handler (%x)\n",
 721                     __func__, result);
 722                 goto hdac_irq_alloc_fail;
 723         }
 724
 725         return (0);
 726
 727 hdac_irq_alloc_fail:
 728         hdac_irq_free(sc);
 729
 730         return (ENXIO);
 731 }
 732
 733 /****************************************************************************
 734  * void hdac_irq_free(struct hdac_softc *)
 735  *
 736  * Free up resources previously allocated by hdac_irq_alloc.
 737  ****************************************************************************/
 738 static void
 739 hdac_irq_free(struct hdac_softc *sc)
 740 {
 741         struct hdac_irq *irq;
 742
 743         irq = &sc->irq;
 744         if (irq->irq_res != NULL && irq->irq_handle != NULL)
 745                 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
 746         if (irq->irq_res != NULL)
 747                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
 748                     irq->irq_res);
 749         if (irq->irq_rid == 0x1)
 750                 pci_release_msi(sc->dev);
 751         irq->irq_handle = NULL;
 752         irq->irq_res = NULL;
 753         irq->irq_rid = 0x0;
 754 }
 755
 756 /****************************************************************************
 757  * void hdac_corb_init(struct hdac_softc *)
 758  *
 759  * Initialize the corb registers for operations but do not start it up yet.
 760  * The CORB engine must not be running when this function is called.
 761  ****************************************************************************/
 762 static void
 763 hdac_corb_init(struct hdac_softc *sc)
 764 {
 765         uint8_t corbsize;
 766         uint64_t corbpaddr;
 767
 768         /* Setup the CORB size. */
 769         switch (sc->corb_size) {
 770         case 256:
 771                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
 772                 break;
 773         case 16:
 774                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
 775                 break;
 776         case 2:
 777                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
 778                 break;
 779         default:
 780                 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
 781         }
 782         HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
 783
 784         /* Setup the CORB Address in the hdac */
 785         corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
 786         HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
 787         HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
 788
 789         /* Set the WP and RP */
 790         sc->corb_wp = 0;
 791         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 792         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
 793         /*
 794          * The HDA specification indicates that the CORBRPRST bit will always
 795          * read as zero. Unfortunately, it seems that at least the 82801G
 796          * doesn't reset the bit to zero, which stalls the corb engine.
 797          * manually reset the bit to zero before continuing.
 798          */
 799         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
 800
 801         /* Enable CORB error reporting */
 802 #if 0
 803         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
 804 #endif
 805 }
 806
 807 /****************************************************************************
 808  * void hdac_rirb_init(struct hdac_softc *)
 809  *
 810  * Initialize the rirb registers for operations but do not start it up yet.
 811  * The RIRB engine must not be running when this function is called.
 812  ****************************************************************************/
 813 static void
 814 hdac_rirb_init(struct hdac_softc *sc)
 815 {
 816         uint8_t rirbsize;
 817         uint64_t rirbpaddr;
 818
 819         /* Setup the RIRB size. */
 820         switch (sc->rirb_size) {
 821         case 256:
 822                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
 823                 break;
 824         case 16:
 825                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
 826                 break;
 827         case 2:
 828                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
 829                 break;
 830         default:
 831                 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
 832         }
 833         HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
 834
 835         /* Setup the RIRB Address in the hdac */
 836         rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
 837         HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
 838         HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
 839
 840         /* Setup the WP and RP */
 841         sc->rirb_rp = 0;
 842         HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
 843
 844         /* Setup the interrupt threshold */
 845         HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
 846
 847         /* Enable Overrun and response received reporting */
 848 #if 0
 849         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
 850             HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
 851 #else
 852         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
 853 #endif
 854
 855 #if 0
 856         /*
 857          * Make sure that the Host CPU cache doesn't contain any dirty
 858          * cache lines that falls in the rirb. If I understood correctly, it
 859          * should be sufficient to do this only once as the rirb is purely
 860          * read-only from now on.
 861          */
 862         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 863             BUS_DMASYNC_PREREAD);
 864 #endif
 865 }
 866
 867 /****************************************************************************
 868  * void hdac_corb_start(hdac_softc *)
 869  *
 870  * Startup the corb DMA engine
 871  ****************************************************************************/
 872 static void
 873 hdac_corb_start(struct hdac_softc *sc)
 874 {
 875         uint32_t corbctl;
 876
 877         corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
 878         corbctl |= HDAC_CORBCTL_CORBRUN;
 879         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
 880 }
 881
 882 /****************************************************************************
 883  * void hdac_rirb_start(hdac_softc *)
 884  *
 885  * Startup the rirb DMA engine
 886  ****************************************************************************/
 887 static void
 888 hdac_rirb_start(struct hdac_softc *sc)
 889 {
 890         uint32_t rirbctl;
 891
 892         rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
 893         rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
 894         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
 895 }
 896
 897 static int
 898 hdac_rirb_flush(struct hdac_softc *sc)
 899 {
 900         struct hdac_rirb *rirb_base, *rirb;
 901         nid_t cad;
 902         uint32_t resp;
 903         uint8_t rirbwp;
 904         int ret;
 905
 906         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
 907         rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
 908 #if 0
 909         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 910             BUS_DMASYNC_POSTREAD);
 911 #endif
 912
 913         ret = 0;
 914         while (sc->rirb_rp != rirbwp) {
 915                 sc->rirb_rp++;
 916                 sc->rirb_rp %= sc->rirb_size;
 917                 rirb = &rirb_base[sc->rirb_rp];
 918                 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
 919                 resp = rirb->response;
 920                 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
 921                         sc->unsolq[sc->unsolq_wp++] = resp;
 922                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 923                         sc->unsolq[sc->unsolq_wp++] = cad;
 924                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 925                 } else if (sc->codecs[cad].pending <= 0) {
 926                         device_printf(sc->dev, "Unexpected unsolicited "
 927                             "response from address %d: %08x\n", cad, resp);
 928                 } else {
 929                         sc->codecs[cad].response = resp;
 930                         sc->codecs[cad].pending--;
 931                 }
 932                 ret++;
 933         }
 934         return (ret);
 935 }
 936
 937 static int
 938 hdac_unsolq_flush(struct hdac_softc *sc)
 939 {
 940         device_t child;
 941         nid_t cad;
 942         uint32_t resp;
 943         int ret = 0;
 944
 945         if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
 946                 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
 947                 while (sc->unsolq_rp != sc->unsolq_wp) {
 948                         resp = sc->unsolq[sc->unsolq_rp++];
 949                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 950                         cad = sc->unsolq[sc->unsolq_rp++];
 951                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 952                         if ((child = sc->codecs[cad].dev) != NULL)
 953                                 HDAC_UNSOL_INTR(child, resp);
 954                         ret++;
 955                 }
 956                 sc->unsolq_st = HDAC_UNSOLQ_READY;
 957         }
 958
 959         return (ret);
 960 }
 961
 962 /****************************************************************************
 963  * uint32_t hdac_command_sendone_internal
 964  *
 965  * Wrapper function that sends only one command to a given codec
 966  ****************************************************************************/
 967 static uint32_t
 968 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
 969 {
 970         int timeout;
 971         uint32_t *corb;
 972
 973         if (!hdac_lockowned(sc))
 974                 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
 975         verb &= ~HDA_CMD_CAD_MASK;
 976         verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
 977         sc->codecs[cad].response = HDA_INVALID;
 978
 979         sc->codecs[cad].pending++;
 980         sc->corb_wp++;
 981         sc->corb_wp %= sc->corb_size;
 982         corb = (uint32_t *)sc->corb_dma.dma_vaddr;
 983 #if 0
 984         bus_dmamap_sync(sc->corb_dma.dma_tag,
 985             sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
 986 #endif
 987         corb[sc->corb_wp] = verb;
 988 #if 0
 989         bus_dmamap_sync(sc->corb_dma.dma_tag,
 990             sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
 991 #endif
 992         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 993
 994         timeout = 10000;
 995         do {
 996                 if (hdac_rirb_flush(sc) == 0)
 997                         DELAY(10);
 998         } while (sc->codecs[cad].pending != 0 && --timeout);
 999
1000         if (sc->codecs[cad].pending != 0) {
1001                 device_printf(sc->dev, "Command timeout on address %d\n", cad);
1002                 sc->codecs[cad].pending = 0;
1003         }
1004
1005         if (sc->unsolq_rp != sc->unsolq_wp)
1006                 taskqueue_enqueue(taskqueue_thread[mycpuid], &sc->unsolq_task);
1007         return (sc->codecs[cad].response);
1008 }
1009
1010 /****************************************************************************
1011  * Device Methods
1012  ****************************************************************************/
1013
1014 /****************************************************************************
1015  * int hdac_probe(device_t)
1016  *
1017  * Probe for the presence of an hdac. If none is found, check for a generic
1018  * match using the subclass of the device.
1019  ****************************************************************************/
1020 static int
1021 hdac_probe(device_t dev)
1022 {
1023         int i, result;
1024         uint32_t model;
1025         uint16_t class, subclass;
1026         char desc[64];
1027
1028         model = (uint32_t)pci_get_device(dev) << 16;
1029         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1030         class = pci_get_class(dev);
1031         subclass = pci_get_subclass(dev);
1032
1033         bzero(desc, sizeof(desc));
1034         result = ENXIO;
1035         for (i = 0; i < nitems(hdac_devices); i++) {
1036                 if (hdac_devices[i].model == model) {
1037                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1038                         result = BUS_PROBE_DEFAULT;
1039                         break;
1040                 }
1041                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1042                     class == PCIC_MULTIMEDIA &&
1043                     subclass == PCIS_MULTIMEDIA_HDA) {
1044                         ksnprintf(desc, sizeof(desc),
1045                             "%s (0x%04x)",
1046                             hdac_devices[i].desc, pci_get_device(dev));
1047                         result = BUS_PROBE_GENERIC;
1048                         break;
1049                 }
1050         }
1051         if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1052             subclass == PCIS_MULTIMEDIA_HDA) {
1053                 ksnprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1054                 result = BUS_PROBE_GENERIC;
1055         }
1056         if (result != ENXIO) {
1057                 strlcat(desc, " HDA Controller", sizeof(desc));
1058                 device_set_desc_copy(dev, desc);
1059         }
1060
1061         return (result);
1062 }
1063
1064 static void
1065 hdac_unsolq_task(void *context, int pending)
1066 {
1067         struct hdac_softc *sc;
1068
1069         sc = (struct hdac_softc *)context;
1070
1071         hdac_lock(sc);
1072         hdac_unsolq_flush(sc);
1073         hdac_unlock(sc);
1074 }
1075
1076 /****************************************************************************
1077  * int hdac_attach(device_t)
1078  *
1079  * Attach the device into the kernel. Interrupts usually won't be enabled
1080  * when this function is called. Setup everything that doesn't require
1081  * interrupts and defer probing of codecs until interrupts are enabled.
1082  ****************************************************************************/
1083 static int
1084 hdac_attach(device_t dev)
1085 {
1086         struct hdac_softc *sc;
1087         int result;
1088         int i, devid = -1;
1089         uint32_t model;
1090         uint16_t class, subclass;
1091         uint16_t vendor;
1092         uint8_t v;
1093
1094         sc = device_get_softc(dev);
1095         HDA_BOOTVERBOSE(
1096                 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1097                     pci_get_subvendor(dev), pci_get_subdevice(dev));
1098                 device_printf(dev, "HDA Driver Revision: %s\n",
1099                     HDA_DRV_TEST_REV);
1100         );
1101
1102         model = (uint32_t)pci_get_device(dev) << 16;
1103         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1104         class = pci_get_class(dev);
1105         subclass = pci_get_subclass(dev);
1106
1107         for (i = 0; i < nitems(hdac_devices); i++) {
1108                 if (hdac_devices[i].model == model) {
1109                         devid = i;
1110                         break;
1111                 }
1112                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1113                     class == PCIC_MULTIMEDIA &&
1114                     subclass == PCIS_MULTIMEDIA_HDA) {
1115                         devid = i;
1116                         break;
1117                 }
1118         }
1119
1120         sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1121         sc->dev = dev;
1122         TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1123         callout_init_mp(&sc->poll_callout);
1124         for (i = 0; i < HDAC_CODEC_MAX; i++)
1125                 sc->codecs[i].dev = NULL;
1126         if (devid >= 0) {
1127                 sc->quirks_on = hdac_devices[devid].quirks_on;
1128                 sc->quirks_off = hdac_devices[devid].quirks_off;
1129         } else {
1130                 sc->quirks_on = 0;
1131                 sc->quirks_off = 0;
1132         }
1133         hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1134         if (resource_int_value(device_get_name(dev),
1135                                device_get_unit(dev), "msi", &i) == 0) {
1136                 if (i == 0) {
1137                         sc->quirks_on &= ~HDAC_QUIRK_MSI;
1138                         sc->quirks_off |= HDAC_QUIRK_MSI;
1139                 } else {
1140                         sc->quirks_on |= HDAC_QUIRK_MSI;
1141                         sc->quirks_off &= ~HDAC_QUIRK_MSI;
1142                 }
1143         }
1144         HDA_BOOTVERBOSE(
1145                 device_printf(sc->dev,
1146                     "Config options: on=0x%08x off=0x%08x\n",
1147                     sc->quirks_on, sc->quirks_off);
1148         );
1149         sc->poll_ival = hz;
1150         if (resource_int_value(device_get_name(dev),
1151             device_get_unit(dev), "polling", &i) == 0 && i != 0)
1152                 sc->polling = 1;
1153         else
1154                 sc->polling = 0;
1155
1156         pci_enable_busmaster(dev);
1157
1158         vendor = pci_get_vendor(dev);
1159         if (vendor == INTEL_VENDORID) {
1160                 /* TCSEL -> TC0 */
1161                 v = pci_read_config(dev, 0x44, 1);
1162                 pci_write_config(dev, 0x44, v & 0xf8, 1);
1163                 HDA_BOOTHVERBOSE(
1164                         device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1165                             pci_read_config(dev, 0x44, 1));
1166                 );
1167         }
1168
1169         sc->flags |= HDAC_F_DMA_NOCACHE;
1170         /*
1171          * Try to enable PCIe snoop to avoid messing around with
1172          * uncacheable DMA attribute.
1173          */
1174         if (pci_is_pcie(dev)) {
1175                 int pcie_cap = pci_get_pciecap_ptr(dev);
1176                 uint16_t dev_ctl;
1177
1178                 dev_ctl = pci_read_config(dev,
1179                     pcie_cap + PCIER_DEVCTRL, 2);
1180                 device_printf(dev, "link ctrl %#x\n", dev_ctl);
1181
1182                 if (dev_ctl & PCIEM_DEVCTL_NOSNOOP) {
1183                         dev_ctl &= ~PCIEM_DEVCTL_NOSNOOP;
1184                         pci_write_config(dev,
1185                             pcie_cap + PCIER_DEVCTRL, dev_ctl, 2);
1186
1187                         device_printf(dev, "disable nosnoop\n");
1188                 }
1189                 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1190         }
1191
1192         HDA_BOOTHVERBOSE(
1193                 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1194                     (sc->flags & HDAC_F_DMA_NOCACHE) ?
1195                     "Uncacheable" : "PCIe snoop", vendor);
1196         );
1197
1198         /* Allocate resources */
1199         result = hdac_mem_alloc(sc);
1200         if (result != 0)
1201                 goto hdac_attach_fail;
1202         result = hdac_irq_alloc(sc);
1203         if (result != 0)
1204                 goto hdac_attach_fail;
1205
1206         /* Get Capabilities */
1207         result = hdac_get_capabilities(sc);
1208         if (result != 0)
1209                 goto hdac_attach_fail;
1210
1211         /* Allocate CORB, RIRB, POS and BDLs dma memory */
1212         result = hdac_dma_alloc(sc, &sc->corb_dma,
1213             sc->corb_size * sizeof(uint32_t));
1214         if (result != 0)
1215                 goto hdac_attach_fail;
1216         result = hdac_dma_alloc(sc, &sc->rirb_dma,
1217             sc->rirb_size * sizeof(struct hdac_rirb));
1218         if (result != 0)
1219                 goto hdac_attach_fail;
1220         sc->streams = kmalloc(sizeof(struct hdac_stream) * sc->num_ss,
1221             M_HDAC, M_ZERO | M_WAITOK);
1222         for (i = 0; i < sc->num_ss; i++) {
1223                 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1224                     sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1225                 if (result != 0)
1226                         goto hdac_attach_fail;
1227         }
1228         if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1229                 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1230                         HDA_BOOTVERBOSE(
1231                                 device_printf(dev, "Failed to "
1232                                     "allocate DMA pos buffer "
1233                                     "(non-fatal)\n");
1234                         );
1235                 } else {
1236                         uint64_t addr = sc->pos_dma.dma_paddr;
1237
1238                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1239                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1240                             (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1241                             HDAC_DPLBASE_DPLBASE_DMAPBE);
1242                 }
1243         }
1244
1245         result = bus_dma_tag_create(
1246             bus_get_dma_tag(sc->dev),           /* parent */
1247             HDA_DMA_ALIGNMENT,                  /* alignment */
1248             0,                                  /* boundary */
1249             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1250                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
1251             BUS_SPACE_MAXADDR,                  /* highaddr */
1252             NULL,                               /* filtfunc */
1253             NULL,                               /* fistfuncarg */
1254             HDA_BUFSZ_MAX,                      /* maxsize */
1255             1,                                  /* nsegments */
1256             HDA_BUFSZ_MAX,                      /* maxsegsz */
1257             0,                                  /* flags */
1258             &sc->chan_dmat);                    /* dmat */
1259         if (result != 0) {
1260                 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
1261                      __func__, result);
1262                 goto hdac_attach_fail;
1263         }
1264
1265         /* Quiesce everything */
1266         HDA_BOOTHVERBOSE(
1267                 device_printf(dev, "Reset controller...\n");
1268         );
1269         hdac_reset(sc, 1);
1270
1271         /* Initialize the CORB and RIRB */
1272         hdac_corb_init(sc);
1273         hdac_rirb_init(sc);
1274
1275         /* Defer remaining of initialization until interrupts are enabled */
1276         sc->intrhook.ich_func = hdac_attach2;
1277         sc->intrhook.ich_arg = (void *)sc;
1278         sc->intrhook.ich_desc = "snd_hda";
1279         if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1280                 sc->intrhook.ich_func = NULL;
1281                 hdac_attach2((void *)sc);
1282         }
1283
1284         return (0);
1285
1286 hdac_attach_fail:
1287         hdac_irq_free(sc);
1288         for (i = 0; i < sc->num_ss; i++)
1289                 hdac_dma_free(sc, &sc->streams[i].bdl);
1290         if (sc->streams != NULL)
1291                 kfree(sc->streams, M_HDAC);
1292         hdac_dma_free(sc, &sc->rirb_dma);
1293         hdac_dma_free(sc, &sc->corb_dma);
1294         hdac_mem_free(sc);
1295         snd_mtxfree(sc->lock);
1296
1297         return (ENXIO);
1298 }
1299
1300 static int
1301 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1302 {
1303         struct hdac_softc *sc;
1304         device_t *devlist;
1305         device_t dev;
1306         int devcount, i, err, val;
1307
1308         dev = oidp->oid_arg1;
1309         sc = device_get_softc(dev);
1310         if (sc == NULL)
1311                 return (EINVAL);
1312         val = 0;
1313         err = sysctl_handle_int(oidp, &val, 0, req);
1314         if (err != 0 || req->newptr == NULL || val == 0)
1315                 return (err);
1316
1317         /* XXX: Temporary. For debugging. */
1318         if (val == 100) {
1319                 hdac_suspend(dev);
1320                 return (0);
1321         } else if (val == 101) {
1322                 hdac_resume(dev);
1323                 return (0);
1324         }
1325
1326         if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1327                 return (err);
1328         hdac_lock(sc);
1329         for (i = 0; i < devcount; i++)
1330                 HDAC_PINDUMP(devlist[i]);
1331         hdac_unlock(sc);
1332         kfree(devlist, M_TEMP);
1333         return (0);
1334 }
1335
1336 static int
1337 hdac_mdata_rate(uint16_t fmt)
1338 {
1339         static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1340         int rate, bits;
1341
1342         if (fmt & (1 << 14))
1343                 rate = 44100;
1344         else
1345                 rate = 48000;
1346         rate *= ((fmt >> 11) & 0x07) + 1;
1347         rate /= ((fmt >> 8) & 0x07) + 1;
1348         bits = mbits[(fmt >> 4) & 0x03];
1349         bits *= (fmt & 0x0f) + 1;
1350         return (rate * bits);
1351 }
1352
1353 static int
1354 hdac_bdata_rate(uint16_t fmt, int output)
1355 {
1356         static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1357         int rate, bits;
1358
1359         rate = 48000;
1360         rate *= ((fmt >> 11) & 0x07) + 1;
1361         bits = bbits[(fmt >> 4) & 0x03];
1362         bits *= (fmt & 0x0f) + 1;
1363         if (!output)
1364                 bits = ((bits + 7) & ~0x07) + 10;
1365         return (rate * bits);
1366 }
1367
1368 static void
1369 hdac_poll_reinit(struct hdac_softc *sc)
1370 {
1371         int i, pollticks, min = 1000000;
1372         struct hdac_stream *s;
1373
1374         if (sc->polling == 0)
1375                 return;
1376         if (sc->unsol_registered > 0)
1377                 min = hz / 2;
1378         for (i = 0; i < sc->num_ss; i++) {
1379                 s = &sc->streams[i];
1380                 if (s->running == 0)
1381                         continue;
1382                 pollticks = ((uint64_t)hz * s->blksz) /
1383                     (hdac_mdata_rate(s->format) / 8);
1384                 pollticks >>= 1;
1385                 if (pollticks > hz)
1386                         pollticks = hz;
1387                 if (pollticks < 1) {
1388                         HDA_BOOTVERBOSE(
1389                                 device_printf(sc->dev,
1390                                     "poll interval < 1 tick !\n");
1391                         );
1392                         pollticks = 1;
1393                 }
1394                 if (min > pollticks)
1395                         min = pollticks;
1396         }
1397         HDA_BOOTVERBOSE(
1398                 device_printf(sc->dev,
1399                     "poll interval %d -> %d ticks\n",
1400                     sc->poll_ival, min);
1401         );
1402         sc->poll_ival = min;
1403         if (min == 1000000)
1404                 callout_stop(&sc->poll_callout);
1405         else
1406                 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1407 }
1408
1409 static int
1410 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1411 {
1412         struct hdac_softc *sc;
1413         device_t dev;
1414         uint32_t ctl;
1415         int err, val;
1416
1417         dev = oidp->oid_arg1;
1418         sc = device_get_softc(dev);
1419         if (sc == NULL)
1420                 return (EINVAL);
1421         hdac_lock(sc);
1422         val = sc->polling;
1423         hdac_unlock(sc);
1424         err = sysctl_handle_int(oidp, &val, 0, req);
1425
1426         if (err != 0 || req->newptr == NULL)
1427                 return (err);
1428         if (val < 0 || val > 1)
1429                 return (EINVAL);
1430
1431         hdac_lock(sc);
1432         if (val != sc->polling) {
1433                 if (val == 0) {
1434                         callout_stop(&sc->poll_callout);
1435                         hdac_unlock(sc);
1436                         callout_drain(&sc->poll_callout);
1437                         hdac_lock(sc);
1438                         sc->polling = 0;
1439                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1440                         ctl |= HDAC_INTCTL_GIE;
1441                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1442                 } else {
1443                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1444                         ctl &= ~HDAC_INTCTL_GIE;
1445                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1446                         sc->polling = 1;
1447                         hdac_poll_reinit(sc);
1448                 }
1449         }
1450         hdac_unlock(sc);
1451
1452         return (err);
1453 }
1454
1455 static void
1456 hdac_attach2(void *arg)
1457 {
1458         struct hdac_softc *sc;
1459         device_t child;
1460         uint32_t vendorid, revisionid;
1461         int i;
1462         uint16_t statests;
1463
1464         sc = (struct hdac_softc *)arg;
1465
1466         hdac_lock(sc);
1467
1468         /* Remove ourselves from the config hooks */
1469         if (sc->intrhook.ich_func != NULL) {
1470                 config_intrhook_disestablish(&sc->intrhook);
1471                 sc->intrhook.ich_func = NULL;
1472         }
1473
1474         HDA_BOOTHVERBOSE(
1475                 device_printf(sc->dev, "Starting CORB Engine...\n");
1476         );
1477         hdac_corb_start(sc);
1478         HDA_BOOTHVERBOSE(
1479                 device_printf(sc->dev, "Starting RIRB Engine...\n");
1480         );
1481         hdac_rirb_start(sc);
1482         HDA_BOOTHVERBOSE(
1483                 device_printf(sc->dev,
1484                     "Enabling controller interrupt...\n");
1485         );
1486         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1487             HDAC_GCTL_UNSOL);
1488         if (sc->polling == 0) {
1489                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1490                     HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1491         }
1492         DELAY(1000);
1493
1494         HDA_BOOTHVERBOSE(
1495                 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1496         );
1497         statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1498         hdac_unlock(sc);
1499         for (i = 0; i < HDAC_CODEC_MAX; i++) {
1500                 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1501                         HDA_BOOTHVERBOSE(
1502                                 device_printf(sc->dev,
1503                                     "Found CODEC at address %d\n", i);
1504                         );
1505                         hdac_lock(sc);
1506                         vendorid = hdac_send_command(sc, i,
1507                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1508                         revisionid = hdac_send_command(sc, i,
1509                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1510                         hdac_unlock(sc);
1511                         if (vendorid == HDA_INVALID &&
1512                             revisionid == HDA_INVALID) {
1513                                 device_printf(sc->dev,
1514                                     "CODEC is not responding!\n");
1515                                 continue;
1516                         }
1517                         sc->codecs[i].vendor_id =
1518                             HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1519                         sc->codecs[i].device_id =
1520                             HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1521                         sc->codecs[i].revision_id =
1522                             HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1523                         sc->codecs[i].stepping_id =
1524                             HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1525                         child = device_add_child(sc->dev, "hdacc", -1);
1526                         if (child == NULL) {
1527                                 device_printf(sc->dev,
1528                                     "Failed to add CODEC device\n");
1529                                 continue;
1530                         }
1531                         device_set_ivars(child, (void *)(intptr_t)i);
1532                         sc->codecs[i].dev = child;
1533                 }
1534         }
1535         bus_generic_attach(sc->dev);
1536
1537         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1538             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1539             "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1540             sysctl_hdac_pindump, "I", "Dump pin states/data");
1541         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1542             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1543             "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1544             sysctl_hdac_polling, "I", "Enable polling mode");
1545 }
1546
1547 /****************************************************************************
1548  * int hdac_suspend(device_t)
1549  *
1550  * Suspend and power down HDA bus and codecs.
1551  ****************************************************************************/
1552 static int
1553 hdac_suspend(device_t dev)
1554 {
1555         struct hdac_softc *sc = device_get_softc(dev);
1556
1557         HDA_BOOTHVERBOSE(
1558                 device_printf(dev, "Suspend...\n");
1559         );
1560         bus_generic_suspend(dev);
1561
1562         hdac_lock(sc);
1563         HDA_BOOTHVERBOSE(
1564                 device_printf(dev, "Reset controller...\n");
1565         );
1566         callout_stop(&sc->poll_callout);
1567         hdac_reset(sc, 0);
1568         hdac_unlock(sc);
1569         callout_drain(&sc->poll_callout);
1570         taskqueue_drain(taskqueue_thread[mycpuid], &sc->unsolq_task);
1571         HDA_BOOTHVERBOSE(
1572                 device_printf(dev, "Suspend done\n");
1573         );
1574         return (0);
1575 }
1576
1577 /****************************************************************************
1578  * int hdac_resume(device_t)
1579  *
1580  * Powerup and restore HDA bus and codecs state.
1581  ****************************************************************************/
1582 static int
1583 hdac_resume(device_t dev)
1584 {
1585         struct hdac_softc *sc = device_get_softc(dev);
1586         int error;
1587
1588         HDA_BOOTHVERBOSE(
1589                 device_printf(dev, "Resume...\n");
1590         );
1591         hdac_lock(sc);
1592
1593         /* Quiesce everything */
1594         HDA_BOOTHVERBOSE(
1595                 device_printf(dev, "Reset controller...\n");
1596         );
1597         hdac_reset(sc, 1);
1598
1599         /* Initialize the CORB and RIRB */
1600         hdac_corb_init(sc);
1601         hdac_rirb_init(sc);
1602
1603         HDA_BOOTHVERBOSE(
1604                 device_printf(dev, "Starting CORB Engine...\n");
1605         );
1606         hdac_corb_start(sc);
1607         HDA_BOOTHVERBOSE(
1608                 device_printf(dev, "Starting RIRB Engine...\n");
1609         );
1610         hdac_rirb_start(sc);
1611         HDA_BOOTHVERBOSE(
1612                 device_printf(dev, "Enabling controller interrupt...\n");
1613         );
1614         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1615             HDAC_GCTL_UNSOL);
1616         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1617         DELAY(1000);
1618         hdac_poll_reinit(sc);
1619         hdac_unlock(sc);
1620
1621         error = bus_generic_resume(dev);
1622         HDA_BOOTHVERBOSE(
1623                 device_printf(dev, "Resume done\n");
1624         );
1625         return (error);
1626 }
1627
1628 /****************************************************************************
1629  * int hdac_detach(device_t)
1630  *
1631  * Detach and free up resources utilized by the hdac device.
1632  ****************************************************************************/
1633 static int
1634 hdac_detach(device_t dev)
1635 {
1636         struct hdac_softc *sc = device_get_softc(dev);
1637         device_t *devlist;
1638         int cad, i, devcount, error;
1639
1640         if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1641                 return (error);
1642         for (i = 0; i < devcount; i++) {
1643                 cad = (intptr_t)device_get_ivars(devlist[i]);
1644                 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1645                         kfree(devlist, M_TEMP);
1646                         return (error);
1647                 }
1648                 sc->codecs[cad].dev = NULL;
1649         }
1650         kfree(devlist, M_TEMP);
1651
1652         hdac_lock(sc);
1653         hdac_reset(sc, 0);
1654         hdac_unlock(sc);
1655         taskqueue_drain(taskqueue_thread[mycpuid], &sc->unsolq_task);
1656         hdac_irq_free(sc);
1657
1658         /* give pending interrupts stuck on the lock a chance to clear */
1659         /* bad hack */
1660         tsleep(&sc->irq, 0, "hdaslp", hz / 10);
1661
1662         for (i = 0; i < sc->num_ss; i++)
1663                 hdac_dma_free(sc, &sc->streams[i].bdl);
1664         kfree(sc->streams, M_HDAC);
1665         hdac_dma_free(sc, &sc->pos_dma);
1666         hdac_dma_free(sc, &sc->rirb_dma);
1667         hdac_dma_free(sc, &sc->corb_dma);
1668         if (sc->chan_dmat != NULL) {
1669                 bus_dma_tag_destroy(sc->chan_dmat);
1670                 sc->chan_dmat = NULL;
1671         }
1672         hdac_mem_free(sc);
1673         snd_mtxfree(sc->lock);
1674         return (0);
1675 }
1676
1677 static bus_dma_tag_t
1678 hdac_get_dma_tag(device_t dev, device_t child)
1679 {
1680         struct hdac_softc *sc = device_get_softc(dev);
1681
1682         return (sc->chan_dmat);
1683 }
1684
1685 static int
1686 hdac_print_child(device_t dev, device_t child)
1687 {
1688         int retval;
1689
1690         retval = bus_print_child_header(dev, child);
1691         retval += kprintf(" at cad %d",
1692             (int)(intptr_t)device_get_ivars(child));
1693         retval += bus_print_child_footer(dev, child);
1694
1695         return (retval);
1696 }
1697
1698 static int
1699 hdac_child_location_str(device_t dev, device_t child, char *buf,
1700     size_t buflen)
1701 {
1702
1703         ksnprintf(buf, buflen, "cad=%d",
1704             (int)(intptr_t)device_get_ivars(child));
1705         return (0);
1706 }
1707
1708 static int
1709 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1710     size_t buflen)
1711 {
1712         struct hdac_softc *sc = device_get_softc(dev);
1713         nid_t cad = (uintptr_t)device_get_ivars(child);
1714
1715         ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1716             "stepping=0x%02x",
1717             sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1718             sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1719         return (0);
1720 }
1721
1722 static int
1723 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1724 {
1725         struct hdac_softc *sc = device_get_softc(dev);
1726         nid_t cad = (uintptr_t)device_get_ivars(child);
1727
1728         switch (which) {
1729         case HDA_IVAR_CODEC_ID:
1730                 *result = cad;
1731                 break;
1732         case HDA_IVAR_VENDOR_ID:
1733                 *result = sc->codecs[cad].vendor_id;
1734                 break;
1735         case HDA_IVAR_DEVICE_ID:
1736                 *result = sc->codecs[cad].device_id;
1737                 break;
1738         case HDA_IVAR_REVISION_ID:
1739                 *result = sc->codecs[cad].revision_id;
1740                 break;
1741         case HDA_IVAR_STEPPING_ID:
1742                 *result = sc->codecs[cad].stepping_id;
1743                 break;
1744         case HDA_IVAR_SUBVENDOR_ID:
1745                 *result = pci_get_subvendor(dev);
1746                 break;
1747         case HDA_IVAR_SUBDEVICE_ID:
1748                 *result = pci_get_subdevice(dev);
1749                 break;
1750         case HDA_IVAR_DMA_NOCACHE:
1751                 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1752                 break;
1753         default:
1754                 return (ENOENT);
1755         }
1756         return (0);
1757 }
1758
1759 static struct lock *
1760 hdac_get_mtx(device_t dev, device_t child)
1761 {
1762         struct hdac_softc *sc = device_get_softc(dev);
1763
1764         return (sc->lock);
1765 }
1766
1767 static uint32_t
1768 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1769 {
1770
1771         return (hdac_send_command(device_get_softc(dev),
1772             (intptr_t)device_get_ivars(child), verb));
1773 }
1774
1775 static int
1776 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1777 {
1778         int i, ss;
1779
1780         ss = -1;
1781         /* Allocate ISS/BSS first. */
1782         if (dir == 0) {
1783                 for (i = 0; i < sc->num_iss; i++) {
1784                         if (sc->streams[i].stream == stream) {
1785                                 ss = i;
1786                                 break;
1787                         }
1788                 }
1789         } else {
1790                 for (i = 0; i < sc->num_oss; i++) {
1791                         if (sc->streams[i + sc->num_iss].stream == stream) {
1792                                 ss = i + sc->num_iss;
1793                                 break;
1794                         }
1795                 }
1796         }
1797         /* Fallback to BSS. */
1798         if (ss == -1) {
1799                 for (i = 0; i < sc->num_bss; i++) {
1800                         if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1801                             == stream) {
1802                                 ss = i + sc->num_iss + sc->num_oss;
1803                                 break;
1804                         }
1805                 }
1806         }
1807         return (ss);
1808 }
1809
1810 static int
1811 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1812     uint32_t **dmapos)
1813 {
1814         struct hdac_softc *sc = device_get_softc(dev);
1815         nid_t cad = (uintptr_t)device_get_ivars(child);
1816         int stream, ss, bw, maxbw, prevbw;
1817
1818         /* Look for empty stream. */
1819         ss = hdac_find_stream(sc, dir, 0);
1820
1821         /* Return if found nothing. */
1822         if (ss < 0)
1823                 return (0);
1824
1825         /* Check bus bandwidth. */
1826         bw = hdac_bdata_rate(format, dir);
1827         if (dir == 1) {
1828                 bw *= 1 << (sc->num_sdo - stripe);
1829                 prevbw = sc->sdo_bw_used;
1830                 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1831         } else {
1832                 prevbw = sc->codecs[cad].sdi_bw_used;
1833                 maxbw = 48000 * 464;
1834         }
1835         HDA_BOOTHVERBOSE(
1836                 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1837                     (bw + prevbw) / 1000, maxbw / 1000,
1838                     bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1839         );
1840         if (bw + prevbw > maxbw)
1841                 return (0);
1842         if (dir == 1)
1843                 sc->sdo_bw_used += bw;
1844         else
1845                 sc->codecs[cad].sdi_bw_used += bw;
1846
1847         /* Allocate stream number */
1848         if (ss >= sc->num_iss + sc->num_oss)
1849                 stream = 15 - (ss - sc->num_iss + sc->num_oss);
1850         else if (ss >= sc->num_iss)
1851                 stream = ss - sc->num_iss + 1;
1852         else
1853                 stream = ss + 1;
1854
1855         sc->streams[ss].dev = child;
1856         sc->streams[ss].dir = dir;
1857         sc->streams[ss].stream = stream;
1858         sc->streams[ss].bw = bw;
1859         sc->streams[ss].format = format;
1860         sc->streams[ss].stripe = stripe;
1861         if (dmapos != NULL) {
1862                 if (sc->pos_dma.dma_vaddr != NULL)
1863                         *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1864                 else
1865                         *dmapos = NULL;
1866         }
1867         return (stream);
1868 }
1869
1870 static void
1871 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1872 {
1873         struct hdac_softc *sc = device_get_softc(dev);
1874         nid_t cad = (uintptr_t)device_get_ivars(child);
1875         int ss;
1876
1877         ss = hdac_find_stream(sc, dir, stream);
1878         KASSERT(ss >= 0,
1879             ("Free for not allocated stream (%d/%d)\n", dir, stream));
1880         if (dir == 1)
1881                 sc->sdo_bw_used -= sc->streams[ss].bw;
1882         else
1883                 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1884         sc->streams[ss].stream = 0;
1885         sc->streams[ss].dev = NULL;
1886 }
1887
1888 static int
1889 hdac_stream_start(device_t dev, device_t child,
1890     int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1891 {
1892         struct hdac_softc *sc = device_get_softc(dev);
1893         struct hdac_bdle *bdle;
1894         uint64_t addr;
1895         int i, ss, off;
1896         uint32_t ctl;
1897
1898         ss = hdac_find_stream(sc, dir, stream);
1899         KASSERT(ss >= 0,
1900             ("Start for not allocated stream (%d/%d)\n", dir, stream));
1901
1902         addr = (uint64_t)buf;
1903         bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1904         for (i = 0; i < blkcnt; i++, bdle++) {
1905                 bdle->addrl = (uint32_t)addr;
1906                 bdle->addrh = (uint32_t)(addr >> 32);
1907                 bdle->len = blksz;
1908                 bdle->ioc = 1;
1909                 addr += blksz;
1910         }
1911
1912         off = ss << 5;
1913         HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1914         HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1915         addr = sc->streams[ss].bdl.dma_paddr;
1916         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1917         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1918
1919         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1920         if (dir)
1921                 ctl |= HDAC_SDCTL2_DIR;
1922         else
1923                 ctl &= ~HDAC_SDCTL2_DIR;
1924         ctl &= ~HDAC_SDCTL2_STRM_MASK;
1925         ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1926         ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1927         ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1928         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1929
1930         HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1931
1932         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1933         ctl |= 1 << ss;
1934         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1935
1936         HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1937             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1938         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1939         ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1940             HDAC_SDCTL_RUN;
1941         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1942
1943         sc->streams[ss].blksz = blksz;
1944         sc->streams[ss].running = 1;
1945         hdac_poll_reinit(sc);
1946         return (0);
1947 }
1948
1949 static void
1950 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1951 {
1952         struct hdac_softc *sc = device_get_softc(dev);
1953         int ss, off;
1954         uint32_t ctl;
1955
1956         ss = hdac_find_stream(sc, dir, stream);
1957         KASSERT(ss >= 0,
1958             ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1959
1960         off = ss << 5;
1961         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1962         ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1963             HDAC_SDCTL_RUN);
1964         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1965
1966         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1967         ctl &= ~(1 << ss);
1968         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1969
1970         sc->streams[ss].running = 0;
1971         hdac_poll_reinit(sc);
1972 }
1973
1974 static void
1975 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
1976 {
1977         struct hdac_softc *sc = device_get_softc(dev);
1978         int timeout = 1000;
1979         int to = timeout;
1980         int ss, off;
1981         uint32_t ctl;
1982
1983         ss = hdac_find_stream(sc, dir, stream);
1984         KASSERT(ss >= 0,
1985             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
1986
1987         off = ss << 5;
1988         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1989         ctl |= HDAC_SDCTL_SRST;
1990         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1991         do {
1992                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1993                 if (ctl & HDAC_SDCTL_SRST)
1994                         break;
1995                 DELAY(10);
1996         } while (--to);
1997         if (!(ctl & HDAC_SDCTL_SRST))
1998                 device_printf(dev, "Reset setting timeout\n");
1999         ctl &= ~HDAC_SDCTL_SRST;
2000         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2001         to = timeout;
2002         do {
2003                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2004                 if (!(ctl & HDAC_SDCTL_SRST))
2005                         break;
2006                 DELAY(10);
2007         } while (--to);
2008         if (ctl & HDAC_SDCTL_SRST)
2009                 device_printf(dev, "Reset timeout!\n");
2010 }
2011
2012 static uint32_t
2013 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2014 {
2015         struct hdac_softc *sc = device_get_softc(dev);
2016         int ss, off;
2017
2018         ss = hdac_find_stream(sc, dir, stream);
2019         KASSERT(ss >= 0,
2020             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2021
2022         off = ss << 5;
2023         return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2024 }
2025
2026 static int
2027 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2028 {
2029         struct hdac_softc *sc = device_get_softc(dev);
2030
2031         sc->unsol_registered++;
2032         hdac_poll_reinit(sc);
2033         return (tag);
2034 }
2035
2036 static void
2037 hdac_unsol_free(device_t dev, device_t child, int tag)
2038 {
2039         struct hdac_softc *sc = device_get_softc(dev);
2040
2041         sc->unsol_registered--;
2042         hdac_poll_reinit(sc);
2043 }
2044
2045 static device_method_t hdac_methods[] = {
2046         /* device interface */
2047         DEVMETHOD(device_probe,         hdac_probe),
2048         DEVMETHOD(device_attach,        hdac_attach),
2049         DEVMETHOD(device_detach,        hdac_detach),
2050         DEVMETHOD(device_suspend,       hdac_suspend),
2051         DEVMETHOD(device_resume,        hdac_resume),
2052         /* Bus interface */
2053         DEVMETHOD(bus_get_dma_tag,      hdac_get_dma_tag),
2054         DEVMETHOD(bus_print_child,      hdac_print_child),
2055         DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2056         DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2057         DEVMETHOD(bus_read_ivar,        hdac_read_ivar),
2058         DEVMETHOD(hdac_get_mtx,         hdac_get_mtx),
2059         DEVMETHOD(hdac_codec_command,   hdac_codec_command),
2060         DEVMETHOD(hdac_stream_alloc,    hdac_stream_alloc),
2061         DEVMETHOD(hdac_stream_free,     hdac_stream_free),
2062         DEVMETHOD(hdac_stream_start,    hdac_stream_start),
2063         DEVMETHOD(hdac_stream_stop,     hdac_stream_stop),
2064         DEVMETHOD(hdac_stream_reset,    hdac_stream_reset),
2065         DEVMETHOD(hdac_stream_getptr,   hdac_stream_getptr),
2066         DEVMETHOD(hdac_unsol_alloc,     hdac_unsol_alloc),
2067         DEVMETHOD(hdac_unsol_free,      hdac_unsol_free),
2068         DEVMETHOD_END
2069 };
2070
2071 static driver_t hdac_driver = {
2072         "hdac",
2073         hdac_methods,
2074         sizeof(struct hdac_softc),
2075 };
2076
2077 static devclass_t hdac_devclass;
2078
2079 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL);