1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_fb_helper.h>
32 #include <drm/drm_legacy.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
36 #include "i915_vgpu.h"
39 static int i915_getparam(struct drm_device *dev, void *data,
40 struct drm_file *file_priv)
42 struct drm_i915_private *dev_priv = dev->dev_private;
43 drm_i915_getparam_t *param = data;
46 switch (param->param) {
47 case I915_PARAM_IRQ_ACTIVE:
48 case I915_PARAM_ALLOW_BATCHBUFFER:
49 case I915_PARAM_LAST_DISPATCH:
50 /* Reject all old ums/dri params. */
52 case I915_PARAM_CHIPSET_ID:
53 value = dev->pdev->device;
55 case I915_PARAM_REVISION:
56 value = dev->pdev->revision;
58 case I915_PARAM_HAS_GEM:
61 case I915_PARAM_NUM_FENCES_AVAIL:
62 value = dev_priv->num_fence_regs;
64 case I915_PARAM_HAS_OVERLAY:
65 value = dev_priv->overlay ? 1 : 0;
67 case I915_PARAM_HAS_PAGEFLIPPING:
70 case I915_PARAM_HAS_EXECBUF2:
74 case I915_PARAM_HAS_BSD:
75 value = intel_ring_initialized(&dev_priv->ring[VCS]);
77 case I915_PARAM_HAS_BLT:
78 value = intel_ring_initialized(&dev_priv->ring[BCS]);
80 case I915_PARAM_HAS_VEBOX:
81 value = intel_ring_initialized(&dev_priv->ring[VECS]);
83 case I915_PARAM_HAS_BSD2:
84 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
86 case I915_PARAM_HAS_RELAXED_FENCING:
89 case I915_PARAM_HAS_COHERENT_RINGS:
92 case I915_PARAM_HAS_EXEC_CONSTANTS:
93 value = INTEL_INFO(dev)->gen >= 4;
95 case I915_PARAM_HAS_RELAXED_DELTA:
98 case I915_PARAM_HAS_GEN7_SOL_RESET:
101 case I915_PARAM_HAS_LLC:
102 value = HAS_LLC(dev);
104 case I915_PARAM_HAS_WT:
107 case I915_PARAM_HAS_ALIASING_PPGTT:
108 value = USES_PPGTT(dev);
110 case I915_PARAM_HAS_WAIT_TIMEOUT:
113 case I915_PARAM_HAS_SEMAPHORES:
114 value = i915_semaphore_is_enabled(dev);
116 case I915_PARAM_HAS_PINNED_BATCHES:
119 case I915_PARAM_HAS_EXEC_NO_RELOC:
122 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
125 case I915_PARAM_CMD_PARSER_VERSION:
126 value = i915_cmd_parser_get_version();
128 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
131 case I915_PARAM_SUBSLICE_TOTAL:
132 value = INTEL_INFO(dev)->subslice_total;
136 case I915_PARAM_EU_TOTAL:
137 value = INTEL_INFO(dev)->eu_total;
141 case I915_PARAM_HAS_GPU_RESET:
142 value = i915.enable_hangcheck &&
143 intel_has_gpu_reset(dev);
145 case I915_PARAM_HAS_RESOURCE_STREAMER:
146 value = HAS_RESOURCE_STREAMER(dev);
148 case I915_PARAM_HAS_EXEC_SOFTPIN:
152 DRM_DEBUG("Unknown parameter %d\n", param->param);
156 if (copy_to_user(param->value, &value, sizeof(int))) {
157 DRM_ERROR("copy_to_user failed\n");
164 static int i915_get_bridge_dev(struct drm_device *dev)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 static struct pci_dev i915_bridge_dev;
169 i915_bridge_dev.dev.bsddev = pci_find_dbsf(0, 0, 0, 0);
170 if (!i915_bridge_dev.dev.bsddev) {
171 DRM_ERROR("bridge device not found\n");
175 dev_priv->bridge_dev = &i915_bridge_dev;
179 #define MCHBAR_I915 0x44
180 #define MCHBAR_I965 0x48
181 #define MCHBAR_SIZE (4*4096)
183 #define DEVEN_REG 0x54
184 #define DEVEN_MCHBAR_EN (1 << 28)
186 /* Allocate space for the MCH regs if needed, return nonzero on error */
188 intel_alloc_mchbar_resource(struct drm_device *dev)
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
193 u32 temp_lo, temp_hi = 0;
196 if (INTEL_INFO(dev)->gen >= 4)
197 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
198 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
199 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
201 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
204 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
208 /* Get some space for it */
209 vga = device_get_parent(dev->dev->bsddev);
210 dev_priv->mch_res_rid = 0x100;
211 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
212 dev->dev->bsddev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
213 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
214 if (dev_priv->mch_res == NULL) {
215 DRM_ERROR("failed mchbar resource alloc\n");
219 if (INTEL_INFO(dev)->gen >= 4)
220 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
221 upper_32_bits(rman_get_start(dev_priv->mch_res)));
223 pci_write_config_dword(dev_priv->bridge_dev, reg,
224 lower_32_bits(rman_get_start(dev_priv->mch_res)));
228 /* Setup MCHBAR if possible, return true if we should disable it again */
230 intel_setup_mchbar(struct drm_device *dev)
232 struct drm_i915_private *dev_priv = dev->dev_private;
233 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
237 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
240 dev_priv->mchbar_need_disable = false;
242 if (IS_I915G(dev) || IS_I915GM(dev)) {
243 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
244 enabled = !!(temp & DEVEN_MCHBAR_EN);
246 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
250 /* If it's already enabled, don't have to do anything */
254 if (intel_alloc_mchbar_resource(dev))
257 dev_priv->mchbar_need_disable = true;
259 /* Space is allocated or reserved, so enable it. */
260 if (IS_I915G(dev) || IS_I915GM(dev)) {
261 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
262 temp | DEVEN_MCHBAR_EN);
264 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
265 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
270 intel_teardown_mchbar(struct drm_device *dev)
272 struct drm_i915_private *dev_priv = dev->dev_private;
273 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
277 if (dev_priv->mchbar_need_disable) {
278 if (IS_I915G(dev) || IS_I915GM(dev)) {
279 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
280 temp &= ~DEVEN_MCHBAR_EN;
281 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
283 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
285 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
289 if (dev_priv->mch_res != NULL) {
290 vga = device_get_parent(dev->dev->bsddev);
291 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev->bsddev,
292 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
293 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev->bsddev,
294 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
295 dev_priv->mch_res = NULL;
300 /* true = enable decode, false = disable decoder */
301 static unsigned int i915_vga_set_decode(void *cookie, bool state)
303 struct drm_device *dev = cookie;
305 intel_modeset_vga_set_state(dev, state);
307 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
308 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
310 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
313 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
315 struct drm_device *dev = pci_get_drvdata(pdev);
316 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
318 if (state == VGA_SWITCHEROO_ON) {
319 pr_info("switched on\n");
320 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
321 /* i915 resume handler doesn't set to D0 */
322 pci_set_power_state(dev->pdev, PCI_D0);
323 i915_resume_switcheroo(dev);
324 dev->switch_power_state = DRM_SWITCH_POWER_ON;
326 pr_info("switched off\n");
327 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
328 i915_suspend_switcheroo(dev, pmm);
329 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
333 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
335 struct drm_device *dev = pci_get_drvdata(pdev);
338 * FIXME: open_count is protected by drm_global_mutex but that would lead to
339 * locking inversion with the driver load path. And the access here is
340 * completely racy anyway. So don't bother with locking for now.
342 return dev->open_count == 0;
345 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
346 .set_gpu_state = i915_switcheroo_set_state,
348 .can_switch = i915_switcheroo_can_switch,
352 static int i915_load_modeset_init(struct drm_device *dev)
354 struct drm_i915_private *dev_priv = dev->dev_private;
357 ret = intel_bios_init(dev_priv);
359 DRM_INFO("failed to find VBIOS tables\n");
362 /* If we have > 1 VGA cards, then we need to arbitrate access
363 * to the common VGA resources.
365 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
366 * then we do not take part in VGA arbitration and the
367 * vga_client_register() fails with -ENODEV.
369 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
370 if (ret && ret != -ENODEV)
373 intel_register_dsm_handler();
375 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
377 goto cleanup_vga_client;
379 /* Initialise stolen first so that we may reserve preallocated
380 * objects for the BIOS to KMS transition.
382 ret = i915_gem_init_stolen(dev);
384 goto cleanup_vga_switcheroo;
387 intel_power_domains_init_hw(dev_priv, false);
389 intel_csr_ucode_init(dev_priv);
391 ret = intel_irq_install(dev_priv);
393 goto cleanup_gem_stolen;
395 intel_setup_gmbus(dev);
397 /* Important: The output setup functions called by modeset_init need
398 * working irqs for e.g. gmbus and dp aux transfers. */
399 intel_modeset_init(dev);
401 intel_guc_ucode_init(dev);
403 ret = i915_gem_init(dev);
407 intel_modeset_gem_init(dev);
409 /* Always safe in the mode setting case. */
410 /* FIXME: do pre/post-mode set stuff in core KMS code */
411 dev->vblank_disable_allowed = 1;
412 if (INTEL_INFO(dev)->num_pipes == 0)
415 ret = intel_fbdev_init(dev);
419 /* Only enable hotplug handling once the fbdev is fully set up. */
420 intel_hpd_init(dev_priv);
423 * Some ports require correctly set-up hpd registers for detection to
424 * work properly (leading to ghost connected connector status), e.g. VGA
425 * on gm45. Hence we can only set up the initial fbdev config after hpd
426 * irqs are fully enabled. Now we should scan for the initial config
427 * only once hotplug handling is enabled, but due to screwed-up locking
428 * around kms/fbdev init we can't protect the fdbev initial config
429 * scanning against hotplug events. Hence do this first and ignore the
430 * tiny window where we will loose hotplug notifactions.
432 intel_fbdev_initial_config_async(dev);
434 drm_kms_helper_poll_init(dev);
439 mutex_lock(&dev->struct_mutex);
440 i915_gem_cleanup_ringbuffer(dev);
441 i915_gem_context_fini(dev);
442 mutex_unlock(&dev->struct_mutex);
444 intel_guc_ucode_fini(dev);
445 drm_irq_uninstall(dev);
446 intel_teardown_gmbus(dev);
448 i915_gem_cleanup_stolen(dev);
450 cleanup_vga_switcheroo:
451 vga_switcheroo_unregister_client(dev->pdev);
453 vga_client_register(dev->pdev, NULL, NULL, NULL);
459 #if IS_ENABLED(CONFIG_FB)
460 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
462 struct apertures_struct *ap;
463 struct pci_dev *pdev = dev_priv->dev->pdev;
467 ap = alloc_apertures(1);
471 ap->ranges[0].base = dev_priv->gtt.mappable_base;
472 ap->ranges[0].size = dev_priv->gtt.mappable_end;
475 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
477 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
484 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
490 #if !defined(CONFIG_VGA_CONSOLE)
491 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
495 #elif !defined(CONFIG_DUMMY_CONSOLE)
496 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
501 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
505 DRM_INFO("Replacing VGA console driver\n");
508 if (con_is_bound(&vga_con))
509 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
511 ret = do_unregister_con_driver(&vga_con);
513 /* Ignore "already unregistered". */
523 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
526 const struct intel_device_info *info = &dev_priv->info;
528 #define PRINT_S(name) "%s"
530 #define PRINT_FLAG(name) info->name ? #name "," : ""
532 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
533 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
535 dev_priv->dev->pdev->device,
536 dev_priv->dev->pdev->revision,
537 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
545 static void cherryview_sseu_info_init(struct drm_device *dev)
547 struct drm_i915_private *dev_priv = dev->dev_private;
548 struct intel_device_info *info;
551 info = (struct intel_device_info *)&dev_priv->info;
552 fuse = I915_READ(CHV_FUSE_GT);
554 info->slice_total = 1;
556 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
557 info->subslice_per_slice++;
558 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
559 CHV_FGT_EU_DIS_SS0_R1_MASK);
560 info->eu_total += 8 - hweight32(eu_dis);
563 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
564 info->subslice_per_slice++;
565 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
566 CHV_FGT_EU_DIS_SS1_R1_MASK);
567 info->eu_total += 8 - hweight32(eu_dis);
570 info->subslice_total = info->subslice_per_slice;
572 * CHV expected to always have a uniform distribution of EU
575 info->eu_per_subslice = info->subslice_total ?
576 info->eu_total / info->subslice_total :
579 * CHV supports subslice power gating on devices with more than
580 * one subslice, and supports EU power gating on devices with
581 * more than one EU pair per subslice.
583 info->has_slice_pg = 0;
584 info->has_subslice_pg = (info->subslice_total > 1);
585 info->has_eu_pg = (info->eu_per_subslice > 2);
588 static void gen9_sseu_info_init(struct drm_device *dev)
590 struct drm_i915_private *dev_priv = dev->dev_private;
591 struct intel_device_info *info;
592 int s_max = 3, ss_max = 4, eu_max = 8;
594 u32 fuse2, s_enable, ss_disable, eu_disable;
597 info = (struct intel_device_info *)&dev_priv->info;
598 fuse2 = I915_READ(GEN8_FUSE2);
599 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
601 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
602 GEN9_F2_SS_DIS_SHIFT;
604 info->slice_total = hweight32(s_enable);
606 * The subslice disable field is global, i.e. it applies
607 * to each of the enabled slices.
609 info->subslice_per_slice = ss_max - hweight32(ss_disable);
610 info->subslice_total = info->slice_total *
611 info->subslice_per_slice;
614 * Iterate through enabled slices and subslices to
615 * count the total enabled EU.
617 for (s = 0; s < s_max; s++) {
618 if (!(s_enable & (0x1 << s)))
619 /* skip disabled slice */
622 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
623 for (ss = 0; ss < ss_max; ss++) {
626 if (ss_disable & (0x1 << ss))
627 /* skip disabled subslice */
630 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
634 * Record which subslice(s) has(have) 7 EUs. we
635 * can tune the hash used to spread work among
636 * subslices if they are unbalanced.
639 info->subslice_7eu[s] |= 1 << ss;
641 info->eu_total += eu_per_ss;
646 * SKL is expected to always have a uniform distribution
647 * of EU across subslices with the exception that any one
648 * EU in any one subslice may be fused off for die
649 * recovery. BXT is expected to be perfectly uniform in EU
652 info->eu_per_subslice = info->subslice_total ?
653 DIV_ROUND_UP(info->eu_total,
654 info->subslice_total) : 0;
656 * SKL supports slice power gating on devices with more than
657 * one slice, and supports EU power gating on devices with
658 * more than one EU pair per subslice. BXT supports subslice
659 * power gating on devices with more than one subslice, and
660 * supports EU power gating on devices with more than one EU
663 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
664 (info->slice_total > 1));
665 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
666 info->has_eu_pg = (info->eu_per_subslice > 2);
669 static void broadwell_sseu_info_init(struct drm_device *dev)
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 struct intel_device_info *info;
673 const int s_max = 3, ss_max = 3, eu_max = 8;
675 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
677 fuse2 = I915_READ(GEN8_FUSE2);
678 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
679 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
681 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
682 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
683 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
684 (32 - GEN8_EU_DIS0_S1_SHIFT));
685 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
686 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
687 (32 - GEN8_EU_DIS1_S2_SHIFT));
690 info = (struct intel_device_info *)&dev_priv->info;
691 info->slice_total = hweight32(s_enable);
694 * The subslice disable field is global, i.e. it applies
695 * to each of the enabled slices.
697 info->subslice_per_slice = ss_max - hweight32(ss_disable);
698 info->subslice_total = info->slice_total * info->subslice_per_slice;
701 * Iterate through enabled slices and subslices to
702 * count the total enabled EU.
704 for (s = 0; s < s_max; s++) {
705 if (!(s_enable & (0x1 << s)))
706 /* skip disabled slice */
709 for (ss = 0; ss < ss_max; ss++) {
712 if (ss_disable & (0x1 << ss))
713 /* skip disabled subslice */
716 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
719 * Record which subslices have 7 EUs.
721 if (eu_max - n_disabled == 7)
722 info->subslice_7eu[s] |= 1 << ss;
724 info->eu_total += eu_max - n_disabled;
729 * BDW is expected to always have a uniform distribution of EU across
730 * subslices with the exception that any one EU in any one subslice may
731 * be fused off for die recovery.
733 info->eu_per_subslice = info->subslice_total ?
734 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
737 * BDW supports slice power gating on devices with more than
740 info->has_slice_pg = (info->slice_total > 1);
741 info->has_subslice_pg = 0;
746 * Determine various intel_device_info fields at runtime.
748 * Use it when either:
749 * - it's judged too laborious to fill n static structures with the limit
750 * when a simple if statement does the job,
751 * - run-time checks (eg read fuse/strap registers) are needed.
753 * This function needs to be called:
754 * - after the MMIO has been setup as we are reading registers,
755 * - after the PCH has been detected,
756 * - before the first usage of the fields it can tweak.
758 static void intel_device_info_runtime_init(struct drm_device *dev)
760 struct drm_i915_private *dev_priv = dev->dev_private;
761 struct intel_device_info *info;
764 info = (struct intel_device_info *)&dev_priv->info;
767 * Skylake and Broxton currently don't expose the topmost plane as its
768 * use is exclusive with the legacy cursor and we only want to expose
769 * one of those, not both. Until we can safely expose the topmost plane
770 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
771 * we don't expose the topmost plane at all to prevent ABI breakage
774 if (IS_BROXTON(dev)) {
775 info->num_sprites[PIPE_A] = 2;
776 info->num_sprites[PIPE_B] = 2;
777 info->num_sprites[PIPE_C] = 1;
778 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
779 for_each_pipe(dev_priv, pipe)
780 info->num_sprites[pipe] = 2;
782 for_each_pipe(dev_priv, pipe)
783 info->num_sprites[pipe] = 1;
785 if (i915.disable_display) {
786 DRM_INFO("Display disabled (module parameter)\n");
788 } else if (info->num_pipes > 0 &&
789 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
790 HAS_PCH_SPLIT(dev)) {
791 u32 fuse_strap = I915_READ(FUSE_STRAP);
792 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
795 * SFUSE_STRAP is supposed to have a bit signalling the display
796 * is fused off. Unfortunately it seems that, at least in
797 * certain cases, fused off display means that PCH display
798 * reads don't land anywhere. In that case, we read 0s.
800 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
801 * should be set when taking over after the firmware.
803 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
804 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
805 (dev_priv->pch_type == PCH_CPT &&
806 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
807 DRM_INFO("Display fused off, disabling\n");
812 /* Initialize slice/subslice/EU info */
813 if (IS_CHERRYVIEW(dev))
814 cherryview_sseu_info_init(dev);
815 else if (IS_BROADWELL(dev))
816 broadwell_sseu_info_init(dev);
817 else if (INTEL_INFO(dev)->gen >= 9)
818 gen9_sseu_info_init(dev);
820 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
821 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
822 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
823 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
824 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
825 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
826 info->has_slice_pg ? "y" : "n");
827 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
828 info->has_subslice_pg ? "y" : "n");
829 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
830 info->has_eu_pg ? "y" : "n");
833 static void intel_init_dpio(struct drm_i915_private *dev_priv)
836 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
837 * CHV x1 PHY (DP/HDMI D)
838 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
840 if (IS_CHERRYVIEW(dev_priv)) {
841 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
842 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
843 } else if (IS_VALLEYVIEW(dev_priv)) {
844 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
849 * i915_driver_load - setup chip and create an initial config
851 * @flags: startup flags
853 * The driver load routine has to do several things:
854 * - drive output discovery via intel_modeset_init()
855 * - initialize the memory manager
856 * - allocate initial config memory
857 * - setup the DRM framebuffer with the allocated memory
859 int i915_driver_load(struct drm_device *dev, unsigned long flags)
861 struct drm_i915_private *dev_priv;
862 struct intel_device_info *info, *device_info;
863 int ret = 0, mmio_bar, mmio_size;
864 uint32_t aperture_size;
866 /* XXX: struct pci_dev */
867 info = i915_get_device_id(dev->pdev->device);
869 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
870 if (dev_priv == NULL)
873 dev->dev_private = dev_priv;
876 /* Setup the write-once "constant" device info */
877 device_info = (struct intel_device_info *)&dev_priv->info;
878 memcpy(device_info, info, sizeof(dev_priv->info));
879 device_info->device_id = dev->pdev->device;
881 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
882 lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
883 lockinit(&dev_priv->backlight_lock, "i915bl", 0, LK_CANRECURSE);
884 lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
885 spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
886 spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
887 lockinit(&dev_priv->sb_lock, "i915sbl", 0, LK_CANRECURSE);
888 lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
889 lockinit(&dev_priv->av_mutex, "i915am", 0, LK_CANRECURSE);
893 intel_runtime_pm_get(dev_priv);
895 intel_display_crc_init(dev);
897 i915_dump_device_info(dev_priv);
899 /* Not all pre-production machines fall into this category, only the
900 * very first ones. Almost everything should work, except for maybe
901 * suspend/resume. And we don't implement workarounds that affect only
902 * pre-production machines. */
903 if (IS_HSW_EARLY_SDV(dev))
904 DRM_INFO("This is an early pre-production Haswell machine. "
905 "It may not be fully functional.\n");
907 if (i915_get_bridge_dev(dev)) {
912 mmio_bar = IS_GEN2(dev) ? 1 : 0;
913 /* Before gen4, the registers and the GTT are behind different BARs.
914 * However, from gen4 onwards, the registers and the GTT are shared
915 * in the same BAR, so we want to restrict this ioremap from
916 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
917 * the register BAR remains the same size for all the earlier
918 * generations up to Ironlake.
921 mmio_size = 512*1024;
923 mmio_size = 2*1024*1024;
925 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
926 if (!dev_priv->regs) {
927 DRM_ERROR("failed to map registers\n");
932 /* This must be called before any calls to HAS_PCH_* */
933 intel_detect_pch(dev);
935 intel_uncore_init(dev);
937 ret = i915_gem_gtt_init(dev);
941 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
942 * otherwise the vga fbdev driver falls over. */
943 ret = i915_kick_out_firmware_fb(dev_priv);
945 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
949 ret = i915_kick_out_vgacon(dev_priv);
951 DRM_ERROR("failed to remove conflicting VGA console\n");
956 pci_set_master(dev->pdev);
958 /* overlay on gen2 is broken and can't address above 1G */
960 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
962 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
963 * using 32bit addressing, overwriting memory if HWS is located
966 * The documentation also mentions an issue with undefined
967 * behaviour if any general state is accessed within a page above 4GB,
968 * which also needs to be handled carefully.
970 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
971 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
974 aperture_size = dev_priv->gtt.mappable_end;
976 dev_priv->gtt.mappable =
977 io_mapping_create_wc(dev_priv->gtt.mappable_base,
979 if (dev_priv->gtt.mappable == NULL) {
984 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
987 /* The i915 workqueue is primarily used for batched retirement of
988 * requests (and thus managing bo) once the task has been completed
989 * by the GPU. i915_gem_retire_requests() is called directly when we
990 * need high-priority retirement, such as waiting for an explicit
993 * It is also used for periodic low-priority events, such as
994 * idle-timers and recording error state.
996 * All tasks on the workqueue are expected to acquire the dev mutex
997 * so there is no point in running more than one instance of the
998 * workqueue at any time. Use an ordered one.
1000 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1001 if (dev_priv->wq == NULL) {
1002 DRM_ERROR("Failed to create our workqueue.\n");
1007 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1008 if (dev_priv->hotplug.dp_wq == NULL) {
1009 DRM_ERROR("Failed to create our dp workqueue.\n");
1014 dev_priv->gpu_error.hangcheck_wq =
1015 alloc_ordered_workqueue("i915-hangcheck", 0);
1016 if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1017 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1022 intel_irq_init(dev_priv);
1023 intel_uncore_sanitize(dev);
1025 /* Try to make sure MCHBAR is enabled before poking at it */
1026 intel_setup_mchbar(dev);
1027 intel_opregion_setup(dev);
1031 /* On the 945G/GM, the chipset reports the MSI capability on the
1032 * integrated graphics even though the support isn't actually there
1033 * according to the published specs. It doesn't appear to function
1034 * correctly in testing on 945G.
1035 * This may be a side effect of MSI having been made available for PEG
1036 * and the registers being closely associated.
1038 * According to chipset errata, on the 965GM, MSI interrupts may
1039 * be lost or delayed, but we use them anyways to avoid
1040 * stuck interrupts on some machines.
1043 if (!IS_I945G(dev) && !IS_I945GM(dev))
1044 pci_enable_msi(dev->pdev);
1047 intel_device_info_runtime_init(dev);
1049 intel_init_dpio(dev_priv);
1051 if (INTEL_INFO(dev)->num_pipes) {
1052 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1054 goto out_gem_unload;
1057 intel_power_domains_init(dev_priv);
1059 ret = i915_load_modeset_init(dev);
1061 DRM_ERROR("failed to init modeset\n");
1062 goto out_power_well;
1066 * Notify a valid surface after modesetting,
1067 * when running inside a VM.
1069 if (intel_vgpu_active(dev))
1070 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1072 i915_setup_sysfs(dev);
1074 if (INTEL_INFO(dev)->num_pipes) {
1075 /* Must be done after probing outputs */
1076 intel_opregion_init(dev);
1078 acpi_video_register();
1083 intel_gpu_ips_init(dev_priv);
1085 intel_runtime_pm_enable(dev_priv);
1087 i915_audio_component_init(dev_priv);
1089 intel_runtime_pm_put(dev_priv);
1094 intel_power_domains_fini(dev_priv);
1095 drm_vblank_cleanup(dev);
1098 intel_teardown_mchbar(dev);
1099 pm_qos_remove_request(&dev_priv->pm_qos);
1100 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1102 destroy_workqueue(dev_priv->hotplug.dp_wq);
1104 destroy_workqueue(dev_priv->wq);
1106 arch_phys_wc_del(dev_priv->gtt.mtrr);
1108 io_mapping_free(dev_priv->gtt.mappable);
1111 i915_global_gtt_cleanup(dev);
1113 intel_csr_ucode_fini(dev_priv);
1114 intel_uncore_fini(dev);
1116 pci_iounmap(dev->pdev, dev_priv->regs);
1119 pci_dev_put(dev_priv->bridge_dev);
1122 intel_runtime_pm_put(dev_priv);
1128 int i915_driver_unload(struct drm_device *dev)
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1133 intel_fbdev_fini(dev);
1135 i915_audio_component_cleanup(dev_priv);
1137 ret = i915_gem_suspend(dev);
1139 DRM_ERROR("failed to idle hardware: %d\n", ret);
1143 intel_power_domains_fini(dev_priv);
1145 intel_gpu_ips_teardown();
1147 i915_teardown_sysfs(dev);
1150 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1151 unregister_shrinker(&dev_priv->mm.shrinker);
1153 io_mapping_free(dev_priv->gtt.mappable);
1155 arch_phys_wc_del(dev_priv->gtt.mtrr);
1158 acpi_video_unregister();
1161 drm_vblank_cleanup(dev);
1163 intel_modeset_cleanup(dev);
1166 * free the memory space allocated for the child device
1167 * config parsed from VBT
1169 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1170 kfree(dev_priv->vbt.child_dev);
1171 dev_priv->vbt.child_dev = NULL;
1172 dev_priv->vbt.child_dev_num = 0;
1174 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1175 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1176 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1177 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1180 vga_switcheroo_unregister_client(dev->pdev);
1181 vga_client_register(dev->pdev, NULL, NULL, NULL);
1184 /* Free error state after interrupts are fully disabled. */
1185 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1187 i915_destroy_error_state(dev);
1189 if (dev->pdev->msi_enabled)
1190 pci_disable_msi(dev->pdev);
1193 intel_opregion_fini(dev);
1195 /* Flush any outstanding unpin_work. */
1196 flush_workqueue(dev_priv->wq);
1198 intel_guc_ucode_fini(dev);
1199 mutex_lock(&dev->struct_mutex);
1200 i915_gem_cleanup_ringbuffer(dev);
1201 i915_gem_context_fini(dev);
1202 mutex_unlock(&dev->struct_mutex);
1203 intel_fbc_cleanup_cfb(dev_priv);
1204 i915_gem_cleanup_stolen(dev);
1206 intel_csr_ucode_fini(dev_priv);
1208 intel_teardown_mchbar(dev);
1210 destroy_workqueue(dev_priv->hotplug.dp_wq);
1211 destroy_workqueue(dev_priv->wq);
1212 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1213 pm_qos_remove_request(&dev_priv->pm_qos);
1215 i915_global_gtt_cleanup(dev);
1217 intel_uncore_fini(dev);
1219 if (dev_priv->regs != NULL)
1220 pci_iounmap(dev->pdev, dev_priv->regs);
1223 pci_dev_put(dev_priv->bridge_dev);
1229 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1233 ret = i915_gem_open(dev, file);
1241 * i915_driver_lastclose - clean up after all DRM clients have exited
1244 * Take care of cleaning up after all DRM clients have exited. In the
1245 * mode setting case, we want to restore the kernel's initial mode (just
1246 * in case the last client left us in a bad state).
1248 * Additionally, in the non-mode setting case, we'll tear down the GTT
1249 * and DMA structures, since the kernel won't be using them, and clea
1252 void i915_driver_lastclose(struct drm_device *dev)
1254 intel_fbdev_restore_mode(dev);
1256 vga_switcheroo_process_delayed_switch();
1260 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1262 mutex_lock(&dev->struct_mutex);
1263 i915_gem_context_close(dev, file);
1264 i915_gem_release(dev, file);
1265 mutex_unlock(&dev->struct_mutex);
1267 intel_modeset_preclose(dev, file);
1270 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1272 struct drm_i915_file_private *file_priv = file->driver_priv;
1278 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1279 struct drm_file *file)
1284 const struct drm_ioctl_desc i915_ioctls[] = {
1285 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1286 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1287 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1288 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1289 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1290 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1291 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1292 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1293 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1294 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1295 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1296 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1297 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1298 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1299 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1300 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1301 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1302 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1303 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1304 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1305 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1306 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1307 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1308 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1309 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1310 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1311 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1312 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1313 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1314 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1315 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1316 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1317 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1318 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1319 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1320 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1321 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1322 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1323 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1324 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1325 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1326 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1327 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1328 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1329 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1330 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1331 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1332 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1333 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1335 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1337 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1338 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1341 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);