2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
40 #define RQ_BUG_ON(expr)
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
52 return HAS_LLC(dev) || level != I915_CACHE_NONE;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
57 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
60 return obj->pin_display;
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
67 spin_lock(&dev_priv->mm.object_stat_lock);
68 dev_priv->mm.object_count++;
69 dev_priv->mm.object_memory += size;
70 spin_unlock(&dev_priv->mm.object_stat_lock);
73 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
76 spin_lock(&dev_priv->mm.object_stat_lock);
77 dev_priv->mm.object_count--;
78 dev_priv->mm.object_memory -= size;
79 spin_unlock(&dev_priv->mm.object_stat_lock);
83 i915_gem_wait_for_error(struct i915_gpu_error *error)
87 #define EXIT_COND (!i915_reset_in_progress(error) || \
88 i915_terminally_wedged(error))
93 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
94 * userspace. If it takes that long something really bad is going on and
95 * we should simply try to bail out and fail as gracefully as possible.
97 ret = wait_event_interruptible_timeout(error->reset_queue,
101 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
103 } else if (ret < 0) {
111 int i915_mutex_lock_interruptible(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
116 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
120 ret = mutex_lock_interruptible(&dev->struct_mutex);
124 WARN_ON(i915_verify_lists(dev));
129 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
130 struct drm_file *file)
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct drm_i915_gem_get_aperture *args = data;
134 struct i915_gtt *ggtt = &dev_priv->gtt;
135 struct i915_vma *vma;
139 mutex_lock(&dev->struct_mutex);
140 list_for_each_entry(vma, &ggtt->base.active_list, mm_list)
142 pinned += vma->node.size;
143 list_for_each_entry(vma, &ggtt->base.inactive_list, mm_list)
145 pinned += vma->node.size;
146 mutex_unlock(&dev->struct_mutex);
148 args->aper_size = dev_priv->gtt.base.total;
149 args->aper_available_size = args->aper_size - pinned;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
158 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
159 char *vaddr = obj->phys_handle->vaddr;
161 struct scatterlist *sg;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
167 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
171 page = shmem_read_mapping_page(mapping, i);
173 return PTR_ERR(page);
175 src = kmap_atomic(page);
176 memcpy(vaddr, src, PAGE_SIZE);
177 drm_clflush_virt_range(vaddr, PAGE_SIZE);
180 page_cache_release(page);
184 i915_gem_chipset_flush(obj->base.dev);
186 st = kmalloc(sizeof(*st), GFP_KERNEL);
190 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
197 sg->length = obj->base.size;
199 sg_dma_address(sg) = obj->phys_handle->busaddr;
200 sg_dma_len(sg) = obj->base.size;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
211 BUG_ON(obj->madv == __I915_MADV_PURGED);
213 ret = i915_gem_object_set_to_cpu_domain(obj, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret != -EIO);
219 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
222 if (obj->madv == I915_MADV_DONTNEED)
226 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
227 char *vaddr = obj->phys_handle->vaddr;
230 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
234 page = shmem_read_mapping_page(mapping, i);
238 dst = kmap_atomic(page);
239 drm_clflush_virt_range(vaddr, PAGE_SIZE);
240 memcpy(dst, vaddr, PAGE_SIZE);
243 set_page_dirty(page);
244 if (obj->madv == I915_MADV_WILLNEED)
245 mark_page_accessed(page);
246 page_cache_release(page);
252 sg_free_table(obj->pages);
257 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
259 drm_pci_free(obj->base.dev, obj->phys_handle);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
263 .get_pages = i915_gem_object_get_pages_phys,
264 .put_pages = i915_gem_object_put_pages_phys,
265 .release = i915_gem_object_release_phys,
270 drop_pages(struct drm_i915_gem_object *obj)
272 struct i915_vma *vma, *next;
275 drm_gem_object_reference(&obj->base);
276 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
277 if (i915_vma_unbind(vma))
280 ret = i915_gem_object_put_pages(obj);
281 drm_gem_object_unreference(&obj->base);
287 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
290 drm_dma_handle_t *phys;
293 if (obj->phys_handle) {
294 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
300 if (obj->madv != I915_MADV_WILLNEED)
304 if (obj->base.filp == NULL)
308 ret = drop_pages(obj);
312 /* create a new object */
313 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
317 obj->phys_handle = phys;
319 obj->ops = &i915_gem_phys_ops;
322 return i915_gem_object_get_pages(obj);
326 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
327 struct drm_i915_gem_pwrite *args,
328 struct drm_file *file_priv)
330 struct drm_device *dev = obj->base.dev;
331 void *vaddr = (char *)obj->phys_handle->vaddr + args->offset;
332 char __user *user_data = to_user_ptr(args->data_ptr);
335 /* We manually control the domain here and pretend that it
336 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
338 ret = i915_gem_object_wait_rendering(obj, false);
342 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
343 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
344 unsigned long unwritten;
346 /* The physical object once assigned is fixed for the lifetime
347 * of the obj, so we can safely drop the lock and continue
350 mutex_unlock(&dev->struct_mutex);
351 unwritten = copy_from_user(vaddr, user_data, args->size);
352 mutex_lock(&dev->struct_mutex);
359 drm_clflush_virt_range(vaddr, args->size);
360 i915_gem_chipset_flush(dev);
363 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
367 void *i915_gem_object_alloc(struct drm_device *dev)
369 return kmalloc(sizeof(struct drm_i915_gem_object),
370 M_DRM, M_WAITOK | M_ZERO);
373 void i915_gem_object_free(struct drm_i915_gem_object *obj)
379 i915_gem_create(struct drm_file *file,
380 struct drm_device *dev,
384 struct drm_i915_gem_object *obj;
388 size = roundup(size, PAGE_SIZE);
392 /* Allocate the new object */
393 obj = i915_gem_alloc_object(dev, size);
397 ret = drm_gem_handle_create(file, &obj->base, &handle);
398 /* drop reference from allocate - handle holds it now */
399 drm_gem_object_unreference_unlocked(&obj->base);
408 i915_gem_dumb_create(struct drm_file *file,
409 struct drm_device *dev,
410 struct drm_mode_create_dumb *args)
412 /* have to work out size/pitch and return them */
413 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
414 args->size = args->pitch * args->height;
415 return i915_gem_create(file, dev,
416 args->size, &args->handle);
420 * Creates a new mm object and returns a handle to it.
423 i915_gem_create_ioctl(struct drm_device *dev, void *data,
424 struct drm_file *file)
426 struct drm_i915_gem_create *args = data;
428 return i915_gem_create(file, dev,
429 args->size, &args->handle);
433 __copy_to_user_swizzled(char __user *cpu_vaddr,
434 const char *gpu_vaddr, int gpu_offset,
437 int ret, cpu_offset = 0;
440 int cacheline_end = ALIGN(gpu_offset + 1, 64);
441 int this_length = min(cacheline_end - gpu_offset, length);
442 int swizzled_gpu_offset = gpu_offset ^ 64;
444 ret = __copy_to_user(cpu_vaddr + cpu_offset,
445 gpu_vaddr + swizzled_gpu_offset,
450 cpu_offset += this_length;
451 gpu_offset += this_length;
452 length -= this_length;
459 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
460 const char __user *cpu_vaddr,
463 int ret, cpu_offset = 0;
466 int cacheline_end = ALIGN(gpu_offset + 1, 64);
467 int this_length = min(cacheline_end - gpu_offset, length);
468 int swizzled_gpu_offset = gpu_offset ^ 64;
470 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
471 cpu_vaddr + cpu_offset,
476 cpu_offset += this_length;
477 gpu_offset += this_length;
478 length -= this_length;
485 * Pins the specified object's pages and synchronizes the object with
486 * GPU accesses. Sets needs_clflush to non-zero if the caller should
487 * flush the object from the CPU cache.
489 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
501 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
502 /* If we're not in the cpu read domain, set ourself into the gtt
503 * read domain and manually flush cachelines (if required). This
504 * optimizes for the case when the gpu will dirty the data
505 * anyway again before the next pread happens. */
506 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
508 ret = i915_gem_object_wait_rendering(obj, true);
513 ret = i915_gem_object_get_pages(obj);
517 i915_gem_object_pin_pages(obj);
522 /* Per-page copy function for the shmem pread fastpath.
523 * Flushes invalid cachelines before reading the target if
524 * needs_clflush is set. */
526 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
527 char __user *user_data,
528 bool page_do_bit17_swizzling, bool needs_clflush)
533 if (unlikely(page_do_bit17_swizzling))
536 vaddr = kmap_atomic(page);
538 drm_clflush_virt_range(vaddr + shmem_page_offset,
540 ret = __copy_to_user_inatomic(user_data,
541 vaddr + shmem_page_offset,
543 kunmap_atomic(vaddr);
545 return ret ? -EFAULT : 0;
549 shmem_clflush_swizzled_range(char *addr, unsigned long length,
552 if (unlikely(swizzled)) {
553 unsigned long start = (unsigned long) addr;
554 unsigned long end = (unsigned long) addr + length;
556 /* For swizzling simply ensure that we always flush both
557 * channels. Lame, but simple and it works. Swizzled
558 * pwrite/pread is far from a hotpath - current userspace
559 * doesn't use it at all. */
560 start = round_down(start, 128);
561 end = round_up(end, 128);
563 drm_clflush_virt_range((void *)start, end - start);
565 drm_clflush_virt_range(addr, length);
570 /* Only difference to the fast-path function is that this can handle bit17
571 * and uses non-atomic copy and kmap functions. */
573 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
574 char __user *user_data,
575 bool page_do_bit17_swizzling, bool needs_clflush)
582 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
584 page_do_bit17_swizzling);
586 if (page_do_bit17_swizzling)
587 ret = __copy_to_user_swizzled(user_data,
588 vaddr, shmem_page_offset,
591 ret = __copy_to_user(user_data,
592 vaddr + shmem_page_offset,
596 return ret ? - EFAULT : 0;
600 i915_gem_shmem_pread(struct drm_device *dev,
601 struct drm_i915_gem_object *obj,
602 struct drm_i915_gem_pread *args,
603 struct drm_file *file)
605 char __user *user_data;
608 int shmem_page_offset, page_length, ret = 0;
609 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
611 int needs_clflush = 0;
612 struct sg_page_iter sg_iter;
614 user_data = to_user_ptr(args->data_ptr);
617 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
619 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
623 offset = args->offset;
625 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
626 offset >> PAGE_SHIFT) {
627 struct vm_page *page = sg_page_iter_page(&sg_iter);
632 /* Operation in this page
634 * shmem_page_offset = offset within page in shmem file
635 * page_length = bytes to copy for this page
637 shmem_page_offset = offset_in_page(offset);
638 page_length = remain;
639 if ((shmem_page_offset + page_length) > PAGE_SIZE)
640 page_length = PAGE_SIZE - shmem_page_offset;
642 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
643 (page_to_phys(page) & (1 << 17)) != 0;
645 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
646 user_data, page_do_bit17_swizzling,
651 mutex_unlock(&dev->struct_mutex);
653 if (likely(!i915.prefault_disable) && !prefaulted) {
654 ret = fault_in_multipages_writeable(user_data, remain);
655 /* Userspace is tricking us, but we've already clobbered
656 * its pages with the prefault and promised to write the
657 * data up to the first fault. Hence ignore any errors
658 * and just continue. */
663 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
664 user_data, page_do_bit17_swizzling,
667 mutex_lock(&dev->struct_mutex);
673 remain -= page_length;
674 user_data += page_length;
675 offset += page_length;
679 i915_gem_object_unpin_pages(obj);
685 * Reads data from the object referenced by handle.
687 * On error, the contents of *data are undefined.
690 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
691 struct drm_file *file)
693 struct drm_i915_gem_pread *args = data;
694 struct drm_i915_gem_object *obj;
700 ret = i915_mutex_lock_interruptible(dev);
704 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
705 if (&obj->base == NULL) {
710 /* Bounds check source. */
711 if (args->offset > obj->base.size ||
712 args->size > obj->base.size - args->offset) {
717 /* prime objects have no backing filp to GEM pread/pwrite
721 trace_i915_gem_object_pread(obj, args->offset, args->size);
723 ret = i915_gem_shmem_pread(dev, obj, args, file);
726 drm_gem_object_unreference(&obj->base);
728 mutex_unlock(&dev->struct_mutex);
732 /* This is the fast write path which cannot handle
733 * page faults in the source data
737 fast_user_write(struct io_mapping *mapping,
738 loff_t page_base, int page_offset,
739 char __user *user_data,
742 void __iomem *vaddr_atomic;
744 unsigned long unwritten;
746 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
747 /* We can use the cpu mem copy function because this is X86. */
748 vaddr = (char __force*)vaddr_atomic + page_offset;
749 unwritten = __copy_from_user_inatomic_nocache(vaddr,
751 io_mapping_unmap_atomic(vaddr_atomic);
756 * This is the fast pwrite path, where we copy the data directly from the
757 * user into the GTT, uncached.
760 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
761 struct drm_i915_gem_object *obj,
762 struct drm_i915_gem_pwrite *args,
763 struct drm_file *file)
765 struct drm_i915_private *dev_priv = dev->dev_private;
767 loff_t offset, page_base;
768 char __user *user_data;
769 int page_offset, page_length, ret;
771 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
775 ret = i915_gem_object_set_to_gtt_domain(obj, true);
779 ret = i915_gem_object_put_fence(obj);
783 user_data = to_user_ptr(args->data_ptr);
786 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
788 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
791 /* Operation in this page
793 * page_base = page offset within aperture
794 * page_offset = offset within page
795 * page_length = bytes to copy for this page
797 page_base = offset & ~PAGE_MASK;
798 page_offset = offset_in_page(offset);
799 page_length = remain;
800 if ((page_offset + remain) > PAGE_SIZE)
801 page_length = PAGE_SIZE - page_offset;
803 /* If we get a fault while copying data, then (presumably) our
804 * source page isn't available. Return the error and we'll
805 * retry in the slow path.
807 if (fast_user_write(dev_priv->gtt.mappable, page_base,
808 page_offset, user_data, page_length)) {
813 remain -= page_length;
814 user_data += page_length;
815 offset += page_length;
819 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
821 i915_gem_object_ggtt_unpin(obj);
826 /* Per-page copy function for the shmem pwrite fastpath.
827 * Flushes invalid cachelines before writing to the target if
828 * needs_clflush_before is set and flushes out any written cachelines after
829 * writing if needs_clflush is set. */
831 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
832 char __user *user_data,
833 bool page_do_bit17_swizzling,
834 bool needs_clflush_before,
835 bool needs_clflush_after)
840 if (unlikely(page_do_bit17_swizzling))
843 vaddr = kmap_atomic(page);
844 if (needs_clflush_before)
845 drm_clflush_virt_range(vaddr + shmem_page_offset,
847 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
848 user_data, page_length);
849 if (needs_clflush_after)
850 drm_clflush_virt_range(vaddr + shmem_page_offset,
852 kunmap_atomic(vaddr);
854 return ret ? -EFAULT : 0;
857 /* Only difference to the fast-path function is that this can handle bit17
858 * and uses non-atomic copy and kmap functions. */
860 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
861 char __user *user_data,
862 bool page_do_bit17_swizzling,
863 bool needs_clflush_before,
864 bool needs_clflush_after)
870 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
871 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
873 page_do_bit17_swizzling);
874 if (page_do_bit17_swizzling)
875 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
879 ret = __copy_from_user(vaddr + shmem_page_offset,
882 if (needs_clflush_after)
883 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
885 page_do_bit17_swizzling);
888 return ret ? -EFAULT : 0;
892 i915_gem_shmem_pwrite(struct drm_device *dev,
893 struct drm_i915_gem_object *obj,
894 struct drm_i915_gem_pwrite *args,
895 struct drm_file *file)
899 char __user *user_data;
900 int shmem_page_offset, page_length, ret = 0;
901 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
902 int hit_slowpath = 0;
903 int needs_clflush_after = 0;
904 int needs_clflush_before = 0;
905 struct sg_page_iter sg_iter;
907 user_data = to_user_ptr(args->data_ptr);
910 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
912 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
913 /* If we're not in the cpu write domain, set ourself into the gtt
914 * write domain and manually flush cachelines (if required). This
915 * optimizes for the case when the gpu will use the data
916 * right away and we therefore have to clflush anyway. */
917 needs_clflush_after = cpu_write_needs_clflush(obj);
918 ret = i915_gem_object_wait_rendering(obj, false);
922 /* Same trick applies to invalidate partially written cachelines read
924 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
925 needs_clflush_before =
926 !cpu_cache_is_coherent(dev, obj->cache_level);
928 ret = i915_gem_object_get_pages(obj);
932 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
934 i915_gem_object_pin_pages(obj);
936 offset = args->offset;
939 VM_OBJECT_LOCK(obj->base.vm_obj);
940 vm_object_pip_add(obj->base.vm_obj, 1);
942 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
943 offset >> PAGE_SHIFT) {
944 struct vm_page *page = sg_page_iter_page(&sg_iter);
945 int partial_cacheline_write;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset = offset_in_page(offset);
957 page_length = remain;
958 if ((shmem_page_offset + page_length) > PAGE_SIZE)
959 page_length = PAGE_SIZE - shmem_page_offset;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write = needs_clflush_before &&
965 ((shmem_page_offset | page_length)
966 & (cpu_clflush_line_size - 1));
968 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
969 (page_to_phys(page) & (1 << 17)) != 0;
971 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
972 user_data, page_do_bit17_swizzling,
973 partial_cacheline_write,
974 needs_clflush_after);
979 mutex_unlock(&dev->struct_mutex);
980 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
981 user_data, page_do_bit17_swizzling,
982 partial_cacheline_write,
983 needs_clflush_after);
985 mutex_lock(&dev->struct_mutex);
991 remain -= page_length;
992 user_data += page_length;
993 offset += page_length;
995 vm_object_pip_wakeup(obj->base.vm_obj);
996 VM_OBJECT_UNLOCK(obj->base.vm_obj);
999 i915_gem_object_unpin_pages(obj);
1003 * Fixup: Flush cpu caches in case we didn't flush the dirty
1004 * cachelines in-line while writing and the object moved
1005 * out of the cpu write domain while we've dropped the lock.
1007 if (!needs_clflush_after &&
1008 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1009 if (i915_gem_clflush_object(obj, obj->pin_display))
1010 i915_gem_chipset_flush(dev);
1014 if (needs_clflush_after)
1015 i915_gem_chipset_flush(dev);
1017 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1022 * Writes data to the object referenced by handle.
1024 * On error, the contents of the buffer that were to be modified are undefined.
1027 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1028 struct drm_file *file)
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct drm_i915_gem_pwrite *args = data;
1032 struct drm_i915_gem_object *obj;
1035 if (args->size == 0)
1038 if (likely(!i915.prefault_disable)) {
1039 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1045 intel_runtime_pm_get(dev_priv);
1047 ret = i915_mutex_lock_interruptible(dev);
1051 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1052 if (&obj->base == NULL) {
1057 /* Bounds check destination. */
1058 if (args->offset > obj->base.size ||
1059 args->size > obj->base.size - args->offset) {
1064 /* prime objects have no backing filp to GEM pread/pwrite
1068 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1071 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1072 * it would end up going through the fenced access, and we'll get
1073 * different detiling behavior between reading and writing.
1074 * pread/pwrite currently are reading and writing from the CPU
1075 * perspective, requiring manual detiling by the client.
1077 if (obj->tiling_mode == I915_TILING_NONE &&
1078 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1079 cpu_write_needs_clflush(obj)) {
1080 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1081 /* Note that the gtt paths might fail with non-page-backed user
1082 * pointers (e.g. gtt mappings when moving data between
1083 * textures). Fallback to the shmem path in that case. */
1086 if (ret == -EFAULT || ret == -ENOSPC) {
1087 if (obj->phys_handle)
1088 ret = i915_gem_phys_pwrite(obj, args, file);
1090 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1094 drm_gem_object_unreference(&obj->base);
1096 mutex_unlock(&dev->struct_mutex);
1098 intel_runtime_pm_put(dev_priv);
1104 i915_gem_check_wedge(struct i915_gpu_error *error,
1107 if (i915_reset_in_progress(error)) {
1108 /* Non-interruptible callers can't handle -EAGAIN, hence return
1109 * -EIO unconditionally for these. */
1113 /* Recovery complete, but the reset failed ... */
1114 if (i915_terminally_wedged(error))
1118 * Check if GPU Reset is in progress - we need intel_ring_begin
1119 * to work properly to reinit the hw state while the gpu is
1120 * still marked as reset-in-progress. Handle this with a flag.
1122 if (!error->reload_in_reset)
1129 static void fake_irq(unsigned long data)
1131 wakeup_one((void *)data);
1134 static bool missed_irq(struct drm_i915_private *dev_priv,
1135 struct intel_engine_cs *ring)
1137 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1141 static int __i915_spin_request(struct drm_i915_gem_request *req)
1143 unsigned long timeout;
1145 if (i915_gem_request_get_ring(req)->irq_refcount)
1148 timeout = jiffies + 1;
1149 while (!need_resched()) {
1150 if (i915_gem_request_completed(req, true))
1153 if (time_after_eq(jiffies, timeout))
1156 cpu_relax_lowlatency();
1158 if (i915_gem_request_completed(req, false))
1166 * __i915_wait_request - wait until execution of request has finished
1168 * @reset_counter: reset sequence associated with the given request
1169 * @interruptible: do an interruptible wait (normally yes)
1170 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1172 * Note: It is of utmost importance that the passed in seqno and reset_counter
1173 * values have been read by the caller in an smp safe manner. Where read-side
1174 * locks are involved, it is sufficient to read the reset_counter before
1175 * unlocking the lock that protects the seqno. For lockless tricks, the
1176 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1179 * Returns 0 if the request was found within the alloted time. Else returns the
1180 * errno with remaining time filled in timeout argument.
1182 int __i915_wait_request(struct drm_i915_gem_request *req,
1183 unsigned reset_counter,
1186 struct intel_rps_client *rps)
1188 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1189 struct drm_device *dev = ring->dev;
1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 const bool irq_test_in_progress =
1192 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1193 unsigned long timeout_expire;
1195 int ret, sl_timeout = 1;
1197 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1199 if (list_empty(&req->list))
1202 if (i915_gem_request_completed(req, true))
1205 timeout_expire = timeout ?
1206 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1208 if (INTEL_INFO(dev_priv)->gen >= 6)
1209 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1211 /* Record current time in case interrupted by signal, or wedged */
1212 trace_i915_gem_request_wait_begin(req);
1213 before = ktime_get_raw_ns();
1215 /* Optimistic spin for the next jiffie before touching IRQs */
1217 ret = __i915_spin_request(req);
1222 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1227 lockmgr(&ring->irq_queue.lock, LK_EXCLUSIVE);
1229 struct timer_list timer;
1231 /* We need to check whether any gpu reset happened in between
1232 * the caller grabbing the seqno and now ... */
1233 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1234 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1235 * is truely gone. */
1236 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1242 if (i915_gem_request_completed(req, false)) {
1247 if (interruptible && signal_pending(curthread->td_lwp)) {
1252 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1257 timer.function = NULL;
1258 if (timeout || missed_irq(dev_priv, ring)) {
1259 unsigned long expire;
1261 setup_timer_on_stack(&timer, fake_irq, (unsigned long)&ring->irq_queue);
1262 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1263 sl_timeout = expire - jiffies;
1266 mod_timer(&timer, expire);
1273 if (timer.function) {
1274 del_singleshot_timer_sync(&timer);
1275 destroy_timer_on_stack(&timer);
1278 lksleep(&ring->irq_queue, &ring->irq_queue.lock,
1279 interruptible ? PCATCH : 0, "lwe", sl_timeout);
1281 lockmgr(&ring->irq_queue.lock, LK_RELEASE);
1282 if (!irq_test_in_progress)
1283 ring->irq_put(ring);
1286 now = ktime_get_raw_ns();
1287 trace_i915_gem_request_wait_end(req);
1290 s64 tres = *timeout - (now - before);
1292 *timeout = tres < 0 ? 0 : tres;
1295 * Apparently ktime isn't accurate enough and occasionally has a
1296 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1297 * things up to make the test happy. We allow up to 1 jiffy.
1299 * This is a regrssion from the timespec->ktime conversion.
1301 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1308 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1309 struct drm_file *file)
1311 struct drm_i915_private *dev_private;
1312 struct drm_i915_file_private *file_priv;
1314 WARN_ON(!req || !file || req->file_priv);
1322 dev_private = req->ring->dev->dev_private;
1323 file_priv = file->driver_priv;
1325 spin_lock(&file_priv->mm.lock);
1326 req->file_priv = file_priv;
1327 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1328 spin_unlock(&file_priv->mm.lock);
1330 req->pid = curproc->p_pid;
1336 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1338 struct drm_i915_file_private *file_priv = request->file_priv;
1343 spin_lock(&file_priv->mm.lock);
1344 list_del(&request->client_list);
1345 request->file_priv = NULL;
1346 spin_unlock(&file_priv->mm.lock);
1349 put_pid(request->pid);
1350 request->pid = NULL;
1354 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1356 trace_i915_gem_request_retire(request);
1358 /* We know the GPU must have read the request to have
1359 * sent us the seqno + interrupt, so use the position
1360 * of tail of the request to update the last known position
1363 * Note this requires that we are always called in request
1366 request->ringbuf->last_retired_head = request->postfix;
1368 list_del_init(&request->list);
1369 i915_gem_request_remove_from_client(request);
1371 i915_gem_request_unreference(request);
1375 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1377 struct intel_engine_cs *engine = req->ring;
1378 struct drm_i915_gem_request *tmp;
1380 lockdep_assert_held(&engine->dev->struct_mutex);
1382 if (list_empty(&req->list))
1386 tmp = list_first_entry(&engine->request_list,
1387 typeof(*tmp), list);
1389 i915_gem_request_retire(tmp);
1390 } while (tmp != req);
1392 WARN_ON(i915_verify_lists(engine->dev));
1396 * Waits for a request to be signaled, and cleans up the
1397 * request and object lists appropriately for that event.
1400 i915_wait_request(struct drm_i915_gem_request *req)
1402 struct drm_device *dev;
1403 struct drm_i915_private *dev_priv;
1407 BUG_ON(req == NULL);
1409 dev = req->ring->dev;
1410 dev_priv = dev->dev_private;
1411 interruptible = dev_priv->mm.interruptible;
1413 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1415 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1419 ret = __i915_wait_request(req,
1420 atomic_read(&dev_priv->gpu_error.reset_counter),
1421 interruptible, NULL, NULL);
1425 __i915_gem_request_retire__upto(req);
1430 * Ensures that all rendering to the object has completed and the object is
1431 * safe to unbind from the GTT or access from the CPU.
1434 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1443 if (obj->last_write_req != NULL) {
1444 ret = i915_wait_request(obj->last_write_req);
1448 i = obj->last_write_req->ring->id;
1449 if (obj->last_read_req[i] == obj->last_write_req)
1450 i915_gem_object_retire__read(obj, i);
1452 i915_gem_object_retire__write(obj);
1455 for (i = 0; i < I915_NUM_RINGS; i++) {
1456 if (obj->last_read_req[i] == NULL)
1459 ret = i915_wait_request(obj->last_read_req[i]);
1463 i915_gem_object_retire__read(obj, i);
1465 RQ_BUG_ON(obj->active);
1472 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1473 struct drm_i915_gem_request *req)
1475 int ring = req->ring->id;
1477 if (obj->last_read_req[ring] == req)
1478 i915_gem_object_retire__read(obj, ring);
1479 else if (obj->last_write_req == req)
1480 i915_gem_object_retire__write(obj);
1482 __i915_gem_request_retire__upto(req);
1485 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1486 * as the object state may change during this call.
1488 static __must_check int
1489 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1490 struct intel_rps_client *rps,
1493 struct drm_device *dev = obj->base.dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1496 unsigned reset_counter;
1499 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1500 BUG_ON(!dev_priv->mm.interruptible);
1505 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1509 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1512 struct drm_i915_gem_request *req;
1514 req = obj->last_write_req;
1518 requests[n++] = i915_gem_request_reference(req);
1520 for (i = 0; i < I915_NUM_RINGS; i++) {
1521 struct drm_i915_gem_request *req;
1523 req = obj->last_read_req[i];
1527 requests[n++] = i915_gem_request_reference(req);
1531 mutex_unlock(&dev->struct_mutex);
1532 for (i = 0; ret == 0 && i < n; i++)
1533 ret = __i915_wait_request(requests[i], reset_counter, true,
1535 mutex_lock(&dev->struct_mutex);
1537 for (i = 0; i < n; i++) {
1539 i915_gem_object_retire_request(obj, requests[i]);
1540 i915_gem_request_unreference(requests[i]);
1546 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1548 struct drm_i915_file_private *fpriv = file->driver_priv;
1553 * Called when user space prepares to use an object with the CPU, either
1554 * through the mmap ioctl's mapping or a GTT mapping.
1557 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1558 struct drm_file *file)
1560 struct drm_i915_gem_set_domain *args = data;
1561 struct drm_i915_gem_object *obj;
1562 uint32_t read_domains = args->read_domains;
1563 uint32_t write_domain = args->write_domain;
1566 /* Only handle setting domains to types used by the CPU. */
1567 if (write_domain & I915_GEM_GPU_DOMAINS)
1570 if (read_domains & I915_GEM_GPU_DOMAINS)
1573 /* Having something in the write domain implies it's in the read
1574 * domain, and only that read domain. Enforce that in the request.
1576 if (write_domain != 0 && read_domains != write_domain)
1579 ret = i915_mutex_lock_interruptible(dev);
1583 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1584 if (&obj->base == NULL) {
1589 /* Try to flush the object off the GPU without holding the lock.
1590 * We will repeat the flush holding the lock in the normal manner
1591 * to catch cases where we are gazumped.
1593 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1594 to_rps_client(file),
1599 if (read_domains & I915_GEM_DOMAIN_GTT)
1600 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1602 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1604 if (write_domain != 0)
1605 intel_fb_obj_invalidate(obj,
1606 write_domain == I915_GEM_DOMAIN_GTT ?
1607 ORIGIN_GTT : ORIGIN_CPU);
1610 drm_gem_object_unreference(&obj->base);
1612 mutex_unlock(&dev->struct_mutex);
1617 * Called when user space has done writes to this buffer
1620 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1621 struct drm_file *file)
1623 struct drm_i915_gem_sw_finish *args = data;
1624 struct drm_i915_gem_object *obj;
1627 ret = i915_mutex_lock_interruptible(dev);
1631 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1632 if (&obj->base == NULL) {
1637 /* Pinned buffers may be scanout, so flush the cache */
1638 if (obj->pin_display)
1639 i915_gem_object_flush_cpu_write_domain(obj);
1641 drm_gem_object_unreference(&obj->base);
1643 mutex_unlock(&dev->struct_mutex);
1648 * Maps the contents of an object, returning the address it is mapped
1651 * While the mapping holds a reference on the contents of the object, it doesn't
1652 * imply a ref on the object itself.
1656 * DRM driver writers who look a this function as an example for how to do GEM
1657 * mmap support, please don't implement mmap support like here. The modern way
1658 * to implement DRM mmap support is with an mmap offset ioctl (like
1659 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1660 * That way debug tooling like valgrind will understand what's going on, hiding
1661 * the mmap call in a driver private ioctl will break that. The i915 driver only
1662 * does cpu mmaps this way because we didn't know better.
1665 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1666 struct drm_file *file)
1668 struct drm_i915_gem_mmap *args = data;
1669 struct drm_gem_object *obj;
1672 struct proc *p = curproc;
1673 vm_map_t map = &p->p_vmspace->vm_map;
1677 if (args->flags & ~(I915_MMAP_WC))
1680 obj = drm_gem_object_lookup(dev, file, args->handle);
1684 if (args->size == 0)
1687 size = round_page(args->size);
1688 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1693 /* prime objects have no backing filp to GEM mmap
1698 * Call hint to ensure that NULL is not returned as a valid address
1699 * and to reduce vm_map traversals. XXX causes instability, use a
1700 * fixed low address as the start point instead to avoid the NULL
1707 * Use 256KB alignment. It is unclear why this matters for a
1708 * virtual address but it appears to fix a number of application/X
1709 * crashes and kms console switching is much faster.
1711 vm_object_hold(obj->vm_obj);
1712 vm_object_reference_locked(obj->vm_obj);
1713 vm_object_drop(obj->vm_obj);
1715 rv = vm_map_find(map, obj->vm_obj, NULL,
1716 args->offset, &addr, args->size,
1717 256 * 1024, /* align */
1719 VM_MAPTYPE_NORMAL, /* maptype */
1720 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1721 VM_PROT_READ | VM_PROT_WRITE, /* max */
1722 MAP_SHARED /* cow */);
1723 if (rv != KERN_SUCCESS) {
1724 vm_object_deallocate(obj->vm_obj);
1725 error = -vm_mmap_to_errno(rv);
1727 args->addr_ptr = (uint64_t)addr;
1730 drm_gem_object_unreference(obj);
1735 * i915_gem_fault - fault a page into the GTT
1737 * vm_obj is locked on entry and expected to be locked on return.
1739 * The vm_pager has placemarked the object with an anonymous memory page
1740 * which we must replace atomically to avoid races against concurrent faults
1741 * on the same page. XXX we currently are unable to do this atomically.
1743 * If we are to return an error we should not touch the anonymous page,
1744 * the caller will deallocate it.
1746 * XXX Most GEM calls appear to be interruptable, but we can't hard loop
1747 * in that case. Release all resources and wait 1 tick before retrying.
1748 * This is a huge problem which needs to be fixed by getting rid of most
1749 * of the interruptability. The linux code does not retry but does appear
1750 * to have some sort of mechanism (VM_FAULT_NOPAGE ?) for the higher level
1751 * to be able to retry.
1754 * vma: VMA in question
1757 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1758 * from userspace. The fault handler takes care of binding the object to
1759 * the GTT (if needed), allocating and programming a fence register (again,
1760 * only if needed based on whether the old reg is still valid or the object
1761 * is tiled) and inserting a new PTE into the faulting process.
1763 * Note that the faulting process may involve evicting existing objects
1764 * from the GTT and/or fence registers to make room. So performance may
1765 * suffer if the GTT working set is large or there are few fence registers
1768 * vm_obj is locked on entry and expected to be locked on return. The VM
1769 * pager has placed an anonymous memory page at (obj,offset) which we have
1772 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres)
1774 struct drm_i915_gem_object *obj = to_intel_bo(vm_obj->handle);
1775 struct drm_device *dev = obj->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct i915_ggtt_view view = i915_ggtt_view_normal;
1778 unsigned long page_offset;
1779 vm_page_t m, oldm = NULL;
1781 bool write = !!(prot & VM_PROT_WRITE);
1783 intel_runtime_pm_get(dev_priv);
1785 /* We don't use vmf->pgoff since that has the fake offset */
1786 page_offset = (unsigned long)offset;
1789 ret = i915_mutex_lock_interruptible(dev);
1793 trace_i915_gem_object_fault(obj, page_offset, true, write);
1795 /* Try to flush the object off the GPU first without holding the lock.
1796 * Upon reacquiring the lock, we will perform our sanity checks and then
1797 * repeat the flush holding the lock in the normal manner to catch cases
1798 * where we are gazumped.
1800 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1804 /* Access to snoopable pages through the GTT is incoherent. */
1805 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1810 /* Use a partial view if the object is bigger than the aperture. */
1811 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1812 obj->tiling_mode == I915_TILING_NONE) {
1814 static const unsigned int chunk_size = 256; // 1 MiB
1816 memset(&view, 0, sizeof(view));
1817 view.type = I915_GGTT_VIEW_PARTIAL;
1818 view.params.partial.offset = rounddown(page_offset, chunk_size);
1819 view.params.partial.size =
1822 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1823 view.params.partial.offset);
1827 /* Now pin it into the GTT if needed */
1828 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1832 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1836 ret = i915_gem_object_get_fence(obj);
1841 * START FREEBSD MAGIC
1843 * Add a pip count to avoid destruction and certain other
1844 * complex operations (such as collapses?) while unlocked.
1846 vm_object_pip_add(vm_obj, 1);
1849 * XXX We must currently remove the placeholder page now to avoid
1850 * a deadlock against a concurrent i915_gem_release_mmap().
1851 * Otherwise concurrent operation will block on the busy page
1852 * while holding locks which we need to obtain.
1854 if (*mres != NULL) {
1856 if ((oldm->flags & PG_BUSY) == 0)
1857 kprintf("i915_gem_fault: Page was not busy\n");
1859 vm_page_remove(oldm);
1869 * Since the object lock was dropped, another thread might have
1870 * faulted on the same GTT address and instantiated the mapping.
1873 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1876 * Try to busy the page, retry on failure (non-zero ret).
1878 if (vm_page_busy_try(m, false)) {
1879 kprintf("i915_gem_fault: PG_BUSY\n");
1889 obj->fault_mappable = true;
1891 /* Finally, remap it using the new GTT offset */
1892 m = vm_phys_fictitious_to_vm_page(dev_priv->gtt.mappable_base +
1893 i915_gem_obj_ggtt_offset_view(obj, &view) + offset);
1898 KASSERT((m->flags & PG_FICTITIOUS) != 0, ("not fictitious %p", m));
1899 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1902 * Try to busy the page. Fails on non-zero return.
1904 if (vm_page_busy_try(m, false)) {
1905 kprintf("i915_gem_fault: PG_BUSY(2)\n");
1909 m->valid = VM_PAGE_BITS_ALL;
1912 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1913 /* Overriding existing pages in partial view does not cause
1914 * us any trouble as TLBs are still valid because the fault
1915 * is due to userspace losing part of the mapping or never
1916 * having accessed it before (at this partials' range).
1918 unsigned long base = vma->vm_start +
1919 (view.params.partial.offset << PAGE_SHIFT);
1922 for (i = 0; i < view.params.partial.size; i++) {
1923 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1928 obj->fault_mappable = true;
1930 if (!obj->fault_mappable) {
1931 unsigned long size = min_t(unsigned long,
1932 vma->vm_end - vma->vm_start,
1936 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1937 ret = vm_insert_pfn(vma,
1938 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1944 obj->fault_mappable = true;
1946 ret = vm_insert_pfn(vma,
1947 (unsigned long)vmf->virtual_address,
1950 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1958 i915_gem_object_ggtt_unpin_view(obj, &view);
1959 mutex_unlock(&dev->struct_mutex);
1964 * ALTERNATIVE ERROR RETURN.
1966 * OBJECT EXPECTED TO BE LOCKED.
1969 i915_gem_object_ggtt_unpin_view(obj, &view);
1971 mutex_unlock(&dev->struct_mutex);
1976 * We eat errors when the gpu is terminally wedged to avoid
1977 * userspace unduly crashing (gl has no provisions for mmaps to
1978 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1979 * and so needs to be reported.
1981 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1982 // ret = VM_FAULT_SIGBUS;
1987 * EAGAIN means the gpu is hung and we'll wait for the error
1988 * handler to reset everything when re-faulting in
1989 * i915_mutex_lock_interruptible.
1993 VM_OBJECT_UNLOCK(vm_obj);
1995 tsleep(&dummy, 0, "delay", 1); /* XXX */
1996 VM_OBJECT_LOCK(vm_obj);
1999 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2000 ret = VM_PAGER_ERROR;
2007 vm_object_pip_wakeup(vm_obj);
2009 intel_runtime_pm_put(dev_priv);
2014 * i915_gem_release_mmap - remove physical page mappings
2015 * @obj: obj in question
2017 * Preserve the reservation of the mmapping with the DRM core code, but
2018 * relinquish ownership of the pages back to the system.
2020 * It is vital that we remove the page mapping if we have mapped a tiled
2021 * object through the GTT and then lose the fence register due to
2022 * resource pressure. Similarly if the object has been moved out of the
2023 * aperture, than pages mapped into userspace must be revoked. Removing the
2024 * mapping will then trigger a page fault on the next user access, allowing
2025 * fixup by i915_gem_fault().
2028 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2034 if (!obj->fault_mappable)
2037 devobj = cdev_pager_lookup(obj);
2038 if (devobj != NULL) {
2039 page_count = OFF_TO_IDX(obj->base.size);
2041 VM_OBJECT_LOCK(devobj);
2042 for (i = 0; i < page_count; i++) {
2043 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
2046 cdev_pager_free_page(devobj, m);
2048 VM_OBJECT_UNLOCK(devobj);
2049 vm_object_deallocate(devobj);
2052 obj->fault_mappable = false;
2056 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
2058 struct drm_i915_gem_object *obj;
2060 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
2061 i915_gem_release_mmap(obj);
2065 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
2069 if (INTEL_INFO(dev)->gen >= 4 ||
2070 tiling_mode == I915_TILING_NONE)
2073 /* Previous chips need a power-of-two fence region when tiling */
2074 if (INTEL_INFO(dev)->gen == 3)
2075 gtt_size = 1024*1024;
2077 gtt_size = 512*1024;
2079 while (gtt_size < size)
2086 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2087 * @obj: object to check
2089 * Return the required GTT alignment for an object, taking into account
2090 * potential fence register mapping.
2093 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2094 int tiling_mode, bool fenced)
2097 * Minimum alignment is 4k (GTT page size), but might be greater
2098 * if a fence register is needed for the object.
2100 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2101 tiling_mode == I915_TILING_NONE)
2105 * Previous chips need to be aligned to the size of the smallest
2106 * fence register that can contain the object.
2108 return i915_gem_get_gtt_size(dev, size, tiling_mode);
2111 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2113 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2117 if (drm_vma_node_has_offset(&obj->base.vma_node))
2121 dev_priv->mm.shrinker_no_lock_stealing = true;
2123 ret = drm_gem_create_mmap_offset(&obj->base);
2127 /* Badly fragmented mmap space? The only way we can recover
2128 * space is by destroying unwanted objects. We can't randomly release
2129 * mmap_offsets as userspace expects them to be persistent for the
2130 * lifetime of the objects. The closest we can is to release the
2131 * offsets on purgeable objects by truncating it and marking it purged,
2132 * which prevents userspace from ever using that object again.
2134 i915_gem_shrink(dev_priv,
2135 obj->base.size >> PAGE_SHIFT,
2137 I915_SHRINK_UNBOUND |
2138 I915_SHRINK_PURGEABLE);
2139 ret = drm_gem_create_mmap_offset(&obj->base);
2143 i915_gem_shrink_all(dev_priv);
2144 ret = drm_gem_create_mmap_offset(&obj->base);
2146 dev_priv->mm.shrinker_no_lock_stealing = false;
2151 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2153 drm_gem_free_mmap_offset(&obj->base);
2157 i915_gem_mmap_gtt(struct drm_file *file,
2158 struct drm_device *dev,
2162 struct drm_i915_gem_object *obj;
2165 ret = i915_mutex_lock_interruptible(dev);
2169 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2170 if (&obj->base == NULL) {
2175 if (obj->madv != I915_MADV_WILLNEED) {
2176 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2181 ret = i915_gem_object_create_mmap_offset(obj);
2185 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
2186 DRM_GEM_MAPPING_KEY;
2189 drm_gem_object_unreference(&obj->base);
2191 mutex_unlock(&dev->struct_mutex);
2196 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2198 * @data: GTT mapping ioctl data
2199 * @file: GEM object info
2201 * Simply returns the fake offset to userspace so it can mmap it.
2202 * The mmap call will end up in drm_gem_mmap(), which will set things
2203 * up so we can get faults in the handler above.
2205 * The fault handler will take care of binding the object into the GTT
2206 * (since it may have been evicted to make room for something), allocating
2207 * a fence register, and mapping the appropriate aperture address into
2211 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2212 struct drm_file *file)
2214 struct drm_i915_gem_mmap_gtt *args = data;
2216 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2219 /* Immediately discard the backing storage */
2221 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2225 vm_obj = obj->base.vm_obj;
2226 VM_OBJECT_LOCK(vm_obj);
2227 vm_object_page_remove(vm_obj, 0, 0, false);
2228 VM_OBJECT_UNLOCK(vm_obj);
2230 obj->madv = __I915_MADV_PURGED;
2233 /* Try to discard unwanted pages */
2235 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2238 struct address_space *mapping;
2241 switch (obj->madv) {
2242 case I915_MADV_DONTNEED:
2243 i915_gem_object_truncate(obj);
2244 case __I915_MADV_PURGED:
2249 if (obj->base.filp == NULL)
2252 mapping = file_inode(obj->base.filp)->i_mapping,
2253 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2258 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2260 struct sg_page_iter sg_iter;
2263 BUG_ON(obj->madv == __I915_MADV_PURGED);
2265 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2267 /* In the event of a disaster, abandon all caches and
2268 * hope for the best.
2270 WARN_ON(ret != -EIO);
2271 i915_gem_clflush_object(obj, true);
2272 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2275 i915_gem_gtt_finish_object(obj);
2277 if (i915_gem_object_needs_bit17_swizzle(obj))
2278 i915_gem_object_save_bit_17_swizzle(obj);
2280 if (obj->madv == I915_MADV_DONTNEED)
2283 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2284 struct vm_page *page = sg_page_iter_page(&sg_iter);
2287 set_page_dirty(page);
2289 if (obj->madv == I915_MADV_WILLNEED)
2290 mark_page_accessed(page);
2292 vm_page_busy_wait(page, FALSE, "i915gem");
2293 vm_page_unwire(page, 1);
2294 vm_page_wakeup(page);
2298 sg_free_table(obj->pages);
2303 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2305 const struct drm_i915_gem_object_ops *ops = obj->ops;
2307 if (obj->pages == NULL)
2310 if (obj->pages_pin_count)
2313 BUG_ON(i915_gem_obj_bound_any(obj));
2315 /* ->put_pages might need to allocate memory for the bit17 swizzle
2316 * array, hence protect them from being reaped by removing them from gtt
2318 list_del(&obj->global_list);
2320 ops->put_pages(obj);
2323 i915_gem_object_invalidate(obj);
2329 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2331 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2334 struct sg_table *st;
2335 struct scatterlist *sg;
2336 struct sg_page_iter sg_iter;
2337 struct vm_page *page;
2338 unsigned long last_pfn = 0; /* suppress gcc warning */
2341 /* Assert that the object is not currently in any GPU domain. As it
2342 * wasn't in the GTT, there shouldn't be any way it could have been in
2345 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2346 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2348 st = kmalloc(sizeof(*st), M_DRM, M_WAITOK);
2352 page_count = obj->base.size / PAGE_SIZE;
2353 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2358 /* Get the list of pages out of our struct file. They'll be pinned
2359 * at this point until we release them.
2361 * Fail silently without starting the shrinker
2363 vm_obj = obj->base.vm_obj;
2364 VM_OBJECT_LOCK(vm_obj);
2367 for (i = 0; i < page_count; i++) {
2368 page = shmem_read_mapping_page(vm_obj, i);
2370 i915_gem_shrink(dev_priv,
2373 I915_SHRINK_UNBOUND |
2374 I915_SHRINK_PURGEABLE);
2375 page = shmem_read_mapping_page(vm_obj, i);
2378 /* We've tried hard to allocate the memory by reaping
2379 * our own buffer, now let the real VM do its job and
2380 * go down in flames if truly OOM.
2382 i915_gem_shrink_all(dev_priv);
2383 page = shmem_read_mapping_page(vm_obj, i);
2385 ret = PTR_ERR(page);
2389 #ifdef CONFIG_SWIOTLB
2390 if (swiotlb_nr_tbl()) {
2392 sg_set_page(sg, page, PAGE_SIZE, 0);
2397 if (!i || page_to_pfn(page) != last_pfn + 1) {
2401 sg_set_page(sg, page, PAGE_SIZE, 0);
2403 sg->length += PAGE_SIZE;
2405 last_pfn = page_to_pfn(page);
2407 /* Check that the i965g/gm workaround works. */
2409 #ifdef CONFIG_SWIOTLB
2410 if (!swiotlb_nr_tbl())
2414 VM_OBJECT_UNLOCK(vm_obj);
2416 ret = i915_gem_gtt_prepare_object(obj);
2420 if (i915_gem_object_needs_bit17_swizzle(obj))
2421 i915_gem_object_do_bit_17_swizzle(obj);
2423 if (obj->tiling_mode != I915_TILING_NONE &&
2424 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2425 i915_gem_object_pin_pages(obj);
2431 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2432 page = sg_page_iter_page(&sg_iter);
2433 vm_page_busy_wait(page, FALSE, "i915gem");
2434 vm_page_unwire(page, 0);
2435 vm_page_wakeup(page);
2437 VM_OBJECT_UNLOCK(vm_obj);
2441 /* shmemfs first checks if there is enough memory to allocate the page
2442 * and reports ENOSPC should there be insufficient, along with the usual
2443 * ENOMEM for a genuine allocation failure.
2445 * We use ENOSPC in our driver to mean that we have run out of aperture
2446 * space and so want to translate the error from shmemfs back to our
2447 * usual understanding of ENOMEM.
2455 /* Ensure that the associated pages are gathered from the backing storage
2456 * and pinned into our object. i915_gem_object_get_pages() may be called
2457 * multiple times before they are released by a single call to
2458 * i915_gem_object_put_pages() - once the pages are no longer referenced
2459 * either as a result of memory pressure (reaping pages under the shrinker)
2460 * or as the object is itself released.
2463 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2465 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2466 const struct drm_i915_gem_object_ops *ops = obj->ops;
2472 if (obj->madv != I915_MADV_WILLNEED) {
2473 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2477 BUG_ON(obj->pages_pin_count);
2479 ret = ops->get_pages(obj);
2483 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2485 obj->get_page.sg = obj->pages->sgl;
2486 obj->get_page.last = 0;
2491 void i915_vma_move_to_active(struct i915_vma *vma,
2492 struct drm_i915_gem_request *req)
2494 struct drm_i915_gem_object *obj = vma->obj;
2495 struct intel_engine_cs *ring;
2497 ring = i915_gem_request_get_ring(req);
2499 /* Add a reference if we're newly entering the active list. */
2500 if (obj->active == 0)
2501 drm_gem_object_reference(&obj->base);
2502 obj->active |= intel_ring_flag(ring);
2504 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2505 i915_gem_request_assign(&obj->last_read_req[ring->id], req);
2507 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2511 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2513 RQ_BUG_ON(obj->last_write_req == NULL);
2514 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2516 i915_gem_request_assign(&obj->last_write_req, NULL);
2517 intel_fb_obj_flush(obj, true, ORIGIN_CS);
2521 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2523 struct i915_vma *vma;
2525 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2526 RQ_BUG_ON(!(obj->active & (1 << ring)));
2528 list_del_init(&obj->ring_list[ring]);
2529 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2531 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2532 i915_gem_object_retire__write(obj);
2534 obj->active &= ~(1 << ring);
2538 /* Bump our place on the bound list to keep it roughly in LRU order
2539 * so that we don't steal from recently used but inactive objects
2540 * (unless we are forced to ofc!)
2542 list_move_tail(&obj->global_list,
2543 &to_i915(obj->base.dev)->mm.bound_list);
2545 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2546 if (!list_empty(&vma->mm_list))
2547 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2550 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2551 drm_gem_object_unreference(&obj->base);
2555 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_engine_cs *ring;
2561 /* Carefully retire all requests without writing to the rings */
2562 for_each_ring(ring, dev_priv, i) {
2563 ret = intel_ring_idle(ring);
2567 i915_gem_retire_requests(dev);
2569 /* Finally reset hw state */
2570 for_each_ring(ring, dev_priv, i) {
2571 intel_ring_init_seqno(ring, seqno);
2573 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2574 ring->semaphore.sync_seqno[j] = 0;
2580 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2588 /* HWS page needs to be set less than what we
2589 * will inject to ring
2591 ret = i915_gem_init_seqno(dev, seqno - 1);
2595 /* Carefully set the last_seqno value so that wrap
2596 * detection still works
2598 dev_priv->next_seqno = seqno;
2599 dev_priv->last_seqno = seqno - 1;
2600 if (dev_priv->last_seqno == 0)
2601 dev_priv->last_seqno--;
2607 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2611 /* reserve 0 for non-seqno */
2612 if (dev_priv->next_seqno == 0) {
2613 int ret = i915_gem_init_seqno(dev, 0);
2617 dev_priv->next_seqno = 1;
2620 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2625 * NB: This function is not allowed to fail. Doing so would mean the the
2626 * request is not being tracked for completion but the work itself is
2627 * going to happen on the hardware. This would be a Bad Thing(tm).
2629 void __i915_add_request(struct drm_i915_gem_request *request,
2630 struct drm_i915_gem_object *obj,
2633 struct intel_engine_cs *ring;
2634 struct drm_i915_private *dev_priv;
2635 struct intel_ringbuffer *ringbuf;
2639 if (WARN_ON(request == NULL))
2642 ring = request->ring;
2643 dev_priv = ring->dev->dev_private;
2644 ringbuf = request->ringbuf;
2647 * To ensure that this call will not fail, space for its emissions
2648 * should already have been reserved in the ring buffer. Let the ring
2649 * know that it is time to use that space up.
2651 intel_ring_reserved_space_use(ringbuf);
2653 request_start = intel_ring_get_tail(ringbuf);
2655 * Emit any outstanding flushes - execbuf can fail to emit the flush
2656 * after having emitted the batchbuffer command. Hence we need to fix
2657 * things up similar to emitting the lazy request. The difference here
2658 * is that the flush _must_ happen before the next request, no matter
2662 if (i915.enable_execlists)
2663 ret = logical_ring_flush_all_caches(request);
2665 ret = intel_ring_flush_all_caches(request);
2666 /* Not allowed to fail! */
2667 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2670 /* Record the position of the start of the request so that
2671 * should we detect the updated seqno part-way through the
2672 * GPU processing the request, we never over-estimate the
2673 * position of the head.
2675 request->postfix = intel_ring_get_tail(ringbuf);
2677 if (i915.enable_execlists)
2678 ret = ring->emit_request(request);
2680 ret = ring->add_request(request);
2682 request->tail = intel_ring_get_tail(ringbuf);
2685 /* Not allowed to fail! */
2686 WARN(ret, "emit|add_request failed: %d!\n", ret);
2688 request->head = request_start;
2690 /* Whilst this request exists, batch_obj will be on the
2691 * active_list, and so will hold the active reference. Only when this
2692 * request is retired will the the batch_obj be moved onto the
2693 * inactive_list and lose its active reference. Hence we do not need
2694 * to explicitly hold another reference here.
2696 request->batch_obj = obj;
2698 request->emitted_jiffies = jiffies;
2699 list_add_tail(&request->list, &ring->request_list);
2701 trace_i915_gem_request_add(request);
2703 i915_queue_hangcheck(ring->dev);
2705 queue_delayed_work(dev_priv->wq,
2706 &dev_priv->mm.retire_work,
2707 round_jiffies_up_relative(HZ));
2708 intel_mark_busy(dev_priv->dev);
2710 /* Sanity check that the reserved size was large enough. */
2711 intel_ring_reserved_space_end(ringbuf);
2714 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2715 const struct intel_context *ctx)
2717 unsigned long elapsed;
2719 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2721 if (ctx->hang_stats.banned)
2724 if (ctx->hang_stats.ban_period_seconds &&
2725 elapsed <= ctx->hang_stats.ban_period_seconds) {
2726 if (!i915_gem_context_is_default(ctx)) {
2727 DRM_DEBUG("context hanging too fast, banning!\n");
2729 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2730 if (i915_stop_ring_allow_warn(dev_priv))
2731 DRM_ERROR("gpu hanging too fast, banning!\n");
2739 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2740 struct intel_context *ctx,
2743 struct i915_ctx_hang_stats *hs;
2748 hs = &ctx->hang_stats;
2751 hs->banned = i915_context_is_banned(dev_priv, ctx);
2753 hs->guilty_ts = get_seconds();
2755 hs->batch_pending++;
2759 void i915_gem_request_free(struct kref *req_ref)
2761 struct drm_i915_gem_request *req = container_of(req_ref,
2763 struct intel_context *ctx = req->ctx;
2766 i915_gem_request_remove_from_client(req);
2769 if (i915.enable_execlists) {
2770 if (ctx != req->ring->default_context)
2771 intel_lr_context_unpin(req);
2774 i915_gem_context_unreference(ctx);
2780 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2781 struct intel_context *ctx,
2782 struct drm_i915_gem_request **req_out)
2784 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2785 struct drm_i915_gem_request *req;
2793 req = kzalloc(sizeof(*req), GFP_KERNEL);
2797 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2801 kref_init(&req->ref);
2802 req->i915 = dev_priv;
2805 i915_gem_context_reference(req->ctx);
2807 if (i915.enable_execlists)
2808 ret = intel_logical_ring_alloc_request_extras(req);
2810 ret = intel_ring_alloc_request_extras(req);
2812 i915_gem_context_unreference(req->ctx);
2817 * Reserve space in the ring buffer for all the commands required to
2818 * eventually emit this request. This is to guarantee that the
2819 * i915_add_request() call can't fail. Note that the reserve may need
2820 * to be redone if the request is not actually submitted straight
2821 * away, e.g. because a GPU scheduler has deferred it.
2823 if (i915.enable_execlists)
2824 ret = intel_logical_ring_reserve_space(req);
2826 ret = intel_ring_reserve_space(req);
2829 * At this point, the request is fully allocated even if not
2830 * fully prepared. Thus it can be cleaned up using the proper
2833 i915_gem_request_cancel(req);
2845 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2847 intel_ring_reserved_space_cancel(req->ringbuf);
2849 i915_gem_request_unreference(req);
2852 struct drm_i915_gem_request *
2853 i915_gem_find_active_request(struct intel_engine_cs *ring)
2855 struct drm_i915_gem_request *request;
2857 list_for_each_entry(request, &ring->request_list, list) {
2858 if (i915_gem_request_completed(request, false))
2867 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2868 struct intel_engine_cs *ring)
2870 struct drm_i915_gem_request *request;
2873 request = i915_gem_find_active_request(ring);
2875 if (request == NULL)
2878 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2880 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2882 list_for_each_entry_continue(request, &ring->request_list, list)
2883 i915_set_reset_status(dev_priv, request->ctx, false);
2886 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2887 struct intel_engine_cs *ring)
2889 while (!list_empty(&ring->active_list)) {
2890 struct drm_i915_gem_object *obj;
2892 obj = list_first_entry(&ring->active_list,
2893 struct drm_i915_gem_object,
2894 ring_list[ring->id]);
2896 i915_gem_object_retire__read(obj, ring->id);
2900 * Clear the execlists queue up before freeing the requests, as those
2901 * are the ones that keep the context and ringbuffer backing objects
2904 while (!list_empty(&ring->execlist_queue)) {
2905 struct drm_i915_gem_request *submit_req;
2907 submit_req = list_first_entry(&ring->execlist_queue,
2908 struct drm_i915_gem_request,
2910 list_del(&submit_req->execlist_link);
2912 if (submit_req->ctx != ring->default_context)
2913 intel_lr_context_unpin(submit_req);
2915 i915_gem_request_unreference(submit_req);
2919 * We must free the requests after all the corresponding objects have
2920 * been moved off active lists. Which is the same order as the normal
2921 * retire_requests function does. This is important if object hold
2922 * implicit references on things like e.g. ppgtt address spaces through
2925 while (!list_empty(&ring->request_list)) {
2926 struct drm_i915_gem_request *request;
2928 request = list_first_entry(&ring->request_list,
2929 struct drm_i915_gem_request,
2932 i915_gem_request_retire(request);
2936 void i915_gem_reset(struct drm_device *dev)
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct intel_engine_cs *ring;
2943 * Before we free the objects from the requests, we need to inspect
2944 * them for finding the guilty party. As the requests only borrow
2945 * their reference to the objects, the inspection must be done first.
2947 for_each_ring(ring, dev_priv, i)
2948 i915_gem_reset_ring_status(dev_priv, ring);
2950 for_each_ring(ring, dev_priv, i)
2951 i915_gem_reset_ring_cleanup(dev_priv, ring);
2953 i915_gem_context_reset(dev);
2955 i915_gem_restore_fences(dev);
2957 WARN_ON(i915_verify_lists(dev));
2961 * This function clears the request list as sequence numbers are passed.
2964 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2966 WARN_ON(i915_verify_lists(ring->dev));
2968 /* Retire requests first as we use it above for the early return.
2969 * If we retire requests last, we may use a later seqno and so clear
2970 * the requests lists without clearing the active list, leading to
2973 while (!list_empty(&ring->request_list)) {
2974 struct drm_i915_gem_request *request;
2976 request = list_first_entry(&ring->request_list,
2977 struct drm_i915_gem_request,
2980 if (!i915_gem_request_completed(request, true))
2983 i915_gem_request_retire(request);
2986 /* Move any buffers on the active list that are no longer referenced
2987 * by the ringbuffer to the flushing/inactive lists as appropriate,
2988 * before we free the context associated with the requests.
2990 while (!list_empty(&ring->active_list)) {
2991 struct drm_i915_gem_object *obj;
2993 obj = list_first_entry(&ring->active_list,
2994 struct drm_i915_gem_object,
2995 ring_list[ring->id]);
2997 if (!list_empty(&obj->last_read_req[ring->id]->list))
3000 i915_gem_object_retire__read(obj, ring->id);
3003 if (unlikely(ring->trace_irq_req &&
3004 i915_gem_request_completed(ring->trace_irq_req, true))) {
3005 ring->irq_put(ring);
3006 i915_gem_request_assign(&ring->trace_irq_req, NULL);
3009 WARN_ON(i915_verify_lists(ring->dev));
3013 i915_gem_retire_requests(struct drm_device *dev)
3015 struct drm_i915_private *dev_priv = dev->dev_private;
3016 struct intel_engine_cs *ring;
3020 for_each_ring(ring, dev_priv, i) {
3021 i915_gem_retire_requests_ring(ring);
3022 idle &= list_empty(&ring->request_list);
3023 if (i915.enable_execlists) {
3025 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
3026 idle &= list_empty(&ring->execlist_queue);
3027 lockmgr(&ring->execlist_lock, LK_RELEASE);
3029 intel_execlists_retire_requests(ring);
3034 mod_delayed_work(dev_priv->wq,
3035 &dev_priv->mm.idle_work,
3036 msecs_to_jiffies(100));
3042 i915_gem_retire_work_handler(struct work_struct *work)
3044 struct drm_i915_private *dev_priv =
3045 container_of(work, typeof(*dev_priv), mm.retire_work.work);
3046 struct drm_device *dev = dev_priv->dev;
3049 /* Come back later if the device is busy... */
3051 if (mutex_trylock(&dev->struct_mutex)) {
3052 idle = i915_gem_retire_requests(dev);
3053 mutex_unlock(&dev->struct_mutex);
3056 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3057 round_jiffies_up_relative(HZ));
3061 i915_gem_idle_work_handler(struct work_struct *work)
3063 struct drm_i915_private *dev_priv =
3064 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3065 struct drm_device *dev = dev_priv->dev;
3066 struct intel_engine_cs *ring;
3069 for_each_ring(ring, dev_priv, i)
3070 if (!list_empty(&ring->request_list))
3073 intel_mark_idle(dev);
3075 if (mutex_trylock(&dev->struct_mutex)) {
3076 struct intel_engine_cs *ring;
3079 for_each_ring(ring, dev_priv, i)
3080 i915_gem_batch_pool_fini(&ring->batch_pool);
3082 mutex_unlock(&dev->struct_mutex);
3087 * Ensures that an object will eventually get non-busy by flushing any required
3088 * write domains, emitting any outstanding lazy request and retiring and
3089 * completed requests.
3092 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3099 for (i = 0; i < I915_NUM_RINGS; i++) {
3100 struct drm_i915_gem_request *req;
3102 req = obj->last_read_req[i];
3106 if (list_empty(&req->list))
3109 if (i915_gem_request_completed(req, true)) {
3110 __i915_gem_request_retire__upto(req);
3112 i915_gem_object_retire__read(obj, i);
3120 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3121 * @DRM_IOCTL_ARGS: standard ioctl arguments
3123 * Returns 0 if successful, else an error is returned with the remaining time in
3124 * the timeout parameter.
3125 * -ETIME: object is still busy after timeout
3126 * -ERESTARTSYS: signal interrupted the wait
3127 * -ENONENT: object doesn't exist
3128 * Also possible, but rare:
3129 * -EAGAIN: GPU wedged
3131 * -ENODEV: Internal IRQ fail
3132 * -E?: The add request failed
3134 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3135 * non-zero timeout parameter the wait ioctl will wait for the given number of
3136 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3137 * without holding struct_mutex the object may become re-busied before this
3138 * function completes. A similar but shorter * race condition exists in the busy
3142 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct drm_i915_gem_wait *args = data;
3146 struct drm_i915_gem_object *obj;
3147 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3148 unsigned reset_counter;
3152 if (args->flags != 0)
3155 ret = i915_mutex_lock_interruptible(dev);
3159 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3160 if (&obj->base == NULL) {
3161 mutex_unlock(&dev->struct_mutex);
3165 /* Need to make sure the object gets inactive eventually. */
3166 ret = i915_gem_object_flush_active(obj);
3173 /* Do this after OLR check to make sure we make forward progress polling
3174 * on this IOCTL with a timeout == 0 (like busy ioctl)
3176 if (args->timeout_ns == 0) {
3181 drm_gem_object_unreference(&obj->base);
3182 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3184 for (i = 0; i < I915_NUM_RINGS; i++) {
3185 if (obj->last_read_req[i] == NULL)
3188 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3191 mutex_unlock(&dev->struct_mutex);
3193 for (i = 0; i < n; i++) {
3195 ret = __i915_wait_request(req[i], reset_counter, true,
3196 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3198 i915_gem_request_unreference__unlocked(req[i]);
3203 drm_gem_object_unreference(&obj->base);
3204 mutex_unlock(&dev->struct_mutex);
3209 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3210 struct intel_engine_cs *to,
3211 struct drm_i915_gem_request *from_req,
3212 struct drm_i915_gem_request **to_req)
3214 struct intel_engine_cs *from;
3217 from = i915_gem_request_get_ring(from_req);
3221 if (i915_gem_request_completed(from_req, true))
3224 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3225 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3226 ret = __i915_wait_request(from_req,
3227 atomic_read(&i915->gpu_error.reset_counter),
3228 i915->mm.interruptible,
3230 &i915->rps.semaphores);
3234 i915_gem_object_retire_request(obj, from_req);
3236 int idx = intel_ring_sync_index(from, to);
3237 u32 seqno = i915_gem_request_get_seqno(from_req);
3241 if (seqno <= from->semaphore.sync_seqno[idx])
3244 if (*to_req == NULL) {
3245 ret = i915_gem_request_alloc(to, to->default_context, to_req);
3250 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3251 ret = to->semaphore.sync_to(*to_req, from, seqno);
3255 /* We use last_read_req because sync_to()
3256 * might have just caused seqno wrap under
3259 from->semaphore.sync_seqno[idx] =
3260 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3267 * i915_gem_object_sync - sync an object to a ring.
3269 * @obj: object which may be in use on another ring.
3270 * @to: ring we wish to use the object on. May be NULL.
3271 * @to_req: request we wish to use the object for. See below.
3272 * This will be allocated and returned if a request is
3273 * required but not passed in.
3275 * This code is meant to abstract object synchronization with the GPU.
3276 * Calling with NULL implies synchronizing the object with the CPU
3277 * rather than a particular GPU ring. Conceptually we serialise writes
3278 * between engines inside the GPU. We only allow one engine to write
3279 * into a buffer at any time, but multiple readers. To ensure each has
3280 * a coherent view of memory, we must:
3282 * - If there is an outstanding write request to the object, the new
3283 * request must wait for it to complete (either CPU or in hw, requests
3284 * on the same ring will be naturally ordered).
3286 * - If we are a write request (pending_write_domain is set), the new
3287 * request must wait for outstanding read requests to complete.
3289 * For CPU synchronisation (NULL to) no request is required. For syncing with
3290 * rings to_req must be non-NULL. However, a request does not have to be
3291 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3292 * request will be allocated automatically and returned through *to_req. Note
3293 * that it is not guaranteed that commands will be emitted (because the system
3294 * might already be idle). Hence there is no need to create a request that
3295 * might never have any work submitted. Note further that if a request is
3296 * returned in *to_req, it is the responsibility of the caller to submit
3297 * that request (after potentially adding more work to it).
3299 * Returns 0 if successful, else propagates up the lower layer error.
3302 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3303 struct intel_engine_cs *to,
3304 struct drm_i915_gem_request **to_req)
3306 const bool readonly = obj->base.pending_write_domain == 0;
3307 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3314 return i915_gem_object_wait_rendering(obj, readonly);
3318 if (obj->last_write_req)
3319 req[n++] = obj->last_write_req;
3321 for (i = 0; i < I915_NUM_RINGS; i++)
3322 if (obj->last_read_req[i])
3323 req[n++] = obj->last_read_req[i];
3325 for (i = 0; i < n; i++) {
3326 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3334 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3336 u32 old_write_domain, old_read_domains;
3338 /* Force a pagefault for domain tracking on next user access */
3339 i915_gem_release_mmap(obj);
3341 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3344 /* Wait for any direct GTT access to complete */
3347 old_read_domains = obj->base.read_domains;
3348 old_write_domain = obj->base.write_domain;
3350 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3351 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3353 trace_i915_gem_object_change_domain(obj,
3358 int i915_vma_unbind(struct i915_vma *vma)
3360 struct drm_i915_gem_object *obj = vma->obj;
3361 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3364 if (list_empty(&vma->vma_link))
3367 if (!drm_mm_node_allocated(&vma->node)) {
3368 i915_gem_vma_destroy(vma);
3375 BUG_ON(obj->pages == NULL);
3377 ret = i915_gem_object_wait_rendering(obj, false);
3380 /* Continue on if we fail due to EIO, the GPU is hung so we
3381 * should be safe and we need to cleanup or else we might
3382 * cause memory corruption through use-after-free.
3385 if (i915_is_ggtt(vma->vm) &&
3386 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3387 i915_gem_object_finish_gtt(obj);
3389 /* release the fence reg _after_ flushing */
3390 ret = i915_gem_object_put_fence(obj);
3395 trace_i915_vma_unbind(vma);
3397 vma->vm->unbind_vma(vma);
3400 list_del_init(&vma->mm_list);
3401 if (i915_is_ggtt(vma->vm)) {
3402 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3403 obj->map_and_fenceable = false;
3404 } else if (vma->ggtt_view.pages) {
3405 sg_free_table(vma->ggtt_view.pages);
3406 kfree(vma->ggtt_view.pages);
3408 vma->ggtt_view.pages = NULL;
3411 drm_mm_remove_node(&vma->node);
3412 i915_gem_vma_destroy(vma);
3414 /* Since the unbound list is global, only move to that list if
3415 * no more VMAs exist. */
3416 if (list_empty(&obj->vma_list))
3417 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3419 /* And finally now the object is completely decoupled from this vma,
3420 * we can drop its hold on the backing storage and allow it to be
3421 * reaped by the shrinker.
3423 i915_gem_object_unpin_pages(obj);
3428 int i915_gpu_idle(struct drm_device *dev)
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3431 struct intel_engine_cs *ring;
3434 /* Flush everything onto the inactive list. */
3435 for_each_ring(ring, dev_priv, i) {
3436 if (!i915.enable_execlists) {
3437 struct drm_i915_gem_request *req;
3439 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
3443 ret = i915_switch_context(req);
3445 i915_gem_request_cancel(req);
3449 i915_add_request_no_flush(req);
3452 ret = intel_ring_idle(ring);
3457 WARN_ON(i915_verify_lists(dev));
3461 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3462 unsigned long cache_level)
3464 struct drm_mm_node *gtt_space = &vma->node;
3465 struct drm_mm_node *other;
3468 * On some machines we have to be careful when putting differing types
3469 * of snoopable memory together to avoid the prefetcher crossing memory
3470 * domains and dying. During vm initialisation, we decide whether or not
3471 * these constraints apply and set the drm_mm.color_adjust
3474 if (vma->vm->mm.color_adjust == NULL)
3477 if (!drm_mm_node_allocated(gtt_space))
3480 if (list_empty(>t_space->node_list))
3483 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3484 if (other->allocated && !other->hole_follows && other->color != cache_level)
3487 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3488 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3495 * Finds free space in the GTT aperture and binds the object or a view of it
3498 static struct i915_vma *
3499 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3500 struct i915_address_space *vm,
3501 const struct i915_ggtt_view *ggtt_view,
3505 struct drm_device *dev = obj->base.dev;
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 u32 size, fence_size, fence_alignment, unfenced_alignment;
3509 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3511 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3512 struct i915_vma *vma;
3515 if (i915_is_ggtt(vm)) {
3518 if (WARN_ON(!ggtt_view))
3519 return ERR_PTR(-EINVAL);
3521 view_size = i915_ggtt_view_size(obj, ggtt_view);
3523 fence_size = i915_gem_get_gtt_size(dev,
3526 fence_alignment = i915_gem_get_gtt_alignment(dev,
3530 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3534 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3536 fence_size = i915_gem_get_gtt_size(dev,
3539 fence_alignment = i915_gem_get_gtt_alignment(dev,
3543 unfenced_alignment =
3544 i915_gem_get_gtt_alignment(dev,
3548 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3552 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3554 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3555 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3556 ggtt_view ? ggtt_view->type : 0,
3558 return ERR_PTR(-EINVAL);
3561 /* If binding the object/GGTT view requires more space than the entire
3562 * aperture has, reject it early before evicting everything in a vain
3563 * attempt to find space.
3566 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3567 ggtt_view ? ggtt_view->type : 0,
3569 flags & PIN_MAPPABLE ? "mappable" : "total",
3571 return ERR_PTR(-E2BIG);
3574 ret = i915_gem_object_get_pages(obj);
3576 return ERR_PTR(ret);
3578 i915_gem_object_pin_pages(obj);
3580 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3581 i915_gem_obj_lookup_or_create_vma(obj, vm);
3587 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3591 DRM_MM_SEARCH_DEFAULT,
3592 DRM_MM_CREATE_DEFAULT);
3594 ret = i915_gem_evict_something(dev, vm, size, alignment,
3603 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3605 goto err_remove_node;
3608 trace_i915_vma_bind(vma, flags);
3609 ret = i915_vma_bind(vma, obj->cache_level, flags);
3611 goto err_remove_node;
3613 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3614 list_add_tail(&vma->mm_list, &vm->inactive_list);
3619 drm_mm_remove_node(&vma->node);
3621 i915_gem_vma_destroy(vma);
3624 i915_gem_object_unpin_pages(obj);
3629 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3632 /* If we don't have a page list set up, then we're not pinned
3633 * to GPU, and we can ignore the cache flush because it'll happen
3634 * again at bind time.
3636 if (obj->pages == NULL)
3640 * Stolen memory is always coherent with the GPU as it is explicitly
3641 * marked as wc by the system, or the system is cache-coherent.
3643 if (obj->stolen || obj->phys_handle)
3646 /* If the GPU is snooping the contents of the CPU cache,
3647 * we do not need to manually clear the CPU cache lines. However,
3648 * the caches are only snooped when the render cache is
3649 * flushed/invalidated. As we always have to emit invalidations
3650 * and flushes when moving into and out of the RENDER domain, correct
3651 * snooping behaviour occurs naturally as the result of our domain
3654 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3655 obj->cache_dirty = true;
3659 trace_i915_gem_object_clflush(obj);
3660 drm_clflush_sg(obj->pages);
3661 obj->cache_dirty = false;
3666 /** Flushes the GTT write domain for the object if it's dirty. */
3668 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3670 uint32_t old_write_domain;
3672 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3675 /* No actual flushing is required for the GTT write domain. Writes
3676 * to it immediately go to main memory as far as we know, so there's
3677 * no chipset flush. It also doesn't land in render cache.
3679 * However, we do have to enforce the order so that all writes through
3680 * the GTT land before any writes to the device, such as updates to
3685 old_write_domain = obj->base.write_domain;
3686 obj->base.write_domain = 0;
3688 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3690 trace_i915_gem_object_change_domain(obj,
3691 obj->base.read_domains,
3695 /** Flushes the CPU write domain for the object if it's dirty. */
3697 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3699 uint32_t old_write_domain;
3701 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3704 if (i915_gem_clflush_object(obj, obj->pin_display))
3705 i915_gem_chipset_flush(obj->base.dev);
3707 old_write_domain = obj->base.write_domain;
3708 obj->base.write_domain = 0;
3710 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3712 trace_i915_gem_object_change_domain(obj,
3713 obj->base.read_domains,
3718 * Moves a single object to the GTT read, and possibly write domain.
3720 * This function returns when the move is complete, including waiting on
3724 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3726 uint32_t old_write_domain, old_read_domains;
3727 struct i915_vma *vma;
3730 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3733 ret = i915_gem_object_wait_rendering(obj, !write);
3737 /* Flush and acquire obj->pages so that we are coherent through
3738 * direct access in memory with previous cached writes through
3739 * shmemfs and that our cache domain tracking remains valid.
3740 * For example, if the obj->filp was moved to swap without us
3741 * being notified and releasing the pages, we would mistakenly
3742 * continue to assume that the obj remained out of the CPU cached
3745 ret = i915_gem_object_get_pages(obj);
3749 i915_gem_object_flush_cpu_write_domain(obj);
3751 /* Serialise direct access to this object with the barriers for
3752 * coherent writes from the GPU, by effectively invalidating the
3753 * GTT domain upon first access.
3755 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3758 old_write_domain = obj->base.write_domain;
3759 old_read_domains = obj->base.read_domains;
3761 /* It should now be out of any other write domains, and we can update
3762 * the domain values for our changes.
3764 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3765 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3767 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3768 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3772 trace_i915_gem_object_change_domain(obj,
3776 /* And bump the LRU for this access */
3777 vma = i915_gem_obj_to_ggtt(obj);
3778 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3779 list_move_tail(&vma->mm_list,
3780 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3785 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3786 enum i915_cache_level cache_level)
3788 struct drm_device *dev = obj->base.dev;
3789 struct i915_vma *vma, *next;
3792 if (obj->cache_level == cache_level)
3795 if (i915_gem_obj_is_pinned(obj)) {
3796 DRM_DEBUG("can not change the cache level of pinned objects\n");
3800 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3801 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3802 ret = i915_vma_unbind(vma);
3808 if (i915_gem_obj_bound_any(obj)) {
3809 ret = i915_gem_object_wait_rendering(obj, false);
3813 i915_gem_object_finish_gtt(obj);
3815 /* Before SandyBridge, you could not use tiling or fence
3816 * registers with snooped memory, so relinquish any fences
3817 * currently pointing to our region in the aperture.
3819 if (INTEL_INFO(dev)->gen < 6) {
3820 ret = i915_gem_object_put_fence(obj);
3825 list_for_each_entry(vma, &obj->vma_list, vma_link)
3826 if (drm_mm_node_allocated(&vma->node)) {
3827 ret = i915_vma_bind(vma, cache_level,
3834 list_for_each_entry(vma, &obj->vma_list, vma_link)
3835 vma->node.color = cache_level;
3836 obj->cache_level = cache_level;
3838 if (obj->cache_dirty &&
3839 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3840 cpu_write_needs_clflush(obj)) {
3841 if (i915_gem_clflush_object(obj, true))
3842 i915_gem_chipset_flush(obj->base.dev);
3848 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3849 struct drm_file *file)
3851 struct drm_i915_gem_caching *args = data;
3852 struct drm_i915_gem_object *obj;
3854 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3855 if (&obj->base == NULL)
3858 switch (obj->cache_level) {
3859 case I915_CACHE_LLC:
3860 case I915_CACHE_L3_LLC:
3861 args->caching = I915_CACHING_CACHED;
3865 args->caching = I915_CACHING_DISPLAY;
3869 args->caching = I915_CACHING_NONE;
3873 drm_gem_object_unreference_unlocked(&obj->base);
3877 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3878 struct drm_file *file)
3880 struct drm_i915_gem_caching *args = data;
3881 struct drm_i915_gem_object *obj;
3882 enum i915_cache_level level;
3885 switch (args->caching) {
3886 case I915_CACHING_NONE:
3887 level = I915_CACHE_NONE;
3889 case I915_CACHING_CACHED:
3890 level = I915_CACHE_LLC;
3892 case I915_CACHING_DISPLAY:
3893 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3899 ret = i915_mutex_lock_interruptible(dev);
3903 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3904 if (&obj->base == NULL) {
3909 ret = i915_gem_object_set_cache_level(obj, level);
3911 drm_gem_object_unreference(&obj->base);
3913 mutex_unlock(&dev->struct_mutex);
3918 * Prepare buffer for display plane (scanout, cursors, etc).
3919 * Can be called from an uninterruptible phase (modesetting) and allows
3920 * any flushes to be pipelined (for pageflips).
3923 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3925 struct intel_engine_cs *pipelined,
3926 struct drm_i915_gem_request **pipelined_request,
3927 const struct i915_ggtt_view *view)
3929 u32 old_read_domains, old_write_domain;
3932 ret = i915_gem_object_sync(obj, pipelined, pipelined_request);
3936 /* Mark the pin_display early so that we account for the
3937 * display coherency whilst setting up the cache domains.
3941 /* The display engine is not coherent with the LLC cache on gen6. As
3942 * a result, we make sure that the pinning that is about to occur is
3943 * done with uncached PTEs. This is lowest common denominator for all
3946 * However for gen6+, we could do better by using the GFDT bit instead
3947 * of uncaching, which would allow us to flush all the LLC-cached data
3948 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3950 ret = i915_gem_object_set_cache_level(obj,
3951 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3953 goto err_unpin_display;
3955 /* As the user may map the buffer once pinned in the display plane
3956 * (e.g. libkms for the bootup splash), we have to ensure that we
3957 * always use map_and_fenceable for all scanout buffers.
3959 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
3960 view->type == I915_GGTT_VIEW_NORMAL ?
3963 goto err_unpin_display;
3965 i915_gem_object_flush_cpu_write_domain(obj);
3967 old_write_domain = obj->base.write_domain;
3968 old_read_domains = obj->base.read_domains;
3970 /* It should now be out of any other write domains, and we can update
3971 * the domain values for our changes.
3973 obj->base.write_domain = 0;
3974 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3976 trace_i915_gem_object_change_domain(obj,
3988 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3989 const struct i915_ggtt_view *view)
3991 if (WARN_ON(obj->pin_display == 0))
3994 i915_gem_object_ggtt_unpin_view(obj, view);
4000 * Moves a single object to the CPU read, and possibly write domain.
4002 * This function returns when the move is complete, including waiting on
4006 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4008 uint32_t old_write_domain, old_read_domains;
4011 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4014 ret = i915_gem_object_wait_rendering(obj, !write);
4018 i915_gem_object_flush_gtt_write_domain(obj);
4020 old_write_domain = obj->base.write_domain;
4021 old_read_domains = obj->base.read_domains;
4023 /* Flush the CPU cache if it's still invalid. */
4024 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4025 i915_gem_clflush_object(obj, false);
4027 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4030 /* It should now be out of any other write domains, and we can update
4031 * the domain values for our changes.
4033 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4035 /* If we're writing through the CPU, then the GPU read domains will
4036 * need to be invalidated at next use.
4039 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4040 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4043 trace_i915_gem_object_change_domain(obj,
4050 /* Throttle our rendering by waiting until the ring has completed our requests
4051 * emitted over 20 msec ago.
4053 * Note that if we were to use the current jiffies each time around the loop,
4054 * we wouldn't escape the function with any frames outstanding if the time to
4055 * render a frame was over 20ms.
4057 * This should get us reasonable parallelism between CPU and GPU but also
4058 * relatively low latency when blocking on a particular request to finish.
4061 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4063 struct drm_i915_private *dev_priv = dev->dev_private;
4064 struct drm_i915_file_private *file_priv = file->driver_priv;
4065 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4066 struct drm_i915_gem_request *request, *target = NULL;
4067 unsigned reset_counter;
4070 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4074 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4078 spin_lock(&file_priv->mm.lock);
4079 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4080 if (time_after_eq(request->emitted_jiffies, recent_enough))
4084 * Note that the request might not have been submitted yet.
4085 * In which case emitted_jiffies will be zero.
4087 if (!request->emitted_jiffies)
4092 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4094 i915_gem_request_reference(target);
4095 spin_unlock(&file_priv->mm.lock);
4100 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4102 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4104 i915_gem_request_unreference__unlocked(target);
4110 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4112 struct drm_i915_gem_object *obj = vma->obj;
4115 vma->node.start & (alignment - 1))
4118 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4121 if (flags & PIN_OFFSET_BIAS &&
4122 vma->node.start < (flags & PIN_OFFSET_MASK))
4129 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4130 struct i915_address_space *vm,
4131 const struct i915_ggtt_view *ggtt_view,
4135 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4136 struct i915_vma *vma;
4140 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4143 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4146 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4149 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4152 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4153 i915_gem_obj_to_vma(obj, vm);
4156 return PTR_ERR(vma);
4159 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4162 if (i915_vma_misplaced(vma, alignment, flags)) {
4163 unsigned long offset;
4164 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4165 i915_gem_obj_offset(obj, vm);
4166 WARN(vma->pin_count,
4167 "bo is already pinned in %s with incorrect alignment:"
4168 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4169 " obj->map_and_fenceable=%d\n",
4170 ggtt_view ? "ggtt" : "ppgtt",
4173 !!(flags & PIN_MAPPABLE),
4174 obj->map_and_fenceable);
4175 ret = i915_vma_unbind(vma);
4183 bound = vma ? vma->bound : 0;
4184 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4185 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4188 return PTR_ERR(vma);
4190 ret = i915_vma_bind(vma, obj->cache_level, flags);
4195 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4196 (bound ^ vma->bound) & GLOBAL_BIND) {
4197 bool mappable, fenceable;
4198 u32 fence_size, fence_alignment;
4200 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4203 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4208 fenceable = (vma->node.size == fence_size &&
4209 (vma->node.start & (fence_alignment - 1)) == 0);
4211 mappable = (vma->node.start + fence_size <=
4212 dev_priv->gtt.mappable_end);
4214 obj->map_and_fenceable = mappable && fenceable;
4216 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4224 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4225 struct i915_address_space *vm,
4229 return i915_gem_object_do_pin(obj, vm,
4230 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4235 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4236 const struct i915_ggtt_view *view,
4240 if (WARN_ONCE(!view, "no view specified"))
4243 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4244 alignment, flags | PIN_GLOBAL);
4248 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4249 const struct i915_ggtt_view *view)
4251 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4254 WARN_ON(vma->pin_count == 0);
4255 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4261 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4262 struct drm_file *file)
4264 struct drm_i915_gem_busy *args = data;
4265 struct drm_i915_gem_object *obj;
4268 ret = i915_mutex_lock_interruptible(dev);
4272 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4273 if (&obj->base == NULL) {
4278 /* Count all active objects as busy, even if they are currently not used
4279 * by the gpu. Users of this interface expect objects to eventually
4280 * become non-busy without any further actions, therefore emit any
4281 * necessary flushes here.
4283 ret = i915_gem_object_flush_active(obj);
4287 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4288 args->busy = obj->active << 16;
4289 if (obj->last_write_req)
4290 args->busy |= obj->last_write_req->ring->id;
4293 drm_gem_object_unreference(&obj->base);
4295 mutex_unlock(&dev->struct_mutex);
4300 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4301 struct drm_file *file_priv)
4303 return i915_gem_ring_throttle(dev, file_priv);
4307 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4308 struct drm_file *file_priv)
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 struct drm_i915_gem_madvise *args = data;
4312 struct drm_i915_gem_object *obj;
4315 switch (args->madv) {
4316 case I915_MADV_DONTNEED:
4317 case I915_MADV_WILLNEED:
4323 ret = i915_mutex_lock_interruptible(dev);
4327 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4328 if (&obj->base == NULL) {
4333 if (i915_gem_obj_is_pinned(obj)) {
4339 obj->tiling_mode != I915_TILING_NONE &&
4340 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4341 if (obj->madv == I915_MADV_WILLNEED)
4342 i915_gem_object_unpin_pages(obj);
4343 if (args->madv == I915_MADV_WILLNEED)
4344 i915_gem_object_pin_pages(obj);
4347 if (obj->madv != __I915_MADV_PURGED)
4348 obj->madv = args->madv;
4350 /* if the object is no longer attached, discard its backing storage */
4351 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4352 i915_gem_object_truncate(obj);
4354 args->retained = obj->madv != __I915_MADV_PURGED;
4357 drm_gem_object_unreference(&obj->base);
4359 mutex_unlock(&dev->struct_mutex);
4363 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4364 const struct drm_i915_gem_object_ops *ops)
4368 INIT_LIST_HEAD(&obj->global_list);
4369 for (i = 0; i < I915_NUM_RINGS; i++)
4370 INIT_LIST_HEAD(&obj->ring_list[i]);
4371 INIT_LIST_HEAD(&obj->obj_exec_link);
4372 INIT_LIST_HEAD(&obj->vma_list);
4373 INIT_LIST_HEAD(&obj->batch_pool_link);
4377 obj->fence_reg = I915_FENCE_REG_NONE;
4378 obj->madv = I915_MADV_WILLNEED;
4380 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4383 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4384 .get_pages = i915_gem_object_get_pages_gtt,
4385 .put_pages = i915_gem_object_put_pages_gtt,
4388 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4391 struct drm_i915_gem_object *obj;
4393 struct address_space *mapping;
4397 obj = i915_gem_object_alloc(dev);
4401 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4402 i915_gem_object_free(obj);
4407 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4408 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4409 /* 965gm cannot relocate objects above 4GiB. */
4410 mask &= ~__GFP_HIGHMEM;
4411 mask |= __GFP_DMA32;
4414 mapping = file_inode(obj->base.filp)->i_mapping;
4415 mapping_set_gfp_mask(mapping, mask);
4418 i915_gem_object_init(obj, &i915_gem_object_ops);
4420 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4421 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4424 /* On some devices, we can have the GPU use the LLC (the CPU
4425 * cache) for about a 10% performance improvement
4426 * compared to uncached. Graphics requests other than
4427 * display scanout are coherent with the CPU in
4428 * accessing this cache. This means in this mode we
4429 * don't need to clflush on the CPU side, and on the
4430 * GPU side we only need to flush internal caches to
4431 * get data visible to the CPU.
4433 * However, we maintain the display planes as UC, and so
4434 * need to rebind when first used as such.
4436 obj->cache_level = I915_CACHE_LLC;
4438 obj->cache_level = I915_CACHE_NONE;
4440 trace_i915_gem_object_create(obj);
4445 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4447 /* If we are the last user of the backing storage (be it shmemfs
4448 * pages or stolen etc), we know that the pages are going to be
4449 * immediately released. In this case, we can then skip copying
4450 * back the contents from the GPU.
4453 if (obj->madv != I915_MADV_WILLNEED)
4456 if (obj->base.vm_obj == NULL)
4459 /* At first glance, this looks racy, but then again so would be
4460 * userspace racing mmap against close. However, the first external
4461 * reference to the filp can only be obtained through the
4462 * i915_gem_mmap_ioctl() which safeguards us against the user
4463 * acquiring such a reference whilst we are in the middle of
4464 * freeing the object.
4467 return atomic_long_read(&obj->base.filp->f_count) == 1;
4473 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4475 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4476 struct drm_device *dev = obj->base.dev;
4477 struct drm_i915_private *dev_priv = dev->dev_private;
4478 struct i915_vma *vma, *next;
4480 intel_runtime_pm_get(dev_priv);
4482 trace_i915_gem_object_destroy(obj);
4484 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4488 ret = i915_vma_unbind(vma);
4489 if (WARN_ON(ret == -ERESTARTSYS)) {
4490 bool was_interruptible;
4492 was_interruptible = dev_priv->mm.interruptible;
4493 dev_priv->mm.interruptible = false;
4495 WARN_ON(i915_vma_unbind(vma));
4497 dev_priv->mm.interruptible = was_interruptible;
4501 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4502 * before progressing. */
4504 i915_gem_object_unpin_pages(obj);
4506 WARN_ON(obj->frontbuffer_bits);
4508 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4509 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4510 obj->tiling_mode != I915_TILING_NONE)
4511 i915_gem_object_unpin_pages(obj);
4513 if (WARN_ON(obj->pages_pin_count))
4514 obj->pages_pin_count = 0;
4515 if (discard_backing_storage(obj))
4516 obj->madv = I915_MADV_DONTNEED;
4517 i915_gem_object_put_pages(obj);
4518 i915_gem_object_free_mmap_offset(obj);
4523 if (obj->base.import_attach)
4524 drm_prime_gem_destroy(&obj->base, NULL);
4527 if (obj->ops->release)
4528 obj->ops->release(obj);
4530 drm_gem_object_release(&obj->base);
4531 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4534 i915_gem_object_free(obj);
4536 intel_runtime_pm_put(dev_priv);
4539 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4540 struct i915_address_space *vm)
4542 struct i915_vma *vma;
4543 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4544 if (i915_is_ggtt(vma->vm) &&
4545 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4553 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4554 const struct i915_ggtt_view *view)
4556 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4557 struct i915_vma *vma;
4559 if (WARN_ONCE(!view, "no view specified"))
4560 return ERR_PTR(-EINVAL);
4562 list_for_each_entry(vma, &obj->vma_list, vma_link)
4563 if (vma->vm == ggtt &&
4564 i915_ggtt_view_equal(&vma->ggtt_view, view))
4569 void i915_gem_vma_destroy(struct i915_vma *vma)
4571 struct i915_address_space *vm = NULL;
4572 WARN_ON(vma->node.allocated);
4574 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4575 if (!list_empty(&vma->exec_list))
4580 if (!i915_is_ggtt(vm))
4581 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4583 list_del(&vma->vma_link);
4589 i915_gem_stop_ringbuffers(struct drm_device *dev)
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592 struct intel_engine_cs *ring;
4595 for_each_ring(ring, dev_priv, i)
4596 dev_priv->gt.stop_ring(ring);
4600 i915_gem_suspend(struct drm_device *dev)
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4605 mutex_lock(&dev->struct_mutex);
4606 ret = i915_gpu_idle(dev);
4610 i915_gem_retire_requests(dev);
4612 i915_gem_stop_ringbuffers(dev);
4613 mutex_unlock(&dev->struct_mutex);
4615 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4616 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4618 flush_delayed_work(&dev_priv->mm.idle_work);
4621 /* Assert that we sucessfully flushed all the work and
4622 * reset the GPU back to its idle, low power state.
4624 WARN_ON(dev_priv->mm.busy);
4629 mutex_unlock(&dev->struct_mutex);
4633 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4635 struct intel_engine_cs *ring = req->ring;
4636 struct drm_device *dev = ring->dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4639 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4642 if (!HAS_L3_DPF(dev) || !remap_info)
4645 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4650 * Note: We do not worry about the concurrent register cacheline hang
4651 * here because no other code should access these registers other than
4652 * at initialization time.
4654 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4655 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4656 intel_ring_emit(ring, reg_base + i);
4657 intel_ring_emit(ring, remap_info[i/4]);
4660 intel_ring_advance(ring);
4665 void i915_gem_init_swizzling(struct drm_device *dev)
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4669 if (INTEL_INFO(dev)->gen < 5 ||
4670 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4673 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4674 DISP_TILE_SURFACE_SWIZZLING);
4679 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4681 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4682 else if (IS_GEN7(dev))
4683 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4684 else if (IS_GEN8(dev))
4685 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4691 intel_enable_blt(struct drm_device *dev)
4696 /* The blitter was dysfunctional on early prototypes */
4697 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4698 DRM_INFO("BLT not supported on this pre-production hardware;"
4699 " graphics performance will be degraded.\n");
4706 static void init_unused_ring(struct drm_device *dev, u32 base)
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4710 I915_WRITE(RING_CTL(base), 0);
4711 I915_WRITE(RING_HEAD(base), 0);
4712 I915_WRITE(RING_TAIL(base), 0);
4713 I915_WRITE(RING_START(base), 0);
4716 static void init_unused_rings(struct drm_device *dev)
4719 init_unused_ring(dev, PRB1_BASE);
4720 init_unused_ring(dev, SRB0_BASE);
4721 init_unused_ring(dev, SRB1_BASE);
4722 init_unused_ring(dev, SRB2_BASE);
4723 init_unused_ring(dev, SRB3_BASE);
4724 } else if (IS_GEN2(dev)) {
4725 init_unused_ring(dev, SRB0_BASE);
4726 init_unused_ring(dev, SRB1_BASE);
4727 } else if (IS_GEN3(dev)) {
4728 init_unused_ring(dev, PRB1_BASE);
4729 init_unused_ring(dev, PRB2_BASE);
4733 int i915_gem_init_rings(struct drm_device *dev)
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4738 ret = intel_init_render_ring_buffer(dev);
4743 ret = intel_init_bsd_ring_buffer(dev);
4745 goto cleanup_render_ring;
4748 if (intel_enable_blt(dev)) {
4749 ret = intel_init_blt_ring_buffer(dev);
4751 goto cleanup_bsd_ring;
4754 if (HAS_VEBOX(dev)) {
4755 ret = intel_init_vebox_ring_buffer(dev);
4757 goto cleanup_blt_ring;
4760 if (HAS_BSD2(dev)) {
4761 ret = intel_init_bsd2_ring_buffer(dev);
4763 goto cleanup_vebox_ring;
4766 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4768 goto cleanup_bsd2_ring;
4773 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4775 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4777 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4779 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4780 cleanup_render_ring:
4781 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4787 i915_gem_init_hw(struct drm_device *dev)
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 struct intel_engine_cs *ring;
4794 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4798 /* Double layer security blanket, see i915_gem_init() */
4799 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4801 if (dev_priv->ellc_size)
4802 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4804 if (IS_HASWELL(dev))
4805 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4806 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4808 if (HAS_PCH_NOP(dev)) {
4809 if (IS_IVYBRIDGE(dev)) {
4810 u32 temp = I915_READ(GEN7_MSG_CTL);
4811 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4812 I915_WRITE(GEN7_MSG_CTL, temp);
4813 } else if (INTEL_INFO(dev)->gen >= 7) {
4814 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4815 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4816 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4820 i915_gem_init_swizzling(dev);
4823 * At least 830 can leave some of the unused rings
4824 * "active" (ie. head != tail) after resume which
4825 * will prevent c3 entry. Makes sure all unused rings
4828 init_unused_rings(dev);
4830 BUG_ON(!dev_priv->ring[RCS].default_context);
4832 ret = i915_ppgtt_init_hw(dev);
4834 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4838 /* Need to do basic initialisation of all rings first: */
4839 for_each_ring(ring, dev_priv, i) {
4840 ret = ring->init_hw(ring);
4845 /* Now it is safe to go back round and do everything else: */
4846 for_each_ring(ring, dev_priv, i) {
4847 struct drm_i915_gem_request *req;
4849 WARN_ON(!ring->default_context);
4851 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
4853 i915_gem_cleanup_ringbuffer(dev);
4857 if (ring->id == RCS) {
4858 for (j = 0; j < NUM_L3_SLICES(dev); j++)
4859 i915_gem_l3_remap(req, j);
4862 ret = i915_ppgtt_init_ring(req);
4863 if (ret && ret != -EIO) {
4864 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
4865 i915_gem_request_cancel(req);
4866 i915_gem_cleanup_ringbuffer(dev);
4870 ret = i915_gem_context_enable(req);
4871 if (ret && ret != -EIO) {
4872 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
4873 i915_gem_request_cancel(req);
4874 i915_gem_cleanup_ringbuffer(dev);
4878 i915_add_request_no_flush(req);
4882 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4886 int i915_gem_init(struct drm_device *dev)
4888 struct drm_i915_private *dev_priv = dev->dev_private;
4891 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4892 i915.enable_execlists);
4894 mutex_lock(&dev->struct_mutex);
4896 if (IS_VALLEYVIEW(dev)) {
4897 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4898 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4899 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4900 VLV_GTLC_ALLOWWAKEACK), 10))
4901 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4904 if (!i915.enable_execlists) {
4905 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4906 dev_priv->gt.init_rings = i915_gem_init_rings;
4907 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4908 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4910 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4911 dev_priv->gt.init_rings = intel_logical_rings_init;
4912 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4913 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4916 /* This is just a security blanket to placate dragons.
4917 * On some systems, we very sporadically observe that the first TLBs
4918 * used by the CS may be stale, despite us poking the TLB reset. If
4919 * we hold the forcewake during initialisation these problems
4920 * just magically go away.
4922 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4924 ret = i915_gem_init_userptr(dev);
4928 i915_gem_init_global_gtt(dev);
4930 ret = i915_gem_context_init(dev);
4934 ret = dev_priv->gt.init_rings(dev);
4938 ret = i915_gem_init_hw(dev);
4940 /* Allow ring initialisation to fail by marking the GPU as
4941 * wedged. But we only want to do this where the GPU is angry,
4942 * for all other failure, such as an allocation failure, bail.
4944 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4945 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4950 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4951 mutex_unlock(&dev->struct_mutex);
4957 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4959 struct drm_i915_private *dev_priv = dev->dev_private;
4960 struct intel_engine_cs *ring;
4963 for_each_ring(ring, dev_priv, i)
4964 dev_priv->gt.cleanup_ring(ring);
4966 if (i915.enable_execlists)
4968 * Neither the BIOS, ourselves or any other kernel
4969 * expects the system to be in execlists mode on startup,
4970 * so we need to reset the GPU back to legacy mode.
4972 intel_gpu_reset(dev);
4976 init_ring_lists(struct intel_engine_cs *ring)
4978 INIT_LIST_HEAD(&ring->active_list);
4979 INIT_LIST_HEAD(&ring->request_list);
4982 void i915_init_vm(struct drm_i915_private *dev_priv,
4983 struct i915_address_space *vm)
4985 if (!i915_is_ggtt(vm))
4986 drm_mm_init(&vm->mm, vm->start, vm->total);
4987 vm->dev = dev_priv->dev;
4988 INIT_LIST_HEAD(&vm->active_list);
4989 INIT_LIST_HEAD(&vm->inactive_list);
4990 INIT_LIST_HEAD(&vm->global_link);
4991 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4995 i915_gem_load(struct drm_device *dev)
4997 struct drm_i915_private *dev_priv = dev->dev_private;
5000 INIT_LIST_HEAD(&dev_priv->vm_list);
5001 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5003 INIT_LIST_HEAD(&dev_priv->context_list);
5004 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5005 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5006 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5007 for (i = 0; i < I915_NUM_RINGS; i++)
5008 init_ring_lists(&dev_priv->ring[i]);
5009 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5010 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5011 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5012 i915_gem_retire_work_handler);
5013 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5014 i915_gem_idle_work_handler);
5015 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5017 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5019 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5020 dev_priv->num_fence_regs = 32;
5021 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5022 dev_priv->num_fence_regs = 16;
5024 dev_priv->num_fence_regs = 8;
5026 if (intel_vgpu_active(dev))
5027 dev_priv->num_fence_regs =
5028 I915_READ(vgtif_reg(avail_rs.fence_num));
5030 /* Initialize fence registers to zero */
5031 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5032 i915_gem_restore_fences(dev);
5034 i915_gem_detect_bit_6_swizzle(dev);
5035 init_waitqueue_head(&dev_priv->pending_flip_queue);
5037 dev_priv->mm.interruptible = true;
5039 i915_gem_shrinker_init(dev_priv);
5041 lockinit(&dev_priv->fb_tracking.lock, "drmftl", 0, LK_CANRECURSE);
5044 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5046 struct drm_i915_file_private *file_priv = file->driver_priv;
5048 /* Clean up our request list when the client is going away, so that
5049 * later retire_requests won't dereference our soon-to-be-gone
5052 spin_lock(&file_priv->mm.lock);
5053 while (!list_empty(&file_priv->mm.request_list)) {
5054 struct drm_i915_gem_request *request;
5056 request = list_first_entry(&file_priv->mm.request_list,
5057 struct drm_i915_gem_request,
5059 list_del(&request->client_list);
5060 request->file_priv = NULL;
5062 spin_unlock(&file_priv->mm.lock);
5064 if (!list_empty(&file_priv->rps.link)) {
5065 lockmgr(&to_i915(dev)->rps.client_lock, LK_EXCLUSIVE);
5066 list_del(&file_priv->rps.link);
5067 lockmgr(&to_i915(dev)->rps.client_lock, LK_RELEASE);
5072 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
5073 vm_ooffset_t foff, struct ucred *cred, u_short *color)
5075 *color = 0; /* XXXKIB */
5080 i915_gem_pager_dtor(void *handle)
5082 struct drm_gem_object *obj;
5083 struct drm_device *dev;
5088 mutex_lock(&dev->struct_mutex);
5089 drm_gem_free_mmap_offset(obj);
5090 i915_gem_release_mmap(to_intel_bo(obj));
5091 drm_gem_object_unreference(obj);
5092 mutex_unlock(&dev->struct_mutex);
5095 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5097 struct drm_i915_file_private *file_priv;
5100 DRM_DEBUG_DRIVER("\n");
5102 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5106 file->driver_priv = file_priv;
5107 file_priv->dev_priv = dev->dev_private;
5108 file_priv->file = file;
5109 INIT_LIST_HEAD(&file_priv->rps.link);
5111 spin_init(&file_priv->mm.lock, "i915_priv");
5112 INIT_LIST_HEAD(&file_priv->mm.request_list);
5114 ret = i915_gem_context_open(dev, file);
5122 * i915_gem_track_fb - update frontbuffer tracking
5123 * old: current GEM buffer for the frontbuffer slots
5124 * new: new GEM buffer for the frontbuffer slots
5125 * frontbuffer_bits: bitmask of frontbuffer slots
5127 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5128 * from @old and setting them in @new. Both @old and @new can be NULL.
5130 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5131 struct drm_i915_gem_object *new,
5132 unsigned frontbuffer_bits)
5135 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5136 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5137 old->frontbuffer_bits &= ~frontbuffer_bits;
5141 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5142 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5143 new->frontbuffer_bits |= frontbuffer_bits;
5147 /* All the new VM stuff */
5149 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5150 struct i915_address_space *vm)
5152 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5153 struct i915_vma *vma;
5155 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5157 list_for_each_entry(vma, &o->vma_list, vma_link) {
5158 if (i915_is_ggtt(vma->vm) &&
5159 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5162 return vma->node.start;
5165 WARN(1, "%s vma for this object not found.\n",
5166 i915_is_ggtt(vm) ? "global" : "ppgtt");
5171 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5172 const struct i915_ggtt_view *view)
5174 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5175 struct i915_vma *vma;
5177 list_for_each_entry(vma, &o->vma_list, vma_link)
5178 if (vma->vm == ggtt &&
5179 i915_ggtt_view_equal(&vma->ggtt_view, view))
5180 return vma->node.start;
5182 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5186 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5187 struct i915_address_space *vm)
5189 struct i915_vma *vma;
5191 list_for_each_entry(vma, &o->vma_list, vma_link) {
5192 if (i915_is_ggtt(vma->vm) &&
5193 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5195 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5202 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5203 const struct i915_ggtt_view *view)
5205 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5206 struct i915_vma *vma;
5208 list_for_each_entry(vma, &o->vma_list, vma_link)
5209 if (vma->vm == ggtt &&
5210 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5211 drm_mm_node_allocated(&vma->node))
5217 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5219 struct i915_vma *vma;
5221 list_for_each_entry(vma, &o->vma_list, vma_link)
5222 if (drm_mm_node_allocated(&vma->node))
5228 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5229 struct i915_address_space *vm)
5231 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5232 struct i915_vma *vma;
5234 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5236 BUG_ON(list_empty(&o->vma_list));
5238 list_for_each_entry(vma, &o->vma_list, vma_link) {
5239 if (i915_is_ggtt(vma->vm) &&
5240 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5243 return vma->node.size;
5248 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5250 struct i915_vma *vma;
5251 list_for_each_entry(vma, &obj->vma_list, vma_link)
5252 if (vma->pin_count > 0)
5259 /* Allocate a new GEM object and fill it with the supplied data */
5260 struct drm_i915_gem_object *
5261 i915_gem_object_create_from_data(struct drm_device *dev,
5262 const void *data, size_t size)
5264 struct drm_i915_gem_object *obj;
5265 struct sg_table *sg;
5269 obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5270 if (IS_ERR_OR_NULL(obj))
5273 ret = i915_gem_object_set_to_cpu_domain(obj, true);
5277 ret = i915_gem_object_get_pages(obj);
5281 i915_gem_object_pin_pages(obj);
5283 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5284 i915_gem_object_unpin_pages(obj);
5286 if (WARN_ON(bytes != size)) {
5287 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5295 drm_gem_object_unreference(&obj->base);
5296 return ERR_PTR(ret);