sys/dev/drm/radeon/sumo_dpm.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sumod.h"
  28 #include "r600_dpm.h"
  29 #include "cypress_dpm.h"
  30 #include "sumo_dpm.h"
  31 #include <linux/seq_file.h>
  32
  33 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
  34 #define SUMO_MINIMUM_ENGINE_CLOCK 800
  35 #define BOOST_DPM_LEVEL 7
  36
  37 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
  38 {
  39         SUMO_UTC_DFLT_00,
  40         SUMO_UTC_DFLT_01,
  41         SUMO_UTC_DFLT_02,
  42         SUMO_UTC_DFLT_03,
  43         SUMO_UTC_DFLT_04,
  44         SUMO_UTC_DFLT_05,
  45         SUMO_UTC_DFLT_06,
  46         SUMO_UTC_DFLT_07,
  47         SUMO_UTC_DFLT_08,
  48         SUMO_UTC_DFLT_09,
  49         SUMO_UTC_DFLT_10,
  50         SUMO_UTC_DFLT_11,
  51         SUMO_UTC_DFLT_12,
  52         SUMO_UTC_DFLT_13,
  53         SUMO_UTC_DFLT_14,
  54 };
  55
  56 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
  57 {
  58         SUMO_DTC_DFLT_00,
  59         SUMO_DTC_DFLT_01,
  60         SUMO_DTC_DFLT_02,
  61         SUMO_DTC_DFLT_03,
  62         SUMO_DTC_DFLT_04,
  63         SUMO_DTC_DFLT_05,
  64         SUMO_DTC_DFLT_06,
  65         SUMO_DTC_DFLT_07,
  66         SUMO_DTC_DFLT_08,
  67         SUMO_DTC_DFLT_09,
  68         SUMO_DTC_DFLT_10,
  69         SUMO_DTC_DFLT_11,
  70         SUMO_DTC_DFLT_12,
  71         SUMO_DTC_DFLT_13,
  72         SUMO_DTC_DFLT_14,
  73 };
  74
  75 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
  76 void sumo_dpm_reset_asic(struct radeon_device *rdev);
  77
  78 static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
  79 {
  80         struct sumo_ps *ps = rps->ps_priv;
  81
  82         return ps;
  83 }
  84
  85 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
  86 {
  87         struct sumo_power_info *pi = rdev->pm.dpm.priv;
  88
  89         return pi;
  90 }
  91
  92 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
  93 {
  94         if (enable)
  95                 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
  96         else {
  97                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  98                 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
  99                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
 100                 RREG32(GB_ADDR_CONFIG);
 101         }
 102 }
 103
 104 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
 105 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
 106
 107 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
 108 {
 109         u32 local0;
 110         u32 local1;
 111
 112         local0 = RREG32(CG_CGTT_LOCAL_0);
 113         local1 = RREG32(CG_CGTT_LOCAL_1);
 114
 115         if (enable) {
 116                 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
 117                 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
 118         } else {
 119                 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
 120                 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
 121         }
 122 }
 123
 124 static void sumo_program_git(struct radeon_device *rdev)
 125 {
 126         u32 p, u;
 127         u32 xclk = radeon_get_xclk(rdev);
 128
 129         r600_calculate_u_and_p(SUMO_GICST_DFLT,
 130                                xclk, 16, &p, &u);
 131
 132         WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
 133 }
 134
 135 static void sumo_program_grsd(struct radeon_device *rdev)
 136 {
 137         u32 p, u;
 138         u32 xclk = radeon_get_xclk(rdev);
 139         u32 grs = 256 * 25 / 100;
 140
 141         r600_calculate_u_and_p(1, xclk, 14, &p, &u);
 142
 143         WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
 144 }
 145
 146 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
 147 {
 148         sumo_program_git(rdev);
 149         sumo_program_grsd(rdev);
 150 }
 151
 152 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
 153 {
 154         u32 rcu_pwr_gating_cntl;
 155         u32 p, u;
 156         u32 p_c, p_p, d_p;
 157         u32 r_t, i_t;
 158         u32 xclk = radeon_get_xclk(rdev);
 159
 160         if (rdev->family == CHIP_PALM) {
 161                 p_c = 4;
 162                 d_p = 10;
 163                 r_t = 10;
 164                 i_t = 4;
 165                 p_p = 50 + 1000/200 + 6 * 32;
 166         } else {
 167                 p_c = 16;
 168                 d_p = 50;
 169                 r_t = 50;
 170                 i_t  = 50;
 171                 p_p = 113;
 172         }
 173
 174         WREG32(CG_SCRATCH2, 0x01B60A17);
 175
 176         r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
 177                                xclk, 16, &p, &u);
 178
 179         WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
 180                  ~(PGP_MASK | PGU_MASK));
 181
 182         r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
 183                                xclk, 16, &p, &u);
 184
 185         WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
 186                  ~(PGP_MASK | PGU_MASK));
 187
 188         if (rdev->family == CHIP_PALM) {
 189                 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
 190                 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
 191         } else {
 192                 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
 193                 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
 194         }
 195
 196         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 197         rcu_pwr_gating_cntl &=
 198                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 199         rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
 200         if (rdev->family == CHIP_PALM) {
 201                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 202                 rcu_pwr_gating_cntl |= PCP(0x77);
 203         }
 204         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 205
 206         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 207         rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 208         rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
 209         WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 210
 211         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 212         rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 213         rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
 214         WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 215
 216         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
 217         rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
 218         rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
 219         WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
 220
 221         if (rdev->family == CHIP_PALM)
 222                 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
 223
 224         sumo_smu_pg_init(rdev);
 225
 226         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 227         rcu_pwr_gating_cntl &=
 228                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 229         rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
 230         if (rdev->family == CHIP_PALM) {
 231                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 232                 rcu_pwr_gating_cntl |= PCP(0x77);
 233         }
 234         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 235
 236         if (rdev->family == CHIP_PALM) {
 237                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 238                 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 239                 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
 240                 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 241
 242                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 243                 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 244                 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
 245                 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 246         }
 247
 248         sumo_smu_pg_init(rdev);
 249
 250         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 251         rcu_pwr_gating_cntl &=
 252                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 253         rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
 254
 255         if (rdev->family == CHIP_PALM) {
 256                 rcu_pwr_gating_cntl |= PCV(4);
 257                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 258                 rcu_pwr_gating_cntl |= PCP(0x77);
 259         } else
 260                 rcu_pwr_gating_cntl |= PCV(11);
 261         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 262
 263         if (rdev->family == CHIP_PALM) {
 264                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 265                 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 266                 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
 267                 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 268
 269                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 270                 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 271                 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
 272                 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 273         }
 274
 275         sumo_smu_pg_init(rdev);
 276 }
 277
 278 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
 279 {
 280         if (enable)
 281                 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
 282         else {
 283                 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
 284                 RREG32(GB_ADDR_CONFIG);
 285         }
 286 }
 287
 288 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
 289 {
 290         struct sumo_power_info *pi = sumo_get_pi(rdev);
 291
 292         if (pi->enable_gfx_clock_gating)
 293                 sumo_gfx_clockgating_initialize(rdev);
 294         if (pi->enable_gfx_power_gating)
 295                 sumo_gfx_powergating_initialize(rdev);
 296         if (pi->enable_mg_clock_gating)
 297                 sumo_mg_clockgating_enable(rdev, true);
 298         if (pi->enable_gfx_clock_gating)
 299                 sumo_gfx_clockgating_enable(rdev, true);
 300         if (pi->enable_gfx_power_gating)
 301                 sumo_gfx_powergating_enable(rdev, true);
 302
 303         return 0;
 304 }
 305
 306 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
 307 {
 308         struct sumo_power_info *pi = sumo_get_pi(rdev);
 309
 310         if (pi->enable_gfx_clock_gating)
 311                 sumo_gfx_clockgating_enable(rdev, false);
 312         if (pi->enable_gfx_power_gating)
 313                 sumo_gfx_powergating_enable(rdev, false);
 314         if (pi->enable_mg_clock_gating)
 315                 sumo_mg_clockgating_enable(rdev, false);
 316 }
 317
 318 static void sumo_calculate_bsp(struct radeon_device *rdev,
 319                                u32 high_clk)
 320 {
 321         struct sumo_power_info *pi = sumo_get_pi(rdev);
 322         u32 xclk = radeon_get_xclk(rdev);
 323
 324         pi->pasi = 65535 * 100 / high_clk;
 325         pi->asi = 65535 * 100 / high_clk;
 326
 327         r600_calculate_u_and_p(pi->asi,
 328                                xclk, 16, &pi->bsp, &pi->bsu);
 329
 330         r600_calculate_u_and_p(pi->pasi,
 331                                xclk, 16, &pi->pbsp, &pi->pbsu);
 332
 333         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
 334         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
 335 }
 336
 337 static void sumo_init_bsp(struct radeon_device *rdev)
 338 {
 339         struct sumo_power_info *pi = sumo_get_pi(rdev);
 340
 341         WREG32(CG_BSP_0, pi->psp);
 342 }
 343
 344
 345 static void sumo_program_bsp(struct radeon_device *rdev,
 346                              struct radeon_ps *rps)
 347 {
 348         struct sumo_power_info *pi = sumo_get_pi(rdev);
 349         struct sumo_ps *ps = sumo_get_ps(rps);
 350         u32 i;
 351         u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
 352
 353         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 354                 highest_engine_clock = pi->boost_pl.sclk;
 355
 356         sumo_calculate_bsp(rdev, highest_engine_clock);
 357
 358         for (i = 0; i < ps->num_levels - 1; i++)
 359                 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
 360
 361         WREG32(CG_BSP_0 + (i * 4), pi->psp);
 362
 363         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 364                 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
 365 }
 366
 367 static void sumo_write_at(struct radeon_device *rdev,
 368                           u32 index, u32 value)
 369 {
 370         if (index == 0)
 371                 WREG32(CG_AT_0, value);
 372         else if (index == 1)
 373                 WREG32(CG_AT_1, value);
 374         else if (index == 2)
 375                 WREG32(CG_AT_2, value);
 376         else if (index == 3)
 377                 WREG32(CG_AT_3, value);
 378         else if (index == 4)
 379                 WREG32(CG_AT_4, value);
 380         else if (index == 5)
 381                 WREG32(CG_AT_5, value);
 382         else if (index == 6)
 383                 WREG32(CG_AT_6, value);
 384         else if (index == 7)
 385                 WREG32(CG_AT_7, value);
 386 }
 387
 388 static void sumo_program_at(struct radeon_device *rdev,
 389                             struct radeon_ps *rps)
 390 {
 391         struct sumo_power_info *pi = sumo_get_pi(rdev);
 392         struct sumo_ps *ps = sumo_get_ps(rps);
 393         u32 asi;
 394         u32 i;
 395         u32 m_a;
 396         u32 a_t;
 397         u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
 398         u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
 399
 400         r[0] = SUMO_R_DFLT0;
 401         r[1] = SUMO_R_DFLT1;
 402         r[2] = SUMO_R_DFLT2;
 403         r[3] = SUMO_R_DFLT3;
 404         r[4] = SUMO_R_DFLT4;
 405
 406         l[0] = SUMO_L_DFLT0;
 407         l[1] = SUMO_L_DFLT1;
 408         l[2] = SUMO_L_DFLT2;
 409         l[3] = SUMO_L_DFLT3;
 410         l[4] = SUMO_L_DFLT4;
 411
 412         for (i = 0; i < ps->num_levels; i++) {
 413                 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
 414
 415                 m_a = asi * ps->levels[i].sclk / 100;
 416
 417                 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
 418
 419                 sumo_write_at(rdev, i, a_t);
 420         }
 421
 422         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
 423                 asi = pi->pasi;
 424
 425                 m_a = asi * pi->boost_pl.sclk / 100;
 426
 427                 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
 428                         CG_L(m_a * l[ps->num_levels - 1] / 100);
 429
 430                 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
 431         }
 432 }
 433
 434 static void sumo_program_tp(struct radeon_device *rdev)
 435 {
 436         int i;
 437         enum r600_td td = R600_TD_DFLT;
 438
 439         for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
 440                 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
 441                 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
 442         }
 443
 444         if (td == R600_TD_AUTO)
 445                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
 446         else
 447                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
 448
 449         if (td == R600_TD_UP)
 450                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
 451
 452         if (td == R600_TD_DOWN)
 453                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
 454 }
 455
 456 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
 457 {
 458         WREG32(CG_FTV, vrc);
 459 }
 460
 461 void sumo_clear_vc(struct radeon_device *rdev)
 462 {
 463         WREG32(CG_FTV, 0);
 464 }
 465
 466 void sumo_program_sstp(struct radeon_device *rdev)
 467 {
 468         u32 p, u;
 469         u32 xclk = radeon_get_xclk(rdev);
 470
 471         r600_calculate_u_and_p(SUMO_SST_DFLT,
 472                                xclk, 16, &p, &u);
 473
 474         WREG32(CG_SSP, SSTU(u) | SST(p));
 475 }
 476
 477 static void sumo_set_divider_value(struct radeon_device *rdev,
 478                                    u32 index, u32 divider)
 479 {
 480         u32 reg_index = index / 4;
 481         u32 field_index = index % 4;
 482
 483         if (field_index == 0)
 484                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 485                          SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
 486         else if (field_index == 1)
 487                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 488                          SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
 489         else if (field_index == 2)
 490                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 491                          SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
 492         else if (field_index == 3)
 493                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 494                          SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
 495 }
 496
 497 static void sumo_set_ds_dividers(struct radeon_device *rdev,
 498                                  u32 index, u32 divider)
 499 {
 500         struct sumo_power_info *pi = sumo_get_pi(rdev);
 501
 502         if (pi->enable_sclk_ds) {
 503                 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
 504
 505                 dpm_ctrl &= ~(0x7 << (index * 3));
 506                 dpm_ctrl |= (divider << (index * 3));
 507                 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
 508         }
 509 }
 510
 511 static void sumo_set_ss_dividers(struct radeon_device *rdev,
 512                                  u32 index, u32 divider)
 513 {
 514         struct sumo_power_info *pi = sumo_get_pi(rdev);
 515
 516         if (pi->enable_sclk_ds) {
 517                 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
 518
 519                 dpm_ctrl &= ~(0x7 << (index * 3));
 520                 dpm_ctrl |= (divider << (index * 3));
 521                 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
 522         }
 523 }
 524
 525 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
 526 {
 527         u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
 528
 529         voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
 530         voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
 531         WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
 532 }
 533
 534 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
 535 {
 536         struct sumo_power_info *pi = sumo_get_pi(rdev);
 537         u32 temp = gnb_slow;
 538         u32 cg_sclk_dpm_ctrl_3;
 539
 540         if (pi->driver_nbps_policy_disable)
 541                 temp = 1;
 542
 543         cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
 544         cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
 545         cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
 546
 547         WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
 548 }
 549
 550 static void sumo_program_power_level(struct radeon_device *rdev,
 551                                      struct sumo_pl *pl, u32 index)
 552 {
 553         struct sumo_power_info *pi = sumo_get_pi(rdev);
 554         int ret;
 555         struct atom_clock_dividers dividers;
 556         u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
 557
 558         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 559                                              pl->sclk, false, &dividers);
 560         if (ret)
 561                 return;
 562
 563         sumo_set_divider_value(rdev, index, dividers.post_div);
 564
 565         sumo_set_vid(rdev, index, pl->vddc_index);
 566
 567         if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
 568                 if (ds_en)
 569                         WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
 570         } else {
 571                 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
 572                 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
 573
 574                 if (!ds_en)
 575                         WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
 576         }
 577
 578         sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
 579
 580         if (pi->enable_boost)
 581                 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
 582 }
 583
 584 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
 585 {
 586         u32 reg_index = index / 4;
 587         u32 field_index = index % 4;
 588
 589         if (field_index == 0)
 590                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 591                          enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
 592         else if (field_index == 1)
 593                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 594                          enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
 595         else if (field_index == 2)
 596                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 597                          enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
 598         else if (field_index == 3)
 599                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 600                          enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
 601 }
 602
 603 static bool sumo_dpm_enabled(struct radeon_device *rdev)
 604 {
 605         if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
 606                 return true;
 607         else
 608                 return false;
 609 }
 610
 611 static void sumo_start_dpm(struct radeon_device *rdev)
 612 {
 613         WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
 614 }
 615
 616 static void sumo_stop_dpm(struct radeon_device *rdev)
 617 {
 618         WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
 619 }
 620
 621 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
 622 {
 623         if (enable)
 624                 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
 625         else
 626                 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
 627 }
 628
 629 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
 630 {
 631         int i;
 632
 633         sumo_set_forced_mode(rdev, true);
 634         for (i = 0; i < rdev->usec_timeout; i++) {
 635                 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
 636                         break;
 637                 udelay(1);
 638         }
 639 }
 640
 641 static void sumo_wait_for_level_0(struct radeon_device *rdev)
 642 {
 643         int i;
 644
 645         for (i = 0; i < rdev->usec_timeout; i++) {
 646                 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
 647                         break;
 648                 udelay(1);
 649         }
 650         for (i = 0; i < rdev->usec_timeout; i++) {
 651                 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
 652                         break;
 653                 udelay(1);
 654         }
 655 }
 656
 657 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
 658 {
 659         sumo_set_forced_mode(rdev, false);
 660 }
 661
 662 static void sumo_enable_power_level_0(struct radeon_device *rdev)
 663 {
 664         sumo_power_level_enable(rdev, 0, true);
 665 }
 666
 667 static void sumo_patch_boost_state(struct radeon_device *rdev,
 668                                    struct radeon_ps *rps)
 669 {
 670         struct sumo_power_info *pi = sumo_get_pi(rdev);
 671         struct sumo_ps *new_ps = sumo_get_ps(rps);
 672
 673         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
 674                 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
 675                 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
 676                 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
 677                 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
 678         }
 679 }
 680
 681 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
 682                                              struct radeon_ps *new_rps,
 683                                              struct radeon_ps *old_rps)
 684 {
 685         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 686         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 687         u32 nbps1_old = 0;
 688         u32 nbps1_new = 0;
 689
 690         if (old_ps != NULL)
 691                 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
 692
 693         nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
 694
 695         if (nbps1_old == 1 && nbps1_new == 0)
 696                 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
 697 }
 698
 699 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
 700                                               struct radeon_ps *new_rps,
 701                                               struct radeon_ps *old_rps)
 702 {
 703         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 704         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 705         u32 nbps1_old = 0;
 706         u32 nbps1_new = 0;
 707
 708         if (old_ps != NULL)
 709                 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
 710
 711         nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
 712
 713         if (nbps1_old == 0 && nbps1_new == 1)
 714                 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
 715 }
 716
 717 static void sumo_enable_boost(struct radeon_device *rdev,
 718                               struct radeon_ps *rps,
 719                               bool enable)
 720 {
 721         struct sumo_ps *new_ps = sumo_get_ps(rps);
 722
 723         if (enable) {
 724                 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 725                         sumo_boost_state_enable(rdev, true);
 726         } else
 727                 sumo_boost_state_enable(rdev, false);
 728 }
 729
 730 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
 731 {
 732         WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
 733 }
 734
 735 static void sumo_set_forced_level_0(struct radeon_device *rdev)
 736 {
 737         sumo_set_forced_level(rdev, 0);
 738 }
 739
 740 static void sumo_program_wl(struct radeon_device *rdev,
 741                             struct radeon_ps *rps)
 742 {
 743         struct sumo_ps *new_ps = sumo_get_ps(rps);
 744         u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
 745
 746         dpm_ctrl4 &= 0xFFFFFF00;
 747         dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
 748
 749         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 750                 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
 751
 752         WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
 753 }
 754
 755 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
 756                                              struct radeon_ps *new_rps,
 757                                              struct radeon_ps *old_rps)
 758 {
 759         struct sumo_power_info *pi = sumo_get_pi(rdev);
 760         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 761         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 762         u32 i;
 763         u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
 764
 765         for (i = 0; i < new_ps->num_levels; i++) {
 766                 sumo_program_power_level(rdev, &new_ps->levels[i], i);
 767                 sumo_power_level_enable(rdev, i, true);
 768         }
 769
 770         for (i = new_ps->num_levels; i < n_current_state_levels; i++)
 771                 sumo_power_level_enable(rdev, i, false);
 772
 773         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 774                 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
 775 }
 776
 777 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
 778 {
 779         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
 780 }
 781
 782 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
 783 {
 784         WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
 785 }
 786
 787 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
 788 {
 789         struct sumo_power_info *pi = sumo_get_pi(rdev);
 790         struct atom_clock_dividers dividers;
 791         int ret;
 792
 793         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 794                                              pi->acpi_pl.sclk,
 795                                              false, &dividers);
 796         if (ret)
 797                 return;
 798
 799         WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
 800         WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
 801 }
 802
 803 static void sumo_program_bootup_state(struct radeon_device *rdev)
 804 {
 805         struct sumo_power_info *pi = sumo_get_pi(rdev);
 806         u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
 807         u32 i;
 808
 809         sumo_program_power_level(rdev, &pi->boot_pl, 0);
 810
 811         dpm_ctrl4 &= 0xFFFFFF00;
 812         WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
 813
 814         for (i = 1; i < 8; i++)
 815                 sumo_power_level_enable(rdev, i, false);
 816 }
 817
 818 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
 819                                   struct radeon_ps *new_rps,
 820                                   struct radeon_ps *old_rps)
 821 {
 822         struct sumo_power_info *pi = sumo_get_pi(rdev);
 823
 824         if (pi->enable_gfx_power_gating) {
 825                 sumo_gfx_powergating_enable(rdev, false);
 826         }
 827
 828         radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
 829
 830         if (pi->enable_gfx_power_gating) {
 831                 if (!pi->disable_gfx_power_gating_in_uvd ||
 832                     !r600_is_uvd_state(new_rps->class, new_rps->class2))
 833                         sumo_gfx_powergating_enable(rdev, true);
 834         }
 835 }
 836
 837 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
 838                                                     struct radeon_ps *new_rps,
 839                                                     struct radeon_ps *old_rps)
 840 {
 841         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 842         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
 843
 844         if ((new_rps->vclk == old_rps->vclk) &&
 845             (new_rps->dclk == old_rps->dclk))
 846                 return;
 847
 848         if (new_ps->levels[new_ps->num_levels - 1].sclk >=
 849             current_ps->levels[current_ps->num_levels - 1].sclk)
 850                 return;
 851
 852         sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
 853 }
 854
 855 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
 856                                                    struct radeon_ps *new_rps,
 857                                                    struct radeon_ps *old_rps)
 858 {
 859         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 860         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
 861
 862         if ((new_rps->vclk == old_rps->vclk) &&
 863             (new_rps->dclk == old_rps->dclk))
 864                 return;
 865
 866         if (new_ps->levels[new_ps->num_levels - 1].sclk <
 867             current_ps->levels[current_ps->num_levels - 1].sclk)
 868                 return;
 869
 870         sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
 871 }
 872
 873 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
 874 {
 875 /* This bit selects who handles display phy powergating.
 876  * Clear the bit to let atom handle it.
 877  * Set it to let the driver handle it.
 878  * For now we just let atom handle it.
 879  */
 880 #if 0
 881         u32 v = RREG32(DOUT_SCRATCH3);
 882
 883         if (enable)
 884                 v |= 0x4;
 885         else
 886                 v &= 0xFFFFFFFB;
 887
 888         WREG32(DOUT_SCRATCH3, v);
 889 #endif
 890 }
 891
 892 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
 893 {
 894         if (enable) {
 895                 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
 896                 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
 897                 u32 t = 1;
 898
 899                 deep_sleep_cntl &= ~R_DIS;
 900                 deep_sleep_cntl &= ~HS_MASK;
 901                 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
 902
 903                 deep_sleep_cntl2 |= LB_UFP_EN;
 904                 deep_sleep_cntl2 &= INOUT_C_MASK;
 905                 deep_sleep_cntl2 |= INOUT_C(0xf);
 906
 907                 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
 908                 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
 909         } else
 910                 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
 911 }
 912
 913 static void sumo_program_bootup_at(struct radeon_device *rdev)
 914 {
 915         WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
 916         WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
 917 }
 918
 919 static void sumo_reset_am(struct radeon_device *rdev)
 920 {
 921         WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
 922 }
 923
 924 static void sumo_start_am(struct radeon_device *rdev)
 925 {
 926         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
 927 }
 928
 929 static void sumo_program_ttp(struct radeon_device *rdev)
 930 {
 931         u32 xclk = radeon_get_xclk(rdev);
 932         u32 p, u;
 933         u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
 934
 935         r600_calculate_u_and_p(1000,
 936                                xclk, 16, &p, &u);
 937
 938         cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
 939         cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
 940
 941         WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
 942 }
 943
 944 static void sumo_program_ttt(struct radeon_device *rdev)
 945 {
 946         u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
 947         struct sumo_power_info *pi = sumo_get_pi(rdev);
 948
 949         cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
 950         cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
 951
 952         WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
 953 }
 954
 955
 956 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
 957 {
 958         if (enable) {
 959                 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
 960                 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
 961         } else {
 962                 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
 963                 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
 964         }
 965 }
 966
 967 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
 968 {
 969         WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
 970                  ~CNB_THERMTHRO_MASK_SCLK);
 971 }
 972
 973 static void sumo_program_dc_hto(struct radeon_device *rdev)
 974 {
 975         u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
 976         u32 p, u;
 977         u32 xclk = radeon_get_xclk(rdev);
 978
 979         r600_calculate_u_and_p(100000,
 980                                xclk, 14, &p, &u);
 981
 982         cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
 983         cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
 984
 985         WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
 986 }
 987
 988 static void sumo_force_nbp_state(struct radeon_device *rdev,
 989                                  struct radeon_ps *rps)
 990 {
 991         struct sumo_power_info *pi = sumo_get_pi(rdev);
 992         struct sumo_ps *new_ps = sumo_get_ps(rps);
 993
 994         if (!pi->driver_nbps_policy_disable) {
 995                 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
 996                         WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
 997                 else
 998                         WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
 999         }
1000 }
1001
1002 u32 sumo_get_sleep_divider_from_id(u32 id)
1003 {
1004         return 1 << id;
1005 }
1006
1007 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1008                                          u32 sclk,
1009                                          u32 min_sclk_in_sr)
1010 {
1011         struct sumo_power_info *pi = sumo_get_pi(rdev);
1012         u32 i;
1013         u32 temp;
1014         u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
1015                 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
1016
1017         if (sclk < min)
1018                 return 0;
1019
1020         if (!pi->enable_sclk_ds)
1021                 return 0;
1022
1023         for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1024                 temp = sclk / sumo_get_sleep_divider_from_id(i);
1025
1026                 if (temp >= min || i == 0)
1027                         break;
1028         }
1029         return i;
1030 }
1031
1032 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1033                                        u32 lower_limit)
1034 {
1035         struct sumo_power_info *pi = sumo_get_pi(rdev);
1036         u32 i;
1037
1038         for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1039                 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1040                         return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1041         }
1042
1043         return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1044 }
1045
1046 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1047                                      struct sumo_ps *ps,
1048                                      struct sumo_ps *current_ps)
1049 {
1050         struct sumo_power_info *pi = sumo_get_pi(rdev);
1051         u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1052         u32 current_vddc;
1053         u32 current_sclk;
1054         u32 current_index = 0;
1055
1056         if (current_ps) {
1057                 current_vddc = current_ps->levels[current_index].vddc_index;
1058                 current_sclk = current_ps->levels[current_index].sclk;
1059         } else {
1060                 current_vddc = pi->boot_pl.vddc_index;
1061                 current_sclk = pi->boot_pl.sclk;
1062         }
1063
1064         ps->levels[0].vddc_index = current_vddc;
1065
1066         if (ps->levels[0].sclk > current_sclk)
1067                 ps->levels[0].sclk = current_sclk;
1068
1069         ps->levels[0].ss_divider_index =
1070                 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1071
1072         ps->levels[0].ds_divider_index =
1073                 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1074
1075         if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1076                 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1077
1078         if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1079                 if (ps->levels[0].ss_divider_index > 1)
1080                         ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1081         }
1082
1083         if (ps->levels[0].ss_divider_index == 0)
1084                 ps->levels[0].ds_divider_index = 0;
1085
1086         if (ps->levels[0].ds_divider_index == 0)
1087                 ps->levels[0].ss_divider_index = 0;
1088 }
1089
1090 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1091                                           struct radeon_ps *new_rps,
1092                                           struct radeon_ps *old_rps)
1093 {
1094         struct sumo_ps *ps = sumo_get_ps(new_rps);
1095         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1096         struct sumo_power_info *pi = sumo_get_pi(rdev);
1097         u32 min_voltage = 0; /* ??? */
1098         u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1099         u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1100         u32 i;
1101
1102         if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1103                 return sumo_patch_thermal_state(rdev, ps, current_ps);
1104
1105         if (pi->enable_boost) {
1106                 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1107                         ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1108         }
1109
1110         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1111             (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1112             (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1113                 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1114
1115         for (i = 0; i < ps->num_levels; i++) {
1116                 if (ps->levels[i].vddc_index < min_voltage)
1117                         ps->levels[i].vddc_index = min_voltage;
1118
1119                 if (ps->levels[i].sclk < min_sclk)
1120                         ps->levels[i].sclk =
1121                                 sumo_get_valid_engine_clock(rdev, min_sclk);
1122
1123                 ps->levels[i].ss_divider_index =
1124                         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1125
1126                 ps->levels[i].ds_divider_index =
1127                         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1128
1129                 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1130                         ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1131
1132                 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1133                         if (ps->levels[i].ss_divider_index > 1)
1134                                 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1135                 }
1136
1137                 if (ps->levels[i].ss_divider_index == 0)
1138                         ps->levels[i].ds_divider_index = 0;
1139
1140                 if (ps->levels[i].ds_divider_index == 0)
1141                         ps->levels[i].ss_divider_index = 0;
1142
1143                 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1144                         ps->levels[i].allow_gnb_slow = 1;
1145                 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1146                          (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1147                         ps->levels[i].allow_gnb_slow = 0;
1148                 else if (i == ps->num_levels - 1)
1149                         ps->levels[i].allow_gnb_slow = 0;
1150                 else
1151                         ps->levels[i].allow_gnb_slow = 1;
1152         }
1153 }
1154
1155 static void sumo_cleanup_asic(struct radeon_device *rdev)
1156 {
1157         sumo_take_smu_control(rdev, false);
1158 }
1159
1160 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1161                                               int min_temp, int max_temp)
1162 {
1163         int low_temp = 0 * 1000;
1164         int high_temp = 255 * 1000;
1165
1166         if (low_temp < min_temp)
1167                 low_temp = min_temp;
1168         if (high_temp > max_temp)
1169                 high_temp = max_temp;
1170         if (high_temp < low_temp) {
1171                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1172                 return -EINVAL;
1173         }
1174
1175         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1176         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1177
1178         rdev->pm.dpm.thermal.min_temp = low_temp;
1179         rdev->pm.dpm.thermal.max_temp = high_temp;
1180
1181         return 0;
1182 }
1183
1184 static void sumo_update_current_ps(struct radeon_device *rdev,
1185                                    struct radeon_ps *rps)
1186 {
1187         struct sumo_ps *new_ps = sumo_get_ps(rps);
1188         struct sumo_power_info *pi = sumo_get_pi(rdev);
1189
1190         pi->current_rps = *rps;
1191         pi->current_ps = *new_ps;
1192         pi->current_rps.ps_priv = &pi->current_ps;
1193 }
1194
1195 static void sumo_update_requested_ps(struct radeon_device *rdev,
1196                                      struct radeon_ps *rps)
1197 {
1198         struct sumo_ps *new_ps = sumo_get_ps(rps);
1199         struct sumo_power_info *pi = sumo_get_pi(rdev);
1200
1201         pi->requested_rps = *rps;
1202         pi->requested_ps = *new_ps;
1203         pi->requested_rps.ps_priv = &pi->requested_ps;
1204 }
1205
1206 int sumo_dpm_enable(struct radeon_device *rdev)
1207 {
1208         struct sumo_power_info *pi = sumo_get_pi(rdev);
1209
1210         if (sumo_dpm_enabled(rdev))
1211                 return -EINVAL;
1212
1213         sumo_program_bootup_state(rdev);
1214         sumo_init_bsp(rdev);
1215         sumo_reset_am(rdev);
1216         sumo_program_tp(rdev);
1217         sumo_program_bootup_at(rdev);
1218         sumo_start_am(rdev);
1219         if (pi->enable_auto_thermal_throttling) {
1220                 sumo_program_ttp(rdev);
1221                 sumo_program_ttt(rdev);
1222         }
1223         sumo_program_dc_hto(rdev);
1224         sumo_program_power_level_enter_state(rdev);
1225         sumo_enable_voltage_scaling(rdev, true);
1226         sumo_program_sstp(rdev);
1227         sumo_program_vc(rdev, SUMO_VRC_DFLT);
1228         sumo_override_cnb_thermal_events(rdev);
1229         sumo_start_dpm(rdev);
1230         sumo_wait_for_level_0(rdev);
1231         if (pi->enable_sclk_ds)
1232                 sumo_enable_sclk_ds(rdev, true);
1233         if (pi->enable_boost)
1234                 sumo_enable_boost_timer(rdev);
1235
1236         sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1237
1238         return 0;
1239 }
1240
1241 int sumo_dpm_late_enable(struct radeon_device *rdev)
1242 {
1243         int ret;
1244
1245         ret = sumo_enable_clock_power_gating(rdev);
1246         if (ret)
1247                 return ret;
1248
1249         if (rdev->irq.installed &&
1250             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1251                 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1252                 if (ret)
1253                         return ret;
1254                 rdev->irq.dpm_thermal = true;
1255                 radeon_irq_set(rdev);
1256         }
1257
1258         return 0;
1259 }
1260
1261 void sumo_dpm_disable(struct radeon_device *rdev)
1262 {
1263         struct sumo_power_info *pi = sumo_get_pi(rdev);
1264
1265         if (!sumo_dpm_enabled(rdev))
1266                 return;
1267         sumo_disable_clock_power_gating(rdev);
1268         if (pi->enable_sclk_ds)
1269                 sumo_enable_sclk_ds(rdev, false);
1270         sumo_clear_vc(rdev);
1271         sumo_wait_for_level_0(rdev);
1272         sumo_stop_dpm(rdev);
1273         sumo_enable_voltage_scaling(rdev, false);
1274
1275         if (rdev->irq.installed &&
1276             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1277                 rdev->irq.dpm_thermal = false;
1278                 radeon_irq_set(rdev);
1279         }
1280
1281         sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1282 }
1283
1284 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1285 {
1286         struct sumo_power_info *pi = sumo_get_pi(rdev);
1287         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1288         struct radeon_ps *new_ps = &requested_ps;
1289
1290         sumo_update_requested_ps(rdev, new_ps);
1291
1292         if (pi->enable_dynamic_patch_ps)
1293                 sumo_apply_state_adjust_rules(rdev,
1294                                               &pi->requested_rps,
1295                                               &pi->current_rps);
1296
1297         return 0;
1298 }
1299
1300 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1301 {
1302         struct sumo_power_info *pi = sumo_get_pi(rdev);
1303         struct radeon_ps *new_ps = &pi->requested_rps;
1304         struct radeon_ps *old_ps = &pi->current_rps;
1305
1306         if (pi->enable_dpm)
1307                 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1308         if (pi->enable_boost) {
1309                 sumo_enable_boost(rdev, new_ps, false);
1310                 sumo_patch_boost_state(rdev, new_ps);
1311         }
1312         if (pi->enable_dpm) {
1313                 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1314                 sumo_enable_power_level_0(rdev);
1315                 sumo_set_forced_level_0(rdev);
1316                 sumo_set_forced_mode_enabled(rdev);
1317                 sumo_wait_for_level_0(rdev);
1318                 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1319                 sumo_program_wl(rdev, new_ps);
1320                 sumo_program_bsp(rdev, new_ps);
1321                 sumo_program_at(rdev, new_ps);
1322                 sumo_force_nbp_state(rdev, new_ps);
1323                 sumo_set_forced_mode_disabled(rdev);
1324                 sumo_set_forced_mode_enabled(rdev);
1325                 sumo_set_forced_mode_disabled(rdev);
1326                 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1327         }
1328         if (pi->enable_boost)
1329                 sumo_enable_boost(rdev, new_ps, true);
1330         if (pi->enable_dpm)
1331                 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1332
1333         return 0;
1334 }
1335
1336 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1337 {
1338         struct sumo_power_info *pi = sumo_get_pi(rdev);
1339         struct radeon_ps *new_ps = &pi->requested_rps;
1340
1341         sumo_update_current_ps(rdev, new_ps);
1342 }
1343
1344 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1345 {
1346         sumo_program_bootup_state(rdev);
1347         sumo_enable_power_level_0(rdev);
1348         sumo_set_forced_level_0(rdev);
1349         sumo_set_forced_mode_enabled(rdev);
1350         sumo_wait_for_level_0(rdev);
1351         sumo_set_forced_mode_disabled(rdev);
1352         sumo_set_forced_mode_enabled(rdev);
1353         sumo_set_forced_mode_disabled(rdev);
1354 }
1355
1356 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1357 {
1358         struct sumo_power_info *pi = sumo_get_pi(rdev);
1359
1360         sumo_initialize_m3_arb(rdev);
1361         pi->fw_version = sumo_get_running_fw_version(rdev);
1362         DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1363         sumo_program_acpi_power_level(rdev);
1364         sumo_enable_acpi_pm(rdev);
1365         sumo_take_smu_control(rdev, true);
1366 }
1367
1368 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1369 {
1370
1371 }
1372
1373 union power_info {
1374         struct _ATOM_POWERPLAY_INFO info;
1375         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1376         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1377         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1378         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1379         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1380 };
1381
1382 union pplib_clock_info {
1383         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1384         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1385         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1386         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1387 };
1388
1389 union pplib_power_state {
1390         struct _ATOM_PPLIB_STATE v1;
1391         struct _ATOM_PPLIB_STATE_V2 v2;
1392 };
1393
1394 static void sumo_patch_boot_state(struct radeon_device *rdev,
1395                                   struct sumo_ps *ps)
1396 {
1397         struct sumo_power_info *pi = sumo_get_pi(rdev);
1398
1399         ps->num_levels = 1;
1400         ps->flags = 0;
1401         ps->levels[0] = pi->boot_pl;
1402 }
1403
1404 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1405                                             struct radeon_ps *rps,
1406                                             struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1407                                             u8 table_rev)
1408 {
1409         struct sumo_ps *ps = sumo_get_ps(rps);
1410
1411         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1412         rps->class = le16_to_cpu(non_clock_info->usClassification);
1413         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1414
1415         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1416                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1417                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1418         } else {
1419                 rps->vclk = 0;
1420                 rps->dclk = 0;
1421         }
1422
1423         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1424                 rdev->pm.dpm.boot_ps = rps;
1425                 sumo_patch_boot_state(rdev, ps);
1426         }
1427         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1428                 rdev->pm.dpm.uvd_ps = rps;
1429 }
1430
1431 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1432                                         struct radeon_ps *rps, int index,
1433                                         union pplib_clock_info *clock_info)
1434 {
1435         struct sumo_power_info *pi = sumo_get_pi(rdev);
1436         struct sumo_ps *ps = sumo_get_ps(rps);
1437         struct sumo_pl *pl = &ps->levels[index];
1438         u32 sclk;
1439
1440         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1441         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1442         pl->sclk = sclk;
1443         pl->vddc_index = clock_info->sumo.vddcIndex;
1444         pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1445
1446         ps->num_levels = index + 1;
1447
1448         if (pi->enable_sclk_ds) {
1449                 pl->ds_divider_index = 5;
1450                 pl->ss_divider_index = 4;
1451         }
1452 }
1453
1454 static int sumo_parse_power_table(struct radeon_device *rdev)
1455 {
1456         struct radeon_mode_info *mode_info = &rdev->mode_info;
1457         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1458         union pplib_power_state *power_state;
1459         int i, j, k, non_clock_array_index, clock_array_index;
1460         union pplib_clock_info *clock_info;
1461         struct _StateArray *state_array;
1462         struct _ClockInfoArray *clock_info_array;
1463         struct _NonClockInfoArray *non_clock_info_array;
1464         union power_info *power_info;
1465         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1466         u16 data_offset;
1467         u8 frev, crev;
1468         u8 *power_state_offset;
1469         struct sumo_ps *ps;
1470
1471         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1472                                    &frev, &crev, &data_offset))
1473                 return -EINVAL;
1474         power_info = (union power_info *)((uint8_t*)mode_info->atom_context->bios + data_offset);
1475
1476         state_array = (struct _StateArray *)
1477                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1478                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
1479         clock_info_array = (struct _ClockInfoArray *)
1480                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1481                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1482         non_clock_info_array = (struct _NonClockInfoArray *)
1483                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1484                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1485
1486         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1487                                   state_array->ucNumEntries, GFP_KERNEL);
1488         if (!rdev->pm.dpm.ps)
1489                 return -ENOMEM;
1490         power_state_offset = (u8 *)state_array->states;
1491         for (i = 0; i < state_array->ucNumEntries; i++) {
1492                 u8 *idx;
1493                 power_state = (union pplib_power_state *)power_state_offset;
1494                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1495                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1496                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
1497                 if (!rdev->pm.power_state[i].clock_info)
1498                         return -EINVAL;
1499                 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1500                 if (ps == NULL) {
1501                         kfree(rdev->pm.dpm.ps);
1502                         return -ENOMEM;
1503                 }
1504                 rdev->pm.dpm.ps[i].ps_priv = ps;
1505                 k = 0;
1506                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1507                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1508                         clock_array_index = idx[j];
1509                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1510                                 break;
1511
1512                         clock_info = (union pplib_clock_info *)
1513                                 ((u8 *)&clock_info_array->clockInfo[0] +
1514                                  (clock_array_index * clock_info_array->ucEntrySize));
1515                         sumo_parse_pplib_clock_info(rdev,
1516                                                     &rdev->pm.dpm.ps[i], k,
1517                                                     clock_info);
1518                         k++;
1519                 }
1520                 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1521                                                 non_clock_info,
1522                                                 non_clock_info_array->ucEntrySize);
1523                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1524         }
1525         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1526         return 0;
1527 }
1528
1529 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1530                               struct sumo_vid_mapping_table *vid_mapping_table,
1531                               u32 vid_2bit)
1532 {
1533         u32 i;
1534
1535         for (i = 0; i < vid_mapping_table->num_entries; i++) {
1536                 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1537                         return vid_mapping_table->entries[i].vid_7bit;
1538         }
1539
1540         return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1541 }
1542
1543 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,
1544                               struct sumo_vid_mapping_table *vid_mapping_table,
1545                               u32 vid_7bit)
1546 {
1547         u32 i;
1548
1549         for (i = 0; i < vid_mapping_table->num_entries; i++) {
1550                 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
1551                         return vid_mapping_table->entries[i].vid_2bit;
1552         }
1553
1554         return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
1555 }
1556
1557 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1558                                                u32 vid_2bit)
1559 {
1560         struct sumo_power_info *pi = sumo_get_pi(rdev);
1561         u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1562
1563         if (vid_7bit > 0x7C)
1564                 return 0;
1565
1566         return (15500 - vid_7bit * 125 + 5) / 10;
1567 }
1568
1569 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1570                                                          struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1571                                                          ATOM_CLK_VOLT_CAPABILITY *table)
1572 {
1573         u32 i;
1574
1575         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1576                 if (table[i].ulMaximumSupportedCLK == 0)
1577                         break;
1578
1579                 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1580                         table[i].ulMaximumSupportedCLK;
1581         }
1582
1583         disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1584
1585         if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1586                 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1587                 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1588         }
1589 }
1590
1591 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1592                                                struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1593                                                ATOM_AVAILABLE_SCLK_LIST *table)
1594 {
1595         u32 i;
1596         u32 n = 0;
1597         u32 prev_sclk = 0;
1598
1599         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1600                 if (table[i].ulSupportedSCLK > prev_sclk) {
1601                         sclk_voltage_mapping_table->entries[n].sclk_frequency =
1602                                 table[i].ulSupportedSCLK;
1603                         sclk_voltage_mapping_table->entries[n].vid_2bit =
1604                                 table[i].usVoltageIndex;
1605                         prev_sclk = table[i].ulSupportedSCLK;
1606                         n++;
1607                 }
1608         }
1609
1610         sclk_voltage_mapping_table->num_max_dpm_entries = n;
1611 }
1612
1613 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1614                                       struct sumo_vid_mapping_table *vid_mapping_table,
1615                                       ATOM_AVAILABLE_SCLK_LIST *table)
1616 {
1617         u32 i, j;
1618
1619         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1620                 if (table[i].ulSupportedSCLK != 0) {
1621                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1622                                 table[i].usVoltageID;
1623                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1624                                 table[i].usVoltageIndex;
1625                 }
1626         }
1627
1628         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1629                 if (vid_mapping_table->entries[i].vid_7bit == 0) {
1630                         for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1631                                 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1632                                         vid_mapping_table->entries[i] =
1633                                                 vid_mapping_table->entries[j];
1634                                         vid_mapping_table->entries[j].vid_7bit = 0;
1635                                         break;
1636                                 }
1637                         }
1638
1639                         if (j == SUMO_MAX_NUMBER_VOLTAGES)
1640                                 break;
1641                 }
1642         }
1643
1644         vid_mapping_table->num_entries = i;
1645 }
1646
1647 union igp_info {
1648         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1649         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1650         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1651         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1652 };
1653
1654 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1655 {
1656         struct sumo_power_info *pi = sumo_get_pi(rdev);
1657         struct radeon_mode_info *mode_info = &rdev->mode_info;
1658         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1659         union igp_info *igp_info;
1660         u8 frev, crev;
1661         u16 data_offset;
1662         int i;
1663
1664         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1665                                    &frev, &crev, &data_offset)) {
1666                 igp_info = (union igp_info *)((uint8_t*)mode_info->atom_context->bios +
1667                                               data_offset);
1668
1669                 if (crev != 6) {
1670                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1671                         return -EINVAL;
1672                 }
1673                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1674                 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1675                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1676                 pi->sys_info.bootup_nb_voltage_index =
1677                         le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1678                 if (igp_info->info_6.ucHtcTmpLmt == 0)
1679                         pi->sys_info.htc_tmp_lmt = 203;
1680                 else
1681                         pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1682                 if (igp_info->info_6.ucHtcHystLmt == 0)
1683                         pi->sys_info.htc_hyst_lmt = 5;
1684                 else
1685                         pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1686                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1687                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1688                 }
1689                 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1690                         pi->sys_info.csr_m3_arb_cntl_default[i] =
1691                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1692                         pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1693                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1694                         pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1695                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1696                 }
1697                 pi->sys_info.sclk_dpm_boost_margin =
1698                         le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1699                 pi->sys_info.sclk_dpm_throttle_margin =
1700                         le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1701                 pi->sys_info.sclk_dpm_tdp_limit_pg =
1702                         le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1703                 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1704                 pi->sys_info.sclk_dpm_tdp_limit_boost =
1705                         le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1706                 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1707                 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1708                 if (igp_info->info_6.EnableBoost)
1709                         pi->sys_info.enable_boost = true;
1710                 else
1711                         pi->sys_info.enable_boost = false;
1712                 sumo_construct_display_voltage_mapping_table(rdev,
1713                                                              &pi->sys_info.disp_clk_voltage_mapping_table,
1714                                                              igp_info->info_6.sDISPCLK_Voltage);
1715                 sumo_construct_sclk_voltage_mapping_table(rdev,
1716                                                           &pi->sys_info.sclk_voltage_mapping_table,
1717                                                           igp_info->info_6.sAvail_SCLK);
1718                 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1719                                                  igp_info->info_6.sAvail_SCLK);
1720
1721         }
1722         return 0;
1723 }
1724
1725 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1726 {
1727         struct sumo_power_info *pi = sumo_get_pi(rdev);
1728
1729         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1730         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1731         pi->boot_pl.ds_divider_index = 0;
1732         pi->boot_pl.ss_divider_index = 0;
1733         pi->boot_pl.allow_gnb_slow = 1;
1734         pi->acpi_pl = pi->boot_pl;
1735         pi->current_ps.num_levels = 1;
1736         pi->current_ps.levels[0] = pi->boot_pl;
1737 }
1738
1739 int sumo_dpm_init(struct radeon_device *rdev)
1740 {
1741         struct sumo_power_info *pi;
1742         u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1743         int ret;
1744
1745         pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1746         if (pi == NULL)
1747                 return -ENOMEM;
1748         rdev->pm.dpm.priv = pi;
1749
1750         pi->driver_nbps_policy_disable = false;
1751         if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1752                 pi->disable_gfx_power_gating_in_uvd = true;
1753         else
1754                 pi->disable_gfx_power_gating_in_uvd = false;
1755         pi->enable_alt_vddnb = true;
1756         pi->enable_sclk_ds = true;
1757         pi->enable_dynamic_m3_arbiter = false;
1758         pi->enable_dynamic_patch_ps = true;
1759         /* Some PALM chips don't seem to properly ungate gfx when UVD is in use;
1760          * for now just disable gfx PG.
1761          */
1762         if (rdev->family == CHIP_PALM)
1763                 pi->enable_gfx_power_gating = false;
1764         else
1765                 pi->enable_gfx_power_gating = true;
1766         pi->enable_gfx_clock_gating = true;
1767         pi->enable_mg_clock_gating = true;
1768         pi->enable_auto_thermal_throttling = true;
1769
1770         ret = sumo_parse_sys_info_table(rdev);
1771         if (ret)
1772                 return ret;
1773
1774         sumo_construct_boot_and_acpi_state(rdev);
1775
1776         ret = r600_get_platform_caps(rdev);
1777         if (ret)
1778                 return ret;
1779
1780         ret = sumo_parse_power_table(rdev);
1781         if (ret)
1782                 return ret;
1783
1784         pi->pasi = CYPRESS_HASI_DFLT;
1785         pi->asi = RV770_ASI_DFLT;
1786         pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1787         pi->enable_boost = pi->sys_info.enable_boost;
1788         pi->enable_dpm = true;
1789
1790         return 0;
1791 }
1792
1793 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1794                                 struct radeon_ps *rps)
1795 {
1796         int i;
1797         struct sumo_ps *ps = sumo_get_ps(rps);
1798
1799         r600_dpm_print_class_info(rps->class, rps->class2);
1800         r600_dpm_print_cap_info(rps->caps);
1801         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1802         for (i = 0; i < ps->num_levels; i++) {
1803                 struct sumo_pl *pl = &ps->levels[i];
1804                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
1805                        i, pl->sclk,
1806                        sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1807         }
1808         r600_dpm_print_ps_status(rdev, rps);
1809 }
1810
1811 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1812                                                       struct seq_file *m)
1813 {
1814         struct sumo_power_info *pi = sumo_get_pi(rdev);
1815         struct radeon_ps *rps = &pi->current_rps;
1816         struct sumo_ps *ps = sumo_get_ps(rps);
1817         struct sumo_pl *pl;
1818         u32 current_index =
1819                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1820                 CURR_INDEX_SHIFT;
1821
1822         if (current_index == BOOST_DPM_LEVEL) {
1823                 pl = &pi->boost_pl;
1824                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1825                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1826                            current_index, pl->sclk,
1827                            sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1828         } else if (current_index >= ps->num_levels) {
1829                 seq_printf(m, "invalid dpm profile %d\n", current_index);
1830         } else {
1831                 pl = &ps->levels[current_index];
1832                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1833                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1834                            current_index, pl->sclk,
1835                            sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1836         }
1837 }
1838
1839 void sumo_dpm_fini(struct radeon_device *rdev)
1840 {
1841         int i;
1842
1843         sumo_cleanup_asic(rdev); /* ??? */
1844
1845         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1846                 kfree(rdev->pm.dpm.ps[i].ps_priv);
1847         }
1848         kfree(rdev->pm.dpm.ps);
1849         kfree(rdev->pm.dpm.priv);
1850 }
1851
1852 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1853 {
1854         struct sumo_power_info *pi = sumo_get_pi(rdev);
1855         struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1856
1857         if (low)
1858                 return requested_state->levels[0].sclk;
1859         else
1860                 return requested_state->levels[requested_state->num_levels - 1].sclk;
1861 }
1862
1863 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1864 {
1865         struct sumo_power_info *pi = sumo_get_pi(rdev);
1866
1867         return pi->sys_info.bootup_uma_clk;
1868 }
1869
1870 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
1871                                      enum radeon_dpm_forced_level level)
1872 {
1873         struct sumo_power_info *pi = sumo_get_pi(rdev);
1874         struct radeon_ps *rps = &pi->current_rps;
1875         struct sumo_ps *ps = sumo_get_ps(rps);
1876         int i;
1877
1878         if (ps->num_levels <= 1)
1879                 return 0;
1880
1881         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1882                 if (pi->enable_boost)
1883                         sumo_enable_boost(rdev, rps, false);
1884                 sumo_power_level_enable(rdev, ps->num_levels - 1, true);
1885                 sumo_set_forced_level(rdev, ps->num_levels - 1);
1886                 sumo_set_forced_mode_enabled(rdev);
1887                 for (i = 0; i < ps->num_levels - 1; i++) {
1888                         sumo_power_level_enable(rdev, i, false);
1889                 }
1890                 sumo_set_forced_mode(rdev, false);
1891                 sumo_set_forced_mode_enabled(rdev);
1892                 sumo_set_forced_mode(rdev, false);
1893         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1894                 if (pi->enable_boost)
1895                         sumo_enable_boost(rdev, rps, false);
1896                 sumo_power_level_enable(rdev, 0, true);
1897                 sumo_set_forced_level(rdev, 0);
1898                 sumo_set_forced_mode_enabled(rdev);
1899                 for (i = 1; i < ps->num_levels; i++) {
1900                         sumo_power_level_enable(rdev, i, false);
1901                 }
1902                 sumo_set_forced_mode(rdev, false);
1903                 sumo_set_forced_mode_enabled(rdev);
1904                 sumo_set_forced_mode(rdev, false);
1905         } else {
1906                 for (i = 0; i < ps->num_levels; i++) {
1907                         sumo_power_level_enable(rdev, i, true);
1908                 }
1909                 if (pi->enable_boost)
1910                         sumo_enable_boost(rdev, rps, true);
1911         }
1912
1913         rdev->pm.dpm.forced_level = level;
1914
1915         return 0;
1916 }