sys/dev/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/export.h>
  30 #include <drm/drmP.h>
  31 #include <linux/slab.h>
  32 #include <drm/drm_atomic_helper.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  41
  42 static int disable_aux_irq = 0;
  43 TUNABLE_INT("drm.i915.disable_aux_irq", &disable_aux_irq);
  44
  45 struct dp_link_dpll {
  46         int link_bw;
  47         struct dpll dpll;
  48 };
  49
  50 static const struct dp_link_dpll gen4_dpll[] = {
  51         { DP_LINK_BW_1_62,
  52                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  53         { DP_LINK_BW_2_7,
  54                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  55 };
  56
  57 static const struct dp_link_dpll pch_dpll[] = {
  58         { DP_LINK_BW_1_62,
  59                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  60         { DP_LINK_BW_2_7,
  61                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  62 };
  63
  64 static const struct dp_link_dpll vlv_dpll[] = {
  65         { DP_LINK_BW_1_62,
  66                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  67         { DP_LINK_BW_2_7,
  68                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  69 };
  70
  71 /*
  72  * CHV supports eDP 1.4 that have  more link rates.
  73  * Below only provides the fixed rate but exclude variable rate.
  74  */
  75 static const struct dp_link_dpll chv_dpll[] = {
  76         /*
  77          * CHV requires to program fractional division for m2.
  78          * m2 is stored in fixed point format using formula below
  79          * (m2_int << 22) | m2_fraction
  80          */
  81         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  82                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  83         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  85         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  86                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  87 };
  88
  89 /**
  90  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  91  * @intel_dp: DP struct
  92  *
  93  * If a CPU or PCH DP output is attached to an eDP panel, this function
  94  * will return true, and false otherwise.
  95  */
  96 static bool is_edp(struct intel_dp *intel_dp)
  97 {
  98         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  99
 100         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 101 }
 102
 103 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.base.dev;
 108 }
 109
 110 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 111 {
 112         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 113 }
 114
 115 static void intel_dp_link_down(struct intel_dp *intel_dp);
 116 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 117 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 118 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 119 static void vlv_steal_power_sequencer(struct drm_device *dev,
 120                                       enum i915_pipe pipe);
 121
 122 int
 123 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 124 {
 125         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 126         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 127
 128         switch (max_link_bw) {
 129         case DP_LINK_BW_1_62:
 130         case DP_LINK_BW_2_7:
 131                 break;
 132         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 133                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 134                      INTEL_INFO(dev)->gen >= 8) &&
 135                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 136                         max_link_bw = DP_LINK_BW_5_4;
 137                 else
 138                         max_link_bw = DP_LINK_BW_2_7;
 139                 break;
 140         default:
 141                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 142                      max_link_bw);
 143                 max_link_bw = DP_LINK_BW_1_62;
 144                 break;
 145         }
 146         return max_link_bw;
 147 }
 148
 149 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 150 {
 151         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 152         struct drm_device *dev = intel_dig_port->base.base.dev;
 153         u8 source_max, sink_max;
 154
 155         source_max = 4;
 156         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 157             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 158                 source_max = 2;
 159
 160         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 161
 162         return min(source_max, sink_max);
 163 }
 164
 165 /*
 166  * The units on the numbers in the next two are... bizarre.  Examples will
 167  * make it clearer; this one parallels an example in the eDP spec.
 168  *
 169  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 170  *
 171  *     270000 * 1 * 8 / 10 == 216000
 172  *
 173  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 174  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 175  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 176  * 119000.  At 18bpp that's 2142000 kilobits per second.
 177  *
 178  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 179  * get the result in decakilobits instead of kilobits.
 180  */
 181
 182 static int
 183 intel_dp_link_required(int pixel_clock, int bpp)
 184 {
 185         return (pixel_clock * bpp + 9) / 10;
 186 }
 187
 188 static int
 189 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 190 {
 191         return (max_link_clock * max_lanes * 8) / 10;
 192 }
 193
 194 static enum drm_mode_status
 195 intel_dp_mode_valid(struct drm_connector *connector,
 196                     struct drm_display_mode *mode)
 197 {
 198         struct intel_dp *intel_dp = intel_attached_dp(connector);
 199         struct intel_connector *intel_connector = to_intel_connector(connector);
 200         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 201         int target_clock = mode->clock;
 202         int max_rate, mode_rate, max_lanes, max_link_clock;
 203
 204         if (is_edp(intel_dp) && fixed_mode) {
 205                 if (mode->hdisplay > fixed_mode->hdisplay)
 206                         return MODE_PANEL;
 207
 208                 if (mode->vdisplay > fixed_mode->vdisplay)
 209                         return MODE_PANEL;
 210
 211                 target_clock = fixed_mode->clock;
 212         }
 213
 214         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 215         max_lanes = intel_dp_max_lane_count(intel_dp);
 216
 217         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 218         mode_rate = intel_dp_link_required(target_clock, 18);
 219
 220         if (mode_rate > max_rate)
 221                 return MODE_CLOCK_HIGH;
 222
 223         if (mode->clock < 10000)
 224                 return MODE_CLOCK_LOW;
 225
 226         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 227                 return MODE_H_ILLEGAL;
 228
 229         return MODE_OK;
 230 }
 231
 232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 233 {
 234         int     i;
 235         uint32_t v = 0;
 236
 237         if (src_bytes > 4)
 238                 src_bytes = 4;
 239         for (i = 0; i < src_bytes; i++)
 240                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 241         return v;
 242 }
 243
 244 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 245 {
 246         int i;
 247         if (dst_bytes > 4)
 248                 dst_bytes = 4;
 249         for (i = 0; i < dst_bytes; i++)
 250                 dst[i] = src >> ((3-i) * 8);
 251 }
 252
 253 /* hrawclock is 1/4 the FSB frequency */
 254 static int
 255 intel_hrawclk(struct drm_device *dev)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         uint32_t clkcfg;
 259
 260         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 261         if (IS_VALLEYVIEW(dev))
 262                 return 200;
 263
 264         clkcfg = I915_READ(CLKCFG);
 265         switch (clkcfg & CLKCFG_FSB_MASK) {
 266         case CLKCFG_FSB_400:
 267                 return 100;
 268         case CLKCFG_FSB_533:
 269                 return 133;
 270         case CLKCFG_FSB_667:
 271                 return 166;
 272         case CLKCFG_FSB_800:
 273                 return 200;
 274         case CLKCFG_FSB_1067:
 275                 return 266;
 276         case CLKCFG_FSB_1333:
 277                 return 333;
 278         /* these two are just a guess; one of them might be right */
 279         case CLKCFG_FSB_1600:
 280         case CLKCFG_FSB_1600_ALT:
 281                 return 400;
 282         default:
 283                 return 133;
 284         }
 285 }
 286
 287 static void
 288 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 289                                     struct intel_dp *intel_dp);
 290 static void
 291 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 292                                               struct intel_dp *intel_dp);
 293
 294 static void pps_lock(struct intel_dp *intel_dp)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct intel_encoder *encoder = &intel_dig_port->base;
 298         struct drm_device *dev = encoder->base.dev;
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         enum intel_display_power_domain power_domain;
 301
 302         /*
 303          * See vlv_power_sequencer_reset() why we need
 304          * a power domain reference here.
 305          */
 306         power_domain = intel_display_port_power_domain(encoder);
 307         intel_display_power_get(dev_priv, power_domain);
 308
 309         mutex_lock(&dev_priv->pps_mutex);
 310 }
 311
 312 static void pps_unlock(struct intel_dp *intel_dp)
 313 {
 314         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 315         struct intel_encoder *encoder = &intel_dig_port->base;
 316         struct drm_device *dev = encoder->base.dev;
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318         enum intel_display_power_domain power_domain;
 319
 320         mutex_unlock(&dev_priv->pps_mutex);
 321
 322         power_domain = intel_display_port_power_domain(encoder);
 323         intel_display_power_put(dev_priv, power_domain);
 324 }
 325
 326 static void
 327 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 328 {
 329         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 330         struct drm_device *dev = intel_dig_port->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332         enum i915_pipe pipe = intel_dp->pps_pipe;
 333         bool pll_enabled;
 334         uint32_t DP;
 335
 336         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 337                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 338                  pipe_name(pipe), port_name(intel_dig_port->port)))
 339                 return;
 340
 341         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 342                       pipe_name(pipe), port_name(intel_dig_port->port));
 343
 344         /* Preserve the BIOS-computed detected bit. This is
 345          * supposed to be read-only.
 346          */
 347         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 348         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 349         DP |= DP_PORT_WIDTH(1);
 350         DP |= DP_LINK_TRAIN_PAT_1;
 351
 352         if (IS_CHERRYVIEW(dev))
 353                 DP |= DP_PIPE_SELECT_CHV(pipe);
 354         else if (pipe == PIPE_B)
 355                 DP |= DP_PIPEB_SELECT;
 356
 357         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 358
 359         /*
 360          * The DPLL for the pipe must be enabled for this to work.
 361          * So enable temporarily it if it's not already enabled.
 362          */
 363         if (!pll_enabled)
 364                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 365                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 366
 367         /*
 368          * Similar magic as in intel_dp_enable_port().
 369          * We _must_ do this port enable + disable trick
 370          * to make this power seqeuencer lock onto the port.
 371          * Otherwise even VDD force bit won't work.
 372          */
 373         I915_WRITE(intel_dp->output_reg, DP);
 374         POSTING_READ(intel_dp->output_reg);
 375
 376         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 377         POSTING_READ(intel_dp->output_reg);
 378
 379         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 380         POSTING_READ(intel_dp->output_reg);
 381
 382         if (!pll_enabled)
 383                 vlv_force_pll_off(dev, pipe);
 384 }
 385
 386 static enum i915_pipe
 387 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 388 {
 389         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 390         struct drm_device *dev = intel_dig_port->base.base.dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         struct intel_encoder *encoder;
 393         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 394         enum i915_pipe pipe;
 395
 396         lockdep_assert_held(&dev_priv->pps_mutex);
 397
 398         /* We should never land here with regular DP ports */
 399         WARN_ON(!is_edp(intel_dp));
 400
 401         if (intel_dp->pps_pipe != INVALID_PIPE)
 402                 return intel_dp->pps_pipe;
 403
 404         /*
 405          * We don't have power sequencer currently.
 406          * Pick one that's not used by other ports.
 407          */
 408         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 409                             base.head) {
 410                 struct intel_dp *tmp;
 411
 412                 if (encoder->type != INTEL_OUTPUT_EDP)
 413                         continue;
 414
 415                 tmp = enc_to_intel_dp(&encoder->base);
 416
 417                 if (tmp->pps_pipe != INVALID_PIPE)
 418                         pipes &= ~(1 << tmp->pps_pipe);
 419         }
 420
 421         /*
 422          * Didn't find one. This should not happen since there
 423          * are two power sequencers and up to two eDP ports.
 424          */
 425         if (WARN_ON(pipes == 0))
 426                 pipe = PIPE_A;
 427         else
 428                 pipe = ffs(pipes) - 1;
 429
 430         vlv_steal_power_sequencer(dev, pipe);
 431         intel_dp->pps_pipe = pipe;
 432
 433         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 434                       pipe_name(intel_dp->pps_pipe),
 435                       port_name(intel_dig_port->port));
 436
 437         /* init power sequencer on this pipe and port */
 438         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 439         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 440
 441         /*
 442          * Even vdd force doesn't work until we've made
 443          * the power sequencer lock in on the port.
 444          */
 445         vlv_power_sequencer_kick(intel_dp);
 446
 447         return intel_dp->pps_pipe;
 448 }
 449
 450 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 451                                enum i915_pipe pipe);
 452
 453 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 454                                enum i915_pipe pipe)
 455 {
 456         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 457 }
 458
 459 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 460                                 enum i915_pipe pipe)
 461 {
 462         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 463 }
 464
 465 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 466                          enum i915_pipe pipe)
 467 {
 468         return true;
 469 }
 470
 471 static enum i915_pipe
 472 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 473                      enum port port,
 474                      vlv_pipe_check pipe_check)
 475 {
 476         enum i915_pipe pipe;
 477
 478         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 479                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 480                         PANEL_PORT_SELECT_MASK;
 481
 482                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 483                         continue;
 484
 485                 if (!pipe_check(dev_priv, pipe))
 486                         continue;
 487
 488                 return pipe;
 489         }
 490
 491         return INVALID_PIPE;
 492 }
 493
 494 static void
 495 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 496 {
 497         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 498         struct drm_device *dev = intel_dig_port->base.base.dev;
 499         struct drm_i915_private *dev_priv = dev->dev_private;
 500         enum port port = intel_dig_port->port;
 501
 502         lockdep_assert_held(&dev_priv->pps_mutex);
 503
 504         /* try to find a pipe with this port selected */
 505         /* first pick one where the panel is on */
 506         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 507                                                   vlv_pipe_has_pp_on);
 508         /* didn't find one? pick one where vdd is on */
 509         if (intel_dp->pps_pipe == INVALID_PIPE)
 510                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 511                                                           vlv_pipe_has_vdd_on);
 512         /* didn't find one? pick one with just the correct port */
 513         if (intel_dp->pps_pipe == INVALID_PIPE)
 514                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 515                                                           vlv_pipe_any);
 516
 517         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 518         if (intel_dp->pps_pipe == INVALID_PIPE) {
 519                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 520                               port_name(port));
 521                 return;
 522         }
 523
 524         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 525                       port_name(port), pipe_name(intel_dp->pps_pipe));
 526
 527         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 528         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 529 }
 530
 531 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 532 {
 533         struct drm_device *dev = dev_priv->dev;
 534         struct intel_encoder *encoder;
 535
 536         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 537                 return;
 538
 539         /*
 540          * We can't grab pps_mutex here due to deadlock with power_domain
 541          * mutex when power_domain functions are called while holding pps_mutex.
 542          * That also means that in order to use pps_pipe the code needs to
 543          * hold both a power domain reference and pps_mutex, and the power domain
 544          * reference get/put must be done while _not_ holding pps_mutex.
 545          * pps_{lock,unlock}() do these steps in the correct order, so one
 546          * should use them always.
 547          */
 548
 549         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 550                 struct intel_dp *intel_dp;
 551
 552                 if (encoder->type != INTEL_OUTPUT_EDP)
 553                         continue;
 554
 555                 intel_dp = enc_to_intel_dp(&encoder->base);
 556                 intel_dp->pps_pipe = INVALID_PIPE;
 557         }
 558 }
 559
 560 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 561 {
 562         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 563
 564         if (HAS_PCH_SPLIT(dev))
 565                 return PCH_PP_CONTROL;
 566         else
 567                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 568 }
 569
 570 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 571 {
 572         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 573
 574         if (HAS_PCH_SPLIT(dev))
 575                 return PCH_PP_STATUS;
 576         else
 577                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 578 }
 579
 580 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 581    This function only applicable when panel PM state is not to be tracked */
 582 #if 0
 583 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 584                               void *unused)
 585 {
 586         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 587                                                  edp_notifier);
 588         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 589         struct drm_i915_private *dev_priv = dev->dev_private;
 590         u32 pp_div;
 591         u32 pp_ctrl_reg, pp_div_reg;
 592
 593         if (!is_edp(intel_dp) || code != SYS_RESTART)
 594                 return 0;
 595
 596         pps_lock(intel_dp);
 597
 598         if (IS_VALLEYVIEW(dev)) {
 599                 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 600
 601                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 602                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 603                 pp_div = I915_READ(pp_div_reg);
 604                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 605
 606                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 607                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 608                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 609                 msleep(intel_dp->panel_power_cycle_delay);
 610         }
 611
 612         pps_unlock(intel_dp);
 613
 614         return 0;
 615 }
 616 #endif
 617
 618 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 619 {
 620         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 621         struct drm_i915_private *dev_priv = dev->dev_private;
 622
 623         lockdep_assert_held(&dev_priv->pps_mutex);
 624
 625         if (IS_VALLEYVIEW(dev) &&
 626             intel_dp->pps_pipe == INVALID_PIPE)
 627                 return false;
 628
 629         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 630 }
 631
 632 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 633 {
 634         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 635         struct drm_i915_private *dev_priv = dev->dev_private;
 636
 637         lockdep_assert_held(&dev_priv->pps_mutex);
 638
 639         if (IS_VALLEYVIEW(dev) &&
 640             intel_dp->pps_pipe == INVALID_PIPE)
 641                 return false;
 642
 643         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 644 }
 645
 646 static void
 647 intel_dp_check_edp(struct intel_dp *intel_dp)
 648 {
 649         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 650         struct drm_i915_private *dev_priv = dev->dev_private;
 651
 652         if (!is_edp(intel_dp))
 653                 return;
 654
 655         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 656                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 657                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 658                               I915_READ(_pp_stat_reg(intel_dp)),
 659                               I915_READ(_pp_ctrl_reg(intel_dp)));
 660         }
 661 }
 662
 663 static uint32_t
 664 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 665 {
 666         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 667         struct drm_device *dev = intel_dig_port->base.base.dev;
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 670         uint32_t status;
 671         bool done;
 672
 673 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 674         if (has_aux_irq)
 675                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 676                                           msecs_to_jiffies_timeout(10));
 677         else
 678                 done = wait_for_atomic(C, 10) == 0;
 679         if (!done)
 680                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 681                           has_aux_irq);
 682 #undef C
 683
 684         return status;
 685 }
 686
 687 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 688 {
 689         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 690         struct drm_device *dev = intel_dig_port->base.base.dev;
 691
 692         /*
 693          * The clock divider is based off the hrawclk, and would like to run at
 694          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 695          */
 696         return index ? 0 : intel_hrawclk(dev) / 2;
 697 }
 698
 699 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 700 {
 701         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 702         struct drm_device *dev = intel_dig_port->base.base.dev;
 703
 704         if (index)
 705                 return 0;
 706
 707         if (intel_dig_port->port == PORT_A) {
 708                 if (IS_GEN6(dev) || IS_GEN7(dev))
 709                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 710                 else
 711                         return 225; /* eDP input clock at 450Mhz */
 712         } else {
 713                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 714         }
 715 }
 716
 717 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 718 {
 719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 720         struct drm_device *dev = intel_dig_port->base.base.dev;
 721         struct drm_i915_private *dev_priv = dev->dev_private;
 722
 723         if (intel_dig_port->port == PORT_A) {
 724                 if (index)
 725                         return 0;
 726                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 727         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 728                 /* Workaround for non-ULT HSW */
 729                 switch (index) {
 730                 case 0: return 63;
 731                 case 1: return 72;
 732                 default: return 0;
 733                 }
 734         } else  {
 735                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 736         }
 737 }
 738
 739 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 740 {
 741         return index ? 0 : 100;
 742 }
 743
 744 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 745 {
 746         /*
 747          * SKL doesn't need us to program the AUX clock divider (Hardware will
 748          * derive the clock from CDCLK automatically). We still implement the
 749          * get_aux_clock_divider vfunc to plug-in into the existing code.
 750          */
 751         return index ? 0 : 1;
 752 }
 753
 754 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 755                                       bool has_aux_irq,
 756                                       int send_bytes,
 757                                       uint32_t aux_clock_divider)
 758 {
 759         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 760         struct drm_device *dev = intel_dig_port->base.base.dev;
 761         uint32_t precharge, timeout;
 762
 763         if (IS_GEN6(dev))
 764                 precharge = 3;
 765         else
 766                 precharge = 5;
 767
 768         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 769                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 770         else
 771                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 772
 773         return DP_AUX_CH_CTL_SEND_BUSY |
 774                DP_AUX_CH_CTL_DONE |
 775                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 776                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 777                timeout |
 778                DP_AUX_CH_CTL_RECEIVE_ERROR |
 779                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 780                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 781                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 782 }
 783
 784 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 785                                       bool has_aux_irq,
 786                                       int send_bytes,
 787                                       uint32_t unused)
 788 {
 789         return DP_AUX_CH_CTL_SEND_BUSY |
 790                DP_AUX_CH_CTL_DONE |
 791                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 792                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 793                DP_AUX_CH_CTL_TIME_OUT_1600us |
 794                DP_AUX_CH_CTL_RECEIVE_ERROR |
 795                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 796                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 797 }
 798
 799 static int
 800 intel_dp_aux_ch(struct intel_dp *intel_dp,
 801                 const uint8_t *send, int send_bytes,
 802                 uint8_t *recv, int recv_size)
 803 {
 804         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 805         struct drm_device *dev = intel_dig_port->base.base.dev;
 806         struct drm_i915_private *dev_priv = dev->dev_private;
 807         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 808         uint32_t ch_data = ch_ctl + 4;
 809         uint32_t aux_clock_divider;
 810         int i, ret, recv_bytes;
 811         uint32_t status;
 812         int try, clock = 0;
 813         bool has_aux_irq = HAS_AUX_IRQ(dev) && !disable_aux_irq;
 814         bool vdd;
 815
 816         pps_lock(intel_dp);
 817
 818         /*
 819          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 820          * In such cases we want to leave VDD enabled and it's up to upper layers
 821          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 822          * ourselves.
 823          */
 824         vdd = edp_panel_vdd_on(intel_dp);
 825
 826         /* dp aux is extremely sensitive to irq latency, hence request the
 827          * lowest possible wakeup latency and so prevent the cpu from going into
 828          * deep sleep states.
 829          */
 830         pm_qos_update_request(&dev_priv->pm_qos, 0);
 831
 832         intel_dp_check_edp(intel_dp);
 833
 834         intel_aux_display_runtime_get(dev_priv);
 835
 836         /* Try to wait for any previous AUX channel activity */
 837         for (try = 0; try < 3; try++) {
 838                 status = I915_READ_NOTRACE(ch_ctl);
 839                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 840                         break;
 841                 msleep(1);
 842         }
 843
 844         if (try == 3) {
 845                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 846                      I915_READ(ch_ctl));
 847                 ret = -EBUSY;
 848                 goto out;
 849         }
 850
 851         /* Only 5 data registers! */
 852         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 853                 ret = -E2BIG;
 854                 goto out;
 855         }
 856
 857         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 858                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 859                                                           has_aux_irq,
 860                                                           send_bytes,
 861                                                           aux_clock_divider);
 862
 863                 /* Must try at least 3 times according to DP spec */
 864                 for (try = 0; try < 5; try++) {
 865                         /* Load the send data into the aux channel data registers */
 866                         for (i = 0; i < send_bytes; i += 4)
 867                                 I915_WRITE(ch_data + i,
 868                                            intel_dp_pack_aux(send + i,
 869                                                              send_bytes - i));
 870
 871                         /* Send the command and wait for it to complete */
 872                         I915_WRITE(ch_ctl, send_ctl);
 873
 874                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 875
 876                         /* Clear done status and any errors */
 877                         I915_WRITE(ch_ctl,
 878                                    status |
 879                                    DP_AUX_CH_CTL_DONE |
 880                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 881                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 882
 883                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 884                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 885                                 continue;
 886                         if (status & DP_AUX_CH_CTL_DONE)
 887                                 break;
 888                 }
 889                 if (status & DP_AUX_CH_CTL_DONE)
 890                         break;
 891         }
 892
 893         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 894                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 895                 ret = -EBUSY;
 896                 goto out;
 897         }
 898
 899         /* Check for timeout or receive error.
 900          * Timeouts occur when the sink is not connected
 901          */
 902         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 903                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 904                 ret = -EIO;
 905                 goto out;
 906         }
 907
 908         /* Timeouts occur when the device isn't connected, so they're
 909          * "normal" -- don't fill the kernel log with these */
 910         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 911                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 912                 ret = -ETIMEDOUT;
 913                 goto out;
 914         }
 915
 916         /* Unload any bytes sent back from the other side */
 917         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 918                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 919         if (recv_bytes > recv_size)
 920                 recv_bytes = recv_size;
 921
 922         for (i = 0; i < recv_bytes; i += 4)
 923                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 924                                     recv + i, recv_bytes - i);
 925
 926         ret = recv_bytes;
 927 out:
 928         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 929         intel_aux_display_runtime_put(dev_priv);
 930
 931         if (vdd)
 932                 edp_panel_vdd_off(intel_dp, false);
 933
 934         pps_unlock(intel_dp);
 935
 936         return ret;
 937 }
 938
 939 #define BARE_ADDRESS_SIZE       3
 940 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 941 static ssize_t
 942 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 943 {
 944         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 945         uint8_t txbuf[20], rxbuf[20];
 946         size_t txsize, rxsize;
 947         int ret;
 948
 949         txbuf[0] = msg->request << 4;
 950         txbuf[1] = msg->address >> 8;
 951         txbuf[2] = msg->address & 0xff;
 952         txbuf[3] = msg->size - 1;
 953
 954         switch (msg->request & ~DP_AUX_I2C_MOT) {
 955         case DP_AUX_NATIVE_WRITE:
 956         case DP_AUX_I2C_WRITE:
 957                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 958                 rxsize = 1;
 959
 960                 if (WARN_ON(txsize > 20))
 961                         return -E2BIG;
 962
 963                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 964
 965                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 966                 if (ret > 0) {
 967                         msg->reply = rxbuf[0] >> 4;
 968
 969                         /* Return payload size. */
 970                         ret = msg->size;
 971                 }
 972                 break;
 973
 974         case DP_AUX_NATIVE_READ:
 975         case DP_AUX_I2C_READ:
 976                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 977                 rxsize = msg->size + 1;
 978
 979                 if (WARN_ON(rxsize > 20))
 980                         return -E2BIG;
 981
 982                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 983                 if (ret > 0) {
 984                         msg->reply = rxbuf[0] >> 4;
 985                         /*
 986                          * Assume happy day, and copy the data. The caller is
 987                          * expected to check msg->reply before touching it.
 988                          *
 989                          * Return payload size.
 990                          */
 991                         ret--;
 992                         memcpy(msg->buffer, rxbuf + 1, ret);
 993                 }
 994                 break;
 995
 996         default:
 997                 ret = -EINVAL;
 998                 break;
 999         }
1000
1001         return ret;
1002 }
1003
1004 static int
1005 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
1006                     uint8_t write_byte, uint8_t *read_byte)
1007 {
1008         struct i2c_algo_dp_aux_data *data = device_get_softc(adapter);
1009         struct intel_dp *intel_dp = data->priv;
1010         uint16_t address = data->address;
1011         uint8_t msg[5];
1012         uint8_t reply[2];
1013         unsigned retry;
1014         int msg_bytes;
1015         int reply_bytes;
1016         int ret;
1017
1018         intel_edp_panel_vdd_on(intel_dp);
1019         intel_dp_check_edp(intel_dp);
1020         /* Set up the command byte */
1021         if (mode & MODE_I2C_READ)
1022                 msg[0] = DP_AUX_I2C_READ << 4;
1023         else
1024                 msg[0] = DP_AUX_I2C_WRITE << 4;
1025
1026         if (!(mode & MODE_I2C_STOP))
1027                 msg[0] |= DP_AUX_I2C_MOT << 4;
1028
1029         msg[1] = address >> 8;
1030         msg[2] = address;
1031
1032         switch (mode) {
1033         case MODE_I2C_WRITE:
1034                 msg[3] = 0;
1035                 msg[4] = write_byte;
1036                 msg_bytes = 5;
1037                 reply_bytes = 1;
1038                 break;
1039         case MODE_I2C_READ:
1040                 msg[3] = 0;
1041                 msg_bytes = 4;
1042                 reply_bytes = 2;
1043                 break;
1044         default:
1045                 msg_bytes = 3;
1046                 reply_bytes = 1;
1047                 break;
1048         }
1049
1050         /*
1051          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
1052          * required to retry at least seven times upon receiving AUX_DEFER
1053          * before giving up the AUX transaction.
1054          */
1055         for (retry = 0; retry < 7; retry++) {
1056                 ret = intel_dp_aux_ch(intel_dp,
1057                                       msg, msg_bytes,
1058                                       reply, reply_bytes);
1059                 if (ret < 0) {
1060                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
1061                         goto out;
1062                 }
1063
1064                 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
1065                 case DP_AUX_NATIVE_REPLY_ACK:
1066                         /* I2C-over-AUX Reply field is only valid
1067                          * when paired with AUX ACK.
1068                          */
1069                         break;
1070                 case DP_AUX_NATIVE_REPLY_NACK:
1071                         DRM_DEBUG_KMS("aux_ch native nack\n");
1072                         ret = -EREMOTEIO;
1073                         goto out;
1074                 case DP_AUX_NATIVE_REPLY_DEFER:
1075                         /*
1076                          * For now, just give more slack to branch devices. We
1077                          * could check the DPCD for I2C bit rate capabilities,
1078                          * and if available, adjust the interval. We could also
1079                          * be more careful with DP-to-Legacy adapters where a
1080                          * long legacy cable may force very low I2C bit rates.
1081                          */
1082                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1083                             DP_DWN_STRM_PORT_PRESENT)
1084                                 usleep_range(500, 600);
1085                         else
1086                                 usleep_range(300, 400);
1087                         continue;
1088                 default:
1089                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
1090                                   reply[0]);
1091                         ret = -EREMOTEIO;
1092                         goto out;
1093                 }
1094
1095                 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
1096                 case DP_AUX_I2C_REPLY_ACK:
1097                         if (mode == MODE_I2C_READ) {
1098                                 *read_byte = reply[1];
1099                         }
1100                         ret = 0;        /* reply_bytes - 1 */
1101                         goto out;
1102                 case DP_AUX_I2C_REPLY_NACK:
1103                         DRM_DEBUG_KMS("aux_i2c nack\n");
1104                         ret = -EREMOTEIO;
1105                         goto out;
1106                 case DP_AUX_I2C_REPLY_DEFER:
1107                         DRM_DEBUG_KMS("aux_i2c defer\n");
1108                         udelay(100);
1109                         break;
1110                 default:
1111                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
1112                         ret = -EREMOTEIO;
1113                         goto out;
1114                 }
1115         }
1116
1117         DRM_ERROR("too many retries, giving up\n");
1118         ret = -EREMOTEIO;
1119
1120 out:
1121         return ret;
1122 }
1123
1124 static void
1125 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1126 {
1127         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1128         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1129         enum port port = intel_dig_port->port;
1130         const char *name = NULL;
1131         int ret;
1132
1133         switch (port) {
1134         case PORT_A:
1135                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1136                 name = "DPDDC-A";
1137                 break;
1138         case PORT_B:
1139                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1140                 name = "DPDDC-B";
1141                 break;
1142         case PORT_C:
1143                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1144                 name = "DPDDC-C";
1145                 break;
1146         case PORT_D:
1147                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1148                 name = "DPDDC-D";
1149                 break;
1150         default:
1151                 BUG();
1152         }
1153
1154         /*
1155          * The AUX_CTL register is usually DP_CTL + 0x10.
1156          *
1157          * On Haswell and Broadwell though:
1158          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1159          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1160          *
1161          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1162          */
1163         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1164                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1165
1166         intel_dp->aux.name = name;
1167         intel_dp->aux.dev = dev->dev;
1168         intel_dp->aux.transfer = intel_dp_aux_transfer;
1169
1170         DRM_DEBUG_KMS("i2c_init %s\n", name);
1171         ret = iic_dp_aux_add_bus(connector->base.dev->dev, name,
1172             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
1173             &intel_dp->aux.ddc);
1174         WARN(ret, "intel_dp_i2c_init failed with error %d for port %c\n",
1175              ret, port_name(port));
1176
1177 }
1178
1179 static void
1180 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1181 {
1182         intel_connector_unregister(intel_connector);
1183 }
1184
1185 #if 0
1186 static int
1187 intel_dp_i2c_init(struct intel_dp *intel_dp,
1188                   struct intel_connector *intel_connector, const char *name)
1189 {
1190         int     ret;
1191
1192         DRM_DEBUG_KMS("i2c_init %s\n", name);
1193 #if 0
1194         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
1195         intel_dp->adapter.owner = THIS_MODULE;
1196         intel_dp->adapter.class = I2C_CLASS_DDC;
1197         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
1198         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
1199         intel_dp->adapter.algo_data = &intel_dp->algo;
1200         intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
1201
1202         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
1203         if (ret < 0)
1204                 return ret;
1205
1206         ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
1207                                 &intel_dp->adapter.dev.kobj,
1208                                 intel_dp->adapter.dev.kobj.name);
1209 #endif
1210         ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
1211             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
1212             &intel_dp->adapter);
1213
1214         return ret;
1215 }
1216 #endif
1217
1218 static void
1219 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
1220 {
1221         u32 ctrl1;
1222
1223         pipe_config->ddi_pll_sel = SKL_DPLL0;
1224         pipe_config->dpll_hw_state.cfgcr1 = 0;
1225         pipe_config->dpll_hw_state.cfgcr2 = 0;
1226
1227         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1228         switch (link_bw) {
1229         case DP_LINK_BW_1_62:
1230                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1231                                               SKL_DPLL0);
1232                 break;
1233         case DP_LINK_BW_2_7:
1234                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1235                                               SKL_DPLL0);
1236                 break;
1237         case DP_LINK_BW_5_4:
1238                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1239                                               SKL_DPLL0);
1240                 break;
1241         }
1242         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1243 }
1244
1245 static void
1246 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1247 {
1248         switch (link_bw) {
1249         case DP_LINK_BW_1_62:
1250                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1251                 break;
1252         case DP_LINK_BW_2_7:
1253                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1254                 break;
1255         case DP_LINK_BW_5_4:
1256                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1257                 break;
1258         }
1259 }
1260
1261 static void
1262 intel_dp_set_clock(struct intel_encoder *encoder,
1263                    struct intel_crtc_state *pipe_config, int link_bw)
1264 {
1265         struct drm_device *dev = encoder->base.dev;
1266         const struct dp_link_dpll *divisor = NULL;
1267         int i, count = 0;
1268
1269         if (IS_G4X(dev)) {
1270                 divisor = gen4_dpll;
1271                 count = ARRAY_SIZE(gen4_dpll);
1272         } else if (HAS_PCH_SPLIT(dev)) {
1273                 divisor = pch_dpll;
1274                 count = ARRAY_SIZE(pch_dpll);
1275         } else if (IS_CHERRYVIEW(dev)) {
1276                 divisor = chv_dpll;
1277                 count = ARRAY_SIZE(chv_dpll);
1278         } else if (IS_VALLEYVIEW(dev)) {
1279                 divisor = vlv_dpll;
1280                 count = ARRAY_SIZE(vlv_dpll);
1281         }
1282
1283         if (divisor && count) {
1284                 for (i = 0; i < count; i++) {
1285                         if (link_bw == divisor[i].link_bw) {
1286                                 pipe_config->dpll = divisor[i].dpll;
1287                                 pipe_config->clock_set = true;
1288                                 break;
1289                         }
1290                 }
1291         }
1292 }
1293
1294 bool
1295 intel_dp_compute_config(struct intel_encoder *encoder,
1296                         struct intel_crtc_state *pipe_config)
1297 {
1298         struct drm_device *dev = encoder->base.dev;
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1301         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1302         enum port port = dp_to_dig_port(intel_dp)->port;
1303         struct intel_crtc *intel_crtc = encoder->new_crtc;
1304         struct intel_connector *intel_connector = intel_dp->attached_connector;
1305         int lane_count, clock;
1306         int min_lane_count = 1;
1307         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1308         /* Conveniently, the link BW constants become indices with a shift...*/
1309         int min_clock = 0;
1310         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1311         int bpp, mode_rate;
1312         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1313         int link_avail, link_clock;
1314
1315         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1316                 pipe_config->has_pch_encoder = true;
1317
1318         pipe_config->has_dp_encoder = true;
1319         pipe_config->has_drrs = false;
1320         pipe_config->has_audio = intel_dp->has_audio;
1321
1322         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1323                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1324                                        adjusted_mode);
1325                 if (!HAS_PCH_SPLIT(dev))
1326                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1327                                                  intel_connector->panel.fitting_mode);
1328                 else
1329                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1330                                                 intel_connector->panel.fitting_mode);
1331         }
1332
1333         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1334                 return false;
1335
1336         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1337                       "max bw %02x pixel clock %iKHz\n",
1338                       max_lane_count, bws[max_clock],
1339                       adjusted_mode->crtc_clock);
1340
1341         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1342          * bpc in between. */
1343         bpp = pipe_config->pipe_bpp;
1344         if (is_edp(intel_dp)) {
1345                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1346                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1347                                       dev_priv->vbt.edp_bpp);
1348                         bpp = dev_priv->vbt.edp_bpp;
1349                 }
1350
1351                 /*
1352                  * Use the maximum clock and number of lanes the eDP panel
1353                  * advertizes being capable of. The panels are generally
1354                  * designed to support only a single clock and lane
1355                  * configuration, and typically these values correspond to the
1356                  * native resolution of the panel.
1357                  */
1358                 min_lane_count = max_lane_count;
1359                 min_clock = max_clock;
1360         }
1361
1362         for (; bpp >= 6*3; bpp -= 2*3) {
1363                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1364                                                    bpp);
1365
1366                 for (clock = min_clock; clock <= max_clock; clock++) {
1367                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1368                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1369                                 link_avail = intel_dp_max_data_rate(link_clock,
1370                                                                     lane_count);
1371
1372                                 if (mode_rate <= link_avail) {
1373                                         goto found;
1374                                 }
1375                         }
1376                 }
1377         }
1378
1379         return false;
1380
1381 found:
1382         if (intel_dp->color_range_auto) {
1383                 /*
1384                  * See:
1385                  * CEA-861-E - 5.1 Default Encoding Parameters
1386                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1387                  */
1388                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1389                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1390                 else
1391                         intel_dp->color_range = 0;
1392         }
1393
1394         if (intel_dp->color_range)
1395                 pipe_config->limited_color_range = true;
1396
1397         intel_dp->link_bw = bws[clock];
1398         intel_dp->lane_count = lane_count;
1399         pipe_config->pipe_bpp = bpp;
1400         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1401
1402         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1403                       intel_dp->link_bw, intel_dp->lane_count,
1404                       pipe_config->port_clock, bpp);
1405         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1406                       mode_rate, link_avail);
1407
1408         intel_link_compute_m_n(bpp, lane_count,
1409                                adjusted_mode->crtc_clock,
1410                                pipe_config->port_clock,
1411                                &pipe_config->dp_m_n);
1412
1413         if (intel_connector->panel.downclock_mode != NULL &&
1414                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1415                         pipe_config->has_drrs = true;
1416                         intel_link_compute_m_n(bpp, lane_count,
1417                                 intel_connector->panel.downclock_mode->clock,
1418                                 pipe_config->port_clock,
1419                                 &pipe_config->dp_m2_n2);
1420         }
1421
1422         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1423                 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1424         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1425                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1426         else
1427                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1428
1429         return true;
1430 }
1431
1432 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1433 {
1434         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1435         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1436         struct drm_device *dev = crtc->base.dev;
1437         struct drm_i915_private *dev_priv = dev->dev_private;
1438         u32 dpa_ctl;
1439
1440         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1441                       crtc->config->port_clock);
1442         dpa_ctl = I915_READ(DP_A);
1443         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1444
1445         if (crtc->config->port_clock == 162000) {
1446                 /* For a long time we've carried around a ILK-DevA w/a for the
1447                  * 160MHz clock. If we're really unlucky, it's still required.
1448                  */
1449                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1450                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1451                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1452         } else {
1453                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1454                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1455         }
1456
1457         I915_WRITE(DP_A, dpa_ctl);
1458
1459         POSTING_READ(DP_A);
1460         udelay(500);
1461 }
1462
1463 static void intel_dp_prepare(struct intel_encoder *encoder)
1464 {
1465         struct drm_device *dev = encoder->base.dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1468         enum port port = dp_to_dig_port(intel_dp)->port;
1469         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1470         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1471
1472         /*
1473          * There are four kinds of DP registers:
1474          *
1475          *      IBX PCH
1476          *      SNB CPU
1477          *      IVB CPU
1478          *      CPT PCH
1479          *
1480          * IBX PCH and CPU are the same for almost everything,
1481          * except that the CPU DP PLL is configured in this
1482          * register
1483          *
1484          * CPT PCH is quite different, having many bits moved
1485          * to the TRANS_DP_CTL register instead. That
1486          * configuration happens (oddly) in ironlake_pch_enable
1487          */
1488
1489         /* Preserve the BIOS-computed detected bit. This is
1490          * supposed to be read-only.
1491          */
1492         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1493
1494         /* Handle DP bits in common between all three register formats */
1495         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1496         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1497
1498         if (crtc->config->has_audio)
1499                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1500
1501         /* Split out the IBX/CPU vs CPT settings */
1502
1503         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1504                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1505                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1506                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1507                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1508                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1509
1510                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1511                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1512
1513                 intel_dp->DP |= crtc->pipe << 29;
1514         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1515                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1516                         intel_dp->DP |= intel_dp->color_range;
1517
1518                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1519                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1520                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1521                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1522                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1523
1524                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1525                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1526
1527                 if (!IS_CHERRYVIEW(dev)) {
1528                         if (crtc->pipe == 1)
1529                                 intel_dp->DP |= DP_PIPEB_SELECT;
1530                 } else {
1531                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1532                 }
1533         } else {
1534                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1535         }
1536 }
1537
1538 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1539 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1540
1541 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1542 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1543
1544 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1545 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1546
1547 static void wait_panel_status(struct intel_dp *intel_dp,
1548                                        u32 mask,
1549                                        u32 value)
1550 {
1551         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1552         struct drm_i915_private *dev_priv = dev->dev_private;
1553         u32 pp_stat_reg, pp_ctrl_reg;
1554
1555         lockdep_assert_held(&dev_priv->pps_mutex);
1556
1557         pp_stat_reg = _pp_stat_reg(intel_dp);
1558         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1559
1560         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1561                         mask, value,
1562                         I915_READ(pp_stat_reg),
1563                         I915_READ(pp_ctrl_reg));
1564
1565         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1566                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1567                                 I915_READ(pp_stat_reg),
1568                                 I915_READ(pp_ctrl_reg));
1569         }
1570
1571         DRM_DEBUG_KMS("Wait complete\n");
1572 }
1573
1574 static void wait_panel_on(struct intel_dp *intel_dp)
1575 {
1576         DRM_DEBUG_KMS("Wait for panel power on\n");
1577         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1578 }
1579
1580 static void wait_panel_off(struct intel_dp *intel_dp)
1581 {
1582         DRM_DEBUG_KMS("Wait for panel power off time\n");
1583         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1584 }
1585
1586 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1587 {
1588         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1589
1590         /* When we disable the VDD override bit last we have to do the manual
1591          * wait. */
1592         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1593                                        intel_dp->panel_power_cycle_delay);
1594
1595         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1596 }
1597
1598 static void wait_backlight_on(struct intel_dp *intel_dp)
1599 {
1600         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1601                                        intel_dp->backlight_on_delay);
1602 }
1603
1604 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1605 {
1606         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1607                                        intel_dp->backlight_off_delay);
1608 }
1609
1610 /* Read the current pp_control value, unlocking the register if it
1611  * is locked
1612  */
1613
1614 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1615 {
1616         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         u32 control;
1619
1620         lockdep_assert_held(&dev_priv->pps_mutex);
1621
1622         control = I915_READ(_pp_ctrl_reg(intel_dp));
1623         control &= ~PANEL_UNLOCK_MASK;
1624         control |= PANEL_UNLOCK_REGS;
1625         return control;
1626 }
1627
1628 /*
1629  * Must be paired with edp_panel_vdd_off().
1630  * Must hold pps_mutex around the whole on/off sequence.
1631  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1632  */
1633 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1634 {
1635         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1636         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1637         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1638         struct drm_i915_private *dev_priv = dev->dev_private;
1639         enum intel_display_power_domain power_domain;
1640         u32 pp;
1641         u32 pp_stat_reg, pp_ctrl_reg;
1642         bool need_to_disable = !intel_dp->want_panel_vdd;
1643
1644         lockdep_assert_held(&dev_priv->pps_mutex);
1645
1646         if (!is_edp(intel_dp))
1647                 return false;
1648
1649         cancel_delayed_work(&intel_dp->panel_vdd_work);
1650         intel_dp->want_panel_vdd = true;
1651
1652         if (edp_have_panel_vdd(intel_dp))
1653                 return need_to_disable;
1654
1655         power_domain = intel_display_port_power_domain(intel_encoder);
1656         intel_display_power_get(dev_priv, power_domain);
1657
1658         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1659                       port_name(intel_dig_port->port));
1660
1661         if (!edp_have_panel_power(intel_dp))
1662                 wait_panel_power_cycle(intel_dp);
1663
1664         pp = ironlake_get_pp_control(intel_dp);
1665         pp |= EDP_FORCE_VDD;
1666
1667         pp_stat_reg = _pp_stat_reg(intel_dp);
1668         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1669
1670         I915_WRITE(pp_ctrl_reg, pp);
1671         POSTING_READ(pp_ctrl_reg);
1672         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1673                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1674         /*
1675          * If the panel wasn't on, delay before accessing aux channel
1676          */
1677         if (!edp_have_panel_power(intel_dp)) {
1678                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1679                               port_name(intel_dig_port->port));
1680                 msleep(intel_dp->panel_power_up_delay);
1681         }
1682
1683         return need_to_disable;
1684 }
1685
1686 /*
1687  * Must be paired with intel_edp_panel_vdd_off() or
1688  * intel_edp_panel_off().
1689  * Nested calls to these functions are not allowed since
1690  * we drop the lock. Caller must use some higher level
1691  * locking to prevent nested calls from other threads.
1692  */
1693 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1694 {
1695         bool vdd;
1696
1697         if (!is_edp(intel_dp))
1698                 return;
1699
1700         pps_lock(intel_dp);
1701         vdd = edp_panel_vdd_on(intel_dp);
1702         pps_unlock(intel_dp);
1703
1704         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1705              port_name(dp_to_dig_port(intel_dp)->port));
1706 }
1707
1708 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1709 {
1710         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1711         struct drm_i915_private *dev_priv = dev->dev_private;
1712         struct intel_digital_port *intel_dig_port =
1713                 dp_to_dig_port(intel_dp);
1714         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1715         enum intel_display_power_domain power_domain;
1716         u32 pp;
1717         u32 pp_stat_reg, pp_ctrl_reg;
1718
1719         lockdep_assert_held(&dev_priv->pps_mutex);
1720
1721         WARN_ON(intel_dp->want_panel_vdd);
1722
1723         if (!edp_have_panel_vdd(intel_dp))
1724                 return;
1725
1726         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1727                       port_name(intel_dig_port->port));
1728
1729         pp = ironlake_get_pp_control(intel_dp);
1730         pp &= ~EDP_FORCE_VDD;
1731
1732         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1733         pp_stat_reg = _pp_stat_reg(intel_dp);
1734
1735         I915_WRITE(pp_ctrl_reg, pp);
1736         POSTING_READ(pp_ctrl_reg);
1737
1738         /* Make sure sequencer is idle before allowing subsequent activity */
1739         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1740         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1741
1742         if ((pp & POWER_TARGET_ON) == 0)
1743                 intel_dp->last_power_cycle = jiffies;
1744
1745         power_domain = intel_display_port_power_domain(intel_encoder);
1746         intel_display_power_put(dev_priv, power_domain);
1747 }
1748
1749 static void edp_panel_vdd_work(struct work_struct *__work)
1750 {
1751         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1752                                                  struct intel_dp, panel_vdd_work);
1753
1754         pps_lock(intel_dp);
1755         if (!intel_dp->want_panel_vdd)
1756                 edp_panel_vdd_off_sync(intel_dp);
1757         pps_unlock(intel_dp);
1758 }
1759
1760 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1761 {
1762         unsigned long delay;
1763
1764         /*
1765          * Queue the timer to fire a long time from now (relative to the power
1766          * down delay) to keep the panel power up across a sequence of
1767          * operations.
1768          */
1769         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1770         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1771 }
1772
1773 /*
1774  * Must be paired with edp_panel_vdd_on().
1775  * Must hold pps_mutex around the whole on/off sequence.
1776  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1777  */
1778 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1779 {
1780         struct drm_i915_private *dev_priv =
1781                 intel_dp_to_dev(intel_dp)->dev_private;
1782
1783         lockdep_assert_held(&dev_priv->pps_mutex);
1784
1785         if (!is_edp(intel_dp))
1786                 return;
1787
1788         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1789              port_name(dp_to_dig_port(intel_dp)->port));
1790
1791         intel_dp->want_panel_vdd = false;
1792
1793         if (sync)
1794                 edp_panel_vdd_off_sync(intel_dp);
1795         else
1796                 edp_panel_vdd_schedule_off(intel_dp);
1797 }
1798
1799 static void edp_panel_on(struct intel_dp *intel_dp)
1800 {
1801         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1802         struct drm_i915_private *dev_priv = dev->dev_private;
1803         u32 pp;
1804         u32 pp_ctrl_reg;
1805
1806         lockdep_assert_held(&dev_priv->pps_mutex);
1807
1808         if (!is_edp(intel_dp))
1809                 return;
1810
1811         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1812                       port_name(dp_to_dig_port(intel_dp)->port));
1813
1814         if (WARN(edp_have_panel_power(intel_dp),
1815                  "eDP port %c panel power already on\n",
1816                  port_name(dp_to_dig_port(intel_dp)->port)))
1817                 return;
1818
1819         wait_panel_power_cycle(intel_dp);
1820
1821         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1822         pp = ironlake_get_pp_control(intel_dp);
1823         if (IS_GEN5(dev)) {
1824                 /* ILK workaround: disable reset around power sequence */
1825                 pp &= ~PANEL_POWER_RESET;
1826                 I915_WRITE(pp_ctrl_reg, pp);
1827                 POSTING_READ(pp_ctrl_reg);
1828         }
1829
1830         pp |= POWER_TARGET_ON;
1831         if (!IS_GEN5(dev))
1832                 pp |= PANEL_POWER_RESET;
1833
1834         I915_WRITE(pp_ctrl_reg, pp);
1835         POSTING_READ(pp_ctrl_reg);
1836
1837         wait_panel_on(intel_dp);
1838         intel_dp->last_power_on = jiffies;
1839
1840         if (IS_GEN5(dev)) {
1841                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1842                 I915_WRITE(pp_ctrl_reg, pp);
1843                 POSTING_READ(pp_ctrl_reg);
1844         }
1845 }
1846
1847 void intel_edp_panel_on(struct intel_dp *intel_dp)
1848 {
1849         if (!is_edp(intel_dp))
1850                 return;
1851
1852         pps_lock(intel_dp);
1853         edp_panel_on(intel_dp);
1854         pps_unlock(intel_dp);
1855 }
1856
1857
1858 static void edp_panel_off(struct intel_dp *intel_dp)
1859 {
1860         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1861         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1862         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1863         struct drm_i915_private *dev_priv = dev->dev_private;
1864         enum intel_display_power_domain power_domain;
1865         u32 pp;
1866         u32 pp_ctrl_reg;
1867
1868         lockdep_assert_held(&dev_priv->pps_mutex);
1869
1870         if (!is_edp(intel_dp))
1871                 return;
1872
1873         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1874                       port_name(dp_to_dig_port(intel_dp)->port));
1875
1876         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1877              port_name(dp_to_dig_port(intel_dp)->port));
1878
1879         pp = ironlake_get_pp_control(intel_dp);
1880         /* We need to switch off panel power _and_ force vdd, for otherwise some
1881          * panels get very unhappy and cease to work. */
1882         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1883                 EDP_BLC_ENABLE);
1884
1885         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1886
1887         intel_dp->want_panel_vdd = false;
1888
1889         I915_WRITE(pp_ctrl_reg, pp);
1890         POSTING_READ(pp_ctrl_reg);
1891
1892         intel_dp->last_power_cycle = jiffies;
1893         wait_panel_off(intel_dp);
1894
1895         /* We got a reference when we enabled the VDD. */
1896         power_domain = intel_display_port_power_domain(intel_encoder);
1897         intel_display_power_put(dev_priv, power_domain);
1898 }
1899
1900 void intel_edp_panel_off(struct intel_dp *intel_dp)
1901 {
1902         if (!is_edp(intel_dp))
1903                 return;
1904
1905         pps_lock(intel_dp);
1906         edp_panel_off(intel_dp);
1907         pps_unlock(intel_dp);
1908 }
1909
1910 /* Enable backlight in the panel power control. */
1911 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1912 {
1913         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1914         struct drm_device *dev = intel_dig_port->base.base.dev;
1915         struct drm_i915_private *dev_priv = dev->dev_private;
1916         u32 pp;
1917         u32 pp_ctrl_reg;
1918
1919         /*
1920          * If we enable the backlight right away following a panel power
1921          * on, we may see slight flicker as the panel syncs with the eDP
1922          * link.  So delay a bit to make sure the image is solid before
1923          * allowing it to appear.
1924          */
1925         wait_backlight_on(intel_dp);
1926
1927         pps_lock(intel_dp);
1928
1929         pp = ironlake_get_pp_control(intel_dp);
1930         pp |= EDP_BLC_ENABLE;
1931
1932         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1933
1934         I915_WRITE(pp_ctrl_reg, pp);
1935         POSTING_READ(pp_ctrl_reg);
1936
1937         pps_unlock(intel_dp);
1938 }
1939
1940 /* Enable backlight PWM and backlight PP control. */
1941 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1942 {
1943         if (!is_edp(intel_dp))
1944                 return;
1945
1946         DRM_DEBUG_KMS("\n");
1947
1948         intel_panel_enable_backlight(intel_dp->attached_connector);
1949         _intel_edp_backlight_on(intel_dp);
1950 }
1951
1952 /* Disable backlight in the panel power control. */
1953 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1954 {
1955         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1956         struct drm_i915_private *dev_priv = dev->dev_private;
1957         u32 pp;
1958         u32 pp_ctrl_reg;
1959
1960         if (!is_edp(intel_dp))
1961                 return;
1962
1963         pps_lock(intel_dp);
1964
1965         pp = ironlake_get_pp_control(intel_dp);
1966         pp &= ~EDP_BLC_ENABLE;
1967
1968         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1969
1970         I915_WRITE(pp_ctrl_reg, pp);
1971         POSTING_READ(pp_ctrl_reg);
1972
1973         pps_unlock(intel_dp);
1974
1975         intel_dp->last_backlight_off = jiffies;
1976         edp_wait_backlight_off(intel_dp);
1977 }
1978
1979 /* Disable backlight PP control and backlight PWM. */
1980 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1981 {
1982         if (!is_edp(intel_dp))
1983                 return;
1984
1985         DRM_DEBUG_KMS("\n");
1986
1987         _intel_edp_backlight_off(intel_dp);
1988         intel_panel_disable_backlight(intel_dp->attached_connector);
1989 }
1990
1991 /*
1992  * Hook for controlling the panel power control backlight through the bl_power
1993  * sysfs attribute. Take care to handle multiple calls.
1994  */
1995 static void intel_edp_backlight_power(struct intel_connector *connector,
1996                                       bool enable)
1997 {
1998         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1999         bool is_enabled;
2000
2001         pps_lock(intel_dp);
2002         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2003         pps_unlock(intel_dp);
2004
2005         if (is_enabled == enable)
2006                 return;
2007
2008         DRM_DEBUG_KMS("panel power control backlight %s\n",
2009                       enable ? "enable" : "disable");
2010
2011         if (enable)
2012                 _intel_edp_backlight_on(intel_dp);
2013         else
2014                 _intel_edp_backlight_off(intel_dp);
2015 }
2016
2017 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2018 {
2019         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2020         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2021         struct drm_device *dev = crtc->dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         u32 dpa_ctl;
2024
2025         assert_pipe_disabled(dev_priv,
2026                              to_intel_crtc(crtc)->pipe);
2027
2028         DRM_DEBUG_KMS("\n");
2029         dpa_ctl = I915_READ(DP_A);
2030         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2031         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2032
2033         /* We don't adjust intel_dp->DP while tearing down the link, to
2034          * facilitate link retraining (e.g. after hotplug). Hence clear all
2035          * enable bits here to ensure that we don't enable too much. */
2036         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2037         intel_dp->DP |= DP_PLL_ENABLE;
2038         I915_WRITE(DP_A, intel_dp->DP);
2039         POSTING_READ(DP_A);
2040         udelay(200);
2041 }
2042
2043 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2044 {
2045         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2046         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2047         struct drm_device *dev = crtc->dev;
2048         struct drm_i915_private *dev_priv = dev->dev_private;
2049         u32 dpa_ctl;
2050
2051         assert_pipe_disabled(dev_priv,
2052                              to_intel_crtc(crtc)->pipe);
2053
2054         dpa_ctl = I915_READ(DP_A);
2055         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2056              "dp pll off, should be on\n");
2057         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2058
2059         /* We can't rely on the value tracked for the DP register in
2060          * intel_dp->DP because link_down must not change that (otherwise link
2061          * re-training will fail. */
2062         dpa_ctl &= ~DP_PLL_ENABLE;
2063         I915_WRITE(DP_A, dpa_ctl);
2064         POSTING_READ(DP_A);
2065         udelay(200);
2066 }
2067
2068 /* If the sink supports it, try to set the power state appropriately */
2069 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2070 {
2071         int ret, i;
2072
2073         /* Should have a valid DPCD by this point */
2074         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2075                 return;
2076
2077         if (mode != DRM_MODE_DPMS_ON) {
2078                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2079                                          DP_SET_POWER_D3);
2080         } else {
2081                 /*
2082                  * When turning on, we need to retry for 1ms to give the sink
2083                  * time to wake up.
2084                  */
2085                 for (i = 0; i < 3; i++) {
2086                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2087                                                  DP_SET_POWER_D0);
2088                         if (ret == 1)
2089                                 break;
2090                         msleep(1);
2091                 }
2092         }
2093
2094         if (ret != 1)
2095                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2096                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2097 }
2098
2099 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2100                                   enum i915_pipe *pipe)
2101 {
2102         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103         enum port port = dp_to_dig_port(intel_dp)->port;
2104         struct drm_device *dev = encoder->base.dev;
2105         struct drm_i915_private *dev_priv = dev->dev_private;
2106         enum intel_display_power_domain power_domain;
2107         u32 tmp;
2108
2109         power_domain = intel_display_port_power_domain(encoder);
2110         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2111                 return false;
2112
2113         tmp = I915_READ(intel_dp->output_reg);
2114
2115         if (!(tmp & DP_PORT_EN))
2116                 return false;
2117
2118         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
2119                 *pipe = PORT_TO_PIPE_CPT(tmp);
2120         } else if (IS_CHERRYVIEW(dev)) {
2121                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2122         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
2123                 *pipe = PORT_TO_PIPE(tmp);
2124         } else {
2125                 u32 trans_sel;
2126                 u32 trans_dp;
2127                 int i;
2128
2129                 switch (intel_dp->output_reg) {
2130                 case PCH_DP_B:
2131                         trans_sel = TRANS_DP_PORT_SEL_B;
2132                         break;
2133                 case PCH_DP_C:
2134                         trans_sel = TRANS_DP_PORT_SEL_C;
2135                         break;
2136                 case PCH_DP_D:
2137                         trans_sel = TRANS_DP_PORT_SEL_D;
2138                         break;
2139                 default:
2140                         return true;
2141                 }
2142
2143                 for_each_pipe(dev_priv, i) {
2144                         trans_dp = I915_READ(TRANS_DP_CTL(i));
2145                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2146                                 *pipe = i;
2147                                 return true;
2148                         }
2149                 }
2150
2151                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2152                               intel_dp->output_reg);
2153         }
2154
2155         return true;
2156 }
2157
2158 static void intel_dp_get_config(struct intel_encoder *encoder,
2159                                 struct intel_crtc_state *pipe_config)
2160 {
2161         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2162         u32 tmp, flags = 0;
2163         struct drm_device *dev = encoder->base.dev;
2164         struct drm_i915_private *dev_priv = dev->dev_private;
2165         enum port port = dp_to_dig_port(intel_dp)->port;
2166         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2167         int dotclock;
2168
2169         tmp = I915_READ(intel_dp->output_reg);
2170         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2171                 pipe_config->has_audio = true;
2172
2173         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
2174                 if (tmp & DP_SYNC_HS_HIGH)
2175                         flags |= DRM_MODE_FLAG_PHSYNC;
2176                 else
2177                         flags |= DRM_MODE_FLAG_NHSYNC;
2178
2179                 if (tmp & DP_SYNC_VS_HIGH)
2180                         flags |= DRM_MODE_FLAG_PVSYNC;
2181                 else
2182                         flags |= DRM_MODE_FLAG_NVSYNC;
2183         } else {
2184                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2185                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2186                         flags |= DRM_MODE_FLAG_PHSYNC;
2187                 else
2188                         flags |= DRM_MODE_FLAG_NHSYNC;
2189
2190                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2191                         flags |= DRM_MODE_FLAG_PVSYNC;
2192                 else
2193                         flags |= DRM_MODE_FLAG_NVSYNC;
2194         }
2195
2196         pipe_config->base.adjusted_mode.flags |= flags;
2197
2198         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2199             tmp & DP_COLOR_RANGE_16_235)
2200                 pipe_config->limited_color_range = true;
2201
2202         pipe_config->has_dp_encoder = true;
2203
2204         intel_dp_get_m_n(crtc, pipe_config);
2205
2206         if (port == PORT_A) {
2207                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2208                         pipe_config->port_clock = 162000;
2209                 else
2210                         pipe_config->port_clock = 270000;
2211         }
2212
2213         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2214                                             &pipe_config->dp_m_n);
2215
2216         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2217                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2218
2219         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2220
2221         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2222             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2223                 /*
2224                  * This is a big fat ugly hack.
2225                  *
2226                  * Some machines in UEFI boot mode provide us a VBT that has 18
2227                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2228                  * unknown we fail to light up. Yet the same BIOS boots up with
2229                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2230                  * max, not what it tells us to use.
2231                  *
2232                  * Note: This will still be broken if the eDP panel is not lit
2233                  * up by the BIOS, and thus we can't get the mode at module
2234                  * load.
2235                  */
2236                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2237                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2238                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2239         }
2240 }
2241
2242 static void intel_disable_dp(struct intel_encoder *encoder)
2243 {
2244         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2245         struct drm_device *dev = encoder->base.dev;
2246         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2247
2248         if (crtc->config->has_audio)
2249                 intel_audio_codec_disable(encoder);
2250
2251         if (HAS_PSR(dev) && !HAS_DDI(dev))
2252                 intel_psr_disable(intel_dp);
2253
2254         /* Make sure the panel is off before trying to change the mode. But also
2255          * ensure that we have vdd while we switch off the panel. */
2256         intel_edp_panel_vdd_on(intel_dp);
2257         intel_edp_backlight_off(intel_dp);
2258         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2259         intel_edp_panel_off(intel_dp);
2260
2261         /* disable the port before the pipe on g4x */
2262         if (INTEL_INFO(dev)->gen < 5)
2263                 intel_dp_link_down(intel_dp);
2264 }
2265
2266 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2267 {
2268         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2269         enum port port = dp_to_dig_port(intel_dp)->port;
2270
2271         intel_dp_link_down(intel_dp);
2272         if (port == PORT_A)
2273                 ironlake_edp_pll_off(intel_dp);
2274 }
2275
2276 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2277 {
2278         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2279
2280         intel_dp_link_down(intel_dp);
2281 }
2282
2283 static void chv_post_disable_dp(struct intel_encoder *encoder)
2284 {
2285         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2286         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2287         struct drm_device *dev = encoder->base.dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc *intel_crtc =
2290                 to_intel_crtc(encoder->base.crtc);
2291         enum dpio_channel ch = vlv_dport_to_channel(dport);
2292         enum i915_pipe pipe = intel_crtc->pipe;
2293         u32 val;
2294
2295         intel_dp_link_down(intel_dp);
2296
2297         mutex_lock(&dev_priv->dpio_lock);
2298
2299         /* Propagate soft reset to data lane reset */
2300         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2301         val |= CHV_PCS_REQ_SOFTRESET_EN;
2302         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2303
2304         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2305         val |= CHV_PCS_REQ_SOFTRESET_EN;
2306         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2307
2308         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2309         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2310         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2311
2312         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2313         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2314         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2315
2316         mutex_unlock(&dev_priv->dpio_lock);
2317 }
2318
2319 static void
2320 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2321                          uint32_t *DP,
2322                          uint8_t dp_train_pat)
2323 {
2324         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2325         struct drm_device *dev = intel_dig_port->base.base.dev;
2326         struct drm_i915_private *dev_priv = dev->dev_private;
2327         enum port port = intel_dig_port->port;
2328
2329         if (HAS_DDI(dev)) {
2330                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2331
2332                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2333                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2334                 else
2335                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2336
2337                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2338                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2339                 case DP_TRAINING_PATTERN_DISABLE:
2340                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2341
2342                         break;
2343                 case DP_TRAINING_PATTERN_1:
2344                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2345                         break;
2346                 case DP_TRAINING_PATTERN_2:
2347                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2348                         break;
2349                 case DP_TRAINING_PATTERN_3:
2350                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2351                         break;
2352                 }
2353                 I915_WRITE(DP_TP_CTL(port), temp);
2354
2355         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2356                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2357
2358                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2359                 case DP_TRAINING_PATTERN_DISABLE:
2360                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2361                         break;
2362                 case DP_TRAINING_PATTERN_1:
2363                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2364                         break;
2365                 case DP_TRAINING_PATTERN_2:
2366                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2367                         break;
2368                 case DP_TRAINING_PATTERN_3:
2369                         DRM_ERROR("DP training pattern 3 not supported\n");
2370                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2371                         break;
2372                 }
2373
2374         } else {
2375                 if (IS_CHERRYVIEW(dev))
2376                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2377                 else
2378                         *DP &= ~DP_LINK_TRAIN_MASK;
2379
2380                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2381                 case DP_TRAINING_PATTERN_DISABLE:
2382                         *DP |= DP_LINK_TRAIN_OFF;
2383                         break;
2384                 case DP_TRAINING_PATTERN_1:
2385                         *DP |= DP_LINK_TRAIN_PAT_1;
2386                         break;
2387                 case DP_TRAINING_PATTERN_2:
2388                         *DP |= DP_LINK_TRAIN_PAT_2;
2389                         break;
2390                 case DP_TRAINING_PATTERN_3:
2391                         if (IS_CHERRYVIEW(dev)) {
2392                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2393                         } else {
2394                                 DRM_ERROR("DP training pattern 3 not supported\n");
2395                                 *DP |= DP_LINK_TRAIN_PAT_2;
2396                         }
2397                         break;
2398                 }
2399         }
2400 }
2401
2402 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2403 {
2404         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406
2407         /* enable with pattern 1 (as per spec) */
2408         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2409                                  DP_TRAINING_PATTERN_1);
2410
2411         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2412         POSTING_READ(intel_dp->output_reg);
2413
2414         /*
2415          * Magic for VLV/CHV. We _must_ first set up the register
2416          * without actually enabling the port, and then do another
2417          * write to enable the port. Otherwise link training will
2418          * fail when the power sequencer is freshly used for this port.
2419          */
2420         intel_dp->DP |= DP_PORT_EN;
2421
2422         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2423         POSTING_READ(intel_dp->output_reg);
2424 }
2425
2426 static void intel_enable_dp(struct intel_encoder *encoder)
2427 {
2428         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2429         struct drm_device *dev = encoder->base.dev;
2430         struct drm_i915_private *dev_priv = dev->dev_private;
2431         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2432         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2433
2434         if (WARN_ON(dp_reg & DP_PORT_EN))
2435                 return;
2436
2437         pps_lock(intel_dp);
2438
2439         if (IS_VALLEYVIEW(dev))
2440                 vlv_init_panel_power_sequencer(intel_dp);
2441
2442         intel_dp_enable_port(intel_dp);
2443
2444         edp_panel_vdd_on(intel_dp);
2445         edp_panel_on(intel_dp);
2446         edp_panel_vdd_off(intel_dp, true);
2447
2448         pps_unlock(intel_dp);
2449
2450         if (IS_VALLEYVIEW(dev))
2451                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2452
2453         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2454         intel_dp_start_link_train(intel_dp);
2455         intel_dp_complete_link_train(intel_dp);
2456         intel_dp_stop_link_train(intel_dp);
2457
2458         if (crtc->config->has_audio) {
2459                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2460                                  pipe_name(crtc->pipe));
2461                 intel_audio_codec_enable(encoder);
2462         }
2463 }
2464
2465 static void g4x_enable_dp(struct intel_encoder *encoder)
2466 {
2467         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2468
2469         intel_enable_dp(encoder);
2470         intel_edp_backlight_on(intel_dp);
2471 }
2472
2473 static void vlv_enable_dp(struct intel_encoder *encoder)
2474 {
2475         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2476
2477         intel_edp_backlight_on(intel_dp);
2478         intel_psr_enable(intel_dp);
2479 }
2480
2481 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2482 {
2483         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2485
2486         intel_dp_prepare(encoder);
2487
2488         /* Only ilk+ has port A */
2489         if (dport->port == PORT_A) {
2490                 ironlake_set_pll_cpu_edp(intel_dp);
2491                 ironlake_edp_pll_on(intel_dp);
2492         }
2493 }
2494
2495 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2496 {
2497         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2498         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2499         enum i915_pipe pipe = intel_dp->pps_pipe;
2500         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2501
2502         edp_panel_vdd_off_sync(intel_dp);
2503
2504         /*
2505          * VLV seems to get confused when multiple power seqeuencers
2506          * have the same port selected (even if only one has power/vdd
2507          * enabled). The failure manifests as vlv_wait_port_ready() failing
2508          * CHV on the other hand doesn't seem to mind having the same port
2509          * selected in multiple power seqeuencers, but let's clear the
2510          * port select always when logically disconnecting a power sequencer
2511          * from a port.
2512          */
2513         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2514                       pipe_name(pipe), port_name(intel_dig_port->port));
2515         I915_WRITE(pp_on_reg, 0);
2516         POSTING_READ(pp_on_reg);
2517
2518         intel_dp->pps_pipe = INVALID_PIPE;
2519 }
2520
2521 static void vlv_steal_power_sequencer(struct drm_device *dev,
2522                                       enum i915_pipe pipe)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         struct intel_encoder *encoder;
2526
2527         lockdep_assert_held(&dev_priv->pps_mutex);
2528
2529         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2530                 return;
2531
2532         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2533                             base.head) {
2534                 struct intel_dp *intel_dp;
2535                 enum port port;
2536
2537                 if (encoder->type != INTEL_OUTPUT_EDP)
2538                         continue;
2539
2540                 intel_dp = enc_to_intel_dp(&encoder->base);
2541                 port = dp_to_dig_port(intel_dp)->port;
2542
2543                 if (intel_dp->pps_pipe != pipe)
2544                         continue;
2545
2546                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2547                               pipe_name(pipe), port_name(port));
2548
2549                 WARN(encoder->connectors_active,
2550                      "stealing pipe %c power sequencer from active eDP port %c\n",
2551                      pipe_name(pipe), port_name(port));
2552
2553                 /* make sure vdd is off before we steal it */
2554                 vlv_detach_power_sequencer(intel_dp);
2555         }
2556 }
2557
2558 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2559 {
2560         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2561         struct intel_encoder *encoder = &intel_dig_port->base;
2562         struct drm_device *dev = encoder->base.dev;
2563         struct drm_i915_private *dev_priv = dev->dev_private;
2564         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2565
2566         lockdep_assert_held(&dev_priv->pps_mutex);
2567
2568         if (!is_edp(intel_dp))
2569                 return;
2570
2571         if (intel_dp->pps_pipe == crtc->pipe)
2572                 return;
2573
2574         /*
2575          * If another power sequencer was being used on this
2576          * port previously make sure to turn off vdd there while
2577          * we still have control of it.
2578          */
2579         if (intel_dp->pps_pipe != INVALID_PIPE)
2580                 vlv_detach_power_sequencer(intel_dp);
2581
2582         /*
2583          * We may be stealing the power
2584          * sequencer from another port.
2585          */
2586         vlv_steal_power_sequencer(dev, crtc->pipe);
2587
2588         /* now it's all ours */
2589         intel_dp->pps_pipe = crtc->pipe;
2590
2591         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2592                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2593
2594         /* init power sequencer on this pipe and port */
2595         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2596         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2597 }
2598
2599 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2600 {
2601         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2602         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2603         struct drm_device *dev = encoder->base.dev;
2604         struct drm_i915_private *dev_priv = dev->dev_private;
2605         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2606         enum dpio_channel port = vlv_dport_to_channel(dport);
2607         int pipe = intel_crtc->pipe;
2608         u32 val;
2609
2610         mutex_lock(&dev_priv->dpio_lock);
2611
2612         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2613         val = 0;
2614         if (pipe)
2615                 val |= (1<<21);
2616         else
2617                 val &= ~(1<<21);
2618         val |= 0x001000c4;
2619         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2620         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2621         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2622
2623         mutex_unlock(&dev_priv->dpio_lock);
2624
2625         intel_enable_dp(encoder);
2626 }
2627
2628 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2629 {
2630         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2631         struct drm_device *dev = encoder->base.dev;
2632         struct drm_i915_private *dev_priv = dev->dev_private;
2633         struct intel_crtc *intel_crtc =
2634                 to_intel_crtc(encoder->base.crtc);
2635         enum dpio_channel port = vlv_dport_to_channel(dport);
2636         int pipe = intel_crtc->pipe;
2637
2638         intel_dp_prepare(encoder);
2639
2640         /* Program Tx lane resets to default */
2641         mutex_lock(&dev_priv->dpio_lock);
2642         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2643                          DPIO_PCS_TX_LANE2_RESET |
2644                          DPIO_PCS_TX_LANE1_RESET);
2645         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2646                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2647                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2648                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2649                                  DPIO_PCS_CLK_SOFT_RESET);
2650
2651         /* Fix up inter-pair skew failure */
2652         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2653         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2654         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2655         mutex_unlock(&dev_priv->dpio_lock);
2656 }
2657
2658 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2659 {
2660         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2661         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2662         struct drm_device *dev = encoder->base.dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc =
2665                 to_intel_crtc(encoder->base.crtc);
2666         enum dpio_channel ch = vlv_dport_to_channel(dport);
2667         int pipe = intel_crtc->pipe;
2668         int data, i;
2669         u32 val;
2670
2671         mutex_lock(&dev_priv->dpio_lock);
2672
2673         /* allow hardware to manage TX FIFO reset source */
2674         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2675         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2676         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2677
2678         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2679         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2680         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2681
2682         /* Deassert soft data lane reset*/
2683         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2684         val |= CHV_PCS_REQ_SOFTRESET_EN;
2685         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2686
2687         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2688         val |= CHV_PCS_REQ_SOFTRESET_EN;
2689         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2690
2691         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2692         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2693         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2694
2695         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2696         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2697         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2698
2699         /* Program Tx lane latency optimal setting*/
2700         for (i = 0; i < 4; i++) {
2701                 /* Set the latency optimal bit */
2702                 data = (i == 1) ? 0x0 : 0x6;
2703                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2704                                 data << DPIO_FRC_LATENCY_SHFIT);
2705
2706                 /* Set the upar bit */
2707                 data = (i == 1) ? 0x0 : 0x1;
2708                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2709                                 data << DPIO_UPAR_SHIFT);
2710         }
2711
2712         /* Data lane stagger programming */
2713         /* FIXME: Fix up value only after power analysis */
2714
2715         mutex_unlock(&dev_priv->dpio_lock);
2716
2717         intel_enable_dp(encoder);
2718 }
2719
2720 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2721 {
2722         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2723         struct drm_device *dev = encoder->base.dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         struct intel_crtc *intel_crtc =
2726                 to_intel_crtc(encoder->base.crtc);
2727         enum dpio_channel ch = vlv_dport_to_channel(dport);
2728         enum i915_pipe pipe = intel_crtc->pipe;
2729         u32 val;
2730
2731         mutex_lock(&dev_priv->dpio_lock);
2732
2733         /* program left/right clock distribution */
2734         if (pipe != PIPE_B) {
2735                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2736                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2737                 if (ch == DPIO_CH0)
2738                         val |= CHV_BUFLEFTENA1_FORCE;
2739                 if (ch == DPIO_CH1)
2740                         val |= CHV_BUFRIGHTENA1_FORCE;
2741                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2742         } else {
2743                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2744                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2745                 if (ch == DPIO_CH0)
2746                         val |= CHV_BUFLEFTENA2_FORCE;
2747                 if (ch == DPIO_CH1)
2748                         val |= CHV_BUFRIGHTENA2_FORCE;
2749                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2750         }
2751
2752         /* program clock channel usage */
2753         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2754         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2755         if (pipe != PIPE_B)
2756                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2757         else
2758                 val |= CHV_PCS_USEDCLKCHANNEL;
2759         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2760
2761         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2762         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2763         if (pipe != PIPE_B)
2764                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2765         else
2766                 val |= CHV_PCS_USEDCLKCHANNEL;
2767         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2768
2769         /*
2770          * This a a bit weird since generally CL
2771          * matches the pipe, but here we need to
2772          * pick the CL based on the port.
2773          */
2774         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2775         if (pipe != PIPE_B)
2776                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2777         else
2778                 val |= CHV_CMN_USEDCLKCHANNEL;
2779         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2780
2781         mutex_unlock(&dev_priv->dpio_lock);
2782 }
2783
2784 /*
2785  * Native read with retry for link status and receiver capability reads for
2786  * cases where the sink may still be asleep.
2787  *
2788  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2789  * supposed to retry 3 times per the spec.
2790  */
2791 static ssize_t
2792 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2793                         void *buffer, size_t size)
2794 {
2795         ssize_t ret;
2796         int i;
2797
2798         /*
2799          * Sometime we just get the same incorrect byte repeated
2800          * over the entire buffer. Doing just one throw away read
2801          * initially seems to "solve" it.
2802          */
2803         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2804
2805         for (i = 0; i < 3; i++) {
2806                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2807                 if (ret == size)
2808                         return ret;
2809                 msleep(1);
2810         }
2811
2812         return ret;
2813 }
2814
2815 /*
2816  * Fetch AUX CH registers 0x202 - 0x207 which contain
2817  * link status information
2818  */
2819 static bool
2820 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2821 {
2822         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2823                                        DP_LANE0_1_STATUS,
2824                                        link_status,
2825                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2826 }
2827
2828 /* These are source-specific values. */
2829 static uint8_t
2830 intel_dp_voltage_max(struct intel_dp *intel_dp)
2831 {
2832         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2833         enum port port = dp_to_dig_port(intel_dp)->port;
2834
2835         if (INTEL_INFO(dev)->gen >= 9)
2836                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2837         else if (IS_VALLEYVIEW(dev))
2838                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2839         else if (IS_GEN7(dev) && port == PORT_A)
2840                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2841         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2842                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2843         else
2844                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2845 }
2846
2847 static uint8_t
2848 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2849 {
2850         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2851         enum port port = dp_to_dig_port(intel_dp)->port;
2852
2853         if (INTEL_INFO(dev)->gen >= 9) {
2854                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2855                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2856                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2857                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2858                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2859                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2860                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2861                 default:
2862                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2863                 }
2864         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2865                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2866                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2867                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2868                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2869                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2870                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2871                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2872                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2873                 default:
2874                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2875                 }
2876         } else if (IS_VALLEYVIEW(dev)) {
2877                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2878                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2879                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2880                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2881                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2882                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2883                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2884                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2885                 default:
2886                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2887                 }
2888         } else if (IS_GEN7(dev) && port == PORT_A) {
2889                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2890                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2891                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2892                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2893                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2894                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2895                 default:
2896                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2897                 }
2898         } else {
2899                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2900                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2901                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2902                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2903                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2904                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2905                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2906                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2907                 default:
2908                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2909                 }
2910         }
2911 }
2912
2913 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2914 {
2915         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2918         struct intel_crtc *intel_crtc =
2919                 to_intel_crtc(dport->base.base.crtc);
2920         unsigned long demph_reg_value, preemph_reg_value,
2921                 uniqtranscale_reg_value;
2922         uint8_t train_set = intel_dp->train_set[0];
2923         enum dpio_channel port = vlv_dport_to_channel(dport);
2924         int pipe = intel_crtc->pipe;
2925
2926         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2927         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2928                 preemph_reg_value = 0x0004000;
2929                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2930                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2931                         demph_reg_value = 0x2B405555;
2932                         uniqtranscale_reg_value = 0x552AB83A;
2933                         break;
2934                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2935                         demph_reg_value = 0x2B404040;
2936                         uniqtranscale_reg_value = 0x5548B83A;
2937                         break;
2938                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2939                         demph_reg_value = 0x2B245555;
2940                         uniqtranscale_reg_value = 0x5560B83A;
2941                         break;
2942                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2943                         demph_reg_value = 0x2B405555;
2944                         uniqtranscale_reg_value = 0x5598DA3A;
2945                         break;
2946                 default:
2947                         return 0;
2948                 }
2949                 break;
2950         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2951                 preemph_reg_value = 0x0002000;
2952                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2953                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2954                         demph_reg_value = 0x2B404040;
2955                         uniqtranscale_reg_value = 0x5552B83A;
2956                         break;
2957                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2958                         demph_reg_value = 0x2B404848;
2959                         uniqtranscale_reg_value = 0x5580B83A;
2960                         break;
2961                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2962                         demph_reg_value = 0x2B404040;
2963                         uniqtranscale_reg_value = 0x55ADDA3A;
2964                         break;
2965                 default:
2966                         return 0;
2967                 }
2968                 break;
2969         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2970                 preemph_reg_value = 0x0000000;
2971                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2972                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2973                         demph_reg_value = 0x2B305555;
2974                         uniqtranscale_reg_value = 0x5570B83A;
2975                         break;
2976                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2977                         demph_reg_value = 0x2B2B4040;
2978                         uniqtranscale_reg_value = 0x55ADDA3A;
2979                         break;
2980                 default:
2981                         return 0;
2982                 }
2983                 break;
2984         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2985                 preemph_reg_value = 0x0006000;
2986                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2987                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2988                         demph_reg_value = 0x1B405555;
2989                         uniqtranscale_reg_value = 0x55ADDA3A;
2990                         break;
2991                 default:
2992                         return 0;
2993                 }
2994                 break;
2995         default:
2996                 return 0;
2997         }
2998
2999         mutex_lock(&dev_priv->dpio_lock);
3000         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3001         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3002         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3003                          uniqtranscale_reg_value);
3004         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3005         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3006         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3007         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3008         mutex_unlock(&dev_priv->dpio_lock);
3009
3010         return 0;
3011 }
3012
3013 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3014 {
3015         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3018         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3019         u32 deemph_reg_value, margin_reg_value, val;
3020         uint8_t train_set = intel_dp->train_set[0];
3021         enum dpio_channel ch = vlv_dport_to_channel(dport);
3022         enum i915_pipe pipe = intel_crtc->pipe;
3023         int i;
3024
3025         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3026         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3027                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3028                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3029                         deemph_reg_value = 128;
3030                         margin_reg_value = 52;
3031                         break;
3032                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3033                         deemph_reg_value = 128;
3034                         margin_reg_value = 77;
3035                         break;
3036                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3037                         deemph_reg_value = 128;
3038                         margin_reg_value = 102;
3039                         break;
3040                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3041                         deemph_reg_value = 128;
3042                         margin_reg_value = 154;
3043                         /* FIXME extra to set for 1200 */
3044                         break;
3045                 default:
3046                         return 0;
3047                 }
3048                 break;
3049         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3050                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3051                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3052                         deemph_reg_value = 85;
3053                         margin_reg_value = 78;
3054                         break;
3055                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3056                         deemph_reg_value = 85;
3057                         margin_reg_value = 116;
3058                         break;
3059                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3060                         deemph_reg_value = 85;
3061                         margin_reg_value = 154;
3062                         break;
3063                 default:
3064                         return 0;
3065                 }
3066                 break;
3067         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3068                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3069                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3070                         deemph_reg_value = 64;
3071                         margin_reg_value = 104;
3072                         break;
3073                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3074                         deemph_reg_value = 64;
3075                         margin_reg_value = 154;
3076                         break;
3077                 default:
3078                         return 0;
3079                 }
3080                 break;
3081         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3082                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3083                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3084                         deemph_reg_value = 43;
3085                         margin_reg_value = 154;
3086                         break;
3087                 default:
3088                         return 0;
3089                 }
3090                 break;
3091         default:
3092                 return 0;
3093         }
3094
3095         mutex_lock(&dev_priv->dpio_lock);
3096
3097         /* Clear calc init */
3098         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3099         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3100         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3101         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3102         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3103
3104         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3105         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3106         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3107         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3108         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3109
3110         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3111         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3112         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3113         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3114
3115         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3116         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3117         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3118         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3119
3120         /* Program swing deemph */
3121         for (i = 0; i < 4; i++) {
3122                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3123                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3124                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3125                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3126         }
3127
3128         /* Program swing margin */
3129         for (i = 0; i < 4; i++) {
3130                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3131                 val &= ~DPIO_SWING_MARGIN000_MASK;
3132                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3133                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3134         }
3135
3136         /* Disable unique transition scale */
3137         for (i = 0; i < 4; i++) {
3138                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3139                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3140                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3141         }
3142
3143         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3144                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3145                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3146                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3147
3148                 /*
3149                  * The document said it needs to set bit 27 for ch0 and bit 26
3150                  * for ch1. Might be a typo in the doc.
3151                  * For now, for this unique transition scale selection, set bit
3152                  * 27 for ch0 and ch1.
3153                  */
3154                 for (i = 0; i < 4; i++) {
3155                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3156                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3157                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3158                 }
3159
3160                 for (i = 0; i < 4; i++) {
3161                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3162                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3163                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3164                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3165                 }
3166         }
3167
3168         /* Start swing calculation */
3169         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3170         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3171         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3172
3173         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3174         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3175         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3176
3177         /* LRC Bypass */
3178         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3179         val |= DPIO_LRC_BYPASS;
3180         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3181
3182         mutex_unlock(&dev_priv->dpio_lock);
3183
3184         return 0;
3185 }
3186
3187 static void
3188 intel_get_adjust_train(struct intel_dp *intel_dp,
3189                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3190 {
3191         uint8_t v = 0;
3192         uint8_t p = 0;
3193         int lane;
3194         uint8_t voltage_max;
3195         uint8_t preemph_max;
3196
3197         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3198                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3199                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3200
3201                 if (this_v > v)
3202                         v = this_v;
3203                 if (this_p > p)
3204                         p = this_p;
3205         }
3206
3207         voltage_max = intel_dp_voltage_max(intel_dp);
3208         if (v >= voltage_max)
3209                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3210
3211         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3212         if (p >= preemph_max)
3213                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3214
3215         for (lane = 0; lane < 4; lane++)
3216                 intel_dp->train_set[lane] = v | p;
3217 }
3218
3219 static uint32_t
3220 intel_gen4_signal_levels(uint8_t train_set)
3221 {
3222         uint32_t        signal_levels = 0;
3223
3224         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3225         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3226         default:
3227                 signal_levels |= DP_VOLTAGE_0_4;
3228                 break;
3229         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3230                 signal_levels |= DP_VOLTAGE_0_6;
3231                 break;
3232         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3233                 signal_levels |= DP_VOLTAGE_0_8;
3234                 break;
3235         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3236                 signal_levels |= DP_VOLTAGE_1_2;
3237                 break;
3238         }
3239         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3240         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3241         default:
3242                 signal_levels |= DP_PRE_EMPHASIS_0;
3243                 break;
3244         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3245                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3246                 break;
3247         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3248                 signal_levels |= DP_PRE_EMPHASIS_6;
3249                 break;
3250         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3251                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3252                 break;
3253         }
3254         return signal_levels;
3255 }
3256
3257 /* Gen6's DP voltage swing and pre-emphasis control */
3258 static uint32_t
3259 intel_gen6_edp_signal_levels(uint8_t train_set)
3260 {
3261         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3262                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3263         switch (signal_levels) {
3264         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3265         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3266                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3267         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3268                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3269         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3270         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3271                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3272         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3273         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3274                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3275         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3276         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3277                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3278         default:
3279                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3280                               "0x%x\n", signal_levels);
3281                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3282         }
3283 }
3284
3285 /* Gen7's DP voltage swing and pre-emphasis control */
3286 static uint32_t
3287 intel_gen7_edp_signal_levels(uint8_t train_set)
3288 {
3289         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3290                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3291         switch (signal_levels) {
3292         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3293                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3294         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3295                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3296         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3297                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3298
3299         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3300                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3301         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3302                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3303
3304         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3305                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3306         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3307                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3308
3309         default:
3310                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3311                               "0x%x\n", signal_levels);
3312                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3313         }
3314 }
3315
3316 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3317 static uint32_t
3318 intel_hsw_signal_levels(uint8_t train_set)
3319 {
3320         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3321                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3322         switch (signal_levels) {
3323         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3324                 return DDI_BUF_TRANS_SELECT(0);
3325         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3326                 return DDI_BUF_TRANS_SELECT(1);
3327         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3328                 return DDI_BUF_TRANS_SELECT(2);
3329         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3330                 return DDI_BUF_TRANS_SELECT(3);
3331
3332         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3333                 return DDI_BUF_TRANS_SELECT(4);
3334         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3335                 return DDI_BUF_TRANS_SELECT(5);
3336         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3337                 return DDI_BUF_TRANS_SELECT(6);
3338
3339         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3340                 return DDI_BUF_TRANS_SELECT(7);
3341         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3342                 return DDI_BUF_TRANS_SELECT(8);
3343         default:
3344                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3345                               "0x%x\n", signal_levels);
3346                 return DDI_BUF_TRANS_SELECT(0);
3347         }
3348 }
3349
3350 /* Properly updates "DP" with the correct signal levels. */
3351 static void
3352 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3353 {
3354         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3355         enum port port = intel_dig_port->port;
3356         struct drm_device *dev = intel_dig_port->base.base.dev;
3357         uint32_t signal_levels, mask;
3358         uint8_t train_set = intel_dp->train_set[0];
3359
3360         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3361                 signal_levels = intel_hsw_signal_levels(train_set);
3362                 mask = DDI_BUF_EMP_MASK;
3363         } else if (IS_CHERRYVIEW(dev)) {
3364                 signal_levels = intel_chv_signal_levels(intel_dp);
3365                 mask = 0;
3366         } else if (IS_VALLEYVIEW(dev)) {
3367                 signal_levels = intel_vlv_signal_levels(intel_dp);
3368                 mask = 0;
3369         } else if (IS_GEN7(dev) && port == PORT_A) {
3370                 signal_levels = intel_gen7_edp_signal_levels(train_set);
3371                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3372         } else if (IS_GEN6(dev) && port == PORT_A) {
3373                 signal_levels = intel_gen6_edp_signal_levels(train_set);
3374                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3375         } else {
3376                 signal_levels = intel_gen4_signal_levels(train_set);
3377                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3378         }
3379
3380         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3381
3382         *DP = (*DP & ~mask) | signal_levels;
3383 }
3384
3385 static bool
3386 intel_dp_set_link_train(struct intel_dp *intel_dp,
3387                         uint32_t *DP,
3388                         uint8_t dp_train_pat)
3389 {
3390         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3391         struct drm_device *dev = intel_dig_port->base.base.dev;
3392         struct drm_i915_private *dev_priv = dev->dev_private;
3393         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3394         int ret, len;
3395
3396         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3397
3398         I915_WRITE(intel_dp->output_reg, *DP);
3399         POSTING_READ(intel_dp->output_reg);
3400
3401         buf[0] = dp_train_pat;
3402         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3403             DP_TRAINING_PATTERN_DISABLE) {
3404                 /* don't write DP_TRAINING_LANEx_SET on disable */
3405                 len = 1;
3406         } else {
3407                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3408                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3409                 len = intel_dp->lane_count + 1;
3410         }
3411
3412         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3413                                 buf, len);
3414
3415         return ret == len;
3416 }
3417
3418 static bool
3419 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3420                         uint8_t dp_train_pat)
3421 {
3422         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3423         intel_dp_set_signal_levels(intel_dp, DP);
3424         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3425 }
3426
3427 static bool
3428 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3429                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3430 {
3431         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3432         struct drm_device *dev = intel_dig_port->base.base.dev;
3433         struct drm_i915_private *dev_priv = dev->dev_private;
3434         int ret;
3435
3436         intel_get_adjust_train(intel_dp, link_status);
3437         intel_dp_set_signal_levels(intel_dp, DP);
3438
3439         I915_WRITE(intel_dp->output_reg, *DP);
3440         POSTING_READ(intel_dp->output_reg);
3441
3442         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3443                                 intel_dp->train_set, intel_dp->lane_count);
3444
3445         return ret == intel_dp->lane_count;
3446 }
3447
3448 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3449 {
3450         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3451         struct drm_device *dev = intel_dig_port->base.base.dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         enum port port = intel_dig_port->port;
3454         uint32_t val;
3455
3456         if (!HAS_DDI(dev))
3457                 return;
3458
3459         val = I915_READ(DP_TP_CTL(port));
3460         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3461         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3462         I915_WRITE(DP_TP_CTL(port), val);
3463
3464         /*
3465          * On PORT_A we can have only eDP in SST mode. There the only reason
3466          * we need to set idle transmission mode is to work around a HW issue
3467          * where we enable the pipe while not in idle link-training mode.
3468          * In this case there is requirement to wait for a minimum number of
3469          * idle patterns to be sent.
3470          */
3471         if (port == PORT_A)
3472                 return;
3473
3474         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3475                      1))
3476                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3477 }
3478
3479 /* Enable corresponding port and start training pattern 1 */
3480 void
3481 intel_dp_start_link_train(struct intel_dp *intel_dp)
3482 {
3483         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3484         struct drm_device *dev = encoder->dev;
3485         int i;
3486         uint8_t voltage;
3487         int voltage_tries, loop_tries;
3488         uint32_t DP = intel_dp->DP;
3489         uint8_t link_config[2];
3490
3491         if (HAS_DDI(dev))
3492                 intel_ddi_prepare_link_retrain(encoder);
3493
3494         /* Write the link configuration data */
3495         link_config[0] = intel_dp->link_bw;
3496         link_config[1] = intel_dp->lane_count;
3497         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3498                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3499         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3500
3501         link_config[0] = 0;
3502         link_config[1] = DP_SET_ANSI_8B10B;
3503         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3504
3505         DP |= DP_PORT_EN;
3506
3507         /* clock recovery */
3508         if (!intel_dp_reset_link_train(intel_dp, &DP,
3509                                        DP_TRAINING_PATTERN_1 |
3510                                        DP_LINK_SCRAMBLING_DISABLE)) {
3511                 DRM_ERROR("failed to enable link training\n");
3512                 return;
3513         }
3514
3515         voltage = 0xff;
3516         voltage_tries = 0;
3517         loop_tries = 0;
3518         for (;;) {
3519                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3520
3521                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3522                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3523                         DRM_ERROR("failed to get link status\n");
3524                         break;
3525                 }
3526
3527                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3528                         DRM_DEBUG_KMS("clock recovery OK\n");
3529                         break;
3530                 }
3531
3532                 /* Check to see if we've tried the max voltage */
3533                 for (i = 0; i < intel_dp->lane_count; i++)
3534                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3535                                 break;
3536                 if (i == intel_dp->lane_count) {
3537                         ++loop_tries;
3538                         if (loop_tries == 5) {
3539                                 DRM_ERROR("too many full retries, give up\n");
3540                                 break;
3541                         }
3542                         intel_dp_reset_link_train(intel_dp, &DP,
3543                                                   DP_TRAINING_PATTERN_1 |
3544                                                   DP_LINK_SCRAMBLING_DISABLE);
3545                         voltage_tries = 0;
3546                         continue;
3547                 }
3548
3549                 /* Check to see if we've tried the same voltage 5 times */
3550                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3551                         ++voltage_tries;
3552                         if (voltage_tries == 5) {
3553                                 DRM_ERROR("too many voltage retries, give up\n");
3554                                 break;
3555                         }
3556                 } else
3557                         voltage_tries = 0;
3558                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3559
3560                 /* Update training set as requested by target */
3561                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3562                         DRM_ERROR("failed to update link training\n");
3563                         break;
3564                 }
3565         }
3566
3567         intel_dp->DP = DP;
3568 }
3569
3570 void
3571 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3572 {
3573         bool channel_eq = false;
3574         int tries, cr_tries;
3575         uint32_t DP = intel_dp->DP;
3576         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3577
3578         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3579         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3580                 training_pattern = DP_TRAINING_PATTERN_3;
3581
3582         /* channel equalization */
3583         if (!intel_dp_set_link_train(intel_dp, &DP,
3584                                      training_pattern |
3585                                      DP_LINK_SCRAMBLING_DISABLE)) {
3586                 DRM_ERROR("failed to start channel equalization\n");
3587                 return;
3588         }
3589
3590         tries = 0;
3591         cr_tries = 0;
3592         channel_eq = false;
3593         for (;;) {
3594                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3595
3596                 if (cr_tries > 5) {
3597                         DRM_ERROR("failed to train DP, aborting\n");
3598                         break;
3599                 }
3600
3601                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3602                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3603                         DRM_ERROR("failed to get link status\n");
3604                         break;
3605                 }
3606
3607                 /* Make sure clock is still ok */
3608                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3609                         intel_dp_start_link_train(intel_dp);
3610                         intel_dp_set_link_train(intel_dp, &DP,
3611                                                 training_pattern |
3612                                                 DP_LINK_SCRAMBLING_DISABLE);
3613                         cr_tries++;
3614                         continue;
3615                 }
3616
3617                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3618                         channel_eq = true;
3619                         break;
3620                 }
3621
3622                 /* Try 5 times, then try clock recovery if that fails */
3623                 if (tries > 5) {
3624                         intel_dp_start_link_train(intel_dp);
3625                         intel_dp_set_link_train(intel_dp, &DP,
3626                                                 training_pattern |
3627                                                 DP_LINK_SCRAMBLING_DISABLE);
3628                         tries = 0;
3629                         cr_tries++;
3630                         continue;
3631                 }
3632
3633                 /* Update training set as requested by target */
3634                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3635                         DRM_ERROR("failed to update link training\n");
3636                         break;
3637                 }
3638                 ++tries;
3639         }
3640
3641         intel_dp_set_idle_link_train(intel_dp);
3642
3643         intel_dp->DP = DP;
3644
3645         if (channel_eq)
3646                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3647
3648 }
3649
3650 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3651 {
3652         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3653                                 DP_TRAINING_PATTERN_DISABLE);
3654 }
3655
3656 static void
3657 intel_dp_link_down(struct intel_dp *intel_dp)
3658 {
3659         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3660         enum port port = intel_dig_port->port;
3661         struct drm_device *dev = intel_dig_port->base.base.dev;
3662         struct drm_i915_private *dev_priv = dev->dev_private;
3663         uint32_t DP = intel_dp->DP;
3664
3665         if (WARN_ON(HAS_DDI(dev)))
3666                 return;
3667
3668         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3669                 return;
3670
3671         DRM_DEBUG_KMS("\n");
3672
3673         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3674                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3675                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3676         } else {
3677                 if (IS_CHERRYVIEW(dev))
3678                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3679                 else
3680                         DP &= ~DP_LINK_TRAIN_MASK;
3681                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3682         }
3683         POSTING_READ(intel_dp->output_reg);
3684
3685         if (HAS_PCH_IBX(dev) &&
3686             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3687                 /* Hardware workaround: leaving our transcoder select
3688                  * set to transcoder B while it's off will prevent the
3689                  * corresponding HDMI output on transcoder A.
3690                  *
3691                  * Combine this with another hardware workaround:
3692                  * transcoder select bit can only be cleared while the
3693                  * port is enabled.
3694                  */
3695                 DP &= ~DP_PIPEB_SELECT;
3696                 I915_WRITE(intel_dp->output_reg, DP);
3697                 POSTING_READ(intel_dp->output_reg);
3698         }
3699
3700         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3701         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3702         POSTING_READ(intel_dp->output_reg);
3703         msleep(intel_dp->panel_power_down_delay);
3704 }
3705
3706 static bool
3707 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3708 {
3709         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3710         struct drm_device *dev = dig_port->base.base.dev;
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712
3713         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3714                                     sizeof(intel_dp->dpcd)) < 0)
3715                 return false; /* aux transfer failed */
3716
3717         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3718
3719         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3720                 return false; /* DPCD not present */
3721
3722         /* Check if the panel supports PSR */
3723         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3724         if (is_edp(intel_dp)) {
3725                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3726                                         intel_dp->psr_dpcd,
3727                                         sizeof(intel_dp->psr_dpcd));
3728                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3729                         dev_priv->psr.sink_support = true;
3730                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3731                 }
3732         }
3733
3734         /* Training Pattern 3 support, both source and sink */
3735         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3736             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3737             (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3738                 intel_dp->use_tps3 = true;
3739                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3740         } else
3741                 intel_dp->use_tps3 = false;
3742
3743         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3744               DP_DWN_STRM_PORT_PRESENT))
3745                 return true; /* native DP sink */
3746
3747         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3748                 return true; /* no per-port downstream info */
3749
3750         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3751                                     intel_dp->downstream_ports,
3752                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3753                 return false; /* downstream port status fetch failed */
3754
3755         return true;
3756 }
3757
3758 static void
3759 intel_dp_probe_oui(struct intel_dp *intel_dp)
3760 {
3761         u8 buf[3];
3762
3763         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3764                 return;
3765
3766         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3767                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3768                               buf[0], buf[1], buf[2]);
3769
3770         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3771                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3772                               buf[0], buf[1], buf[2]);
3773 }
3774
3775 #if 0
3776 static bool
3777 intel_dp_probe_mst(struct intel_dp *intel_dp)
3778 {
3779         u8 buf[1];
3780
3781         if (!intel_dp->can_mst)
3782                 return false;
3783
3784         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3785                 return false;
3786
3787         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3788                 if (buf[0] & DP_MST_CAP) {
3789                         DRM_DEBUG_KMS("Sink is MST capable\n");
3790                         intel_dp->is_mst = true;
3791                 } else {
3792                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3793                         intel_dp->is_mst = false;
3794                 }
3795         }
3796
3797         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3798         return intel_dp->is_mst;
3799 }
3800 #endif
3801
3802 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3803 {
3804         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3805         struct drm_device *dev = intel_dig_port->base.base.dev;
3806         struct intel_crtc *intel_crtc =
3807                 to_intel_crtc(intel_dig_port->base.base.crtc);
3808         u8 buf;
3809         int test_crc_count;
3810         int attempts = 6;
3811
3812         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3813                 return -EIO;
3814
3815         if (!(buf & DP_TEST_CRC_SUPPORTED))
3816                 return -ENOTTY;
3817
3818         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3819                 return -EIO;
3820
3821         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3822                                 buf | DP_TEST_SINK_START) < 0)
3823                 return -EIO;
3824
3825         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3826                 return -EIO;
3827         test_crc_count = buf & DP_TEST_COUNT_MASK;
3828
3829         do {
3830                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3831                                       DP_TEST_SINK_MISC, &buf) < 0)
3832                         return -EIO;
3833                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3834         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3835
3836         if (attempts == 0) {
3837                 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3838                 return -ETIMEDOUT;
3839         }
3840
3841         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3842                 return -EIO;
3843
3844         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3845                 return -EIO;
3846         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3847                                buf & ~DP_TEST_SINK_START) < 0)
3848                 return -EIO;
3849
3850         return 0;
3851 }
3852
3853 static bool
3854 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3855 {
3856         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3857                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3858                                        sink_irq_vector, 1) == 1;
3859 }
3860
3861 static void
3862 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3863 {
3864         /* NAK by default */
3865         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3866 }
3867
3868 #if 0
3869 static int
3870 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3871 {
3872         bool bret;
3873
3874         if (intel_dp->is_mst) {
3875                 u8 esi[16] = { 0 };
3876                 int ret = 0;
3877                 int retry;
3878                 bool handled;
3879                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3880 go_again:
3881                 if (bret == true) {
3882
3883                         /* check link status - esi[10] = 0x200c */
3884                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3885                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3886                                 intel_dp_start_link_train(intel_dp);
3887                                 intel_dp_complete_link_train(intel_dp);
3888                                 intel_dp_stop_link_train(intel_dp);
3889                         }
3890
3891                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3892                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3893
3894                         if (handled) {
3895                                 for (retry = 0; retry < 3; retry++) {
3896                                         int wret;
3897                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3898                                                                  DP_SINK_COUNT_ESI+1,
3899                                                                  &esi[1], 3);
3900                                         if (wret == 3) {
3901                                                 break;
3902                                         }
3903                                 }
3904
3905                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3906                                 if (bret == true) {
3907                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3908                                         goto go_again;
3909                                 }
3910                         } else
3911                                 ret = 0;
3912
3913                         return ret;
3914                 } else {
3915                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3916                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3917                         intel_dp->is_mst = false;
3918                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3919                         /* send a hotplug event */
3920                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3921                 }
3922         }
3923         return -EINVAL;
3924 }
3925 #endif
3926
3927 /*
3928  * According to DP spec
3929  * 5.1.2:
3930  *  1. Read DPCD
3931  *  2. Configure link according to Receiver Capabilities
3932  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3933  *  4. Check link status on receipt of hot-plug interrupt
3934  */
3935 void
3936 intel_dp_check_link_status(struct intel_dp *intel_dp)
3937 {
3938         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3939         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3940         u8 sink_irq_vector;
3941         u8 link_status[DP_LINK_STATUS_SIZE];
3942
3943         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3944
3945         if (!intel_encoder->connectors_active)
3946                 return;
3947
3948         if (WARN_ON(!intel_encoder->base.crtc))
3949                 return;
3950
3951         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3952                 return;
3953
3954         /* Try to read receiver status if the link appears to be up */
3955         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3956                 return;
3957         }
3958
3959         /* Now read the DPCD to see if it's actually running */
3960         if (!intel_dp_get_dpcd(intel_dp)) {
3961                 return;
3962         }
3963
3964         /* Try to read the source of the interrupt */
3965         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3966             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3967                 /* Clear interrupt source */
3968                 drm_dp_dpcd_writeb(&intel_dp->aux,
3969                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3970                                    sink_irq_vector);
3971
3972                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3973                         intel_dp_handle_test_request(intel_dp);
3974                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3975                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3976         }
3977
3978         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3979                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3980                               intel_encoder->base.name);
3981                 intel_dp_start_link_train(intel_dp);
3982                 intel_dp_complete_link_train(intel_dp);
3983                 intel_dp_stop_link_train(intel_dp);
3984         }
3985 }
3986
3987 /* XXX this is probably wrong for multiple downstream ports */
3988 static enum drm_connector_status
3989 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3990 {
3991         uint8_t *dpcd = intel_dp->dpcd;
3992         uint8_t type;
3993
3994         if (!intel_dp_get_dpcd(intel_dp))
3995                 return connector_status_disconnected;
3996
3997         /* if there's no downstream port, we're done */
3998         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3999                 return connector_status_connected;
4000
4001         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4002         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4003             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4004                 uint8_t reg;
4005
4006                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4007                                             &reg, 1) < 0)
4008                         return connector_status_unknown;
4009
4010                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4011                                               : connector_status_disconnected;
4012         }
4013
4014         /* If no HPD, poke DDC gently */
4015         if (drm_probe_ddc(intel_dp->aux.ddc))
4016                 return connector_status_connected;
4017
4018         /* Well we tried, say unknown for unreliable port types */
4019         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4020                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4021                 if (type == DP_DS_PORT_TYPE_VGA ||
4022                     type == DP_DS_PORT_TYPE_NON_EDID)
4023                         return connector_status_unknown;
4024         } else {
4025                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4026                         DP_DWN_STRM_PORT_TYPE_MASK;
4027                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4028                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4029                         return connector_status_unknown;
4030         }
4031
4032         /* Anything else is out of spec, warn and ignore */
4033         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4034         return connector_status_disconnected;
4035 }
4036
4037 static enum drm_connector_status
4038 edp_detect(struct intel_dp *intel_dp)
4039 {
4040         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4041         enum drm_connector_status status;
4042
4043         status = intel_panel_detect(dev);
4044         if (status == connector_status_unknown)
4045                 status = connector_status_connected;
4046
4047         return status;
4048 }
4049
4050 static enum drm_connector_status
4051 ironlake_dp_detect(struct intel_dp *intel_dp)
4052 {
4053         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4054         struct drm_i915_private *dev_priv = dev->dev_private;
4055         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4056
4057         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4058                 return connector_status_disconnected;
4059
4060         return intel_dp_detect_dpcd(intel_dp);
4061 }
4062
4063 static int g4x_digital_port_connected(struct drm_device *dev,
4064                                        struct intel_digital_port *intel_dig_port)
4065 {
4066         struct drm_i915_private *dev_priv = dev->dev_private;
4067         uint32_t bit;
4068
4069         if (IS_VALLEYVIEW(dev)) {
4070                 switch (intel_dig_port->port) {
4071                 case PORT_B:
4072                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4073                         break;
4074                 case PORT_C:
4075                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4076                         break;
4077                 case PORT_D:
4078                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4079                         break;
4080                 default:
4081                         return -EINVAL;
4082                 }
4083         } else {
4084                 switch (intel_dig_port->port) {
4085                 case PORT_B:
4086                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4087                         break;
4088                 case PORT_C:
4089                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4090                         break;
4091                 case PORT_D:
4092                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4093                         break;
4094                 default:
4095                         return -EINVAL;
4096                 }
4097         }
4098
4099         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4100                 return 0;
4101         return 1;
4102 }
4103
4104 static enum drm_connector_status
4105 g4x_dp_detect(struct intel_dp *intel_dp)
4106 {
4107         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4108         struct drm_i915_private *dev_priv = dev->dev_private;
4109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4110         uint32_t bit;
4111
4112         if (IS_VALLEYVIEW(dev)) {
4113                 switch (intel_dig_port->port) {
4114                 case PORT_B:
4115                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4116                         break;
4117                 case PORT_C:
4118                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4119                         break;
4120                 case PORT_D:
4121                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4122                         break;
4123                 default:
4124                         return connector_status_unknown;
4125                 }
4126         } else {
4127                 switch (intel_dig_port->port) {
4128                 case PORT_B:
4129                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4130                         break;
4131                 case PORT_C:
4132                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4133                         break;
4134                 case PORT_D:
4135                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4136                         break;
4137                 default:
4138                         return connector_status_unknown;
4139                 }
4140         }
4141
4142         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4143                 return connector_status_disconnected;
4144
4145         return intel_dp_detect_dpcd(intel_dp);
4146 }
4147
4148 static struct edid *
4149 intel_dp_get_edid(struct intel_dp *intel_dp)
4150 {
4151         struct intel_connector *intel_connector = intel_dp->attached_connector;
4152
4153         /* use cached edid if we have one */
4154         if (intel_connector->edid) {
4155                 /* invalid edid */
4156                 if (IS_ERR(intel_connector->edid))
4157                         return NULL;
4158
4159                 return drm_edid_duplicate(intel_connector->edid);
4160         } else
4161                 return drm_get_edid(&intel_connector->base,
4162                                     intel_dp->aux.ddc);
4163 }
4164
4165 static void
4166 intel_dp_set_edid(struct intel_dp *intel_dp)
4167 {
4168         struct intel_connector *intel_connector = intel_dp->attached_connector;
4169         struct edid *edid;
4170
4171         edid = intel_dp_get_edid(intel_dp);
4172         intel_connector->detect_edid = edid;
4173
4174         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4175                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4176         else
4177                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4178 }
4179
4180 static void
4181 intel_dp_unset_edid(struct intel_dp *intel_dp)
4182 {
4183         struct intel_connector *intel_connector = intel_dp->attached_connector;
4184
4185         kfree(intel_connector->detect_edid);
4186         intel_connector->detect_edid = NULL;
4187
4188         intel_dp->has_audio = false;
4189 }
4190
4191 static enum intel_display_power_domain
4192 intel_dp_power_get(struct intel_dp *dp)
4193 {
4194         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4195         enum intel_display_power_domain power_domain;
4196
4197         power_domain = intel_display_port_power_domain(encoder);
4198         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4199
4200         return power_domain;
4201 }
4202
4203 static void
4204 intel_dp_power_put(struct intel_dp *dp,
4205                    enum intel_display_power_domain power_domain)
4206 {
4207         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4208         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4209 }
4210
4211 static enum drm_connector_status
4212 intel_dp_detect(struct drm_connector *connector, bool force)
4213 {
4214         struct intel_dp *intel_dp = intel_attached_dp(connector);
4215         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4216         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4217         struct drm_device *dev = connector->dev;
4218         enum drm_connector_status status;
4219         enum intel_display_power_domain power_domain;
4220
4221         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4222                       connector->base.id, connector->name);
4223         intel_dp_unset_edid(intel_dp);
4224
4225         if (intel_dp->is_mst) {
4226                 /* MST devices are disconnected from a monitor POV */
4227                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4228                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4229                 return connector_status_disconnected;
4230         }
4231
4232         power_domain = intel_dp_power_get(intel_dp);
4233
4234         /* Can't disconnect eDP, but you can close the lid... */
4235         if (is_edp(intel_dp))
4236                 status = edp_detect(intel_dp);
4237         else if (HAS_PCH_SPLIT(dev))
4238                 status = ironlake_dp_detect(intel_dp);
4239         else
4240                 status = g4x_dp_detect(intel_dp);
4241         if (status != connector_status_connected)
4242                 goto out;
4243
4244         intel_dp_probe_oui(intel_dp);
4245
4246 #if 0
4247         ret = intel_dp_probe_mst(intel_dp);
4248         if (ret) {
4249                 /* if we are in MST mode then this connector
4250                    won't appear connected or have anything with EDID on it */
4251                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4252                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4253                 status = connector_status_disconnected;
4254                 goto out;
4255         }
4256 #endif
4257
4258         intel_dp_set_edid(intel_dp);
4259
4260         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4261                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4262         status = connector_status_connected;
4263
4264 out:
4265         intel_dp_power_put(intel_dp, power_domain);
4266         return status;
4267 }
4268
4269 static void
4270 intel_dp_force(struct drm_connector *connector)
4271 {
4272         struct intel_dp *intel_dp = intel_attached_dp(connector);
4273         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4274         enum intel_display_power_domain power_domain;
4275
4276         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4277                       connector->base.id, connector->name);
4278         intel_dp_unset_edid(intel_dp);
4279
4280         if (connector->status != connector_status_connected)
4281                 return;
4282
4283         power_domain = intel_dp_power_get(intel_dp);
4284
4285         intel_dp_set_edid(intel_dp);
4286
4287         intel_dp_power_put(intel_dp, power_domain);
4288
4289         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4290                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4291 }
4292
4293 static int intel_dp_get_modes(struct drm_connector *connector)
4294 {
4295         struct intel_connector *intel_connector = to_intel_connector(connector);
4296         struct edid *edid;
4297
4298         edid = intel_connector->detect_edid;
4299         if (edid) {
4300                 int ret = intel_connector_update_modes(connector, edid);
4301                 if (ret)
4302                         return ret;
4303         }
4304
4305         /* if eDP has no EDID, fall back to fixed mode */
4306         if (is_edp(intel_attached_dp(connector)) &&
4307             intel_connector->panel.fixed_mode) {
4308                 struct drm_display_mode *mode;
4309
4310                 mode = drm_mode_duplicate(connector->dev,
4311                                           intel_connector->panel.fixed_mode);
4312                 if (mode) {
4313                         drm_mode_probed_add(connector, mode);
4314                         return 1;
4315                 }
4316         }
4317
4318         return 0;
4319 }
4320
4321 static bool
4322 intel_dp_detect_audio(struct drm_connector *connector)
4323 {
4324         bool has_audio = false;
4325         struct edid *edid;
4326
4327         edid = to_intel_connector(connector)->detect_edid;
4328         if (edid)
4329                 has_audio = drm_detect_monitor_audio(edid);
4330
4331         return has_audio;
4332 }
4333
4334 static int
4335 intel_dp_set_property(struct drm_connector *connector,
4336                       struct drm_property *property,
4337                       uint64_t val)
4338 {
4339         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4340         struct intel_connector *intel_connector = to_intel_connector(connector);
4341         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4342         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4343         int ret;
4344
4345         ret = drm_object_property_set_value(&connector->base, property, val);
4346         if (ret)
4347                 return ret;
4348
4349         if (property == dev_priv->force_audio_property) {
4350                 int i = val;
4351                 bool has_audio;
4352
4353                 if (i == intel_dp->force_audio)
4354                         return 0;
4355
4356                 intel_dp->force_audio = i;
4357
4358                 if (i == HDMI_AUDIO_AUTO)
4359                         has_audio = intel_dp_detect_audio(connector);
4360                 else
4361                         has_audio = (i == HDMI_AUDIO_ON);
4362
4363                 if (has_audio == intel_dp->has_audio)
4364                         return 0;
4365
4366                 intel_dp->has_audio = has_audio;
4367                 goto done;
4368         }
4369
4370         if (property == dev_priv->broadcast_rgb_property) {
4371                 bool old_auto = intel_dp->color_range_auto;
4372                 uint32_t old_range = intel_dp->color_range;
4373
4374                 switch (val) {
4375                 case INTEL_BROADCAST_RGB_AUTO:
4376                         intel_dp->color_range_auto = true;
4377                         break;
4378                 case INTEL_BROADCAST_RGB_FULL:
4379                         intel_dp->color_range_auto = false;
4380                         intel_dp->color_range = 0;
4381                         break;
4382                 case INTEL_BROADCAST_RGB_LIMITED:
4383                         intel_dp->color_range_auto = false;
4384                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4385                         break;
4386                 default:
4387                         return -EINVAL;
4388                 }
4389
4390                 if (old_auto == intel_dp->color_range_auto &&
4391                     old_range == intel_dp->color_range)
4392                         return 0;
4393
4394                 goto done;
4395         }
4396
4397         if (is_edp(intel_dp) &&
4398             property == connector->dev->mode_config.scaling_mode_property) {
4399                 if (val == DRM_MODE_SCALE_NONE) {
4400                         DRM_DEBUG_KMS("no scaling not supported\n");
4401                         return -EINVAL;
4402                 }
4403
4404                 if (intel_connector->panel.fitting_mode == val) {
4405                         /* the eDP scaling property is not changed */
4406                         return 0;
4407                 }
4408                 intel_connector->panel.fitting_mode = val;
4409
4410                 goto done;
4411         }
4412
4413         return -EINVAL;
4414
4415 done:
4416         if (intel_encoder->base.crtc)
4417                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4418
4419         return 0;
4420 }
4421
4422 static void
4423 intel_dp_connector_destroy(struct drm_connector *connector)
4424 {
4425         struct intel_connector *intel_connector = to_intel_connector(connector);
4426
4427         kfree(intel_connector->detect_edid);
4428
4429         if (!IS_ERR_OR_NULL(intel_connector->edid))
4430                 kfree(intel_connector->edid);
4431
4432         /* Can't call is_edp() since the encoder may have been destroyed
4433          * already. */
4434         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4435                 intel_panel_fini(&intel_connector->panel);
4436
4437         drm_connector_cleanup(connector);
4438         kfree(connector);
4439 }
4440
4441 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4442 {
4443         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4444         struct intel_dp *intel_dp = &intel_dig_port->dp;
4445
4446         drm_dp_aux_unregister(&intel_dp->aux);
4447         intel_dp_mst_encoder_cleanup(intel_dig_port);
4448         if (is_edp(intel_dp)) {
4449                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4450                 /*
4451                  * vdd might still be enabled do to the delayed vdd off.
4452                  * Make sure vdd is actually turned off here.
4453                  */
4454                 pps_lock(intel_dp);
4455                 edp_panel_vdd_off_sync(intel_dp);
4456                 pps_unlock(intel_dp);
4457
4458 #if 0
4459                 if (intel_dp->edp_notifier.notifier_call) {
4460                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4461                         intel_dp->edp_notifier.notifier_call = NULL;
4462                 }
4463 #endif
4464         }
4465         drm_encoder_cleanup(encoder);
4466         kfree(intel_dig_port);
4467 }
4468
4469 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4470 {
4471         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4472
4473         if (!is_edp(intel_dp))
4474                 return;
4475
4476         /*
4477          * vdd might still be enabled do to the delayed vdd off.
4478          * Make sure vdd is actually turned off here.
4479          */
4480         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4481         pps_lock(intel_dp);
4482         edp_panel_vdd_off_sync(intel_dp);
4483         pps_unlock(intel_dp);
4484 }
4485
4486 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4487 {
4488         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4489         struct drm_device *dev = intel_dig_port->base.base.dev;
4490         struct drm_i915_private *dev_priv = dev->dev_private;
4491         enum intel_display_power_domain power_domain;
4492
4493         lockdep_assert_held(&dev_priv->pps_mutex);
4494
4495         if (!edp_have_panel_vdd(intel_dp))
4496                 return;
4497
4498         /*
4499          * The VDD bit needs a power domain reference, so if the bit is
4500          * already enabled when we boot or resume, grab this reference and
4501          * schedule a vdd off, so we don't hold on to the reference
4502          * indefinitely.
4503          */
4504         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4505         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4506         intel_display_power_get(dev_priv, power_domain);
4507
4508         edp_panel_vdd_schedule_off(intel_dp);
4509 }
4510
4511 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4512 {
4513         struct intel_dp *intel_dp;
4514
4515         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4516                 return;
4517
4518         intel_dp = enc_to_intel_dp(encoder);
4519
4520         pps_lock(intel_dp);
4521
4522         /*
4523          * Read out the current power sequencer assignment,
4524          * in case the BIOS did something with it.
4525          */
4526         if (IS_VALLEYVIEW(encoder->dev))
4527                 vlv_initial_power_sequencer_setup(intel_dp);
4528
4529         intel_edp_panel_vdd_sanitize(intel_dp);
4530
4531         pps_unlock(intel_dp);
4532 }
4533
4534 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4535         .dpms = intel_connector_dpms,
4536         .detect = intel_dp_detect,
4537         .force = intel_dp_force,
4538         .fill_modes = drm_helper_probe_single_connector_modes,
4539         .set_property = intel_dp_set_property,
4540         .atomic_get_property = intel_connector_atomic_get_property,
4541         .destroy = intel_dp_connector_destroy,
4542         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4543 };
4544
4545 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4546         .get_modes = intel_dp_get_modes,
4547         .mode_valid = intel_dp_mode_valid,
4548         .best_encoder = intel_best_encoder,
4549 };
4550
4551 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4552         .reset = intel_dp_encoder_reset,
4553         .destroy = intel_dp_encoder_destroy,
4554 };
4555
4556 void
4557 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4558 {
4559         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4560
4561         intel_dp_check_link_status(intel_dp);
4562 }
4563
4564 bool
4565 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4566 {
4567         struct intel_dp *intel_dp = &intel_dig_port->dp;
4568         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4569         struct drm_device *dev = intel_dig_port->base.base.dev;
4570         struct drm_i915_private *dev_priv = dev->dev_private;
4571         enum intel_display_power_domain power_domain;
4572         bool ret = true;
4573
4574         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4575                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4576
4577         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4578                 /*
4579                  * vdd off can generate a long pulse on eDP which
4580                  * would require vdd on to handle it, and thus we
4581                  * would end up in an endless cycle of
4582                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4583                  */
4584                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4585                               port_name(intel_dig_port->port));
4586                 return false;
4587         }
4588
4589         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4590                       port_name(intel_dig_port->port),
4591                       long_hpd ? "long" : "short");
4592
4593         power_domain = intel_display_port_power_domain(intel_encoder);
4594         intel_display_power_get(dev_priv, power_domain);
4595
4596         if (long_hpd) {
4597                 ret = true;
4598                 goto put_power;
4599
4600                 if (HAS_PCH_SPLIT(dev)) {
4601                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4602                                 goto mst_fail;
4603                 } else {
4604                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4605                                 goto mst_fail;
4606                 }
4607
4608                 if (!intel_dp_get_dpcd(intel_dp)) {
4609                         goto mst_fail;
4610                 }
4611         }
4612
4613         /*
4614          * we'll check the link status via the normal hot plug path later -
4615          * but for short hpds we should check it now
4616          */
4617         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4618         intel_dp_check_link_status(intel_dp);
4619         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4620         ret = false;
4621
4622         goto put_power;
4623 mst_fail:
4624         /* if we were in MST mode, and device is not there get out of MST mode */
4625         if (intel_dp->is_mst) {
4626                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4627                 intel_dp->is_mst = false;
4628                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4629         }
4630 put_power:
4631         intel_display_power_put(dev_priv, power_domain);
4632
4633         return ret;
4634 }
4635
4636 /* Return which DP Port should be selected for Transcoder DP control */
4637 int
4638 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4639 {
4640         struct drm_device *dev = crtc->dev;
4641         struct intel_encoder *intel_encoder;
4642         struct intel_dp *intel_dp;
4643
4644         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4645                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4646
4647                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4648                     intel_encoder->type == INTEL_OUTPUT_EDP)
4649                         return intel_dp->output_reg;
4650         }
4651
4652         return -1;
4653 }
4654
4655 /* check the VBT to see whether the eDP is on DP-D port */
4656 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4657 {
4658         struct drm_i915_private *dev_priv = dev->dev_private;
4659         union child_device_config *p_child;
4660         int i;
4661         static const short port_mapping[] = {
4662                 [PORT_B] = PORT_IDPB,
4663                 [PORT_C] = PORT_IDPC,
4664                 [PORT_D] = PORT_IDPD,
4665         };
4666
4667         if (port == PORT_A)
4668                 return true;
4669
4670         if (!dev_priv->vbt.child_dev_num)
4671                 return false;
4672
4673         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4674                 p_child = dev_priv->vbt.child_dev + i;
4675
4676                 if (p_child->common.dvo_port == port_mapping[port] &&
4677                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4678                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4679                         return true;
4680         }
4681         return false;
4682 }
4683
4684 void
4685 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4686 {
4687         struct intel_connector *intel_connector = to_intel_connector(connector);
4688
4689         intel_attach_force_audio_property(connector);
4690         intel_attach_broadcast_rgb_property(connector);
4691         intel_dp->color_range_auto = true;
4692
4693         if (is_edp(intel_dp)) {
4694                 drm_mode_create_scaling_mode_property(connector->dev);
4695                 drm_object_attach_property(
4696                         &connector->base,
4697                         connector->dev->mode_config.scaling_mode_property,
4698                         DRM_MODE_SCALE_ASPECT);
4699                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4700         }
4701 }
4702
4703 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4704 {
4705         intel_dp->last_power_cycle = jiffies;
4706         intel_dp->last_power_on = jiffies;
4707         intel_dp->last_backlight_off = jiffies;
4708 }
4709
4710 static void
4711 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4712                                     struct intel_dp *intel_dp)
4713 {
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         struct edp_power_seq cur, vbt, spec,
4716                 *final = &intel_dp->pps_delays;
4717         u32 pp_on, pp_off, pp_div, pp;
4718         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4719
4720         lockdep_assert_held(&dev_priv->pps_mutex);
4721
4722         /* already initialized? */
4723         if (final->t11_t12 != 0)
4724                 return;
4725
4726         if (HAS_PCH_SPLIT(dev)) {
4727                 pp_ctrl_reg = PCH_PP_CONTROL;
4728                 pp_on_reg = PCH_PP_ON_DELAYS;
4729                 pp_off_reg = PCH_PP_OFF_DELAYS;
4730                 pp_div_reg = PCH_PP_DIVISOR;
4731         } else {
4732                 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4733
4734                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4735                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4736                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4737                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4738         }
4739
4740         /* Workaround: Need to write PP_CONTROL with the unlock key as
4741          * the very first thing. */
4742         pp = ironlake_get_pp_control(intel_dp);
4743         I915_WRITE(pp_ctrl_reg, pp);
4744
4745         pp_on = I915_READ(pp_on_reg);
4746         pp_off = I915_READ(pp_off_reg);
4747         pp_div = I915_READ(pp_div_reg);
4748
4749         /* Pull timing values out of registers */
4750         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4751                 PANEL_POWER_UP_DELAY_SHIFT;
4752
4753         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4754                 PANEL_LIGHT_ON_DELAY_SHIFT;
4755
4756         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4757                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4758
4759         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4760                 PANEL_POWER_DOWN_DELAY_SHIFT;
4761
4762         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4763                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4764
4765         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4766                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4767
4768         vbt = dev_priv->vbt.edp_pps;
4769
4770         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4771          * our hw here, which are all in 100usec. */
4772         spec.t1_t3 = 210 * 10;
4773         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4774         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4775         spec.t10 = 500 * 10;
4776         /* This one is special and actually in units of 100ms, but zero
4777          * based in the hw (so we need to add 100 ms). But the sw vbt
4778          * table multiplies it with 1000 to make it in units of 100usec,
4779          * too. */
4780         spec.t11_t12 = (510 + 100) * 10;
4781
4782         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4783                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4784
4785         /* Use the max of the register settings and vbt. If both are
4786          * unset, fall back to the spec limits. */
4787 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4788                                        spec.field : \
4789                                        max(cur.field, vbt.field))
4790         assign_final(t1_t3);
4791         assign_final(t8);
4792         assign_final(t9);
4793         assign_final(t10);
4794         assign_final(t11_t12);
4795 #undef assign_final
4796
4797 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4798         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4799         intel_dp->backlight_on_delay = get_delay(t8);
4800         intel_dp->backlight_off_delay = get_delay(t9);
4801         intel_dp->panel_power_down_delay = get_delay(t10);
4802         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4803 #undef get_delay
4804
4805         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4806                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4807                       intel_dp->panel_power_cycle_delay);
4808
4809         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4810                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4811 }
4812
4813 static void
4814 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4815                                               struct intel_dp *intel_dp)
4816 {
4817         struct drm_i915_private *dev_priv = dev->dev_private;
4818         u32 pp_on, pp_off, pp_div, port_sel = 0;
4819         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4820         int pp_on_reg, pp_off_reg, pp_div_reg;
4821         enum port port = dp_to_dig_port(intel_dp)->port;
4822         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4823
4824         lockdep_assert_held(&dev_priv->pps_mutex);
4825
4826         if (HAS_PCH_SPLIT(dev)) {
4827                 pp_on_reg = PCH_PP_ON_DELAYS;
4828                 pp_off_reg = PCH_PP_OFF_DELAYS;
4829                 pp_div_reg = PCH_PP_DIVISOR;
4830         } else {
4831                 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4832
4833                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4834                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4835                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4836         }
4837
4838         /*
4839          * And finally store the new values in the power sequencer. The
4840          * backlight delays are set to 1 because we do manual waits on them. For
4841          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4842          * we'll end up waiting for the backlight off delay twice: once when we
4843          * do the manual sleep, and once when we disable the panel and wait for
4844          * the PP_STATUS bit to become zero.
4845          */
4846         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4847                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4848         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4849                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4850         /* Compute the divisor for the pp clock, simply match the Bspec
4851          * formula. */
4852         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4853         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4854                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4855
4856         /* Haswell doesn't have any port selection bits for the panel
4857          * power sequencer any more. */
4858         if (IS_VALLEYVIEW(dev)) {
4859                 port_sel = PANEL_PORT_SELECT_VLV(port);
4860         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4861                 if (port == PORT_A)
4862                         port_sel = PANEL_PORT_SELECT_DPA;
4863                 else
4864                         port_sel = PANEL_PORT_SELECT_DPD;
4865         }
4866
4867         pp_on |= port_sel;
4868
4869         I915_WRITE(pp_on_reg, pp_on);
4870         I915_WRITE(pp_off_reg, pp_off);
4871         I915_WRITE(pp_div_reg, pp_div);
4872
4873         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4874                       I915_READ(pp_on_reg),
4875                       I915_READ(pp_off_reg),
4876                       I915_READ(pp_div_reg));
4877 }
4878
4879 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4880 {
4881         struct drm_i915_private *dev_priv = dev->dev_private;
4882         struct intel_encoder *encoder;
4883         struct intel_digital_port *dig_port = NULL;
4884         struct intel_dp *intel_dp = dev_priv->drrs.dp;
4885         struct intel_crtc_state *config = NULL;
4886         struct intel_crtc *intel_crtc = NULL;
4887         u32 reg, val;
4888         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4889
4890         if (refresh_rate <= 0) {
4891                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4892                 return;
4893         }
4894
4895         if (intel_dp == NULL) {
4896                 DRM_DEBUG_KMS("DRRS not supported.\n");
4897                 return;
4898         }
4899
4900         /*
4901          * FIXME: This needs proper synchronization with psr state for some
4902          * platforms that cannot have PSR and DRRS enabled at the same time.
4903          */
4904
4905         dig_port = dp_to_dig_port(intel_dp);
4906         encoder = &dig_port->base;
4907         intel_crtc = encoder->new_crtc;
4908
4909         if (!intel_crtc) {
4910                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4911                 return;
4912         }
4913
4914         config = intel_crtc->config;
4915
4916         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4917                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4918                 return;
4919         }
4920
4921         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4922                         refresh_rate)
4923                 index = DRRS_LOW_RR;
4924
4925         if (index == dev_priv->drrs.refresh_rate_type) {
4926                 DRM_DEBUG_KMS(
4927                         "DRRS requested for previously set RR...ignoring\n");
4928                 return;
4929         }
4930
4931         if (!intel_crtc->active) {
4932                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4933                 return;
4934         }
4935
4936         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4937                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
4938                 val = I915_READ(reg);
4939                 if (index > DRRS_HIGH_RR) {
4940                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4941                         intel_dp_set_m_n(intel_crtc);
4942                 } else {
4943                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4944                 }
4945                 I915_WRITE(reg, val);
4946         }
4947
4948         dev_priv->drrs.refresh_rate_type = index;
4949
4950         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4951 }
4952
4953 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
4954 {
4955         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4956         struct drm_i915_private *dev_priv = dev->dev_private;
4957         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4958         struct drm_crtc *crtc = dig_port->base.base.crtc;
4959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4960
4961         if (!intel_crtc->config->has_drrs) {
4962                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4963                 return;
4964         }
4965
4966         mutex_lock(&dev_priv->drrs.mutex);
4967         if (WARN_ON(dev_priv->drrs.dp)) {
4968                 DRM_ERROR("DRRS already enabled\n");
4969                 goto unlock;
4970         }
4971
4972         dev_priv->drrs.busy_frontbuffer_bits = 0;
4973
4974         dev_priv->drrs.dp = intel_dp;
4975
4976 unlock:
4977         mutex_unlock(&dev_priv->drrs.mutex);
4978 }
4979
4980 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
4981 {
4982         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4983         struct drm_i915_private *dev_priv = dev->dev_private;
4984         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4985         struct drm_crtc *crtc = dig_port->base.base.crtc;
4986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4987
4988         if (!intel_crtc->config->has_drrs)
4989                 return;
4990
4991         mutex_lock(&dev_priv->drrs.mutex);
4992         if (!dev_priv->drrs.dp) {
4993                 mutex_unlock(&dev_priv->drrs.mutex);
4994                 return;
4995         }
4996
4997         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4998                 intel_dp_set_drrs_state(dev_priv->dev,
4999                         intel_dp->attached_connector->panel.
5000                         fixed_mode->vrefresh);
5001
5002         dev_priv->drrs.dp = NULL;
5003         mutex_unlock(&dev_priv->drrs.mutex);
5004
5005         cancel_delayed_work_sync(&dev_priv->drrs.work);
5006 }
5007
5008 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5009 {
5010         struct drm_i915_private *dev_priv =
5011                 container_of(work, typeof(*dev_priv), drrs.work.work);
5012         struct intel_dp *intel_dp;
5013
5014         mutex_lock(&dev_priv->drrs.mutex);
5015
5016         intel_dp = dev_priv->drrs.dp;
5017
5018         if (!intel_dp)
5019                 goto unlock;
5020
5021         /*
5022          * The delayed work can race with an invalidate hence we need to
5023          * recheck.
5024          */
5025
5026         if (dev_priv->drrs.busy_frontbuffer_bits)
5027                 goto unlock;
5028
5029         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5030                 intel_dp_set_drrs_state(dev_priv->dev,
5031                         intel_dp->attached_connector->panel.
5032                         downclock_mode->vrefresh);
5033
5034 unlock:
5035
5036         mutex_unlock(&dev_priv->drrs.mutex);
5037 }
5038
5039 void intel_edp_drrs_invalidate(struct drm_device *dev,
5040                 unsigned frontbuffer_bits)
5041 {
5042         struct drm_i915_private *dev_priv = dev->dev_private;
5043         struct drm_crtc *crtc;
5044         enum i915_pipe pipe;
5045
5046         if (!dev_priv->drrs.dp)
5047                 return;
5048
5049         mutex_lock(&dev_priv->drrs.mutex);
5050         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5051         pipe = to_intel_crtc(crtc)->pipe;
5052
5053         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
5054                 cancel_delayed_work_sync(&dev_priv->drrs.work);
5055                 intel_dp_set_drrs_state(dev_priv->dev,
5056                                 dev_priv->drrs.dp->attached_connector->panel.
5057                                 fixed_mode->vrefresh);
5058         }
5059
5060         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5061
5062         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5063         mutex_unlock(&dev_priv->drrs.mutex);
5064 }
5065
5066 void intel_edp_drrs_flush(struct drm_device *dev,
5067                 unsigned frontbuffer_bits)
5068 {
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070         struct drm_crtc *crtc;
5071         enum i915_pipe pipe;
5072
5073         if (!dev_priv->drrs.dp)
5074                 return;
5075
5076         mutex_lock(&dev_priv->drrs.mutex);
5077         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5078         pipe = to_intel_crtc(crtc)->pipe;
5079         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5080
5081         cancel_delayed_work_sync(&dev_priv->drrs.work);
5082
5083         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5084                         !dev_priv->drrs.busy_frontbuffer_bits)
5085                 schedule_delayed_work(&dev_priv->drrs.work,
5086                                 msecs_to_jiffies(1000));
5087         mutex_unlock(&dev_priv->drrs.mutex);
5088 }
5089
5090 static struct drm_display_mode *
5091 intel_dp_drrs_init(struct intel_connector *intel_connector,
5092                 struct drm_display_mode *fixed_mode)
5093 {
5094         struct drm_connector *connector = &intel_connector->base;
5095         struct drm_device *dev = connector->dev;
5096         struct drm_i915_private *dev_priv = dev->dev_private;
5097         struct drm_display_mode *downclock_mode = NULL;
5098
5099         if (INTEL_INFO(dev)->gen <= 6) {
5100                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5101                 return NULL;
5102         }
5103
5104         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5105                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5106                 return NULL;
5107         }
5108
5109         downclock_mode = intel_find_panel_downclock
5110                                         (dev, fixed_mode, connector);
5111
5112         if (!downclock_mode) {
5113                 DRM_DEBUG_KMS("DRRS not supported\n");
5114                 return NULL;
5115         }
5116
5117         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5118
5119         lockinit(&dev_priv->drrs.mutex, "i915dm", 0, LK_CANRECURSE);
5120
5121         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5122
5123         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5124         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5125         return downclock_mode;
5126 }
5127
5128 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5129                                      struct intel_connector *intel_connector)
5130 {
5131         struct drm_connector *connector = &intel_connector->base;
5132         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5133         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5134         struct drm_device *dev = intel_encoder->base.dev;
5135         struct drm_i915_private *dev_priv = dev->dev_private;
5136         struct drm_display_mode *fixed_mode = NULL;
5137         struct drm_display_mode *downclock_mode = NULL;
5138         bool has_dpcd;
5139         struct drm_display_mode *scan;
5140         struct edid *edid;
5141         enum i915_pipe pipe = INVALID_PIPE;
5142
5143         dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
5144
5145         if (!is_edp(intel_dp))
5146                 return true;
5147
5148         pps_lock(intel_dp);
5149         intel_edp_panel_vdd_sanitize(intel_dp);
5150         pps_unlock(intel_dp);
5151
5152         /* Cache DPCD and EDID for edp. */
5153         has_dpcd = intel_dp_get_dpcd(intel_dp);
5154
5155         if (has_dpcd) {
5156                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5157                         dev_priv->no_aux_handshake =
5158                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5159                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5160         } else {
5161                 /* if this fails, presume the device is a ghost */
5162                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5163                 return false;
5164         }
5165
5166         /* We now know it's not a ghost, init power sequence regs. */
5167         pps_lock(intel_dp);
5168         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5169         pps_unlock(intel_dp);
5170
5171         mutex_lock(&dev->mode_config.mutex);
5172         edid = drm_get_edid(connector, intel_dp->aux.ddc);
5173         if (edid) {
5174                 if (drm_add_edid_modes(connector, edid)) {
5175                         drm_mode_connector_update_edid_property(connector,
5176                                                                 edid);
5177                         drm_edid_to_eld(connector, edid);
5178                 } else {
5179                         kfree(edid);
5180                         edid = ERR_PTR(-EINVAL);
5181                 }
5182         } else {
5183                 edid = ERR_PTR(-ENOENT);
5184         }
5185         intel_connector->edid = edid;
5186
5187         /* prefer fixed mode from EDID if available */
5188         list_for_each_entry(scan, &connector->probed_modes, head) {
5189                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5190                         fixed_mode = drm_mode_duplicate(dev, scan);
5191                         downclock_mode = intel_dp_drrs_init(
5192                                                 intel_connector, fixed_mode);
5193                         break;
5194                 }
5195         }
5196
5197         /* fallback to VBT if available for eDP */
5198         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5199                 fixed_mode = drm_mode_duplicate(dev,
5200                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5201                 if (fixed_mode)
5202                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5203         }
5204         mutex_unlock(&dev->mode_config.mutex);
5205
5206         if (IS_VALLEYVIEW(dev)) {
5207 #if 0
5208                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5209                 register_reboot_notifier(&intel_dp->edp_notifier);
5210 #endif
5211
5212                 /*
5213                  * Figure out the current pipe for the initial backlight setup.
5214                  * If the current pipe isn't valid, try the PPS pipe, and if that
5215                  * fails just assume pipe A.
5216                  */
5217                 if (IS_CHERRYVIEW(dev))
5218                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5219                 else
5220                         pipe = PORT_TO_PIPE(intel_dp->DP);
5221
5222                 if (pipe != PIPE_A && pipe != PIPE_B)
5223                         pipe = intel_dp->pps_pipe;
5224
5225                 if (pipe != PIPE_A && pipe != PIPE_B)
5226                         pipe = PIPE_A;
5227
5228                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5229                               pipe_name(pipe));
5230         }
5231
5232         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5233         intel_connector->panel.backlight_power = intel_edp_backlight_power;
5234         intel_panel_setup_backlight(connector, pipe);
5235
5236         return true;
5237 }
5238
5239 bool
5240 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5241                         struct intel_connector *intel_connector)
5242 {
5243         struct drm_connector *connector = &intel_connector->base;
5244         struct intel_dp *intel_dp = &intel_dig_port->dp;
5245         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5246         struct drm_device *dev = intel_encoder->base.dev;
5247         struct drm_i915_private *dev_priv = dev->dev_private;
5248         enum port port = intel_dig_port->port;
5249         int type;
5250
5251         intel_dp->pps_pipe = INVALID_PIPE;
5252
5253         /* intel_dp vfuncs */
5254         if (INTEL_INFO(dev)->gen >= 9)
5255                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5256         else if (IS_VALLEYVIEW(dev))
5257                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5258         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5259                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5260         else if (HAS_PCH_SPLIT(dev))
5261                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5262         else
5263                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5264
5265         if (INTEL_INFO(dev)->gen >= 9)
5266                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5267         else
5268                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5269
5270         /* Preserve the current hw state. */
5271         intel_dp->DP = I915_READ(intel_dp->output_reg);
5272         intel_dp->attached_connector = intel_connector;
5273
5274         if (intel_dp_is_edp(dev, port))
5275                 type = DRM_MODE_CONNECTOR_eDP;
5276         else
5277                 type = DRM_MODE_CONNECTOR_DisplayPort;
5278
5279         /*
5280          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5281          * for DP the encoder type can be set by the caller to
5282          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5283          */
5284         if (type == DRM_MODE_CONNECTOR_eDP)
5285                 intel_encoder->type = INTEL_OUTPUT_EDP;
5286
5287         /* eDP only on port B and/or C on vlv/chv */
5288         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5289                     port != PORT_B && port != PORT_C))
5290                 return false;
5291
5292         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5293                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5294                         port_name(port));
5295
5296         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5297         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5298
5299         connector->interlace_allowed = true;
5300         connector->doublescan_allowed = 0;
5301
5302         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5303                           edp_panel_vdd_work);
5304
5305         intel_connector_attach_encoder(intel_connector, intel_encoder);
5306         drm_connector_register(connector);
5307
5308         if (HAS_DDI(dev))
5309                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5310         else
5311                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5312         intel_connector->unregister = intel_dp_connector_unregister;
5313
5314         /* Set up the hotplug pin. */
5315         switch (port) {
5316         case PORT_A:
5317                 intel_encoder->hpd_pin = HPD_PORT_A;
5318                 break;
5319         case PORT_B:
5320                 intel_encoder->hpd_pin = HPD_PORT_B;
5321                 break;
5322         case PORT_C:
5323                 intel_encoder->hpd_pin = HPD_PORT_C;
5324                 break;
5325         case PORT_D:
5326                 intel_encoder->hpd_pin = HPD_PORT_D;
5327                 break;
5328         default:
5329                 BUG();
5330         }
5331
5332         if (is_edp(intel_dp)) {
5333                 pps_lock(intel_dp);
5334                 intel_dp_init_panel_power_timestamps(intel_dp);
5335                 if (IS_VALLEYVIEW(dev))
5336                         vlv_initial_power_sequencer_setup(intel_dp);
5337                 else
5338                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5339                 pps_unlock(intel_dp);
5340         }
5341
5342         intel_dp_aux_init(intel_dp, intel_connector);
5343
5344         /* init MST on ports that can support it */
5345         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
5346                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5347                         intel_dp_mst_encoder_init(intel_dig_port,
5348                                                   intel_connector->base.base.id);
5349                 }
5350         }
5351
5352         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5353                 drm_dp_aux_unregister(&intel_dp->aux);
5354                 if (is_edp(intel_dp)) {
5355                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5356                         /*
5357                          * vdd might still be enabled do to the delayed vdd off.
5358                          * Make sure vdd is actually turned off here.
5359                          */
5360                         pps_lock(intel_dp);
5361                         edp_panel_vdd_off_sync(intel_dp);
5362                         pps_unlock(intel_dp);
5363                 }
5364                 drm_connector_unregister(connector);
5365                 drm_connector_cleanup(connector);
5366                 return false;
5367         }
5368
5369         intel_dp_add_properties(intel_dp, connector);
5370
5371         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5372          * 0xd.  Failure to do so will result in spurious interrupts being
5373          * generated on the port when a cable is not attached.
5374          */
5375         if (IS_G4X(dev) && !IS_GM45(dev)) {
5376                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5377                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5378         }
5379
5380         return true;
5381 }
5382
5383 void
5384 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5385 {
5386         struct drm_i915_private *dev_priv = dev->dev_private;
5387         struct intel_digital_port *intel_dig_port;
5388         struct intel_encoder *intel_encoder;
5389         struct drm_encoder *encoder;
5390         struct intel_connector *intel_connector;
5391
5392         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5393         if (!intel_dig_port)
5394                 return;
5395
5396         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5397         if (!intel_connector) {
5398                 kfree(intel_dig_port);
5399                 return;
5400         }
5401
5402         intel_encoder = &intel_dig_port->base;
5403         encoder = &intel_encoder->base;
5404
5405         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5406                          DRM_MODE_ENCODER_TMDS);
5407
5408         intel_encoder->compute_config = intel_dp_compute_config;
5409         intel_encoder->disable = intel_disable_dp;
5410         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5411         intel_encoder->get_config = intel_dp_get_config;
5412         intel_encoder->suspend = intel_dp_encoder_suspend;
5413         if (IS_CHERRYVIEW(dev)) {
5414                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5415                 intel_encoder->pre_enable = chv_pre_enable_dp;
5416                 intel_encoder->enable = vlv_enable_dp;
5417                 intel_encoder->post_disable = chv_post_disable_dp;
5418         } else if (IS_VALLEYVIEW(dev)) {
5419                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5420                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5421                 intel_encoder->enable = vlv_enable_dp;
5422                 intel_encoder->post_disable = vlv_post_disable_dp;
5423         } else {
5424                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5425                 intel_encoder->enable = g4x_enable_dp;
5426                 if (INTEL_INFO(dev)->gen >= 5)
5427                         intel_encoder->post_disable = ilk_post_disable_dp;
5428         }
5429
5430         intel_dig_port->port = port;
5431         intel_dig_port->dp.output_reg = output_reg;
5432
5433         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5434         if (IS_CHERRYVIEW(dev)) {
5435                 if (port == PORT_D)
5436                         intel_encoder->crtc_mask = 1 << 2;
5437                 else
5438                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5439         } else {
5440                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5441         }
5442         intel_encoder->cloneable = 0;
5443         intel_encoder->hot_plug = intel_dp_hot_plug;
5444
5445         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5446         dev_priv->hpd_irq_port[port] = intel_dig_port;
5447
5448         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5449                 drm_encoder_cleanup(encoder);
5450                 kfree(intel_dig_port);
5451                 kfree(intel_connector);
5452         }
5453 }
5454
5455 void intel_dp_mst_resume(struct drm_device *dev)
5456 {
5457         struct drm_i915_private *dev_priv = dev->dev_private;
5458         int i;
5459
5460         for (i = 0; i < I915_MAX_PORTS; i++) {
5461                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5462                 if (!intel_dig_port)
5463                         continue;
5464                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5465 #if 0
5466                         int ret;
5467
5468                         if (!intel_dig_port->dp.can_mst)
5469                                 continue;
5470
5471                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5472                         if (ret != 0) {
5473                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5474                         }
5475 #endif
5476                 }
5477         }
5478 }