2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c 188866 2009-02-20 22:06:58Z sam $
23 #include "ah_internal.h"
26 #include "ah_desc.h" /* NB: for HAL_PHYERR* */
29 #include "ar5212/ar5212.h"
30 #include "ar5212/ar5212reg.h"
31 #include "ar5212/ar5212phy.h"
33 #include "ah_eeprom_v3.h"
35 #define AR_NUM_GPIO 6 /* 6 GPIO pins */
36 #define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
39 ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
41 struct ath_hal_5212 *ahp = AH5212(ah);
43 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
47 ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
49 struct ath_hal_5212 *ahp = AH5212(ah);
51 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
56 ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
58 struct ath_hal_5212 *ahp = AH5212(ah);
60 OS_MEMCPY(mask, ahp->ah_bssidmask, IEEE80211_ADDR_LEN);
64 ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
66 struct ath_hal_5212 *ahp = AH5212(ah);
68 /* save it since it must be rewritten on reset */
69 OS_MEMCPY(ahp->ah_bssidmask, mask, IEEE80211_ADDR_LEN);
71 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
72 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
77 * Attempt to change the cards operating regulatory domain to the given value
80 ar5212SetRegulatoryDomain(struct ath_hal *ah,
81 uint16_t regDomain, HAL_STATUS *status)
85 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
89 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
93 #ifdef AH_SUPPORT_WRITE_REGDOMAIN
94 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
95 HALDEBUG(ah, HAL_DEBUG_ANY,
96 "%s: set regulatory domain to %u (0x%x)\n",
97 __func__, regDomain, regDomain);
98 AH_PRIVATE(ah)->ah_currentRD = regDomain;
110 * Return the wireless modes (a,b,g,t) supported by hardware.
112 * This value is what is actually supported by the hardware
113 * and is unaffected by regulatory/country code settings.
116 ar5212GetWirelessModes(struct ath_hal *ah)
120 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
122 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
123 mode |= HAL_MODE_TURBO | HAL_MODE_108A;
124 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
125 mode |= HAL_MODE_11A_HALF_RATE;
126 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
127 mode |= HAL_MODE_11A_QUARTER_RATE;
129 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
130 mode |= HAL_MODE_11B;
131 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
132 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
133 mode |= HAL_MODE_11G;
134 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
135 mode |= HAL_MODE_108G;
136 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
137 mode |= HAL_MODE_11G_HALF_RATE;
138 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
139 mode |= HAL_MODE_11G_QUARTER_RATE;
145 * Set the interrupt and GPIO values so the ISR can disable RF
146 * on a switch signal. Assumes GPIO port and interrupt polarity
147 * are set prior to call.
150 ar5212EnableRfKill(struct ath_hal *ah)
152 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
153 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
154 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
157 * Configure the desired GPIO port for input
158 * and enable baseband rf silence.
160 ath_hal_gpioCfgInput(ah, select);
161 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
163 * If radio disable switch connection to GPIO bit x is enabled
164 * program GPIO interrupt.
165 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
166 * verified that it is a later version of eeprom, it has a place for
167 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
168 * connection is present.
170 ath_hal_gpioSetIntr(ah, select,
171 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
175 * Change the LED blinking pattern to correspond to the connectivity
178 ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
180 static const uint32_t ledbits[8] = {
181 AR_PCICFG_LEDCTL_NONE, /* HAL_LED_INIT */
182 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_SCAN */
183 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_AUTH */
184 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_ASSOC*/
185 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_RUN */
186 AR_PCICFG_LEDCTL_NONE,
187 AR_PCICFG_LEDCTL_NONE,
188 AR_PCICFG_LEDCTL_NONE,
192 bits = OS_REG_READ(ah, AR_PCICFG);
195 * Enable LED for Nala. There is a bit marked reserved
196 * that must be set and we also turn on the power led.
197 * Because we mark s/w LED control setting the control
198 * status bits below is meangless (the driver must flash
199 * the LED(s) using the GPIO lines).
201 bits = (bits &~ AR_PCICFG_LEDMODE)
202 | SM(AR_PCICFG_LEDMODE_POWON, AR_PCICFG_LEDMODE)
204 | SM(AR_PCICFG_LEDMODE_NETON, AR_PCICFG_LEDMODE)
208 bits = (bits &~ AR_PCICFG_LEDCTL)
209 | SM(ledbits[state & 0x7], AR_PCICFG_LEDCTL);
210 OS_REG_WRITE(ah, AR_PCICFG, bits);
214 * Change association related fields programmed into the hardware.
215 * Writing a valid BSSID to the hardware effectively enables the hardware
216 * to synchronize its TSF to the correct beacons and receive frames coming
217 * from that BSSID. It is called by the SME JOIN operation.
220 ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
222 struct ath_hal_5212 *ahp = AH5212(ah);
224 /* XXX save bssid for possible re-use on reset */
225 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
226 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
227 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
228 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
232 * Get the current hardware tsf for stamlme
235 ar5212GetTsf64(struct ath_hal *ah)
237 uint32_t low1, low2, u32;
239 /* sync multi-word read */
240 low1 = OS_REG_READ(ah, AR_TSF_L32);
241 u32 = OS_REG_READ(ah, AR_TSF_U32);
242 low2 = OS_REG_READ(ah, AR_TSF_L32);
243 if (low2 < low1) { /* roll over */
245 * If we are not preempted this will work. If we are
246 * then we re-reading AR_TSF_U32 does no good as the
247 * low bits will be meaningless. Likewise reading
248 * L32, U32, U32, then comparing the last two reads
249 * to check for rollover doesn't help if preempted--so
250 * we take this approach as it costs one less PCI read
251 * which can be noticeable when doing things like
252 * timestamping packets in monitor mode.
256 return (((uint64_t) u32) << 32) | ((uint64_t) low2);
260 * Get the current hardware tsf for stamlme
263 ar5212GetTsf32(struct ath_hal *ah)
265 return OS_REG_READ(ah, AR_TSF_L32);
269 * Reset the current hardware tsf for stamlme.
272 ar5212ResetTsf(struct ath_hal *ah)
275 uint32_t val = OS_REG_READ(ah, AR_BEACON);
277 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
279 * When resetting the TSF, write twice to the
280 * corresponding register; each write to the RESET_TSF bit toggles
281 * the internal signal to cause a reset of the TSF - but if the signal
282 * is left high, it will reset the TSF on the next chip reset also!
283 * writing the bit an even number of times fixes this issue
285 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
289 * Set or clear hardware basic rate bit
290 * Set hardware basic rate set if basic rate is found
291 * and basic rate is equal or less than 2Mbps
294 ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
296 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
301 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan))
304 for (i = 0; i < rs->rs_count; i++) {
305 uint8_t rset = rs->rs_rates[i];
306 /* Basic rate defined? */
307 if ((rset & 0x80) && (rset &= 0x7f) >= xset)
311 * Set the h/w bit to reflect whether or not the basic
312 * rate is found to be equal or less than 2Mbps.
314 reg = OS_REG_READ(ah, AR_STA_ID1);
315 if (xset && xset/2 <= 2)
316 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
318 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
322 * Grab a semi-random value from hardware registers - may not
326 ar5212GetRandomSeed(struct ath_hal *ah)
330 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
332 nf = 0 - ((nf ^ 0x1ff) + 1);
333 return (OS_REG_READ(ah, AR_TSF_U32) ^
334 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
338 * Detect if our card is present
341 ar5212DetectCardPresent(struct ath_hal *ah)
343 uint16_t macVersion, macRev;
347 * Read the Silicon Revision register and compare that
348 * to what we read at attach time. If the same, we say
349 * a card/device is present.
351 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
352 macVersion = v >> AR_SREV_ID_S;
353 macRev = v & AR_SREV_REVISION;
354 return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
355 AH_PRIVATE(ah)->ah_macRev == macRev);
359 ar5212EnableMibCounters(struct ath_hal *ah)
361 /* NB: this just resets the mib counter machinery */
362 OS_REG_WRITE(ah, AR_MIBC,
363 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f);
367 ar5212DisableMibCounters(struct ath_hal *ah)
369 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC);
373 * Update MIB Counters
376 ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
378 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
379 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
380 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
381 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
382 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
386 * Detect if the HW supports spreading a CCK signal on channel 14
389 ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
395 * Get the rssi of frame curently being received.
398 ar5212GetCurRssi(struct ath_hal *ah)
400 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
404 ar5212GetDefAntenna(struct ath_hal *ah)
406 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
410 ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
412 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
416 ar5212GetAntennaSwitch(struct ath_hal *ah)
418 return AH5212(ah)->ah_antControl;
422 ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
424 struct ath_hal_5212 *ahp = AH5212(ah);
425 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
427 if (!ahp->ah_phyPowerOn || chan == AH_NULL) {
428 /* PHY powered off, just stash settings */
429 ahp->ah_antControl = setting;
430 ahp->ah_diversity = (setting == HAL_ANT_VARIABLE);
433 return ar5212SetAntennaSwitchInternal(ah, setting, chan);
437 ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
443 ar5212SetSifsTime(struct ath_hal *ah, u_int us)
445 struct ath_hal_5212 *ahp = AH5212(ah);
447 if (us > ath_hal_mac_usec(ah, 0xffff)) {
448 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
450 ahp->ah_sifstime = (u_int) -1; /* restore default handling */
453 /* convert to system clocks */
454 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
455 ahp->ah_slottime = us;
461 ar5212GetSifsTime(struct ath_hal *ah)
463 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
464 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
468 ar5212SetSlotTime(struct ath_hal *ah, u_int us)
470 struct ath_hal_5212 *ahp = AH5212(ah);
472 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
473 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
475 ahp->ah_slottime = (u_int) -1; /* restore default handling */
478 /* convert to system clocks */
479 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
480 ahp->ah_slottime = us;
486 ar5212GetSlotTime(struct ath_hal *ah)
488 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
489 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
493 ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
495 struct ath_hal_5212 *ahp = AH5212(ah);
497 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
498 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
500 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
503 /* convert to system clocks */
504 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
505 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
506 ahp->ah_acktimeout = us;
512 ar5212GetAckTimeout(struct ath_hal *ah)
514 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
515 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
519 ar5212GetAckCTSRate(struct ath_hal *ah)
521 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
525 ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
527 struct ath_hal_5212 *ahp = AH5212(ah);
530 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
531 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
533 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
534 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
540 ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
542 struct ath_hal_5212 *ahp = AH5212(ah);
544 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
545 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
547 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
550 /* convert to system clocks */
551 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
552 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
553 ahp->ah_ctstimeout = us;
559 ar5212GetCTSTimeout(struct ath_hal *ah)
561 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
562 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
565 /* Setup decompression for given key index */
567 ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
569 struct ath_hal_5212 *ahp = AH5212(ah);
571 if (keyidx >= HAL_DECOMP_MASK_SIZE)
573 OS_REG_WRITE(ah, AR_DCM_A, keyidx);
574 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
575 ahp->ah_decompMask[keyidx] = en;
580 /* Setup coverage class */
582 ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
584 uint32_t slot, timeout, eifs;
587 AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
590 if (AH_PRIVATE(ah)->ah_coverageClass == 0)
593 /* Don't apply coverage class to non A channels */
594 if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
597 /* Get core clock rate */
598 clkRate = ath_hal_mac_clks(ah, 1);
601 slot = coverageclass * 3 * clkRate;
602 eifs = coverageclass * 6 * clkRate;
603 if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {
604 slot += IFS_SLOT_HALF_RATE;
605 eifs += IFS_EIFS_HALF_RATE;
606 } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {
607 slot += IFS_SLOT_QUARTER_RATE;
608 eifs += IFS_EIFS_QUARTER_RATE;
609 } else { /* full rate */
610 slot += IFS_SLOT_FULL_RATE;
611 eifs += IFS_EIFS_FULL_RATE;
615 * Add additional time for air propagation for ACK and CTS
616 * timeouts. This value is in core clocks.
618 timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate);
621 * Write the values: slot, eifs, ack/cts timeouts.
623 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
624 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
625 OS_REG_WRITE(ah, AR_TIME_OUT,
626 SM(timeout, AR_TIME_OUT_CTS)
627 | SM(timeout, AR_TIME_OUT_ACK));
632 ar5212SetPCUConfig(struct ath_hal *ah)
634 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
638 * Return whether an external 32KHz crystal should be used
639 * to reduce power consumption when sleeping. We do so if
640 * the crystal is present (obtained from EEPROM) and if we
641 * are not running as an AP and are configured to use it.
644 ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
646 if (opmode != HAL_M_HOSTAP) {
647 struct ath_hal_5212 *ahp = AH5212(ah);
648 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
649 (ahp->ah_enable32kHzClock == USE_32KHZ ||
650 ahp->ah_enable32kHzClock == AUTO_32KHZ);
656 * If 32KHz clock exists, use it to lower power consumption during sleep
658 * Note: If clock is set to 32 KHz, delays on accessing certain
659 * baseband registers (27-31, 124-127) are required.
662 ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
664 if (ar5212Use32KHzclock(ah, opmode)) {
666 * Enable clocks to be turned OFF in BB during sleep
667 * and also enable turning OFF 32MHz/40MHz Refclk
670 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
671 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
672 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
673 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
674 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
675 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
677 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
678 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26);
679 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d);
680 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07);
681 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f);
682 /* # Set sleep clock rate to 32 KHz. */
683 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
685 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a);
686 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
687 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
688 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20);
689 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
692 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
693 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
695 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */
697 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
698 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
701 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
702 else if (IS_HB63(ah))
703 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
705 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
706 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
707 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
708 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
709 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
710 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
711 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
716 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
719 ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
721 if (ar5212Use32KHzclock(ah, opmode)) {
722 /* # Set sleep clock rate back to 32 MHz. */
723 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
724 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
726 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
727 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
728 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
731 * Restore BB registers to power-on defaults
733 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
734 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
735 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
736 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
737 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
738 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
739 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
744 * Adjust NF based on statistical values for 5GHz frequencies.
745 * Default method: this may be overridden by the rf backend.
748 ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
750 static const struct {
754 { 5790, 11 }, /* NB: ordered high -> low */
768 for (i = 0; c->channel <= adjustDef[i].freqLow; i++)
770 return adjustDef[i].adjust;
774 ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
775 uint32_t capability, uint32_t *result)
777 #define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion
778 struct ath_hal_5212 *ahp = AH5212(ah);
779 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
780 const struct ar5212AniState *ani;
783 case HAL_CAP_CIPHER: /* cipher handled in hardware */
784 switch (capability) {
785 case HAL_CIPHER_AES_CCM:
786 return pCap->halCipherAesCcmSupport ?
787 HAL_OK : HAL_ENOTSUPP;
788 case HAL_CIPHER_AES_OCB:
789 case HAL_CIPHER_TKIP:
797 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
798 switch (capability) {
799 case 0: /* hardware capability */
802 return (ahp->ah_staId1Defaults &
803 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
806 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
807 switch (capability) {
808 case 0: /* hardware capability */
809 return pCap->halTkipMicTxRxKeySupport ?
811 case 1: /* current setting */
812 return (ahp->ah_miscMode &
813 AR_MISC_MODE_MIC_NEW_LOC_ENABLE) ? HAL_ENXIO : HAL_OK;
816 case HAL_CAP_WME_TKIPMIC: /* hardware can do TKIP MIC w/ WMM */
817 /* XXX move to capability bit */
818 return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
819 (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
820 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
821 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
822 switch (capability) {
823 case 0: /* hardware capability */
825 case 1: /* current setting */
826 return ahp->ah_diversity ? HAL_OK : HAL_ENXIO;
830 *result = AH_PRIVATE(ah)->ah_diagreg;
833 switch (capability) {
834 case 0: /* hardware capability */
837 return ahp->ah_tpcEnabled ? HAL_OK : HAL_ENXIO;
840 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
841 switch (capability) {
843 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
846 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
847 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
851 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
852 switch (capability) {
853 case 0: /* hardware capability */
856 return (ahp->ah_staId1Defaults &
857 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
860 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
861 switch (capability) {
862 case 0: /* hardware capability */
863 return pCap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
865 return (ahp->ah_miscMode & AR_MISC_MODE_TX_ADD_TSF) ?
869 case HAL_CAP_TPC_ACK:
870 *result = MS(ahp->ah_macTPC, AR_TPC_ACK);
872 case HAL_CAP_TPC_CTS:
873 *result = MS(ahp->ah_macTPC, AR_TPC_CTS);
875 case HAL_CAP_INTMIT: /* interference mitigation */
876 switch (capability) {
877 case 0: /* hardware capability */
880 return (ahp->ah_procPhyErr & HAL_ANI_ENA) ?
882 case 2: /* HAL_ANI_NOISE_IMMUNITY_LEVEL */
883 case 3: /* HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION */
884 case 4: /* HAL_ANI_CCK_WEAK_SIGNAL_THR */
885 case 5: /* HAL_ANI_FIRSTEP_LEVEL */
886 case 6: /* HAL_ANI_SPUR_IMMUNITY_LEVEL */
887 ani = ar5212AniGetCurrentState(ah);
890 switch (capability) {
891 case 2: *result = ani->noiseImmunityLevel; break;
892 case 3: *result = !ani->ofdmWeakSigDetectOff; break;
893 case 4: *result = ani->cckWeakSigThreshold; break;
894 case 5: *result = ani->firstepLevel; break;
895 case 6: *result = ani->spurImmunityLevel; break;
901 return ath_hal_getcapability(ah, type, capability, result);
907 ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
908 uint32_t capability, uint32_t setting, HAL_STATUS *status)
910 struct ath_hal_5212 *ahp = AH5212(ah);
911 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
915 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
917 ahp->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
919 ahp->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
921 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
922 if (!pCap->halTkipMicTxRxKeySupport)
924 /* NB: true =>'s use split key cache layout */
926 ahp->ah_miscMode &= ~AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
928 ahp->ah_miscMode |= AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
929 /* NB: write here so keys can be setup w/o a reset */
930 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
932 case HAL_CAP_DIVERSITY:
933 if (ahp->ah_phyPowerOn) {
934 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
936 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
938 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
939 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
941 ahp->ah_diversity = (setting != 0);
943 case HAL_CAP_DIAG: /* hardware diagnostic support */
945 * NB: could split this up into virtual capabilities,
946 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
947 * seems worth the additional complexity.
949 AH_PRIVATE(ah)->ah_diagreg = setting;
950 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
953 ahp->ah_tpcEnabled = (setting != 0);
955 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
957 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
959 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
961 case HAL_CAP_TPC_ACK:
962 case HAL_CAP_TPC_CTS:
963 setting += ahp->ah_txPowerIndexOffset;
966 if (type == HAL_CAP_TPC_ACK) {
967 ahp->ah_macTPC &= AR_TPC_ACK;
968 ahp->ah_macTPC |= MS(setting, AR_TPC_ACK);
970 ahp->ah_macTPC &= AR_TPC_CTS;
971 ahp->ah_macTPC |= MS(setting, AR_TPC_CTS);
973 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
975 case HAL_CAP_INTMIT: { /* interference mitigation */
976 static const HAL_ANI_CMD cmds[] = {
979 HAL_ANI_NOISE_IMMUNITY_LEVEL,
980 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
981 HAL_ANI_CCK_WEAK_SIGNAL_THR,
982 HAL_ANI_FIRSTEP_LEVEL,
983 HAL_ANI_SPUR_IMMUNITY_LEVEL,
985 return capability < NELEM(cmds) ?
986 ar5212AniControl(ah, cmds[capability], setting) :
989 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
990 if (pCap->halTsfAddSupport) {
992 ahp->ah_miscMode |= AR_MISC_MODE_TX_ADD_TSF;
994 ahp->ah_miscMode &= ~AR_MISC_MODE_TX_ADD_TSF;
999 return ath_hal_setcapability(ah, type, capability,
1005 ar5212GetDiagState(struct ath_hal *ah, int request,
1006 const void *args, uint32_t argsize,
1007 void **result, uint32_t *resultsize)
1009 struct ath_hal_5212 *ahp = AH5212(ah);
1012 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
1015 case HAL_DIAG_EEPROM:
1016 case HAL_DIAG_EEPROM_EXP_11A:
1017 case HAL_DIAG_EEPROM_EXP_11B:
1018 case HAL_DIAG_EEPROM_EXP_11G:
1019 case HAL_DIAG_RFGAIN:
1020 return ath_hal_eepromDiag(ah, request,
1021 args, argsize, result, resultsize);
1022 case HAL_DIAG_RFGAIN_CURSTEP:
1023 *result = __DECONST(void *, ahp->ah_gainValues.currStep);
1024 *resultsize = (*result == AH_NULL) ?
1025 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1027 case HAL_DIAG_PCDAC:
1028 *result = ahp->ah_pcdacTable;
1029 *resultsize = ahp->ah_pcdacTableSize;
1031 case HAL_DIAG_TXRATES:
1032 *result = &ahp->ah_ratesArray[0];
1033 *resultsize = sizeof(ahp->ah_ratesArray);
1035 case HAL_DIAG_ANI_CURRENT:
1036 *result = ar5212AniGetCurrentState(ah);
1037 *resultsize = (*result == AH_NULL) ?
1038 0 : sizeof(struct ar5212AniState);
1040 case HAL_DIAG_ANI_STATS:
1041 *result = ar5212AniGetCurrentStats(ah);
1042 *resultsize = (*result == AH_NULL) ?
1043 0 : sizeof(struct ar5212Stats);
1045 case HAL_DIAG_ANI_CMD:
1046 if (argsize != 2*sizeof(uint32_t))
1048 ar5212AniControl(ah, ((const uint32_t *)args)[0],
1049 ((const uint32_t *)args)[1]);
1051 case HAL_DIAG_ANI_PARAMS:
1053 * NB: We assume struct ar5212AniParams is identical
1054 * to HAL_ANI_PARAMS; if they diverge then we'll need
1057 if (argsize == 0 && args == AH_NULL) {
1058 struct ar5212AniState *aniState =
1059 ar5212AniGetCurrentState(ah);
1060 if (aniState == AH_NULL)
1062 *result = __DECONST(void *, aniState->params);
1063 *resultsize = sizeof(struct ar5212AniParams);
1066 if (argsize != sizeof(struct ar5212AniParams))
1068 return ar5212AniSetParams(ah, args, args);
1075 * Check whether there's an in-progress NF completion.
1077 * Returns AH_TRUE if there's a in-progress NF calibration, AH_FALSE
1081 ar5212IsNFCalInProgress(struct ath_hal *ah)
1083 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1089 * Wait for an in-progress NF calibration to complete.
1091 * The completion function waits "i" times 10uS.
1092 * It returns AH_TRUE if the NF calibration completed (or was never
1093 * in progress); AH_FALSE if it was still in progress after "i" checks.
1096 ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
1100 i = 1; /* it should run at least once */
1101 for (j = 0; j < i; j++) {
1102 if (! ar5212IsNFCalInProgress(ah))