3 * Damien Bergamini <damien.bergamini@free.fr>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: src/sys/dev/ral/rt2661.c,v 1.4 2006/03/21 21:15:43 damien Exp $
18 * $DragonFly: src/sys/dev/netif/ral/rt2661.c,v 1.17 2007/04/22 05:18:38 sephe Exp $
22 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
23 * http://www.ralinktech.com/
26 #include <sys/param.h>
28 #include <sys/endian.h>
29 #include <sys/kernel.h>
30 #include <sys/malloc.h>
32 #include <sys/module.h>
33 #include <sys/queue.h>
35 #include <sys/socket.h>
36 #include <sys/sockio.h>
37 #include <sys/sysctl.h>
38 #include <sys/serialize.h>
42 #include <net/if_arp.h>
43 #include <net/ethernet.h>
44 #include <net/if_dl.h>
45 #include <net/if_media.h>
46 #include <net/ifq_var.h>
48 #include <netproto/802_11/ieee80211_var.h>
49 #include <netproto/802_11/ieee80211_radiotap.h>
51 #include <dev/netif/ral/rt2661reg.h>
52 #include <dev/netif/ral/rt2661var.h>
53 #include <dev/netif/ral/rt2661_ucode.h>
56 #define DPRINTF(x) do { if (ral_debug > 0) kprintf x; } while (0)
57 #define DPRINTFN(n, x) do { if (ral_debug >= (n)) kprintf x; } while (0)
59 SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level");
62 #define DPRINTFN(n, x)
65 MALLOC_DEFINE(M_RT2661, "rt2661_ratectl", "rt2661 rate control data");
67 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
69 static void rt2661_dma_map_mbuf(void *, bus_dma_segment_t *, int,
71 static int rt2661_alloc_tx_ring(struct rt2661_softc *,
72 struct rt2661_tx_ring *, int);
73 static void rt2661_reset_tx_ring(struct rt2661_softc *,
74 struct rt2661_tx_ring *);
75 static void rt2661_free_tx_ring(struct rt2661_softc *,
76 struct rt2661_tx_ring *);
77 static int rt2661_alloc_rx_ring(struct rt2661_softc *,
78 struct rt2661_rx_ring *, int);
79 static void rt2661_reset_rx_ring(struct rt2661_softc *,
80 struct rt2661_rx_ring *);
81 static void rt2661_free_rx_ring(struct rt2661_softc *,
82 struct rt2661_rx_ring *);
83 static int rt2661_media_change(struct ifnet *);
84 static void rt2661_next_scan(void *);
85 static int rt2661_newstate(struct ieee80211com *,
86 enum ieee80211_state, int);
87 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
88 static void rt2661_rx_intr(struct rt2661_softc *);
89 static void rt2661_tx_intr(struct rt2661_softc *);
90 static void rt2661_tx_dma_intr(struct rt2661_softc *,
91 struct rt2661_tx_ring *);
92 static void rt2661_mcu_beacon_expire(struct rt2661_softc *);
93 static void rt2661_mcu_wakeup(struct rt2661_softc *);
94 static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
95 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *);
96 static uint8_t rt2661_plcp_signal(int);
97 static void rt2661_setup_tx_desc(struct rt2661_softc *,
98 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
99 int, const bus_dma_segment_t *, int, int, int);
100 static struct mbuf * rt2661_get_rts(struct rt2661_softc *,
101 struct ieee80211_frame *, uint16_t);
102 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *,
103 struct ieee80211_node *, int);
104 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *,
105 struct ieee80211_node *);
106 static void rt2661_start(struct ifnet *);
107 static void rt2661_watchdog(struct ifnet *);
108 static int rt2661_reset(struct ifnet *);
109 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t,
111 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t,
113 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
114 static void rt2661_rf_write(struct rt2661_softc *, uint8_t,
116 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t,
118 static void rt2661_select_antenna(struct rt2661_softc *);
119 static void rt2661_enable_mrr(struct rt2661_softc *);
120 static void rt2661_set_txpreamble(struct rt2661_softc *);
121 static void rt2661_set_ackrates(struct rt2661_softc *,
122 const struct ieee80211_rateset *);
123 static void rt2661_select_band(struct rt2661_softc *,
124 struct ieee80211_channel *);
125 static void rt2661_set_chan(struct rt2661_softc *,
126 struct ieee80211_channel *);
127 static void rt2661_set_bssid(struct rt2661_softc *,
129 static void rt2661_set_macaddr(struct rt2661_softc *,
131 static void rt2661_update_promisc(struct rt2661_softc *);
132 static int rt2661_wme_update(struct ieee80211com *) __unused;
133 static void rt2661_update_slot(struct ifnet *);
134 static const char *rt2661_get_rf(int);
135 static void rt2661_read_eeprom(struct rt2661_softc *);
136 static int rt2661_bbp_init(struct rt2661_softc *);
137 static void rt2661_init(void *);
138 static void rt2661_stop(void *);
139 static void rt2661_intr(void *);
140 static int rt2661_load_microcode(struct rt2661_softc *,
141 const uint8_t *, int);
143 static void rt2661_rx_tune(struct rt2661_softc *);
144 static void rt2661_radar_start(struct rt2661_softc *);
145 static int rt2661_radar_stop(struct rt2661_softc *);
147 static int rt2661_prepare_beacon(struct rt2661_softc *);
148 static void rt2661_enable_tsf_sync(struct rt2661_softc *);
149 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
150 static void rt2661_led_newstate(struct rt2661_softc *,
151 enum ieee80211_state);
154 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
156 static const struct ieee80211_rateset rt2661_rateset_11a =
157 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } };
159 static const struct ieee80211_rateset rt2661_rateset_11b =
160 { 4, { 2, 4, 11, 22 } };
162 static const struct ieee80211_rateset rt2661_rateset_11g =
163 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
165 static const struct {
168 } rt2661_def_mac[] = {
172 static const struct {
175 } rt2661_def_bbp[] = {
179 static const struct rfprog {
181 uint32_t r1, r2, r3, r4;
182 } rt2661_rf5225_1[] = {
184 }, rt2661_rf5225_2[] = {
188 #define LED_EE2MCU(bit) { \
189 .ee_bit = RT2661_EE_LED_##bit, \
190 .mcu_bit = RT2661_MCU_LED_##bit \
192 static const struct {
207 struct rt2661_dmamap {
208 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
213 rt2661_attach(device_t dev, int id)
215 struct rt2661_softc *sc = device_get_softc(dev);
216 struct ieee80211com *ic = &sc->sc_ic;
217 struct ifnet *ifp = &ic->ic_if;
219 const uint8_t *ucode = NULL;
220 int error, i, ac, ntries, size = 0;
222 callout_init(&sc->scan_ch);
225 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irq_rid,
226 RF_ACTIVE | RF_SHAREABLE);
227 if (sc->sc_irq == NULL) {
228 device_printf(dev, "could not allocate interrupt resource\n");
232 /* wait for NIC to initialize */
233 for (ntries = 0; ntries < 1000; ntries++) {
234 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
238 if (ntries == 1000) {
239 device_printf(sc->sc_dev,
240 "timeout waiting for NIC to initialize\n");
245 /* retrieve RF rev. no and various other things from EEPROM */
246 rt2661_read_eeprom(sc);
248 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val,
249 rt2661_get_rf(sc->rf_rev));
252 * Load 8051 microcode into NIC.
256 ucode = rt2561s_ucode;
257 size = sizeof rt2561s_ucode;
260 ucode = rt2561_ucode;
261 size = sizeof rt2561_ucode;
264 ucode = rt2661_ucode;
265 size = sizeof rt2661_ucode;
269 error = rt2661_load_microcode(sc, ucode, size);
271 device_printf(sc->sc_dev, "could not load 8051 microcode\n");
276 * Allocate Tx and Rx rings.
278 for (ac = 0; ac < 4; ac++) {
279 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
280 RT2661_TX_RING_COUNT);
282 device_printf(sc->sc_dev,
283 "could not allocate Tx ring %d\n", ac);
288 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
290 device_printf(sc->sc_dev, "could not allocate Mgt ring\n");
294 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
296 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
300 STAILQ_INIT(&sc->tx_ratectl);
302 sysctl_ctx_init(&sc->sysctl_ctx);
303 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
304 SYSCTL_STATIC_CHILDREN(_hw),
306 device_get_nameunit(dev),
308 if (sc->sysctl_tree == NULL) {
309 device_printf(dev, "could not add sysctl node\n");
315 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
316 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
317 ifp->if_init = rt2661_init;
318 ifp->if_ioctl = rt2661_ioctl;
319 ifp->if_start = rt2661_start;
320 ifp->if_watchdog = rt2661_watchdog;
321 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
322 ifq_set_ready(&ifp->if_snd);
324 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
325 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
326 ic->ic_state = IEEE80211_S_INIT;
327 rt2661_led_newstate(sc, IEEE80211_S_INIT);
329 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE |
330 IEEE80211_RATECTL_CAP_SAMPLE;
331 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_SAMPLE;
333 /* set device capabilities */
335 IEEE80211_C_IBSS | /* IBSS mode supported */
336 IEEE80211_C_MONITOR | /* monitor mode supported */
337 IEEE80211_C_HOSTAP | /* HostAp mode supported */
338 IEEE80211_C_TXPMGT | /* tx power management */
339 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
340 IEEE80211_C_SHSLOT | /* short slot time supported */
342 IEEE80211_C_WME | /* 802.11e */
344 IEEE80211_C_WEP | /* WEP */
345 IEEE80211_C_WPA; /* 802.11i */
347 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) {
348 /* set supported .11a rates */
349 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a;
351 /* set supported .11a channels */
352 for (i = 36; i <= 64; i += 4) {
353 ic->ic_channels[i].ic_freq =
354 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
355 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A;
357 for (i = 100; i <= 140; i += 4) {
358 ic->ic_channels[i].ic_freq =
359 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
360 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A;
362 for (i = 149; i <= 165; i += 4) {
363 ic->ic_channels[i].ic_freq =
364 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
365 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A;
369 /* set supported .11b and .11g rates */
370 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b;
371 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g;
373 /* set supported .11b and .11g channels (1 through 14) */
374 for (i = 1; i <= 14; i++) {
375 ic->ic_channels[i].ic_freq =
376 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
377 ic->ic_channels[i].ic_flags =
378 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
379 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
382 sc->sc_sifs = IEEE80211_DUR_SIFS; /* Default SIFS */
384 ieee80211_ifattach(ic);
385 /* ic->ic_wme.wme_update = rt2661_wme_update;*/
386 ic->ic_updateslot = rt2661_update_slot;
387 ic->ic_reset = rt2661_reset;
388 /* enable s/w bmiss handling in sta mode */
389 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
391 /* override state transition machine */
392 sc->sc_newstate = ic->ic_newstate;
393 ic->ic_newstate = rt2661_newstate;
394 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status);
396 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
397 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf);
399 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
400 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
401 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT);
403 sc->sc_txtap_len = sizeof sc->sc_txtapu;
404 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
405 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT);
408 * Add a few sysctl knobs.
412 SYSCTL_ADD_INT(&sc->sysctl_ctx,
413 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "dwell",
414 CTLFLAG_RW, &sc->dwelltime, 0,
415 "channel dwell time (ms) for AP/station scanning");
417 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, rt2661_intr,
418 sc, &sc->sc_ih, ifp->if_serializer);
420 device_printf(dev, "could not set up interrupt\n");
422 ieee80211_ifdetach(ic);
427 ieee80211_announce(ic);
435 rt2661_detach(void *xsc)
437 struct rt2661_softc *sc = xsc;
438 struct ieee80211com *ic = &sc->sc_ic;
439 struct ifnet *ifp = &ic->ic_if;
441 if (device_is_attached(sc->sc_dev)) {
442 lwkt_serialize_enter(ifp->if_serializer);
444 callout_stop(&sc->scan_ch);
446 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
448 lwkt_serialize_exit(ifp->if_serializer);
451 ieee80211_ifdetach(ic);
454 rt2661_free_tx_ring(sc, &sc->txq[0]);
455 rt2661_free_tx_ring(sc, &sc->txq[1]);
456 rt2661_free_tx_ring(sc, &sc->txq[2]);
457 rt2661_free_tx_ring(sc, &sc->txq[3]);
458 rt2661_free_tx_ring(sc, &sc->mgtq);
459 rt2661_free_rx_ring(sc, &sc->rxq);
461 if (sc->sc_irq != NULL) {
462 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid,
466 if (sc->sysctl_tree != NULL)
467 sysctl_ctx_free(&sc->sysctl_ctx);
473 rt2661_shutdown(void *xsc)
475 struct rt2661_softc *sc = xsc;
476 struct ifnet *ifp = &sc->sc_ic.ic_if;
478 lwkt_serialize_enter(ifp->if_serializer);
480 lwkt_serialize_exit(ifp->if_serializer);
484 rt2661_suspend(void *xsc)
486 struct rt2661_softc *sc = xsc;
487 struct ifnet *ifp = &sc->sc_ic.ic_if;
489 lwkt_serialize_enter(ifp->if_serializer);
491 lwkt_serialize_exit(ifp->if_serializer);
495 rt2661_resume(void *xsc)
497 struct rt2661_softc *sc = xsc;
498 struct ifnet *ifp = sc->sc_ic.ic_ifp;
500 lwkt_serialize_enter(ifp->if_serializer);
501 if (ifp->if_flags & IFF_UP) {
502 ifp->if_init(ifp->if_softc);
503 if (ifp->if_flags & IFF_RUNNING)
506 lwkt_serialize_exit(ifp->if_serializer);
510 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
515 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
517 *(bus_addr_t *)arg = segs[0].ds_addr;
521 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring,
528 ring->cur = ring->next = 0;
530 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
531 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1,
532 count * RT2661_TX_DESC_SIZE, 0, &ring->desc_dmat);
534 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
538 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
539 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map);
541 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
545 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
546 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
549 device_printf(sc->sc_dev, "could not load desc DMA map\n");
551 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
556 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF,
559 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
560 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * RT2661_MAX_SCATTER,
561 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat);
563 device_printf(sc->sc_dev, "could not create data DMA tag\n");
567 for (i = 0; i < count; i++) {
568 error = bus_dmamap_create(ring->data_dmat, 0,
571 device_printf(sc->sc_dev, "could not create DMA map\n");
577 fail: rt2661_free_tx_ring(sc, ring);
582 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
584 struct rt2661_tx_desc *desc;
585 struct rt2661_data *data;
588 for (i = 0; i < ring->count; i++) {
589 desc = &ring->desc[i];
590 data = &ring->data[i];
592 if (data->m != NULL) {
593 bus_dmamap_sync(ring->data_dmat, data->map,
594 BUS_DMASYNC_POSTWRITE);
595 bus_dmamap_unload(ring->data_dmat, data->map);
603 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
606 ring->cur = ring->next = 0;
610 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
612 struct rt2661_data *data;
615 if (ring->desc != NULL) {
616 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
617 BUS_DMASYNC_POSTWRITE);
618 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
619 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
623 if (ring->desc_dmat != NULL) {
624 bus_dma_tag_destroy(ring->desc_dmat);
625 ring->desc_dmat = NULL;
628 if (ring->data != NULL) {
629 for (i = 0; i < ring->count; i++) {
630 data = &ring->data[i];
632 if (data->m != NULL) {
633 bus_dmamap_sync(ring->data_dmat, data->map,
634 BUS_DMASYNC_POSTWRITE);
635 bus_dmamap_unload(ring->data_dmat, data->map);
640 if (data->map != NULL) {
641 bus_dmamap_destroy(ring->data_dmat, data->map);
646 kfree(ring->data, M_DEVBUF);
650 if (ring->data_dmat != NULL) {
651 bus_dma_tag_destroy(ring->data_dmat);
652 ring->data_dmat = NULL;
657 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring,
660 struct rt2661_rx_desc *desc;
661 struct rt2661_data *data;
666 ring->cur = ring->next = 0;
668 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
669 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1,
670 count * RT2661_RX_DESC_SIZE, 0, &ring->desc_dmat);
672 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
676 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
677 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map);
679 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
683 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
684 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
687 device_printf(sc->sc_dev, "could not load desc DMA map\n");
689 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
694 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF,
698 * Pre-allocate Rx buffers and populate Rx ring.
700 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
701 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0,
704 device_printf(sc->sc_dev, "could not create data DMA tag\n");
708 for (i = 0; i < count; i++) {
709 desc = &sc->rxq.desc[i];
710 data = &sc->rxq.data[i];
712 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
714 device_printf(sc->sc_dev, "could not create DMA map\n");
718 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
719 if (data->m == NULL) {
720 device_printf(sc->sc_dev,
721 "could not allocate rx mbuf\n");
726 error = bus_dmamap_load(ring->data_dmat, data->map,
727 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr,
730 device_printf(sc->sc_dev,
731 "could not load rx buf DMA map");
738 desc->flags = htole32(RT2661_RX_BUSY);
739 desc->physaddr = htole32(physaddr);
742 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
746 fail: rt2661_free_rx_ring(sc, ring);
751 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
755 for (i = 0; i < ring->count; i++)
756 ring->desc[i].flags = htole32(RT2661_RX_BUSY);
758 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
760 ring->cur = ring->next = 0;
764 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
766 struct rt2661_data *data;
769 if (ring->desc != NULL) {
770 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
771 BUS_DMASYNC_POSTWRITE);
772 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
773 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
777 if (ring->desc_dmat != NULL) {
778 bus_dma_tag_destroy(ring->desc_dmat);
779 ring->desc_dmat = NULL;
782 if (ring->data != NULL) {
783 for (i = 0; i < ring->count; i++) {
784 data = &ring->data[i];
786 if (data->m != NULL) {
787 bus_dmamap_sync(ring->data_dmat, data->map,
788 BUS_DMASYNC_POSTREAD);
789 bus_dmamap_unload(ring->data_dmat, data->map);
794 if (data->map != NULL) {
795 bus_dmamap_destroy(ring->data_dmat, data->map);
800 kfree(ring->data, M_DEVBUF);
804 if (ring->data_dmat != NULL) {
805 bus_dma_tag_destroy(ring->data_dmat);
806 ring->data_dmat = NULL;
811 rt2661_media_change(struct ifnet *ifp)
813 struct rt2661_softc *sc = ifp->if_softc;
816 error = ieee80211_media_change(ifp);
817 if (error != ENETRESET)
820 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
826 * This function is called periodically (every 200ms) during scanning to
827 * switch from one channel to another.
830 rt2661_next_scan(void *arg)
832 struct rt2661_softc *sc = arg;
833 struct ieee80211com *ic = &sc->sc_ic;
834 struct ifnet *ifp = &ic->ic_if;
836 lwkt_serialize_enter(ifp->if_serializer);
837 if (ic->ic_state == IEEE80211_S_SCAN)
838 ieee80211_next_scan(ic);
839 lwkt_serialize_exit(ifp->if_serializer);
843 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
845 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
846 enum ieee80211_state ostate;
847 struct ieee80211_node *ni;
851 ostate = ic->ic_state;
852 callout_stop(&sc->scan_ch);
854 if (ostate != nstate)
855 rt2661_led_newstate(sc, nstate);
857 ieee80211_ratectl_newstate(ic, nstate);
860 case IEEE80211_S_INIT:
861 if (ostate == IEEE80211_S_RUN) {
862 /* abort TSF synchronization */
863 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
864 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
868 case IEEE80211_S_SCAN:
869 rt2661_set_chan(sc, ic->ic_curchan);
870 callout_reset(&sc->scan_ch, (sc->dwelltime * hz) / 1000,
871 rt2661_next_scan, sc);
874 case IEEE80211_S_AUTH:
875 case IEEE80211_S_ASSOC:
876 rt2661_set_chan(sc, ic->ic_curchan);
879 case IEEE80211_S_RUN:
880 rt2661_set_chan(sc, ic->ic_curchan);
884 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
885 rt2661_enable_mrr(sc);
886 rt2661_set_txpreamble(sc);
887 rt2661_set_ackrates(sc, &ni->ni_rates);
888 rt2661_set_bssid(sc, ni->ni_bssid);
891 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
892 ic->ic_opmode == IEEE80211_M_IBSS) {
893 if ((error = rt2661_prepare_beacon(sc)) != 0)
897 if (ic->ic_opmode != IEEE80211_M_MONITOR)
898 rt2661_enable_tsf_sync(sc);
902 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg);
906 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
910 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
916 /* clock C once before the first command */
917 RT2661_EEPROM_CTL(sc, 0);
919 RT2661_EEPROM_CTL(sc, RT2661_S);
920 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
921 RT2661_EEPROM_CTL(sc, RT2661_S);
923 /* write start bit (1) */
924 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
925 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
927 /* write READ opcode (10) */
928 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
929 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
930 RT2661_EEPROM_CTL(sc, RT2661_S);
931 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
933 /* write address (A5-A0 or A7-A0) */
934 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
935 for (; n >= 0; n--) {
936 RT2661_EEPROM_CTL(sc, RT2661_S |
937 (((addr >> n) & 1) << RT2661_SHIFT_D));
938 RT2661_EEPROM_CTL(sc, RT2661_S |
939 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
942 RT2661_EEPROM_CTL(sc, RT2661_S);
944 /* read data Q15-Q0 */
946 for (n = 15; n >= 0; n--) {
947 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
948 tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
949 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
950 RT2661_EEPROM_CTL(sc, RT2661_S);
953 RT2661_EEPROM_CTL(sc, 0);
955 /* clear Chip Select and clock C */
956 RT2661_EEPROM_CTL(sc, RT2661_S);
957 RT2661_EEPROM_CTL(sc, 0);
958 RT2661_EEPROM_CTL(sc, RT2661_C);
964 rt2661_tx_intr(struct rt2661_softc *sc)
966 struct ieee80211com *ic = &sc->sc_ic;
967 struct ifnet *ifp = ic->ic_ifp;
968 struct rt2661_tx_ratectl *rctl;
969 uint32_t val, result;
973 struct ieee80211_ratectl_res res;
975 val = RAL_READ(sc, RT2661_STA_CSR4);
976 if (!(val & RT2661_TX_STAT_VALID))
979 /* Gather statistics */
980 result = RT2661_TX_RESULT(val);
981 if (result == RT2661_TX_SUCCESS)
986 /* No rate control */
987 if (RT2661_TX_QID(val) == 0)
990 /* retrieve rate control algorithm context */
991 rctl = STAILQ_FIRST(&sc->tx_ratectl);
995 * This really should not happen. Maybe we should
996 * use assertion here? But why should we rely on
997 * hardware to do the correct things? Even the
998 * reference driver (RT61?) provided by Ralink does
999 * not provide enough clue that this kind of interrupt
1000 * is promised to be generated for each packet. So
1001 * just print a message and keep going ...
1003 if_printf(ifp, "WARNING: no rate control information\n");
1006 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link);
1010 case RT2661_TX_SUCCESS:
1011 retrycnt = RT2661_TX_RETRYCNT(val);
1012 DPRINTFN(10, ("data frame sent successfully after "
1013 "%d retries\n", retrycnt));
1016 case RT2661_TX_RETRY_FAIL:
1017 DPRINTFN(9, ("sending data frame failed (too much "
1023 device_printf(sc->sc_dev,
1024 "sending data frame failed 0x%08x\n", val);
1028 res.rc_res_rateidx = rctl->rateidx;
1029 res.rc_res_tries = retrycnt + 1;
1030 ieee80211_ratectl_tx_complete(rctl->ni, rctl->len, &res, 1,
1031 retrycnt, 0, result != RT2661_TX_SUCCESS);
1033 ieee80211_free_node(rctl->ni);
1035 kfree(rctl, M_RT2661);
1040 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
1042 struct rt2661_tx_desc *desc;
1043 struct rt2661_data *data;
1045 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
1048 desc = &txq->desc[txq->next];
1049 data = &txq->data[txq->next];
1051 if ((le32toh(desc->flags) & RT2661_TX_BUSY) ||
1052 !(le32toh(desc->flags) & RT2661_TX_VALID))
1055 bus_dmamap_sync(txq->data_dmat, data->map,
1056 BUS_DMASYNC_POSTWRITE);
1057 bus_dmamap_unload(txq->data_dmat, data->map);
1061 /* descriptor is no longer valid */
1062 desc->flags &= ~htole32(RT2661_TX_VALID);
1064 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next));
1067 if (++txq->next >= txq->count) /* faster than % count */
1071 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1073 if (txq->queued < txq->count) {
1074 struct ifnet *ifp = &sc->sc_ic.ic_if;
1076 sc->sc_tx_timer = 0;
1077 ifp->if_flags &= ~IFF_OACTIVE;
1083 rt2661_rx_intr(struct rt2661_softc *sc)
1085 struct ieee80211com *ic = &sc->sc_ic;
1086 struct ifnet *ifp = ic->ic_ifp;
1087 struct rt2661_rx_desc *desc;
1088 struct rt2661_data *data;
1089 bus_addr_t physaddr;
1090 struct ieee80211_frame_min *wh;
1091 struct ieee80211_node *ni;
1092 struct mbuf *mnew, *m;
1095 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1096 BUS_DMASYNC_POSTREAD);
1101 desc = &sc->rxq.desc[sc->rxq.cur];
1102 data = &sc->rxq.data[sc->rxq.cur];
1104 if (le32toh(desc->flags) & RT2661_RX_BUSY)
1107 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) ||
1108 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) {
1110 * This should not happen since we did not request
1111 * to receive those frames when we filled TXRX_CSR0.
1113 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n",
1114 le32toh(desc->flags)));
1119 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
1125 * Try to allocate a new mbuf for this ring element and load it
1126 * before processing the current mbuf. If the ring element
1127 * cannot be loaded, drop the received packet and reuse the old
1128 * mbuf. In the unlikely case that the old mbuf can't be
1129 * reloaded either, explicitly panic.
1131 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1137 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1138 BUS_DMASYNC_POSTREAD);
1139 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1141 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1142 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr,
1147 /* try to reload the old mbuf */
1148 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1149 mtod(data->m, void *), MCLBYTES,
1150 rt2661_dma_map_addr, &physaddr, 0);
1152 /* very unlikely that it will fail... */
1153 panic("%s: could not load old rx mbuf",
1154 device_get_name(sc->sc_dev));
1161 * New mbuf successfully loaded, update Rx ring and continue
1166 desc->physaddr = htole32(physaddr);
1169 m->m_pkthdr.rcvif = ifp;
1170 m->m_pkthdr.len = m->m_len =
1171 (le32toh(desc->flags) >> 16) & 0xfff;
1173 rssi = rt2661_get_rssi(sc, desc->rssi);
1175 wh = mtod(m, struct ieee80211_frame_min *);
1176 ni = ieee80211_find_rxnode(ic, wh);
1178 /* Error happened during RSSI conversion. */
1182 if (sc->sc_drvbpf != NULL) {
1183 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap;
1184 uint32_t tsf_lo, tsf_hi;
1186 /* get timestamp (low and high 32 bits) */
1187 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13);
1188 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12);
1191 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1193 tap->wr_rate = rt2661_rxrate(desc);
1194 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
1195 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
1196 tap->wr_antsignal = rssi;
1198 bpf_ptap(sc->sc_drvbpf, m, tap, sc->sc_rxtap_len);
1201 /* send the frame to the 802.11 layer */
1202 ieee80211_input(ic, m, ni, rssi, 0);
1204 /* node is no longer needed */
1205 ieee80211_free_node(ni);
1207 skip: desc->flags |= htole32(RT2661_RX_BUSY);
1209 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur));
1211 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT;
1214 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1215 BUS_DMASYNC_PREWRITE);
1220 rt2661_mcu_beacon_expire(struct rt2661_softc *sc)
1226 rt2661_mcu_wakeup(struct rt2661_softc *sc)
1228 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1230 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1231 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1232 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1234 /* send wakeup command to MCU */
1235 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1239 rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1241 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1242 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1246 rt2661_intr(void *arg)
1248 struct rt2661_softc *sc = arg;
1249 struct ifnet *ifp = &sc->sc_ic.ic_if;
1252 /* disable MAC and MCU interrupts */
1253 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1254 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1256 /* don't re-enable interrupts if we're shutting down */
1257 if (!(ifp->if_flags & IFF_RUNNING))
1260 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR);
1261 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1263 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1264 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1266 if (r1 & RT2661_MGT_DONE)
1267 rt2661_tx_dma_intr(sc, &sc->mgtq);
1269 if (r1 & RT2661_RX_DONE)
1272 if (r1 & RT2661_TX0_DMA_DONE)
1273 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1275 if (r1 & RT2661_TX1_DMA_DONE)
1276 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1278 if (r1 & RT2661_TX2_DMA_DONE)
1279 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1281 if (r1 & RT2661_TX3_DMA_DONE)
1282 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1284 if (r1 & RT2661_TX_DONE)
1287 if (r2 & RT2661_MCU_CMD_DONE)
1288 rt2661_mcu_cmd_intr(sc);
1290 if (r2 & RT2661_MCU_BEACON_EXPIRE)
1291 rt2661_mcu_beacon_expire(sc);
1293 if (r2 & RT2661_MCU_WAKEUP)
1294 rt2661_mcu_wakeup(sc);
1296 /* re-enable MAC and MCU interrupts */
1297 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1298 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1301 /* quickly determine if a given rate is CCK or OFDM */
1302 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
1304 #define RAL_ACK_SIZE (sizeof(struct ieee80211_frame_ack) + IEEE80211_FCS_LEN)
1305 #define RAL_CTS_SIZE (sizeof(struct ieee80211_frame_cts) + IEEE80211_FCS_LEN)
1308 * This function is only used by the Rx radiotap code. It returns the rate at
1309 * which a given frame was received.
1312 rt2661_rxrate(struct rt2661_rx_desc *desc)
1314 if (le32toh(desc->flags) & RT2661_RX_OFDM) {
1315 /* reverse function of rt2661_plcp_signal */
1316 switch (desc->rate & 0xf) {
1317 case 0xb: return 12;
1318 case 0xf: return 18;
1319 case 0xa: return 24;
1320 case 0xe: return 36;
1321 case 0x9: return 48;
1322 case 0xd: return 72;
1323 case 0x8: return 96;
1324 case 0xc: return 108;
1327 if (desc->rate == 10)
1329 if (desc->rate == 20)
1331 if (desc->rate == 55)
1333 if (desc->rate == 110)
1336 return 2; /* should not get there */
1340 rt2661_plcp_signal(int rate)
1343 /* CCK rates (returned values are device-dependent) */
1346 case 11: return 0x2;
1347 case 22: return 0x3;
1349 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1350 case 12: return 0xb;
1351 case 18: return 0xf;
1352 case 24: return 0xa;
1353 case 36: return 0xe;
1354 case 48: return 0x9;
1355 case 72: return 0xd;
1356 case 96: return 0x8;
1357 case 108: return 0xc;
1359 /* unsupported rates (should not get there) */
1360 default: return 0xff;
1365 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1366 uint32_t flags, uint16_t xflags, int len, int rate,
1367 const bus_dma_segment_t *segs, int nsegs, int ac, int ratectl)
1369 struct ieee80211com *ic = &sc->sc_ic;
1370 uint16_t plcp_length;
1373 desc->flags = htole32(flags);
1374 desc->flags |= htole32(len << 16);
1375 desc->flags |= htole32(RT2661_TX_VALID);
1377 desc->xflags = htole16(xflags);
1378 desc->xflags |= htole16(nsegs << 13);
1380 desc->wme = htole16(
1383 RT2661_LOGCWMIN(4) |
1384 RT2661_LOGCWMAX(10));
1387 * Remember whether TX rate control information should be gathered.
1388 * This field is driver private data only. It will be made available
1389 * by the NIC in STA_CSR4 on Tx done interrupts.
1391 desc->qid = ratectl;
1393 /* setup PLCP fields */
1394 desc->plcp_signal = rt2661_plcp_signal(rate);
1395 desc->plcp_service = 4;
1397 len += IEEE80211_CRC_LEN;
1398 if (RAL_RATE_IS_OFDM(rate)) {
1399 desc->flags |= htole32(RT2661_TX_OFDM);
1401 plcp_length = len & 0xfff;
1402 desc->plcp_length_hi = plcp_length >> 6;
1403 desc->plcp_length_lo = plcp_length & 0x3f;
1405 plcp_length = (16 * len + rate - 1) / rate;
1407 remainder = (16 * len) % 22;
1408 if (remainder != 0 && remainder < 7)
1409 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1411 desc->plcp_length_hi = plcp_length >> 8;
1412 desc->plcp_length_lo = plcp_length & 0xff;
1414 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1415 desc->plcp_signal |= 0x08;
1418 /* RT2x61 supports scatter with up to 5 segments */
1419 for (i = 0; i < nsegs; i++) {
1420 desc->addr[i] = htole32(segs[i].ds_addr);
1421 desc->len [i] = htole16(segs[i].ds_len);
1424 desc->flags |= htole32(RT2661_TX_BUSY);
1428 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0,
1429 struct ieee80211_node *ni)
1431 struct ieee80211com *ic = &sc->sc_ic;
1432 struct rt2661_tx_desc *desc;
1433 struct rt2661_data *data;
1434 struct ieee80211_frame *wh;
1435 struct rt2661_dmamap map;
1437 uint32_t flags = 0; /* XXX HWSEQ */
1440 desc = &sc->mgtq.desc[sc->mgtq.cur];
1441 data = &sc->mgtq.data[sc->mgtq.cur];
1443 /* send mgt frames at the lowest available rate */
1444 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
1446 error = bus_dmamap_load_mbuf(sc->mgtq.data_dmat, data->map, m0,
1447 rt2661_dma_map_mbuf, &map, 0);
1449 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1451 ieee80211_free_node(ni);
1456 if (sc->sc_drvbpf != NULL) {
1457 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1460 tap->wt_rate = rate;
1461 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1462 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1464 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len);
1469 wh = mtod(m0, struct ieee80211_frame *);
1471 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1472 flags |= RT2661_TX_NEED_ACK;
1474 dur = ieee80211_txtime(ni, RAL_ACK_SIZE, rate, ic->ic_flags) +
1476 *(uint16_t *)wh->i_dur = htole16(dur);
1478 /* tell hardware to add timestamp in probe responses */
1480 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1481 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1482 flags |= RT2661_TX_TIMESTAMP;
1485 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */,
1486 m0->m_pkthdr.len, rate, map.segs, map.nseg, RT2661_QID_MGT, 0);
1488 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1489 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map,
1490 BUS_DMASYNC_PREWRITE);
1492 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n",
1493 m0->m_pkthdr.len, sc->mgtq.cur, rate));
1497 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT;
1498 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1500 ieee80211_free_node(ni);
1506 * Build a RTS control frame.
1508 static struct mbuf *
1509 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh,
1512 struct ieee80211_frame_rts *rts;
1515 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1517 sc->sc_ic.ic_stats.is_tx_nobuf++;
1518 device_printf(sc->sc_dev, "could not allocate RTS frame\n");
1522 rts = mtod(m, struct ieee80211_frame_rts *);
1524 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL |
1525 IEEE80211_FC0_SUBTYPE_RTS;
1526 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS;
1527 *(uint16_t *)rts->i_dur = htole16(dur);
1528 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1);
1529 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2);
1531 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts);
1537 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0,
1538 struct ieee80211_node *ni, int ac)
1540 struct ieee80211com *ic = &sc->sc_ic;
1541 struct rt2661_tx_ring *txq = &sc->txq[ac];
1542 struct rt2661_tx_desc *desc;
1543 struct rt2661_data *data;
1544 struct rt2661_tx_ratectl *rctl;
1545 struct ieee80211_frame *wh;
1546 struct ieee80211_key *k;
1547 const struct chanAccParams *cap;
1549 struct rt2661_dmamap map;
1552 int error, rate, ackrate, noack = 0, rateidx;
1554 wh = mtod(m0, struct ieee80211_frame *);
1555 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
1556 cap = &ic->ic_wme.wme_chanParams;
1557 noack = cap->cap_wmeParams[ac].wmep_noackPolicy;
1560 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1561 k = ieee80211_crypto_encap(ic, ni, m0);
1567 /* packet header may have moved, reset our local pointer */
1568 wh = mtod(m0, struct ieee80211_frame *);
1571 ieee80211_ratectl_findrate(ni, m0->m_pkthdr.len, &rateidx, 1);
1572 rate = IEEE80211_RS_RATE(&ni->ni_rates, rateidx);
1574 ackrate = ieee80211_ack_rate(ni, rate);
1577 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange
1578 * for directed frames only when the length of the MPDU is greater
1579 * than the length threshold indicated by [...]" ic_rtsthreshold.
1581 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1582 m0->m_pkthdr.len > ic->ic_rtsthreshold) {
1587 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
1589 /* XXX: noack (QoS)? */
1590 dur = ieee80211_txtime(ni, m0->m_pkthdr.len + IEEE80211_FCS_LEN,
1591 rate, ic->ic_flags) +
1592 ieee80211_txtime(ni, RAL_CTS_SIZE, rtsrate, ic->ic_flags)+
1593 ieee80211_txtime(ni, RAL_ACK_SIZE, ackrate, ic->ic_flags)+
1596 m = rt2661_get_rts(sc, wh, dur);
1598 desc = &txq->desc[txq->cur];
1599 data = &txq->data[txq->cur];
1601 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m,
1602 rt2661_dma_map_mbuf, &map, 0);
1604 device_printf(sc->sc_dev,
1605 "could not map mbuf (error %d)\n", error);
1613 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK |
1614 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len,
1615 rtsrate, map.segs, map.nseg, ac, 0);
1617 bus_dmamap_sync(txq->data_dmat, data->map,
1618 BUS_DMASYNC_PREWRITE);
1621 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1624 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the
1625 * asynchronous data frame shall be transmitted after the CTS
1626 * frame and a SIFS period.
1628 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS;
1631 data = &txq->data[txq->cur];
1632 desc = &txq->desc[txq->cur];
1634 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0,
1635 rt2661_dma_map_mbuf, &map, 0);
1636 if (error != 0 && error != EFBIG) {
1637 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1643 mnew = m_defrag(m0, MB_DONTWAIT);
1645 device_printf(sc->sc_dev,
1646 "could not defragment mbuf\n");
1652 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0,
1653 rt2661_dma_map_mbuf, &map, 0);
1655 device_printf(sc->sc_dev,
1656 "could not map mbuf (error %d)\n", error);
1661 /* packet header have moved, reset our local pointer */
1662 wh = mtod(m0, struct ieee80211_frame *);
1665 if (sc->sc_drvbpf != NULL) {
1666 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1669 tap->wt_rate = rate;
1670 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1671 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1673 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len);
1678 rctl = kmalloc(sizeof(*rctl), M_RT2661, M_NOWAIT);
1681 rctl->len = m0->m_pkthdr.len;
1682 rctl->rateidx = rateidx;
1683 STAILQ_INSERT_TAIL(&sc->tx_ratectl, rctl, link);
1686 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1687 flags |= RT2661_TX_NEED_ACK;
1689 dur = ieee80211_txtime(ni, RAL_ACK_SIZE, ackrate, ic->ic_flags)+
1691 *(uint16_t *)wh->i_dur = htole16(dur);
1694 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate,
1695 map.segs, map.nseg, ac, rctl != NULL);
1697 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1698 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1700 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n",
1701 m0->m_pkthdr.len, txq->cur, rate));
1705 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1706 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac);
1709 ieee80211_free_node(ni);
1715 rt2661_start(struct ifnet *ifp)
1717 struct rt2661_softc *sc = ifp->if_softc;
1718 struct ieee80211com *ic = &sc->sc_ic;
1720 struct ether_header *eh;
1721 struct ieee80211_node *ni;
1724 /* prevent management frames from being sent if we're not ready */
1725 if (!(ifp->if_flags & IFF_RUNNING))
1729 IF_POLL(&ic->ic_mgtq, m0);
1731 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) {
1732 ifp->if_flags |= IFF_OACTIVE;
1735 IF_DEQUEUE(&ic->ic_mgtq, m0);
1737 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif;
1738 m0->m_pkthdr.rcvif = NULL;
1740 if (ic->ic_rawbpf != NULL)
1741 bpf_mtap(ic->ic_rawbpf, m0);
1743 if (rt2661_tx_mgt(sc, m0, ni) != 0)
1746 if (ic->ic_state != IEEE80211_S_RUN)
1749 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1753 if (m0->m_len < sizeof (struct ether_header) &&
1754 !(m0 = m_pullup(m0, sizeof (struct ether_header))))
1757 eh = mtod(m0, struct ether_header *);
1758 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1765 /* classify mbuf so we can find which tx ring to use */
1766 if (ieee80211_classify(ic, m0, ni) != 0) {
1768 ieee80211_free_node(ni);
1773 /* no QoS encapsulation for EAPOL frames */
1774 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ?
1775 M_WME_GETAC(m0) : WME_AC_BE;
1777 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
1778 /* there is no place left in this ring */
1779 ifp->if_flags |= IFF_OACTIVE;
1781 ieee80211_free_node(ni);
1787 m0 = ieee80211_encap(ic, m0, ni);
1789 ieee80211_free_node(ni);
1794 if (ic->ic_rawbpf != NULL)
1795 bpf_mtap(ic->ic_rawbpf, m0);
1797 if (rt2661_tx_data(sc, m0, ni, ac) != 0) {
1798 ieee80211_free_node(ni);
1804 sc->sc_tx_timer = 5;
1810 rt2661_watchdog(struct ifnet *ifp)
1812 struct rt2661_softc *sc = ifp->if_softc;
1813 struct ieee80211com *ic = &sc->sc_ic;
1817 if (sc->sc_tx_timer > 0) {
1818 if (--sc->sc_tx_timer == 0) {
1819 device_printf(sc->sc_dev, "device timeout\n");
1827 ieee80211_watchdog(ic);
1831 * This function allows for fast channel switching in monitor mode (used by
1832 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to
1833 * generate a new beacon frame.
1836 rt2661_reset(struct ifnet *ifp)
1838 struct rt2661_softc *sc = ifp->if_softc;
1839 struct ieee80211com *ic = &sc->sc_ic;
1841 if (ic->ic_opmode != IEEE80211_M_MONITOR)
1844 rt2661_set_chan(sc, ic->ic_curchan);
1850 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1852 struct rt2661_softc *sc = ifp->if_softc;
1853 struct ieee80211com *ic = &sc->sc_ic;
1858 if (ifp->if_flags & IFF_UP) {
1859 if (ifp->if_flags & IFF_RUNNING)
1860 rt2661_update_promisc(sc);
1864 if (ifp->if_flags & IFF_RUNNING)
1870 error = ieee80211_ioctl(ic, cmd, data, cr);
1873 if (error == ENETRESET) {
1874 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1875 (IFF_UP | IFF_RUNNING) &&
1876 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL))
1884 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
1889 for (ntries = 0; ntries < 100; ntries++) {
1890 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1894 if (ntries == 100) {
1895 device_printf(sc->sc_dev, "could not write to BBP\n");
1899 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
1900 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
1902 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
1906 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
1911 for (ntries = 0; ntries < 100; ntries++) {
1912 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1916 if (ntries == 100) {
1917 device_printf(sc->sc_dev, "could not read from BBP\n");
1921 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
1922 RAL_WRITE(sc, RT2661_PHY_CSR3, val);
1924 for (ntries = 0; ntries < 100; ntries++) {
1925 val = RAL_READ(sc, RT2661_PHY_CSR3);
1926 if (!(val & RT2661_BBP_BUSY))
1931 device_printf(sc->sc_dev, "could not read from BBP\n");
1936 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
1941 for (ntries = 0; ntries < 100; ntries++) {
1942 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
1946 if (ntries == 100) {
1947 device_printf(sc->sc_dev, "could not write to RF\n");
1951 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
1953 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
1955 /* remember last written value in sc */
1956 sc->rf_regs[reg] = val;
1958 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff));
1962 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1964 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1965 return EIO; /* there is already a command pending */
1967 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1968 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
1970 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1976 rt2661_select_antenna(struct rt2661_softc *sc)
1978 uint8_t bbp4, bbp77;
1981 bbp4 = rt2661_bbp_read(sc, 4);
1982 bbp77 = rt2661_bbp_read(sc, 77);
1986 /* make sure Rx is disabled before switching antenna */
1987 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
1988 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
1990 rt2661_bbp_write(sc, 4, bbp4);
1991 rt2661_bbp_write(sc, 77, bbp77);
1993 /* restore Rx filter */
1994 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1998 * Enable multi-rate retries for frames sent at OFDM rates.
1999 * In 802.11b/g mode, allow fallback to CCK rates.
2002 rt2661_enable_mrr(struct rt2661_softc *sc)
2004 struct ieee80211com *ic = &sc->sc_ic;
2007 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
2009 tmp &= ~RT2661_MRR_CCK_FALLBACK;
2010 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan))
2011 tmp |= RT2661_MRR_CCK_FALLBACK;
2012 tmp |= RT2661_MRR_ENABLED;
2013 tmp |= RT2661_SRETRY_LIMIT(7) | RT2661_LRETRY_LIMIT(4);
2015 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2019 rt2661_set_txpreamble(struct rt2661_softc *sc)
2023 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
2025 tmp &= ~RT2661_SHORT_PREAMBLE;
2026 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
2027 tmp |= RT2661_SHORT_PREAMBLE;
2029 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2033 rt2661_set_ackrates(struct rt2661_softc *sc, const struct ieee80211_rateset *rs)
2035 #define RV(r) ((r) & IEEE80211_RATE_VAL)
2036 struct ieee80211com *ic = &sc->sc_ic;
2041 for (i = 0; i < rs->rs_nrates; i++) {
2042 rate = rs->rs_rates[i];
2044 if (!(rate & IEEE80211_RATE_BASIC))
2048 * Find h/w rate index. We know it exists because the rate
2049 * set has already been negotiated.
2051 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++)
2057 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) &&
2058 ic->ic_curmode != IEEE80211_MODE_11B &&
2059 ieee80211_iserp_rateset(ic, rs)) {
2061 * Always set following rates as ACK rates to conform
2062 * IEEE Std 802.11g-2003 clause 9.6
2071 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
2073 DPRINTF(("Setting ack rate mask to 0x%x\n", mask));
2078 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
2082 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
2084 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
2087 /* update all BBP registers that depend on the band */
2088 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
2089 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
2090 if (IEEE80211_IS_CHAN_5GHZ(c)) {
2091 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
2092 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
2094 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2095 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2096 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
2099 rt2661_bbp_write(sc, 17, bbp17);
2100 rt2661_bbp_write(sc, 96, bbp96);
2101 rt2661_bbp_write(sc, 104, bbp104);
2103 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2104 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2105 rt2661_bbp_write(sc, 75, 0x80);
2106 rt2661_bbp_write(sc, 86, 0x80);
2107 rt2661_bbp_write(sc, 88, 0x80);
2110 rt2661_bbp_write(sc, 35, bbp35);
2111 rt2661_bbp_write(sc, 97, bbp97);
2112 rt2661_bbp_write(sc, 98, bbp98);
2114 tmp = RAL_READ(sc, RT2661_PHY_CSR0);
2115 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
2116 if (IEEE80211_IS_CHAN_2GHZ(c))
2117 tmp |= RT2661_PA_PE_2GHZ;
2119 tmp |= RT2661_PA_PE_5GHZ;
2120 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
2124 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
2126 struct ieee80211com *ic = &sc->sc_ic;
2127 const struct rfprog *rfprog;
2128 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
2132 chan = ieee80211_chan2ieee(ic, c);
2133 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
2136 /* select the appropriate RF settings based on what EEPROM says */
2137 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
2139 /* find the settings for this channel (we know it exists) */
2140 for (i = 0; rfprog[i].chan != chan; i++);
2142 power = sc->txpow[i];
2146 } else if (power > 31) {
2147 bbp94 += power - 31;
2152 * If we are switching from the 2GHz band to the 5GHz band or
2153 * vice-versa, BBP registers need to be reprogrammed.
2155 if (c->ic_flags != sc->sc_curchan->ic_flags) {
2156 rt2661_select_band(sc, c);
2157 rt2661_select_antenna(sc);
2161 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2162 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2163 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2164 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2168 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2169 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2170 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
2171 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2175 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2176 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2177 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2178 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2180 /* enable smart mode for MIMO-capable RFs */
2181 bbp3 = rt2661_bbp_read(sc, 3);
2183 bbp3 &= ~RT2661_SMART_MODE;
2184 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
2185 bbp3 |= RT2661_SMART_MODE;
2187 rt2661_bbp_write(sc, 3, bbp3);
2189 if (bbp94 != RT2661_BBPR94_DEFAULT)
2190 rt2661_bbp_write(sc, 94, bbp94);
2192 /* 5GHz radio needs a 1ms delay here */
2193 if (IEEE80211_IS_CHAN_5GHZ(c))
2196 sc->sc_sifs = IEEE80211_IS_CHAN_5GHZ(c) ? IEEE80211_DUR_OFDM_SIFS
2197 : IEEE80211_DUR_SIFS;
2201 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
2205 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
2206 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
2208 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
2209 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
2213 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
2217 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
2218 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
2220 tmp = addr[4] | addr[5] << 8;
2221 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2225 rt2661_update_promisc(struct rt2661_softc *sc)
2227 struct ifnet *ifp = sc->sc_ic.ic_ifp;
2230 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2232 tmp &= ~RT2661_DROP_NOT_TO_ME;
2233 if (!(ifp->if_flags & IFF_PROMISC))
2234 tmp |= RT2661_DROP_NOT_TO_ME;
2236 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2238 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ?
2239 "entering" : "leaving"));
2243 * Update QoS (802.11e) settings for each h/w Tx ring.
2246 rt2661_wme_update(struct ieee80211com *ic)
2248 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
2249 const struct wmeParams *wmep;
2251 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
2253 /* XXX: not sure about shifts. */
2254 /* XXX: the reference driver plays with AC_VI settings too. */
2257 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2258 wmep[WME_AC_BE].wmep_txopLimit << 16 |
2259 wmep[WME_AC_BK].wmep_txopLimit);
2260 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2261 wmep[WME_AC_VI].wmep_txopLimit << 16 |
2262 wmep[WME_AC_VO].wmep_txopLimit);
2265 RAL_WRITE(sc, RT2661_CWMIN_CSR,
2266 wmep[WME_AC_BE].wmep_logcwmin << 12 |
2267 wmep[WME_AC_BK].wmep_logcwmin << 8 |
2268 wmep[WME_AC_VI].wmep_logcwmin << 4 |
2269 wmep[WME_AC_VO].wmep_logcwmin);
2272 RAL_WRITE(sc, RT2661_CWMAX_CSR,
2273 wmep[WME_AC_BE].wmep_logcwmax << 12 |
2274 wmep[WME_AC_BK].wmep_logcwmax << 8 |
2275 wmep[WME_AC_VI].wmep_logcwmax << 4 |
2276 wmep[WME_AC_VO].wmep_logcwmax);
2279 RAL_WRITE(sc, RT2661_AIFSN_CSR,
2280 wmep[WME_AC_BE].wmep_aifsn << 12 |
2281 wmep[WME_AC_BK].wmep_aifsn << 8 |
2282 wmep[WME_AC_VI].wmep_aifsn << 4 |
2283 wmep[WME_AC_VO].wmep_aifsn);
2289 rt2661_update_slot(struct ifnet *ifp)
2291 struct rt2661_softc *sc = ifp->if_softc;
2292 struct ieee80211com *ic = &sc->sc_ic;
2296 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
2298 tmp = RAL_READ(sc, RT2661_MAC_CSR9);
2299 tmp = (tmp & ~0xff) | slottime;
2300 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2304 rt2661_get_rf(int rev)
2307 case RT2661_RF_5225: return "RT5225";
2308 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
2309 case RT2661_RF_2527: return "RT2527";
2310 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
2311 default: return "unknown";
2316 rt2661_read_eeprom(struct rt2661_softc *sc)
2318 struct ieee80211com *ic = &sc->sc_ic;
2322 /* read MAC address */
2323 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
2324 ic->ic_myaddr[0] = val & 0xff;
2325 ic->ic_myaddr[1] = val >> 8;
2327 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
2328 ic->ic_myaddr[2] = val & 0xff;
2329 ic->ic_myaddr[3] = val >> 8;
2331 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
2332 ic->ic_myaddr[4] = val & 0xff;
2333 ic->ic_myaddr[5] = val >> 8;
2335 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
2336 /* XXX: test if different from 0xffff? */
2337 sc->rf_rev = (val >> 11) & 0x1f;
2338 sc->hw_radio = (val >> 10) & 0x1;
2339 sc->rx_ant = (val >> 4) & 0x3;
2340 sc->tx_ant = (val >> 2) & 0x3;
2341 sc->nb_ant = val & 0x3;
2343 DPRINTF(("RF revision=%d\n", sc->rf_rev));
2345 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
2346 sc->ext_5ghz_lna = (val >> 6) & 0x1;
2347 sc->ext_2ghz_lna = (val >> 4) & 0x1;
2349 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
2350 sc->ext_2ghz_lna, sc->ext_5ghz_lna));
2352 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
2353 if ((val & 0xff) != 0xff)
2354 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
2356 /* Only [-10, 10] is valid */
2357 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10)
2358 sc->rssi_2ghz_corr = 0;
2360 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
2361 if ((val & 0xff) != 0xff)
2362 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
2364 /* Only [-10, 10] is valid */
2365 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10)
2366 sc->rssi_5ghz_corr = 0;
2368 /* adjust RSSI correction for external low-noise amplifier */
2369 if (sc->ext_2ghz_lna)
2370 sc->rssi_2ghz_corr -= 14;
2371 if (sc->ext_5ghz_lna)
2372 sc->rssi_5ghz_corr -= 14;
2374 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
2375 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr));
2377 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
2378 if ((val >> 8) != 0xff)
2379 sc->rfprog = (val >> 8) & 0x3;
2380 if ((val & 0xff) != 0xff)
2381 sc->rffreq = val & 0xff;
2383 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq));
2385 /* read Tx power for all a/b/g channels */
2386 for (i = 0; i < 19; i++) {
2387 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
2388 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
2389 DPRINTF(("Channel=%d Tx power=%d\n",
2390 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]));
2391 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
2392 DPRINTF(("Channel=%d Tx power=%d\n",
2393 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]));
2396 /* read vendor-specific BBP values */
2397 for (i = 0; i < 16; i++) {
2398 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
2399 if (val == 0 || val == 0xffff)
2400 continue; /* skip invalid entries */
2401 sc->bbp_prom[i].reg = val >> 8;
2402 sc->bbp_prom[i].val = val & 0xff;
2403 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,
2404 sc->bbp_prom[i].val));
2407 val = rt2661_eeprom_read(sc, RT2661_EEPROM_LED_OFFSET);
2408 DPRINTF(("LED %02x\n", val));
2409 if (val == 0xffff) {
2410 sc->mcu_led = RT2661_MCU_LED_DEFAULT;
2412 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
2414 for (i = 0; i < N(led_ee2mcu); ++i) {
2415 if (val & led_ee2mcu[i].ee_bit)
2416 sc->mcu_led |= led_ee2mcu[i].mcu_bit;
2421 sc->mcu_led |= ((val >> RT2661_EE_LED_MODE_SHIFT) &
2422 RT2661_EE_LED_MODE_MASK);
2427 rt2661_bbp_init(struct rt2661_softc *sc)
2429 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2433 /* wait for BBP to be ready */
2434 for (ntries = 0; ntries < 100; ntries++) {
2435 val = rt2661_bbp_read(sc, 0);
2436 if (val != 0 && val != 0xff)
2440 if (ntries == 100) {
2441 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2445 /* initialize BBP registers to default values */
2446 for (i = 0; i < N(rt2661_def_bbp); i++) {
2447 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2448 rt2661_def_bbp[i].val);
2451 /* write vendor-specific BBP values (from EEPROM) */
2452 for (i = 0; i < 16; i++) {
2453 if (sc->bbp_prom[i].reg == 0)
2455 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2463 rt2661_init(void *priv)
2465 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2466 struct rt2661_softc *sc = priv;
2467 struct ieee80211com *ic = &sc->sc_ic;
2468 struct ifnet *ifp = ic->ic_ifp;
2469 uint32_t tmp, sta[3];
2474 /* initialize Tx rings */
2475 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2476 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2477 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2478 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2480 /* initialize Mgt ring */
2481 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2483 /* initialize Rx ring */
2484 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2486 /* initialize Tx rings sizes */
2487 RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2488 RT2661_TX_RING_COUNT << 24 |
2489 RT2661_TX_RING_COUNT << 16 |
2490 RT2661_TX_RING_COUNT << 8 |
2491 RT2661_TX_RING_COUNT);
2493 RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2494 RT2661_TX_DESC_WSIZE << 16 |
2495 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */
2496 RT2661_MGT_RING_COUNT);
2498 /* initialize Rx rings */
2499 RAL_WRITE(sc, RT2661_RX_RING_CSR,
2500 RT2661_RX_DESC_BACK << 16 |
2501 RT2661_RX_DESC_WSIZE << 8 |
2502 RT2661_RX_RING_COUNT);
2504 /* XXX: some magic here */
2505 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2507 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2508 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2510 /* load base address of Rx ring */
2511 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2513 /* initialize MAC registers to default values */
2514 for (i = 0; i < N(rt2661_def_mac); i++)
2515 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2517 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
2518 rt2661_set_macaddr(sc, ic->ic_myaddr);
2520 /* set host ready */
2521 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2522 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2524 /* wait for BBP/RF to wakeup */
2525 for (ntries = 0; ntries < 1000; ntries++) {
2526 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8)
2530 if (ntries == 1000) {
2531 kprintf("timeout waiting for BBP/RF to wakeup\n");
2536 if (rt2661_bbp_init(sc) != 0) {
2541 /* select default channel */
2542 sc->sc_curchan = ic->ic_curchan;
2543 rt2661_select_band(sc, sc->sc_curchan);
2544 rt2661_select_antenna(sc);
2545 rt2661_set_chan(sc, sc->sc_curchan);
2547 /* update Rx filter */
2548 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2550 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2551 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2552 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2554 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
2555 tmp |= RT2661_DROP_TODS;
2556 if (!(ifp->if_flags & IFF_PROMISC))
2557 tmp |= RT2661_DROP_NOT_TO_ME;
2560 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2562 /* clear STA registers */
2563 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta));
2565 /* initialize ASIC */
2566 RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2568 /* clear any pending interrupt */
2569 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2571 /* enable interrupts */
2572 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2573 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2576 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2578 ifp->if_flags &= ~IFF_OACTIVE;
2579 ifp->if_flags |= IFF_RUNNING;
2581 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2582 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
2583 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2585 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2590 rt2661_stop(void *priv)
2592 struct rt2661_softc *sc = priv;
2593 struct ieee80211com *ic = &sc->sc_ic;
2594 struct ifnet *ifp = ic->ic_ifp;
2595 struct rt2661_tx_ratectl *rctl;
2598 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2600 sc->sc_tx_timer = 0;
2602 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2604 /* abort Tx (for all 5 Tx rings) */
2605 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2607 /* disable Rx (value remains after reset!) */
2608 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2609 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2612 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2613 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2615 /* disable interrupts */
2616 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff);
2617 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2619 /* clear any pending interrupt */
2620 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2621 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2623 while ((rctl = STAILQ_FIRST(&sc->tx_ratectl)) != NULL) {
2624 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link);
2625 ieee80211_free_node(rctl->ni);
2627 kfree(rctl, M_RT2661);
2630 /* reset Tx and Rx rings */
2631 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2632 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2633 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2634 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2635 rt2661_reset_tx_ring(sc, &sc->mgtq);
2636 rt2661_reset_rx_ring(sc, &sc->rxq);
2640 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size)
2645 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2647 /* cancel any pending Host to MCU command */
2648 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2649 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2650 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2652 /* write 8051's microcode */
2653 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2654 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size);
2655 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2657 /* kick 8051's ass */
2658 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2660 /* wait for 8051 to initialize */
2661 for (ntries = 0; ntries < 500; ntries++) {
2662 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
2666 if (ntries == 500) {
2667 kprintf("timeout waiting for MCU to initialize\n");
2675 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
2676 * false CCA count. This function is called periodically (every seconds) when
2677 * in the RUN state. Values taken from the reference driver.
2680 rt2661_rx_tune(struct rt2661_softc *sc)
2687 * Tuning range depends on operating band and on the presence of an
2688 * external low-noise amplifier.
2691 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
2693 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
2694 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
2698 /* retrieve false CCA count since last call (clear on read) */
2699 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff;
2703 } else if (dbm >= -58) {
2705 } else if (dbm >= -66) {
2707 } else if (dbm >= -74) {
2710 /* RSSI < -74dBm, tune using false CCA count */
2712 bbp17 = sc->bbp17; /* current value */
2714 hi -= 2 * (-74 - dbm);
2721 } else if (cca > 512) {
2724 } else if (cca < 100) {
2730 if (bbp17 != sc->bbp17) {
2731 rt2661_bbp_write(sc, 17, bbp17);
2737 * Enter/Leave radar detection mode.
2738 * This is for 802.11h additional regulatory domains.
2741 rt2661_radar_start(struct rt2661_softc *sc)
2746 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2747 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2749 rt2661_bbp_write(sc, 82, 0x20);
2750 rt2661_bbp_write(sc, 83, 0x00);
2751 rt2661_bbp_write(sc, 84, 0x40);
2753 /* save current BBP registers values */
2754 sc->bbp18 = rt2661_bbp_read(sc, 18);
2755 sc->bbp21 = rt2661_bbp_read(sc, 21);
2756 sc->bbp22 = rt2661_bbp_read(sc, 22);
2757 sc->bbp16 = rt2661_bbp_read(sc, 16);
2758 sc->bbp17 = rt2661_bbp_read(sc, 17);
2759 sc->bbp64 = rt2661_bbp_read(sc, 64);
2761 rt2661_bbp_write(sc, 18, 0xff);
2762 rt2661_bbp_write(sc, 21, 0x3f);
2763 rt2661_bbp_write(sc, 22, 0x3f);
2764 rt2661_bbp_write(sc, 16, 0xbd);
2765 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34);
2766 rt2661_bbp_write(sc, 64, 0x21);
2768 /* restore Rx filter */
2769 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2773 rt2661_radar_stop(struct rt2661_softc *sc)
2777 /* read radar detection result */
2778 bbp66 = rt2661_bbp_read(sc, 66);
2780 /* restore BBP registers values */
2781 rt2661_bbp_write(sc, 16, sc->bbp16);
2782 rt2661_bbp_write(sc, 17, sc->bbp17);
2783 rt2661_bbp_write(sc, 18, sc->bbp18);
2784 rt2661_bbp_write(sc, 21, sc->bbp21);
2785 rt2661_bbp_write(sc, 22, sc->bbp22);
2786 rt2661_bbp_write(sc, 64, sc->bbp64);
2793 rt2661_prepare_beacon(struct rt2661_softc *sc)
2795 struct ieee80211com *ic = &sc->sc_ic;
2796 struct ieee80211_beacon_offsets bo;
2797 struct rt2661_tx_desc desc;
2801 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo);
2803 device_printf(sc->sc_dev, "could not allocate beacon frame\n");
2807 /* send beacons at the lowest available rate */
2808 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2;
2810 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ,
2811 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT, 0);
2813 /* copy the first 24 bytes of Tx descriptor into NIC memory */
2814 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24);
2816 /* copy beacon header and payload into NIC memory */
2817 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24,
2818 mtod(m0, uint8_t *), m0->m_pkthdr.len);
2825 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
2826 * and HostAP operating modes.
2829 rt2661_enable_tsf_sync(struct rt2661_softc *sc)
2831 struct ieee80211com *ic = &sc->sc_ic;
2834 if (ic->ic_opmode != IEEE80211_M_STA) {
2836 * Change default 16ms TBTT adjustment to 8ms.
2837 * Must be done before enabling beacon generation.
2839 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2842 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
2844 /* set beacon interval (in 1/16ms unit) */
2845 tmp |= ic->ic_bss->ni_intval * 16;
2847 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
2848 if (ic->ic_opmode == IEEE80211_M_STA)
2849 tmp |= RT2661_TSF_MODE(1);
2851 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
2853 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2857 * Retrieve the "Received Signal Strength Indicator" from the raw values
2858 * contained in Rx descriptors. The computation depends on which band the
2859 * frame was received. Correction values taken from the reference driver.
2862 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
2866 lna = (raw >> 5) & 0x3;
2873 * NB: Since RSSI is relative to noise floor, -1 is
2874 * adequate for caller to know error happened.
2879 rssi = (2 * agc) - RT2661_NOISE_FLOOR;
2881 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
2882 rssi += sc->rssi_2ghz_corr;
2891 rssi += sc->rssi_5ghz_corr;
2904 rt2661_dma_map_mbuf(void *arg, bus_dma_segment_t *seg, int nseg,
2905 bus_size_t map_size __unused, int error)
2907 struct rt2661_dmamap *map = arg;
2912 KASSERT(nseg <= RT2661_MAX_SCATTER, ("too many DMA segments"));
2914 bcopy(seg, map->segs, nseg * sizeof(bus_dma_segment_t));
2919 rt2661_led_newstate(struct rt2661_softc *sc, enum ieee80211_state nstate)
2921 struct ieee80211com *ic = &sc->sc_ic;
2923 uint32_t mail = sc->mcu_led;
2925 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) {
2926 DPRINTF(("%s failed\n", __func__));
2931 case IEEE80211_S_INIT:
2932 mail &= ~(RT2661_MCU_LED_LINKA | RT2661_MCU_LED_LINKG |
2936 if (ic->ic_curchan == NULL)
2939 on = RT2661_MCU_LED_LINKG;
2940 off = RT2661_MCU_LED_LINKA;
2941 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
2942 on = RT2661_MCU_LED_LINKA;
2943 off = RT2661_MCU_LED_LINKG;
2946 mail |= RT2661_MCU_LED_RF | on;
2951 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
2952 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | mail);
2953 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | RT2661_MCU_SET_LED);