2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/i386/isa/if_le.c,v 1.56.2.4 2002/06/05 23:24:10 paul Exp $
25 * $DragonFly: src/sys/dev/netif/le/if_le.c,v 1.18 2005/02/21 02:33:42 joerg Exp $
29 * DEC EtherWORKS 2 Ethernet Controllers
30 * DEC EtherWORKS 3 Ethernet Controllers
32 * Written by Matt Thomas
33 * BPF support code stolen directly from if_ec.c
35 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
36 * DE2002, DE203, DE204, DE205, and DE422 cards.
43 #include <sys/param.h>
44 #include <sys/systm.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/malloc.h>
50 #include <sys/linker_set.h>
51 #include <sys/module.h>
53 #include <net/ethernet.h>
55 #include <net/if_types.h>
56 #include <net/if_dl.h>
58 #include <netinet/in.h>
59 #include <netinet/if_ether.h>
61 #include <bus/isa/i386/isa_device.h>
62 #include <i386/isa/icu.h>
69 typedef u_short le_mcbits_t;
70 #define LE_MC_NBPW_LOG2 4
71 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
76 int (*bd_probe)(struct le_softc *sc, const struct le_board *bd, int *msize);
79 #if !defined(LE_NOLEMAC)
81 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
83 * Start of DEC EtherWORKS III (LEMAC) dependent structures
86 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
88 DECLARE_DUMMY_MODULE(if_le);
90 static int lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
92 struct le_lemac_info {
93 u_int lemac__lastpage; /* last 2K page */
94 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
95 u_int lemac__membase; /* Physical address of start of RAM */
96 u_int lemac__txctl; /* Transmit Control Byte */
97 u_int lemac__txmax; /* Maximum # of outstanding transmits */
98 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
99 /* local copy of multicast table */
100 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
101 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
102 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
103 #define lemac_memmode le_un.un_lemac.lemac__memmode
104 #define lemac_membase le_un.un_lemac.lemac__membase
105 #define lemac_txctl le_un.un_lemac.lemac__txctl
106 #define lemac_txmax le_un.un_lemac.lemac__txmax
107 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
108 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
109 #define lemac_prodname le_un.un_lemac.lemac__prodname
111 #endif /* !defined(LE_NOLEMAC) */
113 #if !defined(LE_NOLANCE)
115 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
117 * Start of DEC EtherWORKS II (LANCE) dependent structures
121 #include <i386/isa/ic/am7990.h>
127 static int depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
129 typedef struct lance_descinfo lance_descinfo_t;
130 typedef struct lance_ring lance_ring_t;
132 typedef unsigned lance_addr_t;
134 struct lance_descinfo {
135 caddr_t di_addr; /* address of descriptor */
136 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
137 unsigned di_buflen; /* size of buffer owned by descriptor */
138 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
142 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
143 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
144 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
145 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
146 unsigned ri_max; /* Size of Ring - 1 */
147 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
148 lance_addr_t ri_heap; /* Start of RAM for this ring */
149 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
150 lance_addr_t ri_outptr; /* Pointer to first output byte */
151 unsigned ri_outsize; /* Space remaining for output */
154 struct le_lance_info {
155 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
156 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
157 unsigned lance__csr3; /* Copy of CSR3 */
158 unsigned lance__rap; /* IO Port Offset of RAP */
159 unsigned lance__rdp; /* IO Port Offset of RDP */
160 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
161 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
162 unsigned lance__rxbufsize; /* Size of a receive buffer */
163 ln_initb_t lance__initb; /* local copy of LANCE initblock */
164 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
165 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
166 lance_ring_t lance__rxinfo; /* Receive ring information */
167 lance_ring_t lance__txinfo; /* Transmit ring information */
168 #define lance_csr1 le_un.un_lance.lance__csr1
169 #define lance_csr2 le_un.un_lance.lance__csr2
170 #define lance_csr3 le_un.un_lance.lance__csr3
171 #define lance_rap le_un.un_lance.lance__rap
172 #define lance_rdp le_un.un_lance.lance__rdp
173 #define lance_ramoffset le_un.un_lance.lance__ramoffset
174 #define lance_ramsize le_un.un_lance.lance__ramsize
175 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
176 #define lance_initb le_un.un_lance.lance__initb
177 #define lance_raminitb le_un.un_lance.lance__raminitb
178 #define lance_ramdesc le_un.un_lance.lance__ramdesc
179 #define lance_rxinfo le_un.un_lance.lance__rxinfo
180 #define lance_txinfo le_un.un_lance.lance__txinfo
182 #endif /* !defined(LE_NOLANCE) */
185 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
187 * Start of Common Code
191 static void (*le_intrvec[NLE])(struct le_softc *sc);
194 * Ethernet status, per interface.
197 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
198 void (*if_init) (void *);/* Interface init routine */
199 void (*if_reset) (struct le_softc*);/* Interface reset routine */
200 caddr_t le_membase; /* Starting memory address (virtual) */
201 unsigned le_iobase; /* Starting I/O base address */
202 unsigned le_irq; /* Interrupt Request Value */
203 unsigned le_flags; /* local copy of if_flags */
204 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
205 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
206 le_mcbits_t *le_mctbl; /* pointer to multicast table */
207 const char *le_prodname; /* product name DE20x-xx */
208 u_char le_hwaddr[6]; /* local copy of hwaddr */
210 #if !defined(LE_NOLEMAC)
211 struct le_lemac_info un_lemac; /* LEMAC specific information */
213 #if !defined(LE_NOLANCE)
214 struct le_lance_info un_lance; /* Am7990 specific information */
218 #define le_if le_ac.ac_if
221 static int le_probe(struct isa_device *dvp);
222 static int le_attach(struct isa_device *dvp);
223 static ointhand2_t le_intr;
224 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
226 static void le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
227 size_t len2, caddr_t seg2);
228 static void le_multi_filter(struct le_softc *sc);
229 static void le_multi_op(struct le_softc *sc, const u_char *mca, int oper_flg);
230 static int le_read_macaddr(struct le_softc *sc, int ioreg, int skippat);
232 #define LE_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
234 static struct le_softc le_softc[NLE];
236 static const struct le_board le_boards[] = {
237 #if !defined(LE_NOLEMAC)
238 { lemac_probe }, /* DE20[345] */
240 #if !defined(LE_NOLANCE)
241 { depca_probe }, /* DE{20[012],422} */
243 { NULL } /* Must Be Last! */
247 * This tells the autoconf code how to set us up.
249 struct isa_driver ledriver = {
250 le_probe, le_attach, "le",
253 static unsigned le_intrs[NLE];
255 #define LE_ADDREQUAL(a1, a2) \
256 (((u_short *)a1)[0] == ((u_short *)a2)[0] \
257 || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
258 || ((u_short *)a1)[2] == ((u_short *)a2)[2])
259 #define LE_ADDRBRDCST(a1) \
260 (((u_short *)a1)[0] == 0xFFFFU \
261 || ((u_short *)a1)[1] == 0xFFFFU \
262 || ((u_short *)a1)[2] == 0xFFFFU)
264 #define LE_INL(sc, reg) \
266 __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
269 #define LE_OUTL(sc, reg, data) \
270 ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
272 #define LE_INW(sc, reg) \
274 __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
278 #define LE_OUTW(sc, reg, data) \
279 ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
281 #define LE_INB(sc, reg) \
283 __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
287 #define LE_OUTB(sc, reg, data) \
288 ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
290 #define MEMCPY(to, from, len) bcopy(from, to, len)
291 #define MEMSET(where, what, howmuch) bzero(where, howmuch)
292 #define MEMCMP(l, r, len) bcmp(l, r, len)
295 le_probe(struct isa_device *dvp)
297 struct le_softc *sc = &le_softc[dvp->id_unit];
298 const struct le_board *bd;
301 if (dvp->id_unit >= NLE) {
302 printf("%s%d not configured -- too many devices\n",
303 ledriver.name, dvp->id_unit);
307 sc->le_iobase = dvp->id_iobase;
308 sc->le_membase = (u_char *) dvp->id_maddr;
309 sc->le_irq = dvp->id_irq;
310 if_initname(&(sc->le_if), ledriver.name, dvp->id_unit);
313 * Find and Initialize board..
316 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
318 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
319 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
328 le_attach(struct isa_device *dvp)
330 struct le_softc *sc = &le_softc[dvp->id_unit];
331 struct ifnet *ifp = &sc->le_if;
333 dvp->id_ointr = le_intr;
335 ifp->if_mtu = ETHERMTU;
337 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
338 ifp->if_ioctl = le_ioctl;
339 ifp->if_type = IFT_ETHER;
342 ifp->if_init = sc->if_init;
344 ether_ifattach(ifp, sc->le_ac.ac_enaddr);
355 (*le_intrvec[unit])(&le_softc[unit]);
363 le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
364 size_t len1, caddr_t seg2)
366 struct ether_header eh;
369 if (total_len - sizeof(eh) > ETHERMTU
370 || total_len - sizeof(eh) < ETHERMIN) {
371 sc->le_if.if_ierrors++;
374 MEMCPY(&eh, seg1, sizeof(eh));
376 seg1 += sizeof(eh); total_len -= sizeof(eh); len1 -= sizeof(eh);
378 MGETHDR(m, MB_DONTWAIT, MT_DATA);
380 sc->le_if.if_ierrors++;
383 m->m_pkthdr.len = total_len;
384 m->m_pkthdr.rcvif = &sc->le_if;
385 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
386 MCLGET(m, MB_DONTWAIT);
387 if ((m->m_flags & M_EXT) == 0) {
389 sc->le_if.if_ierrors++;
392 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
393 MGET(m->m_next, MB_DONTWAIT, MT_DATA);
394 if (m->m_next == NULL) {
396 sc->le_if.if_ierrors++;
399 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
400 len1 = total_len = MHLEN - LE_XTRA;
401 MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
402 } else if (total_len + LE_XTRA > MHLEN) {
403 panic("le_input: pkt of unknown length");
405 m->m_data += LE_XTRA;
406 m->m_len = total_len;
407 MEMCPY(mtod(m, caddr_t), seg1, len1);
409 MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
410 ether_input(&sc->le_if, &eh, m);
414 le_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
416 struct le_softc *sc = ifp->if_softc;
419 if ((sc->le_flags & IFF_UP) == 0)
428 error = ether_ioctl(ifp, cmd, data);
439 * Update multicast listeners
455 * This is the standard method of reading the DEC Address ROMS.
456 * I don't understand it but it does work.
459 le_read_macaddr(struct le_softc *sc, int ioreg, int skippat)
461 int cksum, rom_cksum;
464 int idx, idx2, found, octet;
465 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
468 for (idx = 0; idx < 32; idx++) {
469 octet = LE_INB(sc, ioreg);
471 if (octet == testpat[idx2]) {
472 if (++idx2 == sizeof testpat) {
486 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
487 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
489 cksum = *(u_short *) &sc->le_hwaddr[0];
491 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
492 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
494 if (cksum > 65535) cksum -= 65535;
495 cksum += *(u_short *) &sc->le_hwaddr[2];
496 if (cksum > 65535) cksum -= 65535;
498 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
499 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
501 if (cksum > 65535) cksum -= 65535;
502 cksum += *(u_short *) &sc->le_hwaddr[4];
503 if (cksum >= 65535) cksum -= 65535;
505 rom_cksum = LE_INB(sc, ioreg);
506 rom_cksum |= LE_INB(sc, ioreg) << 8;
508 if (cksum != rom_cksum)
514 le_multi_filter(struct le_softc *sc)
516 struct ifnet *ifp = &sc->le_ac.ac_if;
517 struct ifmultiaddr *ifma;
519 MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
521 if (sc->le_if.if_flags & IFF_ALLMULTI) {
522 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
525 sc->le_flags &= ~IFF_MULTICAST;
526 /* if (interface has had an address assigned) { */
527 le_multi_op(sc, ifp->if_broadcastaddr, TRUE);
528 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
531 sc->le_flags |= IFF_MULTICAST;
533 for (ifma = ifp->if_multiaddrs.lh_first; ifma;
534 ifma = ifma->ifma_link.le_next) {
535 if (ifma->ifma_addr->sa_family != AF_LINK)
538 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
539 sc->le_flags &= ~LE_BRDCSTONLY;
544 le_multi_op(struct le_softc *sc, const u_char *mca, int enable)
546 u_int idx, bit, data, crc = 0xFFFFFFFFUL;
548 for (idx = 0; idx < 6; idx++)
549 for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
550 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
552 * The following two line convert the N bit index into a longword index
553 * and a longword mask.
555 crc &= sc->le_mcmask;
556 bit = 1 << (crc & (LE_MC_NBPW -1));
557 idx = crc >> (LE_MC_NBPW_LOG2);
560 * Set or clear hash filter bit in our table.
563 sc->le_mctbl[idx] |= bit; /* Set Bit */
565 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
569 #if !defined(LE_NOLEMAC)
571 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
573 * Start of DEC EtherWORKS III (LEMAC) dependent code
577 #define LEMAC_INTR_ENABLE(sc) \
578 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
580 #define LEMAC_INTR_DISABLE(sc) \
581 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
583 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
584 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
585 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
587 static void lemac_init(void *xsc);
588 static void lemac_start(struct ifnet *ifp);
589 static void lemac_reset(struct le_softc *sc);
590 static void lemac_intr(struct le_softc *sc);
591 static void lemac_rne_intr(struct le_softc *sc);
592 static void lemac_tne_intr(struct le_softc *sc);
593 static void lemac_txd_intr(struct le_softc *sc, unsigned cs_value);
594 static void lemac_rxd_intr(struct le_softc *sc, unsigned cs_value);
595 static int lemac_read_eeprom(struct le_softc *sc);
596 static void lemac_init_adapmem(struct le_softc *sc);
598 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
600 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
601 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
602 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
603 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
604 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
607 * An IRQ mapping table. Less space than switch statement.
609 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
612 * Some tuning/monitoring variables.
614 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
615 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
617 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
618 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
619 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
620 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
623 lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
627 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
628 DELAY(LEMAC_EEP_DELAY);
631 * Read Ethernet address if card is present.
633 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
636 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
638 * Clear interrupts and set IRQ.
641 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
642 irq = lemac_irqs[portval >> 5];
643 LE_OUTB(sc, LEMAC_REG_IC, portval);
646 * Make sure settings match.
649 if (irq != sc->le_irq) {
650 if_printf(&sc->le_if, "lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
656 * Try to reset the unit
658 sc->if_init = lemac_init;
659 sc->le_if.if_start = lemac_start;
660 sc->if_reset = lemac_reset;
661 sc->lemac_memmode = 2;
663 if ((sc->le_flags & IFF_UP) == 0)
667 * Check for correct memory base configuration.
669 if (vtophys(sc->le_membase) != sc->lemac_membase) {
670 if_printf(&sc->le_if, "lemac configuration error: expected iomem 0x%llx actual 0x%x\n",
671 vtophys(sc->le_membase), sc->lemac_membase);
675 sc->le_prodname = sc->lemac_prodname;
676 sc->le_mctbl = sc->lemac_mctbl;
677 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
678 sc->lemac_txmax = lemac_deftxmax;
680 le_intrvec[sc->le_if.if_dunit] = lemac_intr;
682 return LEMAC_IOSPACE;
686 * Do a hard reset of the board;
689 lemac_reset(struct le_softc *sc)
691 struct ifnet *ifp = &sc->le_if;
698 sc->le_flags &= IFF_UP;
699 ifp->if_flags &= ~IFF_OACTIVE;
700 LEMAC_INTR_DISABLE(sc);
702 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
703 DELAY(LEMAC_EEP_DELAY);
705 /* Disable Interrupts */
706 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
709 * Read EEPROM information. NOTE - the placement of this function
710 * is important because functions hereafter may rely on information
711 * read from the EEPROM.
713 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
714 if_printf(ifp, "reset: EEPROM checksum failed (0x%x)\n", cksum);
719 * Force to 2K mode if not already configured.
722 portval = LE_INB(sc, LEMAC_REG_MBR);
723 if (!LEMAC_2K_MODE(portval)) {
724 if (LEMAC_64K_MODE(portval)) {
725 portval = (((portval * 2) & 0xF) << 4);
726 sc->lemac_memmode = 64;
727 } else if (LEMAC_32K_MODE(portval)) {
728 portval = ((portval & 0xF) << 4);
729 sc->lemac_memmode = 32;
731 LE_OUTB(sc, LEMAC_REG_MBR, portval);
733 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
736 * Initialize Free Memory Queue, Init mcast table with broadcast.
739 lemac_init_adapmem(sc);
740 sc->le_flags |= IFF_UP;
744 lemac_init(void *xsc)
746 struct le_softc *sc = (struct le_softc *)xsc;
749 if ((sc->le_flags & IFF_UP) == 0)
755 * If the interface has the up flag
757 if (sc->le_if.if_flags & IFF_UP) {
758 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
759 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
760 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
761 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
762 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
763 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
764 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
765 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
767 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
769 if (sc->le_if.if_flags & IFF_PROMISC) {
770 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
772 LEMAC_INTR_DISABLE(sc);
774 LE_OUTB(sc, LEMAC_REG_MPN, 0);
775 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
776 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
778 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
780 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
783 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
785 LEMAC_INTR_ENABLE(sc);
786 sc->le_if.if_flags |= IFF_RUNNING;
788 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
790 LEMAC_INTR_DISABLE(sc);
791 sc->le_if.if_flags &= ~IFF_RUNNING;
797 * What to do upon receipt of an interrupt.
800 lemac_intr(struct le_softc *sc)
804 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
807 * Determine cause of interrupt. Receive events take
808 * priority over Transmit.
811 cs_value = LE_INB(sc, LEMAC_REG_CS);
814 * Check for Receive Queue not being empty.
815 * Check for Transmit Done Queue not being empty.
818 if (cs_value & LEMAC_CS_RNE)
820 if (cs_value & LEMAC_CS_TNE)
824 * Check for Transmitter Disabled.
825 * Check for Receiver Disabled.
828 if (cs_value & LEMAC_CS_TXD)
829 lemac_txd_intr(sc, cs_value);
830 if (cs_value & LEMAC_CS_RXD)
831 lemac_rxd_intr(sc, cs_value);
834 * Toggle LED and unmask interrupts.
837 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
838 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
842 lemac_rne_intr(struct le_softc *sc)
844 int rxcount, rxlen, rxpg;
848 rxcount = LE_INB(sc, LEMAC_REG_RQC);
850 rxpg = LE_INB(sc, LEMAC_REG_RQ);
851 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
853 rxptr = sc->le_membase;
854 sc->le_if.if_ipackets++;
855 if (*rxptr & LEMAC_RX_OK) {
858 * Get receive length - subtract out checksum.
861 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
862 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
863 } else { /* end if (*rxptr & LEMAC_RX_OK) */
864 sc->le_if.if_ierrors++;
866 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
867 } /* end while (recv_count--) */
871 lemac_rxd_intr(struct le_softc *sc, unsigned cs_value)
874 * Handle CS_RXD (Receiver disabled) here.
876 * Check Free Memory Queue Count. If not equal to zero
877 * then just turn Receiver back on. If it is equal to
878 * zero then check to see if transmitter is disabled.
879 * Process transmit TXD loop once more. If all else
880 * fails then do software init (0xC0 to EEPROM Init)
881 * and rebuild Free Memory Queue.
887 * Re-enable Receiver.
890 cs_value &= ~LEMAC_CS_RXD;
891 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
893 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
896 if (cs_value & LEMAC_CS_TXD)
897 lemac_txd_intr(sc, cs_value);
899 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
902 if_printf(&sc->le_if, "fatal RXD error, attempting recovery\n");
905 if (sc->le_flags & IFF_UP) {
911 * Error during initializion. Mark card as disabled.
913 if_printf(&sc->le_if, "recovery failed -- board disabled\n");
917 lemac_start(struct ifnet *ifp)
919 struct le_softc *sc = (struct le_softc *) ifp;
921 if ((ifp->if_flags & IFF_RUNNING) == 0)
924 LEMAC_INTR_DISABLE(sc);
926 while (!IF_QEMPTY(&ifp->if_snd)) {
931 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
932 ifp->if_flags |= IFF_OACTIVE;
936 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
938 * Check for good transmit page.
940 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
942 ifp->if_flags |= IFF_OACTIVE;
946 IF_DEQUEUE(&ifp->if_snd, m);
947 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
950 * The first four bytes of each transmit buffer are for
951 * control information. The first byte is the control
952 * byte, then the length (why not word aligned?), then
953 * the off to the buffer.
956 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
957 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
958 *(u_int *) sc->le_membase = txhdr;
961 * Copy the packet to the board
964 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
966 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
970 m_freem(m); /* free the mbuf */
972 LEMAC_INTR_ENABLE(sc);
976 lemac_tne_intr(struct le_softc *sc)
978 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
982 txsts = LE_INB(sc, LEMAC_REG_TDQ);
983 sc->le_if.if_opackets++; /* another one done */
984 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
985 sc->le_if.if_collisions++;
987 sc->le_if.if_flags &= ~IFF_OACTIVE;
988 lemac_start(&sc->le_if);
992 lemac_txd_intr(struct le_softc *sc, unsigned cs_value)
995 * Read transmit status, remove transmit buffer from
996 * transmit queue and place on free memory queue,
997 * then reset transmitter.
998 * Increment appropriate counters.
1002 sc->le_if.if_oerrors++;
1003 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
1004 sc->le_if.if_collisions++;
1005 sc->le_if.if_flags &= ~IFF_OACTIVE;
1007 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
1008 /* Get Page number and write it back out */
1010 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
1011 /* Turn back on transmitter */
1015 lemac_read_eeprom(struct le_softc *sc)
1017 int word_off, cksum;
1022 ep = sc->lemac_eeprom;
1023 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
1024 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
1025 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
1027 DELAY(LEMAC_EEP_DELAY);
1029 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
1030 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1034 * Set up Transmit Control Byte for use later during transmit.
1037 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1039 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1040 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1042 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1043 sc->lemac_txctl |= LEMAC_TX_LAB;
1045 MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
1046 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1052 lemac_init_adapmem(struct le_softc *sc)
1056 conf = LE_INB(sc, LEMAC_REG_CNF);
1058 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1059 sc->lemac_lastpage = 63;
1060 conf &= ~LEMAC_CNF_DRAM;
1062 sc->lemac_lastpage = 127;
1063 conf |= LEMAC_CNF_DRAM;
1066 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1068 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1069 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1073 #endif /* !defined(LE_NOLEMAC) */
1075 #if !defined(LE_NOLANCE)
1077 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1079 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1082 static void depca_intr(struct le_softc *sc);
1083 static int lance_init_adapmem(struct le_softc *sc);
1084 static int lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1085 unsigned ndescs, unsigned bufoffset,
1086 unsigned descoffset);
1087 static void lance_init(void *xsc);
1088 static void lance_reset(struct le_softc *sc);
1089 static void lance_intr(struct le_softc *sc);
1090 static int lance_rx_intr(struct le_softc *sc);
1091 static void lance_start(struct ifnet *ifp);
1092 static int lance_tx_intr(struct le_softc *sc);
1094 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1095 #define LN_TXDESC_RATIO 2048
1096 #define LN_DESC_MAX 128
1100 unsigned lance_rx_misses;
1101 unsigned lance_rx_badcrc;
1102 unsigned lance_rx_badalign;
1103 unsigned lance_rx_badframe;
1104 unsigned lance_rx_buferror;
1105 unsigned lance_tx_deferred;
1106 unsigned lance_tx_single_collisions;
1107 unsigned lance_tx_multiple_collisions;
1108 unsigned lance_tx_excessive_collisions;
1109 unsigned lance_tx_late_collisions;
1111 unsigned lance_memory_errors;
1112 unsigned lance_inits;
1113 unsigned lance_tx_intrs;
1114 unsigned lance_tx_nospc[2];
1115 unsigned lance_tx_drains[2];
1116 unsigned lance_tx_orphaned;
1117 unsigned lance_tx_adoptions;
1118 unsigned lance_tx_emptied;
1119 unsigned lance_tx_deftxint;
1120 unsigned lance_tx_buferror;
1121 unsigned lance_high_txoutptr;
1122 unsigned lance_low_txheapsize;
1123 unsigned lance_low_txfree;
1124 unsigned lance_tx_intr_hidescs;
1125 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1127 unsigned lance_rx_intrs;
1128 unsigned lance_rx_badsop;
1129 unsigned lance_rx_contig;
1130 unsigned lance_rx_noncontig;
1131 unsigned lance_rx_intr_hidescs;
1132 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1133 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1136 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1137 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1138 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1141 #define LN_STAT(stat) 0
1142 #define LN_MINSTAT(stat, val) 0
1143 #define LN_MAXSTAT(stat, val) 0
1146 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1147 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1149 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1150 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1153 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1154 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1156 #define LN_SETFLAG(sc, vaddr, val) \
1157 (((volatile u_char *) vaddr)[3] = (val))
1159 #define LN_PUTDESC(sc, desc, vaddr) \
1160 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1161 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1162 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1165 * Only get the descriptor flags and length/status. All else
1168 #define LN_GETDESC(sc, desc, vaddr) \
1169 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1170 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1173 * These definitions are specific to the DEC "DEPCA-style" NICs.
1174 * (DEPCA, DE10x, DE20[012], DE422)
1177 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1178 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1179 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1180 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1181 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1183 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1184 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1185 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1186 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1187 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1188 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1189 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1190 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1191 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1193 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1194 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1196 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1198 #define DEPCA_REG_EISAID 0x80
1199 #define DEPCA_EISAID_MASK 0xf0ffffff
1200 #define DEPCA_EISAID_DE422 0x2042A310
1204 DEPCA_DE100, DEPCA_DE101,
1206 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1211 static const char *depca_signatures[] = {
1215 "DE200", "DE201", "DE202",
1221 depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
1223 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1226 * Find out how memory we are dealing with. Adjust
1227 * the ID string offset approriately if we are at
1228 * 32K. Make sure the ROM is enabled.
1230 nicsr = DEPCA_RDNICSR(sc);
1231 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1233 if (nicsr & DEPCA_NICSR_32KRAM) {
1235 * Make we are going to read the upper
1236 * 32K so we do read the ROM.
1238 sc->lance_ramsize = 32 * 1024;
1239 nicsr &= ~DEPCA_NICSR_LOW32K;
1240 sc->lance_ramoffset = 32 * 1024;
1241 idstr_offset -= sc->lance_ramsize;
1243 sc->lance_ramsize = 64 * 1024;
1244 sc->lance_ramoffset = 0;
1246 DEPCA_WRNICSR(sc, nicsr);
1248 sc->le_prodname = NULL;
1249 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1250 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1251 sc->le_prodname = depca_signatures[idx];
1256 if (sc->le_prodname == NULL) {
1258 * Try to get the EISA device if it's a DE422.
1260 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1261 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1262 == DEPCA_EISAID_DE422) {
1263 sc->le_prodname = "DE422";
1268 if (idx == DEPCA_CLASSIC)
1269 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1272 * Try to read the address ROM.
1273 * Stop the LANCE, reset the Address ROM Counter (AAC),
1274 * read the NICSR to "clock" in the reset, and then
1275 * re-enable the Address ROM Counter. Now read the
1278 sc->lance_rdp = DEPCA_REG_RDP;
1279 sc->lance_rap = DEPCA_REG_RAP;
1280 sc->lance_csr3 = LN_CSR3_ALE;
1281 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1282 sc->le_mcmask = LN_MC_MASK;
1283 LN_SELCSR(sc, LN_CSR0);
1284 LN_WRCSR(sc, LN_CSR0_STOP);
1286 if (idx < DEPCA_DE200) {
1287 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1288 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1291 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1294 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
1296 * Renable shared RAM.
1298 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1300 le_intrvec[sc->le_if.if_dunit] = depca_intr;
1301 if (!lance_init_adapmem(sc))
1304 sc->if_reset = lance_reset;
1305 sc->if_init = lance_init;
1306 sc->le_if.if_start = lance_start;
1307 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1310 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1311 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1312 *msize = sc->lance_ramsize;
1313 return DEPCA_IOSPACE;
1317 depca_intr(struct le_softc *sc)
1319 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1324 * Here's as good a place to describe our paritioning of the
1325 * LANCE shared RAM space. (NOTE: this driver does not yet support
1326 * the concept of a LANCE being able to DMA).
1328 * First is the 24 (00:23) bytes for LANCE Initialization Block
1329 * Next are the recieve descriptors. The number is calculated from
1330 * how many LN_BUFSIZE buffers we can allocate (this number must
1331 * be a power of 2). Next are the transmit descriptors. The amount
1332 * of transmit descriptors is derived from the size of the RAM
1333 * divided by 1K. Now come the receive buffers (one for each receive
1334 * descriptor). Finally is the transmit heap. (no fixed buffers are
1335 * allocated so as to make the most use of the limited space).
1338 lance_init_adapmem(struct le_softc *sc)
1340 lance_addr_t rxbufoffset;
1341 lance_addr_t rxdescoffset, txdescoffset;
1342 unsigned rxdescs, txdescs;
1345 * First calculate how many descriptors we heap.
1346 * Note this assumes the ramsize is a power of two.
1348 sc->lance_rxbufsize = LN_BUFSIZE;
1350 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1353 if (rxdescs > LN_DESC_MAX) {
1354 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1355 rxdescs = LN_DESC_MAX;
1357 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1358 if (txdescs > LN_DESC_MAX)
1359 txdescs = LN_DESC_MAX;
1362 * Now calculate where everything goes in memory
1364 rxdescoffset = sizeof(ln_initb_t);
1365 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1366 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1368 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1370 * Remember these for debugging.
1372 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1373 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1376 * Initialize the rings.
1378 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1379 rxdescs, rxbufoffset, rxdescoffset))
1381 sc->lance_rxinfo.ri_heap = rxbufoffset;
1382 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1384 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1385 txdescs, 0, txdescoffset))
1387 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1388 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1391 * Set CSR1 and CSR2 to the address of the init block (which
1392 * for us is always 0.
1394 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1395 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1400 lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1401 unsigned ndescs, lance_addr_t bufoffset, lance_addr_t descoffset)
1403 lance_descinfo_t *di;
1406 * Initialize the ring pointer in the LANCE InitBlock
1408 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1409 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1410 rp->r_log2_size = ffs(ndescs) - 1;
1413 * Allocate the ring entry descriptors and initialize
1414 * our ring information data structure. All these are
1415 * our copies and do not live in the LANCE RAM.
1417 ri->ri_first = malloc(ndescs * sizeof(*di), M_DEVBUF, M_WAITOK);
1418 ri->ri_free = ri->ri_max = ndescs;
1419 ri->ri_last = ri->ri_first + ri->ri_max;
1420 for (di = ri->ri_first; di < ri->ri_last; di++) {
1421 di->di_addr = sc->le_membase + descoffset;
1424 di->di_bufaddr = bufoffset;
1425 di->di_buflen = sc->lance_rxbufsize;
1426 bufoffset += sc->lance_rxbufsize;
1428 descoffset += sizeof(ln_desc_t);
1434 lance_dumpcsrs(struct le_softc *sc, const char *id)
1436 if_printf(&sc->le_if, "%s: nicsr=%04x", id, DEPCA_RDNICSR(sc));
1437 LN_SELCSR(sc, LN_CSR0);
1438 printf(" csr0=%04x", LN_RDCSR(sc));
1439 LN_SELCSR(sc, LN_CSR1);
1440 printf(" csr1=%04x", LN_RDCSR(sc));
1441 LN_SELCSR(sc, LN_CSR2);
1442 printf(" csr2=%04x", LN_RDCSR(sc));
1443 LN_SELCSR(sc, LN_CSR3);
1444 printf(" csr3=%04x\n", LN_RDCSR(sc));
1445 LN_SELCSR(sc, LN_CSR0);
1449 lance_reset(struct le_softc *sc)
1453 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1455 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1456 LN_WRCSR(sc, LN_CSR0_STOP);
1459 sc->le_flags &= ~IFF_UP;
1460 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1462 le_multi_filter(sc); /* initialize the multicast table */
1463 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1464 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1465 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1466 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1467 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1469 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1470 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1471 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1472 if (sc->le_if.if_flags & IFF_PROMISC) {
1473 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1475 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1478 * We force the init block to be at the start
1479 * of the LANCE's RAM buffer.
1481 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1482 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1483 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1484 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1486 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1489 * clear INITDONE and INIT the chip
1491 LN_SELCSR(sc, LN_CSR0);
1492 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1497 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1502 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1503 lance_dumpcsrs(sc, "lance_reset: reset failure");
1505 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1506 sc->le_if.if_flags |= IFF_UP;
1507 sc->le_flags |= IFF_UP;
1512 lance_init(void *xsc)
1514 struct le_softc *sc = (struct le_softc *)xsc;
1516 lance_descinfo_t *di;
1520 if (sc->le_if.if_flags & IFF_RUNNING) {
1524 * If we were running, requeue any pending transmits.
1526 ri = &sc->lance_txinfo;
1527 di = ri->ri_nextout;
1528 while (ri->ri_free < ri->ri_max) {
1529 if (--di == ri->ri_first)
1530 di = ri->ri_nextout - 1;
1531 if (di->di_mbuf == NULL)
1533 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1542 * Reset the transmit ring. Make sure we own all the buffers.
1543 * Also reset the transmit heap.
1545 sc->le_if.if_flags &= ~IFF_OACTIVE;
1546 ri = &sc->lance_txinfo;
1547 for (di = ri->ri_first; di < ri->ri_last; di++) {
1548 if (di->di_mbuf != NULL) {
1549 m_freem(di->di_mbuf);
1553 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1554 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1556 LN_PUTDESC(sc, &desc, di->di_addr);
1558 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1559 ri->ri_free = ri->ri_max;
1560 ri->ri_outptr = ri->ri_heap;
1561 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1563 ri = &sc->lance_rxinfo;
1564 desc.d_flag = LN_DFLAG_OWNER;
1565 desc.d_buflen = 0 - sc->lance_rxbufsize;
1566 for (di = ri->ri_first; di < ri->ri_last; di++) {
1567 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1568 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1569 LN_PUTDESC(sc, &desc, di->di_addr);
1571 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1572 ri->ri_outptr = ri->ri_heap;
1573 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1576 if (sc->le_if.if_flags & IFF_UP) {
1577 sc->le_if.if_flags |= IFF_RUNNING;
1578 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1579 /* lance_dumpcsrs(sc, "lance_init: up"); */
1580 lance_start(&sc->le_if);
1582 /* lance_dumpcsrs(sc, "lance_init: down"); */
1583 sc->le_if.if_flags &= ~IFF_RUNNING;
1588 lance_intr(struct le_softc *sc)
1592 oldcsr = LN_RDCSR(sc);
1593 oldcsr &= ~LN_CSR0_ENABINTR;
1594 LN_WRCSR(sc, oldcsr);
1595 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1597 if (oldcsr & LN_CSR0_ERRSUM) {
1598 if (oldcsr & LN_CSR0_MISS) {
1600 * LN_CSR0_MISS is signaled when the LANCE receiver
1601 * loses a packet because it doesn't own a receive
1602 * descriptor. Rev. D LANCE chips, which are no
1603 * longer used, require a chip reset as described
1606 LN_STAT(rx_misses++);
1608 if (oldcsr & LN_CSR0_MEMERROR) {
1609 LN_STAT(memory_errors++);
1610 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1617 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1622 if (oldcsr & LN_CSR0_TXINT) {
1623 if (lance_tx_intr(sc))
1624 lance_start(&sc->le_if);
1627 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1628 if_printf(&sc->le_if, "lance_intr: stray interrupt\n");
1632 lance_rx_intr(struct le_softc *sc)
1634 lance_ring_t *ri = &sc->lance_rxinfo;
1635 lance_descinfo_t *eop;
1637 int ndescs, total_len, rxdescs;
1639 LN_STAT(rx_intrs++);
1641 for (rxdescs = 0;;) {
1643 * Now to try to find the end of this packet chain.
1645 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1647 * If we don't own this descriptor, the packet ain't
1648 * all here so return because we are done.
1650 LN_GETDESC(sc, &desc, eop->di_addr);
1651 if (desc.d_flag & LN_DFLAG_OWNER)
1654 * In case we have missed a packet and gotten the
1655 * LANCE confused, make sure we are pointing at the
1656 * start of a packet. If we aren't, something is really
1657 * strange so reinit the LANCE.
1659 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1660 LN_STAT(rx_buferror++);
1663 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1664 LN_STAT(rx_badsop++);
1667 if (desc.d_flag & LN_DFLAG_EOP)
1669 if (++eop == ri->ri_last)
1673 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1674 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1676 * Valid Packet -- If the SOP is less than or equal to the EOP
1677 * or the length is less than the receive buffer size, then the
1678 * packet is contiguous in memory and can be copied in one shot.
1679 * Otherwise we need to copy two segments to get the entire
1682 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1683 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1684 total_len, total_len, NULL);
1685 LN_STAT(rx_contig++);
1687 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1689 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1690 sc->le_membase + ri->ri_first->di_bufaddr);
1691 LN_STAT(rx_noncontig++);
1695 * If the packet is bad, increment the
1698 sc->le_if.if_ierrors++;
1699 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1700 LN_STAT(rx_badcrc++);
1701 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1702 LN_STAT(rx_badalign++);
1703 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1704 LN_STAT(rx_badframe++);
1706 sc->le_if.if_ipackets++;
1707 LN_STAT(rx_ndescs[ndescs-1]++);
1709 while (ndescs-- > 0) {
1710 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1711 if (++ri->ri_nextin == ri->ri_last)
1712 ri->ri_nextin = ri->ri_first;
1715 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1716 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1722 lance_start(struct ifnet *ifp)
1724 struct le_softc *sc = (struct le_softc *) ifp;
1725 lance_ring_t *ri = &sc->lance_txinfo;
1726 lance_descinfo_t *di;
1729 struct mbuf *m, *m0;
1732 if ((ifp->if_flags & IFF_RUNNING) == 0)
1736 IF_DEQUEUE(&ifp->if_snd, m);
1741 * Make the packet meets the minimum size for Ethernet.
1742 * The slop is so that we also use an even number of longwards.
1744 len = ETHERMIN + sizeof(struct ether_header);
1745 if (m->m_pkthdr.len > len)
1746 len = m->m_pkthdr.len;
1748 slop = (8 - len) & 3;
1750 * If there are no free ring entries (there must be always
1751 * one owned by the host), or there's not enough space for
1752 * this packet, or this packet would wrap around the end
1753 * of LANCE RAM then wait for the transmits to empty for
1754 * space and ring entries to become available.
1756 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1758 * Try to see if we can free up anything off the transit ring.
1760 if (lance_tx_intr(sc) > 0) {
1761 LN_STAT(tx_drains[0]++);
1762 IF_PREPEND(&ifp->if_snd, m);
1765 LN_STAT(tx_nospc[0]++);
1769 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1771 * Since the packet won't fit in the end of the transmit
1772 * heap, see if there is space at the beginning of the transmit
1773 * heap. If not, try again when there is space.
1775 LN_STAT(tx_orphaned++);
1776 slop += ri->ri_heapend - ri->ri_outptr;
1777 if (len + slop > ri->ri_outsize) {
1778 LN_STAT(tx_nospc[1]++);
1782 * Point to the beginning of the heap
1784 ri->ri_outptr = ri->ri_heap;
1785 LN_STAT(tx_adoptions++);
1789 * Initialize the descriptor (saving the buffer address,
1790 * buffer length, and mbuf) and write the packet out
1793 di = ri->ri_nextout;
1794 di->di_bufaddr = ri->ri_outptr;
1795 di->di_buflen = len + slop;
1797 bp = sc->le_membase + di->di_bufaddr;
1798 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1799 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1803 * Zero out the remainder if needed (< ETHERMIN).
1805 if (m->m_pkthdr.len < len)
1806 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1809 * Finally, copy out the descriptor and tell the
1810 * LANCE to transmit!.
1812 desc.d_buflen = 0 - len;
1813 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1814 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1815 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1816 LN_PUTDESC(sc, &desc, di->di_addr);
1817 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1820 * Do our bookkeeping with our transmit heap.
1821 * (if we wrap, point back to the beginning).
1823 ri->ri_outptr += di->di_buflen;
1824 ri->ri_outsize -= di->di_buflen;
1825 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1826 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1828 if (ri->ri_outptr == ri->ri_heapend)
1829 ri->ri_outptr = ri->ri_heap;
1832 if (++ri->ri_nextout == ri->ri_last)
1833 ri->ri_nextout = ri->ri_first;
1834 LN_MINSTAT(low_txfree, ri->ri_free);
1837 ifp->if_flags |= IFF_OACTIVE;
1838 IF_PREPEND(&ifp->if_snd, m);
1843 lance_tx_intr(struct le_softc *sc)
1845 lance_ring_t *ri = &sc->lance_txinfo;
1848 LN_STAT(tx_intrs++);
1849 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1852 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1853 if (desc.d_flag & LN_DFLAG_OWNER)
1856 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1857 sc->le_if.if_collisions++;
1858 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1859 LN_STAT(tx_deferred++);
1860 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1861 LN_STAT(tx_single_collisions++);
1862 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1863 LN_STAT(tx_multiple_collisions++);
1865 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1866 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1867 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1868 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1870 LN_STAT(tx_excessive_collisions++);
1871 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1873 if_printf(&sc->le_if, "lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1874 tdr, (tdr*99)/1000, (tdr*117)/1000);
1877 if (desc.d_status & LN_DSTS_TxBUFERROR)
1878 LN_STAT(tx_buferror++);
1879 sc->le_if.if_oerrors++;
1880 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1884 LN_STAT(tx_late_collisions++);
1888 m_freem(ri->ri_nextin->di_mbuf);
1889 ri->ri_nextin->di_mbuf = NULL;
1890 sc->le_if.if_opackets++;
1892 ri->ri_outsize += ri->ri_nextin->di_buflen;
1893 if (++ri->ri_nextin == ri->ri_last)
1894 ri->ri_nextin = ri->ri_first;
1895 sc->le_if.if_flags &= ~IFF_OACTIVE;
1898 if (ri->ri_free == ri->ri_max)
1899 LN_STAT(tx_emptied++);
1900 /* LN_STAT(tx_intr_descs[xmits]++); */
1901 LN_MAXSTAT(tx_intr_hidescs, xmits);
1904 #endif /* !defined(LE_NOLANCE) */