1 /* $OpenBSD: ciphy.c,v 1.13 2006/03/10 09:53:16 jsg Exp $ */
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/ciphy.c,v 1.3 2005/09/30 19:39:27 imp Exp $
35 * $DragonFly: src/sys/dev/netif/mii_layer/ciphy.c,v 1.2 2006/08/06 10:32:23 sephe Exp $
39 * Driver for the Cicada CS8201 10/100/1000 copper PHY.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
49 #include <machine/bus.h>
52 #include <net/if_arp.h>
53 #include <net/if_media.h>
55 #include <dev/netif/mii_layer/mii.h>
56 #include <dev/netif/mii_layer/miivar.h>
59 #include "miibus_if.h"
61 #include <dev/netif/mii_layer/ciphyreg.h>
63 static int ciphy_probe(device_t);
64 static int ciphy_attach(device_t);
66 static device_method_t ciphy_methods[] = {
67 /* device interface */
68 DEVMETHOD(device_probe, ciphy_probe),
69 DEVMETHOD(device_attach, ciphy_attach),
70 DEVMETHOD(device_detach, ukphy_detach),
71 DEVMETHOD(device_shutdown, bus_generic_shutdown),
75 static const struct mii_phydesc ciphys[] = {
76 MII_PHYDESC(CICADA, CS8201),
77 MII_PHYDESC(CICADA, CS8201A),
78 MII_PHYDESC(CICADA, CS8201B),
79 MII_PHYDESC(xxCICADA, CS8201),
80 MII_PHYDESC(xxCICADA, CS8201A),
81 MII_PHYDESC(xxCICADA, CS8201B),
85 static devclass_t ciphy_devclass;
87 static driver_t ciphy_driver = {
90 sizeof(struct mii_softc)
93 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
95 static int ciphy_service(struct mii_softc *, struct mii_data *, int);
96 static void ciphy_status(struct mii_softc *);
97 static void ciphy_reset(struct mii_softc *);
98 static void ciphy_fixup(struct mii_softc *);
101 ciphy_probe(device_t dev)
103 struct mii_attach_args *ma = device_get_ivars(dev);
104 const struct mii_phydesc *mpd;
106 mpd = mii_phy_match(ma, ciphys);
108 device_set_desc(dev, mpd->mpd_name);
115 ciphy_attach(device_t dev)
117 struct mii_softc *sc;
118 struct mii_attach_args *ma;
119 struct mii_data *mii;
121 sc = device_get_softc(dev);
122 ma = device_get_ivars(dev);
123 mii_softc_init(sc, ma);
125 sc->mii_dev = device_get_parent(dev);
126 mii = device_get_softc(sc->mii_dev);
127 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
129 sc->mii_inst = mii->mii_instance;
130 sc->mii_service = ciphy_service;
131 sc->mii_reset = ciphy_reset;
134 sc->mii_flags |= MIIF_NOISOLATE;
139 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
140 if (sc->mii_capabilities & BMSR_EXTSTAT)
141 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
143 device_printf(dev, " ");
144 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
145 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
146 printf("no media present");
148 mii_phy_add_media(sc);
151 MIIBUS_MEDIAINIT(sc->mii_dev);
156 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
158 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
164 * If we're not polling our PHY instance, just return.
166 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
172 * If the media indicates a different PHY instance,
175 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
176 reg = PHY_READ(sc, MII_BMCR);
177 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
182 * If the interface is not up, don't do anything.
184 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
187 ciphy_fixup(sc); /* XXX hardware bug work-around */
189 switch (IFM_SUBTYPE(ife->ifm_media)) {
193 * If we're already in auto mode, just return.
195 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
198 if (mii_phy_auto(sc, 0) == EJUSTRETURN)
210 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
211 speed |= CIPHY_BMCR_FDX;
212 gig = CIPHY_1000CTL_AFD;
214 gig = CIPHY_1000CTL_AHD;
217 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
218 PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
219 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
221 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
224 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
225 PHY_WRITE(sc, CIPHY_MII_BMCR,
226 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
229 * When setting the link manually, one side must
230 * be the master and the other the slave. However
231 * ifmedia doesn't give us a good way to specify
232 * this, so we fake it by using one of the LINK
233 * flags. If LINK0 is set, we program the PHY to
234 * be a master, otherwise it's a slave.
236 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
237 PHY_WRITE(sc, CIPHY_MII_1000CTL,
238 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
240 PHY_WRITE(sc, CIPHY_MII_1000CTL,
241 gig|CIPHY_1000CTL_MSE);
245 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
255 * If we're not currently selected, just return.
257 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
260 if (mii_phy_tick(sc) == EJUSTRETURN)
265 /* Update the media status. */
269 * Callback if something changed. Note that we need to poke
270 * apply fixups for certain PHY revs.
272 if (sc->mii_media_active != mii->mii_media_active ||
273 sc->mii_media_status != mii->mii_media_status ||
276 mii_phy_update(sc, cmd);
281 ciphy_status(struct mii_softc *sc)
283 struct mii_data *mii = sc->mii_pdata;
286 mii->mii_media_status = IFM_AVALID;
287 mii->mii_media_active = IFM_ETHER;
289 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
291 if (bmsr & BMSR_LINK)
292 mii->mii_media_status |= IFM_ACTIVE;
294 bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
296 if (bmcr & CIPHY_BMCR_LOOP)
297 mii->mii_media_active |= IFM_LOOP;
299 if (bmcr & CIPHY_BMCR_AUTOEN) {
300 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
301 /* Erg, still trying, I guess... */
302 mii->mii_media_active |= IFM_NONE;
307 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
308 switch (bmsr & CIPHY_AUXCSR_SPEED) {
310 mii->mii_media_active |= IFM_10_T;
313 mii->mii_media_active |= IFM_100_TX;
315 case CIPHY_SPEED1000:
316 mii->mii_media_active |= IFM_1000_T;
319 device_printf(sc->mii_dev, "unknown PHY speed %x\n",
320 bmsr & CIPHY_AUXCSR_SPEED);
324 if (bmsr & CIPHY_AUXCSR_FDX)
325 mii->mii_media_active |= IFM_FDX;
329 ciphy_reset(struct mii_softc *sc)
335 #define PHY_SETBIT(x, y, z) \
336 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
337 #define PHY_CLRBIT(x, y, z) \
338 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
341 ciphy_fixup(struct mii_softc *sc)
343 uint16_t model, status, speed;
346 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
347 status = PHY_READ(sc, CIPHY_MII_AUXCSR);
348 speed = status & CIPHY_AUXCSR_SPEED;
350 parent = device_get_parent(sc->mii_dev);
351 if (strncmp(device_get_name(parent), "nfe", 3) == 0) {
352 /* Need to set for 2.5V RGMII for NVIDIA adapters */
353 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII);
354 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV);
358 case MII_MODEL_CICADA_CS8201: /* MII_MODEL_xxCICADA_CS8201 */
359 /* Turn off "aux mode" (whatever that means) */
360 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
363 * Work around speed polling bug in VT3119/VT3216
364 * when using MII in full duplex mode.
366 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
367 (status & CIPHY_AUXCSR_FDX)) {
368 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
370 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
373 /* Enable link/activity LED blink. */
374 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
377 case MII_MODEL_CICADA_CS8201A: /* MII_MODEL_xxCICADA_CS8201A */
378 case MII_MODEL_CICADA_CS8201B: /* MII_MODEL_xxCICADA_CS8201B */
380 * Work around speed polling bug in VT3119/VT3216
381 * when using MII in full duplex mode.
383 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
384 (status & CIPHY_AUXCSR_FDX)) {
385 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
387 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
392 device_printf(sc->mii_dev,
393 "unknown CICADA PHY model %x\n", model);