sys/dev/netif/e1000/e1000_82571.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  55 static s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  56 static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  57 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  58 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  59 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  60                                   u16 words, u16 *data);
  61 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  62 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  63 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  64 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  65                                           bool active);
  66 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  67 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  73 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  74 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  75 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  77 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  78 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  79 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  81 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  82 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  83                                        u16 words, u16 *data);
  84 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  85 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  86
  87 /**
  88  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  89  *  @hw: pointer to the HW structure
  90  **/
  91 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  92 {
  93         struct e1000_phy_info *phy = &hw->phy;
  94         s32 ret_val = E1000_SUCCESS;
  95
  96         DEBUGFUNC("e1000_init_phy_params_82571");
  97
  98         if (hw->phy.media_type != e1000_media_type_copper) {
  99                 phy->type = e1000_phy_none;
 100                 goto out;
 101         }
 102
 103         phy->addr                        = 1;
 104         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 105         phy->reset_delay_us              = 100;
 106
 107         phy->ops.acquire                 = e1000_get_hw_semaphore_82571;
 108         phy->ops.check_reset_block       = e1000_check_reset_block_generic;
 109         phy->ops.release                 = e1000_put_hw_semaphore_82571;
 110         phy->ops.reset                   = e1000_phy_hw_reset_generic;
 111         phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
 112         phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
 113         phy->ops.power_up                = e1000_power_up_phy_copper;
 114         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 115
 116         switch (hw->mac.type) {
 117         case e1000_82571:
 118         case e1000_82572:
 119                 phy->type                   = e1000_phy_igp_2;
 120                 phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
 121                 phy->ops.get_info           = e1000_get_phy_info_igp;
 122                 phy->ops.check_polarity     = e1000_check_polarity_igp;
 123                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 124                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 125                 phy->ops.read_reg           = e1000_read_phy_reg_igp;
 126                 phy->ops.write_reg          = e1000_write_phy_reg_igp;
 127
 128                 /* This uses above function pointers */
 129                 ret_val = e1000_get_phy_id_82571(hw);
 130
 131                 /* Verify PHY ID */
 132                 if (phy->id != IGP01E1000_I_PHY_ID) {
 133                         ret_val = -E1000_ERR_PHY;
 134                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 135                         goto out;
 136                 }
 137                 break;
 138         case e1000_82573:
 139                 phy->type                   = e1000_phy_m88;
 140                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 141                 phy->ops.get_info           = e1000_get_phy_info_m88;
 142                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 143                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 144                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 145                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 146                 phy->ops.read_reg           = e1000_read_phy_reg_m88;
 147                 phy->ops.write_reg          = e1000_write_phy_reg_m88;
 148
 149                 /* This uses above function pointers */
 150                 ret_val = e1000_get_phy_id_82571(hw);
 151
 152                 /* Verify PHY ID */
 153                 if (phy->id != M88E1111_I_PHY_ID) {
 154                         ret_val = -E1000_ERR_PHY;
 155                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 156                         goto out;
 157                 }
 158                 break;
 159         case e1000_82574:
 160         case e1000_82583:
 161                 phy->type                   = e1000_phy_bm;
 162                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 163                 phy->ops.get_info           = e1000_get_phy_info_m88;
 164                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 165                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 166                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 167                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 168                 phy->ops.read_reg           = e1000_read_phy_reg_bm2;
 169                 phy->ops.write_reg          = e1000_write_phy_reg_bm2;
 170
 171                 /* This uses above function pointers */
 172                 ret_val = e1000_get_phy_id_82571(hw);
 173                 /* Verify PHY ID */
 174                 if (phy->id != BME1000_E_PHY_ID_R2) {
 175                         ret_val = -E1000_ERR_PHY;
 176                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 177                         goto out;
 178                 }
 179                 break;
 180         default:
 181                 ret_val = -E1000_ERR_PHY;
 182                 goto out;
 183                 break;
 184         }
 185
 186 out:
 187         return ret_val;
 188 }
 189
 190 /**
 191  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 192  *  @hw: pointer to the HW structure
 193  **/
 194 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 195 {
 196         struct e1000_nvm_info *nvm = &hw->nvm;
 197         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 198         u16 size;
 199
 200         DEBUGFUNC("e1000_init_nvm_params_82571");
 201
 202         nvm->opcode_bits = 8;
 203         nvm->delay_usec = 1;
 204         switch (nvm->override) {
 205         case e1000_nvm_override_spi_large:
 206                 nvm->page_size = 32;
 207                 nvm->address_bits = 16;
 208                 break;
 209         case e1000_nvm_override_spi_small:
 210                 nvm->page_size = 8;
 211                 nvm->address_bits = 8;
 212                 break;
 213         default:
 214                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 215                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 216                 break;
 217         }
 218
 219         switch (hw->mac.type) {
 220         case e1000_82573:
 221         case e1000_82574:
 222         case e1000_82583:
 223                 if (((eecd >> 15) & 0x3) == 0x3) {
 224                         nvm->type = e1000_nvm_flash_hw;
 225                         nvm->word_size = 2048;
 226                         /*
 227                          * Autonomous Flash update bit must be cleared due
 228                          * to Flash update issue.
 229                          */
 230                         eecd &= ~E1000_EECD_AUPDEN;
 231                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 232                         break;
 233                 }
 234                 /* Fall Through */
 235         default:
 236                 nvm->type = e1000_nvm_eeprom_spi;
 237                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 238                                   E1000_EECD_SIZE_EX_SHIFT);
 239                 /*
 240                  * Added to a constant, "size" becomes the left-shift value
 241                  * for setting word_size.
 242                  */
 243                 size += NVM_WORD_SIZE_BASE_SHIFT;
 244
 245                 /* EEPROM access above 16k is unsupported */
 246                 if (size > 14)
 247                         size = 14;
 248                 nvm->word_size  = 1 << size;
 249                 break;
 250         }
 251
 252         /* Function Pointers */
 253         nvm->ops.acquire       = e1000_acquire_nvm_82571;
 254         nvm->ops.read          = e1000_read_nvm_eerd;
 255         nvm->ops.release       = e1000_release_nvm_82571;
 256         nvm->ops.update        = e1000_update_nvm_checksum_82571;
 257         nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
 258         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 259         nvm->ops.write         = e1000_write_nvm_82571;
 260
 261         return E1000_SUCCESS;
 262 }
 263
 264 /**
 265  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 266  *  @hw: pointer to the HW structure
 267  **/
 268 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 269 {
 270         struct e1000_mac_info *mac = &hw->mac;
 271         u32 swsm = 0;
 272         u32 swsm2 = 0;
 273         bool force_clear_smbi = FALSE;
 274
 275         DEBUGFUNC("e1000_init_mac_params_82571");
 276
 277         /* Set media type and media-dependent function pointers */
 278         switch (hw->device_id) {
 279         case E1000_DEV_ID_82571EB_FIBER:
 280         case E1000_DEV_ID_82572EI_FIBER:
 281         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 282                 hw->phy.media_type = e1000_media_type_fiber;
 283                 mac->ops.setup_physical_interface =
 284                         e1000_setup_fiber_serdes_link_82571;
 285                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 286                 mac->ops.get_link_up_info =
 287                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 288                 break;
 289         case E1000_DEV_ID_82571EB_SERDES:
 290         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 291         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 292         case E1000_DEV_ID_82572EI_SERDES:
 293                 hw->phy.media_type = e1000_media_type_internal_serdes;
 294                 mac->ops.setup_physical_interface =
 295                         e1000_setup_fiber_serdes_link_82571;
 296                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 297                 mac->ops.get_link_up_info =
 298                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 299                 break;
 300         default:
 301                 hw->phy.media_type = e1000_media_type_copper;
 302                 mac->ops.setup_physical_interface =
 303                         e1000_setup_copper_link_82571;
 304                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 305                 mac->ops.get_link_up_info =
 306                         e1000_get_speed_and_duplex_copper_generic;
 307                 break;
 308         }
 309
 310         /* Set mta register count */
 311         mac->mta_reg_count = 128;
 312         /* Set rar entry count */
 313         mac->rar_entry_count = E1000_RAR_ENTRIES;
 314         /* Set if part includes ASF firmware */
 315         mac->asf_firmware_present = TRUE;
 316         /* Set if manageability features are enabled. */
 317         mac->arc_subsystem_valid =
 318                 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 319                         ? TRUE : FALSE;
 320         /* Adaptive IFS supported */
 321         mac->adaptive_ifs = TRUE;
 322
 323         /* Function pointers */
 324
 325         /* bus type/speed/width */
 326         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 327         /* reset */
 328         mac->ops.reset_hw = e1000_reset_hw_82571;
 329         /* hw initialization */
 330         mac->ops.init_hw = e1000_init_hw_82571;
 331         /* link setup */
 332         mac->ops.setup_link = e1000_setup_link_82571;
 333         /* multicast address update */
 334         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 335         /* writing VFTA */
 336         mac->ops.write_vfta = e1000_write_vfta_generic;
 337         /* clearing VFTA */
 338         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 339         /* read mac address */
 340         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 341         /* ID LED init */
 342         mac->ops.id_led_init = e1000_id_led_init_generic;
 343         /* blink LED */
 344         mac->ops.blink_led = e1000_blink_led_generic;
 345         /* setup LED */
 346         mac->ops.setup_led = e1000_setup_led_generic;
 347         /* cleanup LED */
 348         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 349         /* turn off LED */
 350         mac->ops.led_off = e1000_led_off_generic;
 351         /* clear hardware counters */
 352         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 353
 354         /* MAC-specific function pointers */
 355         switch (hw->mac.type) {
 356         case e1000_82573:
 357                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 358                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 359                 mac->ops.led_on = e1000_led_on_generic;
 360                 break;
 361         case e1000_82574:
 362         case e1000_82583:
 363                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 364                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 365                 mac->ops.led_on = e1000_led_on_82574;
 366                 break;
 367         default:
 368                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 369                 mac->ops.led_on = e1000_led_on_generic;
 370                 break;
 371         }
 372
 373         /*
 374          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 375          * first NVM or PHY acess. This should be done for single-port
 376          * devices, and for one port only on dual-port devices so that
 377          * for those devices we can still use the SMBI lock to synchronize
 378          * inter-port accesses to the PHY & NVM.
 379          */
 380         switch (hw->mac.type) {
 381         case e1000_82571:
 382         case e1000_82572:
 383                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 384
 385                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 386                         /* Only do this for the first interface on this card */
 387                         E1000_WRITE_REG(hw, E1000_SWSM2,
 388                             swsm2 | E1000_SWSM2_LOCK);
 389                         force_clear_smbi = TRUE;
 390                 } else
 391                         force_clear_smbi = FALSE;
 392                 break;
 393         default:
 394                 force_clear_smbi = TRUE;
 395                 break;
 396         }
 397
 398         if (force_clear_smbi) {
 399                 /* Make sure SWSM.SMBI is clear */
 400                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 401                 if (swsm & E1000_SWSM_SMBI) {
 402                         /* This bit should not be set on a first interface, and
 403                          * indicates that the bootagent or EFI code has
 404                          * improperly left this bit enabled
 405                          */
 406                         DEBUGOUT("Please update your 82571 Bootagent\n");
 407                 }
 408                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 409         }
 410
 411         /*
 412          * Initialze device specific counter of SMBI acquisition
 413          * timeouts.
 414          */
 415          hw->dev_spec._82571.smb_counter = 0;
 416
 417         return E1000_SUCCESS;
 418 }
 419
 420 /**
 421  *  e1000_init_function_pointers_82571 - Init func ptrs.
 422  *  @hw: pointer to the HW structure
 423  *
 424  *  Called to initialize all function pointers and parameters.
 425  **/
 426 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 427 {
 428         DEBUGFUNC("e1000_init_function_pointers_82571");
 429
 430         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 431         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 432         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 433 }
 434
 435 /**
 436  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 437  *  @hw: pointer to the HW structure
 438  *
 439  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 440  *  revision in the hardware structure.
 441  **/
 442 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 443 {
 444         struct e1000_phy_info *phy = &hw->phy;
 445         s32 ret_val = E1000_SUCCESS;
 446         u16 phy_id = 0;
 447
 448         DEBUGFUNC("e1000_get_phy_id_82571");
 449
 450         switch (hw->mac.type) {
 451         case e1000_82571:
 452         case e1000_82572:
 453                 /*
 454                  * The 82571 firmware may still be configuring the PHY.
 455                  * In this case, we cannot access the PHY until the
 456                  * configuration is done.  So we explicitly set the
 457                  * PHY ID.
 458                  */
 459                 phy->id = IGP01E1000_I_PHY_ID;
 460                 break;
 461         case e1000_82573:
 462                 ret_val = e1000_get_phy_id(hw);
 463                 break;
 464         case e1000_82574:
 465         case e1000_82583:
 466                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 467                 if (ret_val)
 468                         goto out;
 469
 470                 phy->id = (u32)(phy_id << 16);
 471                 usec_delay(20);
 472                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 473                 if (ret_val)
 474                         goto out;
 475
 476                 phy->id |= (u32)(phy_id);
 477                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 478                 break;
 479         default:
 480                 ret_val = -E1000_ERR_PHY;
 481                 break;
 482         }
 483 out:
 484         return ret_val;
 485 }
 486
 487 /**
 488  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 489  *  @hw: pointer to the HW structure
 490  *
 491  *  Acquire the HW semaphore to access the PHY or NVM
 492  **/
 493 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 494 {
 495         u32 swsm;
 496         s32 ret_val = E1000_SUCCESS;
 497         s32 sw_timeout = hw->nvm.word_size + 1;
 498         s32 fw_timeout = hw->nvm.word_size + 1;
 499         s32 i = 0;
 500
 501         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 502
 503         /*
 504          * If we have timedout 3 times on trying to acquire
 505          * the inter-port SMBI semaphore, there is old code
 506          * operating on the other port, and it is not
 507          * releasing SMBI. Modify the number of times that
 508          * we try for the semaphore to interwork with this
 509          * older code.
 510          */
 511         if (hw->dev_spec._82571.smb_counter > 2)
 512                 sw_timeout = 1;
 513
 514         /* Get the SW semaphore */
 515         while (i < sw_timeout) {
 516                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 517                 if (!(swsm & E1000_SWSM_SMBI))
 518                         break;
 519
 520                 usec_delay(50);
 521                 i++;
 522         }
 523
 524         if (i == sw_timeout) {
 525                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 526                 hw->dev_spec._82571.smb_counter++;
 527         }
 528         /* Get the FW semaphore. */
 529         for (i = 0; i < fw_timeout; i++) {
 530                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 531                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 532
 533                 /* Semaphore acquired if bit latched */
 534                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 535                         break;
 536
 537                 usec_delay(50);
 538         }
 539
 540         if (i == fw_timeout) {
 541                 /* Release semaphores */
 542                 e1000_put_hw_semaphore_82571(hw);
 543                 DEBUGOUT("Driver can't access the NVM\n");
 544                 ret_val = -E1000_ERR_NVM;
 545                 goto out;
 546         }
 547
 548 out:
 549         return ret_val;
 550 }
 551
 552 /**
 553  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 554  *  @hw: pointer to the HW structure
 555  *
 556  *  Release hardware semaphore used to access the PHY or NVM
 557  **/
 558 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 559 {
 560         u32 swsm;
 561
 562         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 563
 564         swsm = E1000_READ_REG(hw, E1000_SWSM);
 565
 566         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 567
 568         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 569 }
 570
 571 /**
 572  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 573  *  @hw: pointer to the HW structure
 574  *
 575  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 576  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 577  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 578  *  hardware semaphore.
 579  **/
 580 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 581 {
 582         s32 ret_val;
 583
 584         DEBUGFUNC("e1000_acquire_nvm_82571");
 585
 586         ret_val = e1000_get_hw_semaphore_82571(hw);
 587         if (ret_val)
 588                 goto out;
 589
 590         switch (hw->mac.type) {
 591         case e1000_82573:
 592         case e1000_82574:
 593         case e1000_82583:
 594                 break;
 595         default:
 596                 ret_val = e1000_acquire_nvm_generic(hw);
 597                 break;
 598         }
 599
 600         if (ret_val)
 601                 e1000_put_hw_semaphore_82571(hw);
 602
 603 out:
 604         return ret_val;
 605 }
 606
 607 /**
 608  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 609  *  @hw: pointer to the HW structure
 610  *
 611  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 612  **/
 613 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 614 {
 615         DEBUGFUNC("e1000_release_nvm_82571");
 616
 617         e1000_release_nvm_generic(hw);
 618         e1000_put_hw_semaphore_82571(hw);
 619 }
 620
 621 /**
 622  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 623  *  @hw: pointer to the HW structure
 624  *  @offset: offset within the EEPROM to be written to
 625  *  @words: number of words to write
 626  *  @data: 16 bit word(s) to be written to the EEPROM
 627  *
 628  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 629  *
 630  *  If e1000_update_nvm_checksum is not called after this function, the
 631  *  EEPROM will most likely contain an invalid checksum.
 632  **/
 633 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 634                                  u16 *data)
 635 {
 636         s32 ret_val = E1000_SUCCESS;
 637
 638         DEBUGFUNC("e1000_write_nvm_82571");
 639
 640         switch (hw->mac.type) {
 641         case e1000_82573:
 642         case e1000_82574:
 643         case e1000_82583:
 644                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 645                 break;
 646         case e1000_82571:
 647         case e1000_82572:
 648                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 649                 break;
 650         default:
 651                 ret_val = -E1000_ERR_NVM;
 652                 break;
 653         }
 654
 655         return ret_val;
 656 }
 657
 658 /**
 659  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 660  *  @hw: pointer to the HW structure
 661  *
 662  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 663  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 664  *  value to the EEPROM.
 665  **/
 666 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 667 {
 668         u32 eecd;
 669         s32 ret_val;
 670         u16 i;
 671
 672         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 673
 674         ret_val = e1000_update_nvm_checksum_generic(hw);
 675         if (ret_val)
 676                 goto out;
 677
 678         /*
 679          * If our nvm is an EEPROM, then we're done
 680          * otherwise, commit the checksum to the flash NVM.
 681          */
 682         if (hw->nvm.type != e1000_nvm_flash_hw)
 683                 goto out;
 684
 685         /* Check for pending operations. */
 686         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 687                 msec_delay(1);
 688                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 689                         break;
 690         }
 691
 692         if (i == E1000_FLASH_UPDATES) {
 693                 ret_val = -E1000_ERR_NVM;
 694                 goto out;
 695         }
 696
 697         /* Reset the firmware if using STM opcode. */
 698         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 699                 /*
 700                  * The enabling of and the actual reset must be done
 701                  * in two write cycles.
 702                  */
 703                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 704                 E1000_WRITE_FLUSH(hw);
 705                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 706         }
 707
 708         /* Commit the write to flash */
 709         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 710         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 711
 712         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 713                 msec_delay(1);
 714                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 715                         break;
 716         }
 717
 718         if (i == E1000_FLASH_UPDATES) {
 719                 ret_val = -E1000_ERR_NVM;
 720                 goto out;
 721         }
 722
 723 out:
 724         return ret_val;
 725 }
 726
 727 /**
 728  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 729  *  @hw: pointer to the HW structure
 730  *
 731  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 732  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 733  **/
 734 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 735 {
 736         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 737
 738         if (hw->nvm.type == e1000_nvm_flash_hw)
 739                 e1000_fix_nvm_checksum_82571(hw);
 740
 741         return e1000_validate_nvm_checksum_generic(hw);
 742 }
 743
 744 /**
 745  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 746  *  @hw: pointer to the HW structure
 747  *  @offset: offset within the EEPROM to be written to
 748  *  @words: number of words to write
 749  *  @data: 16 bit word(s) to be written to the EEPROM
 750  *
 751  *  After checking for invalid values, poll the EEPROM to ensure the previous
 752  *  command has completed before trying to write the next word.  After write
 753  *  poll for completion.
 754  *
 755  *  If e1000_update_nvm_checksum is not called after this function, the
 756  *  EEPROM will most likely contain an invalid checksum.
 757  **/
 758 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 759                                       u16 words, u16 *data)
 760 {
 761         struct e1000_nvm_info *nvm = &hw->nvm;
 762         u32 i, eewr = 0;
 763         s32 ret_val = 0;
 764
 765         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 766
 767         /*
 768          * A check for invalid values:  offset too large, too many words,
 769          * and not enough words.
 770          */
 771         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 772             (words == 0)) {
 773                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 774                 ret_val = -E1000_ERR_NVM;
 775                 goto out;
 776         }
 777
 778         for (i = 0; i < words; i++) {
 779                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 780                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 781                        E1000_NVM_RW_REG_START;
 782
 783                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 784                 if (ret_val)
 785                         break;
 786
 787                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 788
 789                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 790                 if (ret_val)
 791                         break;
 792         }
 793
 794 out:
 795         return ret_val;
 796 }
 797
 798 /**
 799  *  e1000_get_cfg_done_82571 - Poll for configuration done
 800  *  @hw: pointer to the HW structure
 801  *
 802  *  Reads the management control register for the config done bit to be set.
 803  **/
 804 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 805 {
 806         s32 timeout = PHY_CFG_TIMEOUT;
 807         s32 ret_val = E1000_SUCCESS;
 808
 809         DEBUGFUNC("e1000_get_cfg_done_82571");
 810
 811         while (timeout) {
 812                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 813                     E1000_NVM_CFG_DONE_PORT_0)
 814                         break;
 815                 msec_delay(1);
 816                 timeout--;
 817         }
 818         if (!timeout) {
 819                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 820                 ret_val = -E1000_ERR_RESET;
 821                 goto out;
 822         }
 823
 824 out:
 825         return ret_val;
 826 }
 827
 828 /**
 829  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 830  *  @hw: pointer to the HW structure
 831  *  @active: TRUE to enable LPLU, FALSE to disable
 832  *
 833  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 834  *  this function also disables smart speed and vice versa.  LPLU will not be
 835  *  activated unless the device autonegotiation advertisement meets standards
 836  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 837  *  pointer entry point only called by PHY setup routines.
 838  **/
 839 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 840 {
 841         struct e1000_phy_info *phy = &hw->phy;
 842         s32 ret_val = E1000_SUCCESS;
 843         u16 data;
 844
 845         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 846
 847         if (!(phy->ops.read_reg))
 848                 goto out;
 849
 850         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 851         if (ret_val)
 852                 goto out;
 853
 854         if (active) {
 855                 data |= IGP02E1000_PM_D0_LPLU;
 856                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 857                                              data);
 858                 if (ret_val)
 859                         goto out;
 860
 861                 /* When LPLU is enabled, we should disable SmartSpeed */
 862                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 863                                             &data);
 864                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 865                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 866                                              data);
 867                 if (ret_val)
 868                         goto out;
 869         } else {
 870                 data &= ~IGP02E1000_PM_D0_LPLU;
 871                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 872                                              data);
 873                 /*
 874                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 875                  * during Dx states where the power conservation is most
 876                  * important.  During driver activity we should enable
 877                  * SmartSpeed, so performance is maintained.
 878                  */
 879                 if (phy->smart_speed == e1000_smart_speed_on) {
 880                         ret_val = phy->ops.read_reg(hw,
 881                                                     IGP01E1000_PHY_PORT_CONFIG,
 882                                                     &data);
 883                         if (ret_val)
 884                                 goto out;
 885
 886                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 887                         ret_val = phy->ops.write_reg(hw,
 888                                                      IGP01E1000_PHY_PORT_CONFIG,
 889                                                      data);
 890                         if (ret_val)
 891                                 goto out;
 892                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 893                         ret_val = phy->ops.read_reg(hw,
 894                                                     IGP01E1000_PHY_PORT_CONFIG,
 895                                                     &data);
 896                         if (ret_val)
 897                                 goto out;
 898
 899                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 900                         ret_val = phy->ops.write_reg(hw,
 901                                                      IGP01E1000_PHY_PORT_CONFIG,
 902                                                      data);
 903                         if (ret_val)
 904                                 goto out;
 905                 }
 906         }
 907
 908 out:
 909         return ret_val;
 910 }
 911
 912 /**
 913  *  e1000_reset_hw_82571 - Reset hardware
 914  *  @hw: pointer to the HW structure
 915  *
 916  *  This resets the hardware into a known state.
 917  **/
 918 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 919 {
 920         u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
 921         s32 ret_val;
 922         u16 i = 0;
 923
 924         DEBUGFUNC("e1000_reset_hw_82571");
 925
 926         /*
 927          * Prevent the PCI-E bus from sticking if there is no TLP connection
 928          * on the last TLP read/write transaction when MAC is reset.
 929          */
 930         ret_val = e1000_disable_pcie_master_generic(hw);
 931         if (ret_val)
 932                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
 933
 934         DEBUGOUT("Masking off all interrupts\n");
 935         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 936
 937         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 938         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 939         E1000_WRITE_FLUSH(hw);
 940
 941         msec_delay(10);
 942
 943         /*
 944          * Must acquire the MDIO ownership before MAC reset.
 945          * Ownership defaults to firmware after a reset.
 946          */
 947         switch (hw->mac.type) {
 948         case e1000_82573:
 949         case e1000_82574:
 950         case e1000_82583:
 951                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 952                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 953
 954                 do {
 955                         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 956                         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 957
 958                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 959                                 break;
 960
 961                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 962
 963                         msec_delay(2);
 964                         i++;
 965                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 966                 break;
 967         default:
 968                 break;
 969         }
 970
 971         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 972
 973         DEBUGOUT("Issuing a global reset to MAC\n");
 974         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 975
 976         if (hw->nvm.type == e1000_nvm_flash_hw) {
 977                 usec_delay(10);
 978                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 979                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 980                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 981                 E1000_WRITE_FLUSH(hw);
 982         }
 983
 984         ret_val = e1000_get_auto_rd_done_generic(hw);
 985         if (ret_val)
 986                 /* We don't want to continue accessing MAC registers. */
 987                 goto out;
 988
 989         /*
 990          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 991          * Need to wait for Phy configuration completion before accessing
 992          * NVM and Phy.
 993          */
 994
 995         switch (hw->mac.type) {
 996         case e1000_82573:
 997         case e1000_82574:
 998         case e1000_82583:
 999                 msec_delay(25);
1000                 break;
1001         default:
1002                 break;
1003         }
1004
1005         /* Clear any pending interrupt events. */
1006         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1007         icr = E1000_READ_REG(hw, E1000_ICR);
1008
1009         /* Install any alternate MAC address into RAR0 */
1010         ret_val = e1000_check_alt_mac_addr_generic(hw);
1011         if (ret_val)
1012                 goto out;
1013
1014         e1000_set_laa_state_82571(hw, TRUE);
1015
1016         /* Reinitialize the 82571 serdes link state machine */
1017         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1018                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1019
1020 out:
1021         return ret_val;
1022 }
1023
1024 /**
1025  *  e1000_init_hw_82571 - Initialize hardware
1026  *  @hw: pointer to the HW structure
1027  *
1028  *  This inits the hardware readying it for operation.
1029  **/
1030 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1031 {
1032         struct e1000_mac_info *mac = &hw->mac;
1033         u32 reg_data;
1034         s32 ret_val;
1035         u16 i, rar_count = mac->rar_entry_count;
1036
1037         DEBUGFUNC("e1000_init_hw_82571");
1038
1039         e1000_initialize_hw_bits_82571(hw);
1040
1041         /* Initialize identification LED */
1042         ret_val = mac->ops.id_led_init(hw);
1043         if (ret_val)
1044                 DEBUGOUT("Error initializing identification LED\n");
1045                 /* This is not fatal and we should not stop init due to this */
1046
1047         /* Disabling VLAN filtering */
1048         DEBUGOUT("Initializing the IEEE VLAN\n");
1049         mac->ops.clear_vfta(hw);
1050
1051         /* Setup the receive address. */
1052         /*
1053          * If, however, a locally administered address was assigned to the
1054          * 82571, we must reserve a RAR for it to work around an issue where
1055          * resetting one port will reload the MAC on the other port.
1056          */
1057         if (e1000_get_laa_state_82571(hw))
1058                 rar_count--;
1059         e1000_init_rx_addrs_generic(hw, rar_count);
1060
1061         /* Zero out the Multicast HASH table */
1062         DEBUGOUT("Zeroing the MTA\n");
1063         for (i = 0; i < mac->mta_reg_count; i++)
1064                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1065
1066         /* Setup link and flow control */
1067         ret_val = mac->ops.setup_link(hw);
1068
1069         /* Set the transmit descriptor write-back policy */
1070         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1071         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1072                    E1000_TXDCTL_FULL_TX_DESC_WB |
1073                    E1000_TXDCTL_COUNT_DESC;
1074         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1075
1076         /* ...for both queues. */
1077         switch (mac->type) {
1078         case e1000_82573:
1079         case e1000_82574:
1080         case e1000_82583:
1081                 e1000_enable_tx_pkt_filtering_generic(hw);
1082                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1083                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1084                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1085                 break;
1086         default:
1087                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1088                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1089                            E1000_TXDCTL_FULL_TX_DESC_WB |
1090                            E1000_TXDCTL_COUNT_DESC;
1091                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1092                 break;
1093         }
1094
1095         /*
1096          * Clear all of the statistics registers (clear on read).  It is
1097          * important that we do this after we have tried to establish link
1098          * because the symbol error count will increment wildly if there
1099          * is no link.
1100          */
1101         e1000_clear_hw_cntrs_82571(hw);
1102
1103         return ret_val;
1104 }
1105
1106 /**
1107  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1108  *  @hw: pointer to the HW structure
1109  *
1110  *  Initializes required hardware-dependent bits needed for normal operation.
1111  **/
1112 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1113 {
1114         u32 reg;
1115
1116         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1117
1118         /* Transmit Descriptor Control 0 */
1119         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1120         reg |= (1 << 22);
1121         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1122
1123         /* Transmit Descriptor Control 1 */
1124         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1125         reg |= (1 << 22);
1126         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1127
1128         /* Transmit Arbitration Control 0 */
1129         reg = E1000_READ_REG(hw, E1000_TARC(0));
1130         reg &= ~(0xF << 27); /* 30:27 */
1131         switch (hw->mac.type) {
1132         case e1000_82571:
1133         case e1000_82572:
1134                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1135                 break;
1136         default:
1137                 break;
1138         }
1139         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1140
1141         /* Transmit Arbitration Control 1 */
1142         reg = E1000_READ_REG(hw, E1000_TARC(1));
1143         switch (hw->mac.type) {
1144         case e1000_82571:
1145         case e1000_82572:
1146                 reg &= ~((1 << 29) | (1 << 30));
1147                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1148                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1149                         reg &= ~(1 << 28);
1150                 else
1151                         reg |= (1 << 28);
1152                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1153                 break;
1154         default:
1155                 break;
1156         }
1157
1158         /* Device Control */
1159         switch (hw->mac.type) {
1160         case e1000_82573:
1161         case e1000_82574:
1162         case e1000_82583:
1163                 reg = E1000_READ_REG(hw, E1000_CTRL);
1164                 reg &= ~(1 << 29);
1165                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1166                 break;
1167         default:
1168                 break;
1169         }
1170
1171         /* Extended Device Control */
1172         switch (hw->mac.type) {
1173         case e1000_82573:
1174         case e1000_82574:
1175         case e1000_82583:
1176                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1177                 reg &= ~(1 << 23);
1178                 reg |= (1 << 22);
1179                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1180                 break;
1181         default:
1182                 break;
1183         }
1184
1185         if (hw->mac.type == e1000_82571) {
1186                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1187                 reg |= E1000_PBA_ECC_CORR_EN;
1188                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1189         }
1190
1191         /*
1192          * Workaround for hardware errata.
1193          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1194          */
1195         if ((hw->mac.type == e1000_82571) ||
1196            (hw->mac.type == e1000_82572)) {
1197                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1198                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1199                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1200         }
1201
1202         /* PCI-Ex Control Registers */
1203         switch (hw->mac.type) {
1204         case e1000_82574:
1205         case e1000_82583:
1206                 reg = E1000_READ_REG(hw, E1000_GCR);
1207                 reg |= (1 << 22);
1208                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1209
1210                 /*
1211                  * Workaround for hardware errata.
1212                  * apply workaround for hardware errata documented in errata
1213                  * docs Fixes issue where some error prone or unreliable PCIe
1214                  * completions are occurring, particularly with ASPM enabled.
1215                  * Without fix, issue can cause tx timeouts.
1216                  */
1217                 reg = E1000_READ_REG(hw, E1000_GCR2);
1218                 reg |= 1;
1219                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1220                 break;
1221         default:
1222                 break;
1223         }
1224
1225         return;
1226 }
1227
1228 /**
1229  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1230  *  @hw: pointer to the HW structure
1231  *
1232  *  Clears the register array which contains the VLAN filter table by
1233  *  setting all the values to 0.
1234  **/
1235 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1236 {
1237         u32 offset;
1238         u32 vfta_value = 0;
1239         u32 vfta_offset = 0;
1240         u32 vfta_bit_in_reg = 0;
1241
1242         DEBUGFUNC("e1000_clear_vfta_82571");
1243
1244         switch (hw->mac.type) {
1245         case e1000_82573:
1246         case e1000_82574:
1247         case e1000_82583:
1248                 if (hw->mng_cookie.vlan_id != 0) {
1249                         /*
1250                          * The VFTA is a 4096b bit-field, each identifying
1251                          * a single VLAN ID.  The following operations
1252                          * determine which 32b entry (i.e. offset) into the
1253                          * array we want to set the VLAN ID (i.e. bit) of
1254                          * the manageability unit.
1255                          */
1256                         vfta_offset = (hw->mng_cookie.vlan_id >>
1257                                 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1258                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1259                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1260                 }
1261                 break;
1262         default:
1263                 break;
1264         }
1265         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1266                 /*
1267                  * If the offset we want to clear is the same offset of the
1268                  * manageability VLAN ID, then clear all bits except that of
1269                  * the manageability unit.
1270                  */
1271                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1272                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1273                 E1000_WRITE_FLUSH(hw);
1274         }
1275 }
1276
1277 /**
1278  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1279  *  @hw: pointer to the HW structure
1280  *
1281  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1282  *  (>0) if any manageability is enabled, else FALSE (0).
1283  **/
1284 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1285 {
1286         u16 data;
1287
1288         DEBUGFUNC("e1000_check_mng_mode_82574");
1289
1290         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1291         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1292 }
1293
1294 /**
1295  *  e1000_led_on_82574 - Turn LED on
1296  *  @hw: pointer to the HW structure
1297  *
1298  *  Turn LED on.
1299  **/
1300 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1301 {
1302         u32 ctrl;
1303         u32 i;
1304
1305         DEBUGFUNC("e1000_led_on_82574");
1306
1307         ctrl = hw->mac.ledctl_mode2;
1308         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1309                 /*
1310                  * If no link, then turn LED on by setting the invert bit
1311                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1312                  */
1313                 for (i = 0; i < 4; i++)
1314                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1315                             E1000_LEDCTL_MODE_LED_ON)
1316                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1317         }
1318         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1319
1320         return E1000_SUCCESS;
1321 }
1322
1323
1324 /**
1325  *  e1000_setup_link_82571 - Setup flow control and link settings
1326  *  @hw: pointer to the HW structure
1327  *
1328  *  Determines which flow control settings to use, then configures flow
1329  *  control.  Calls the appropriate media-specific link configuration
1330  *  function.  Assuming the adapter has a valid link partner, a valid link
1331  *  should be established.  Assumes the hardware has previously been reset
1332  *  and the transmitter and receiver are not enabled.
1333  **/
1334 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1335 {
1336         DEBUGFUNC("e1000_setup_link_82571");
1337
1338         /*
1339          * 82573 does not have a word in the NVM to determine
1340          * the default flow control setting, so we explicitly
1341          * set it to full.
1342          */
1343         switch (hw->mac.type) {
1344         case e1000_82573:
1345         case e1000_82574:
1346         case e1000_82583:
1347                 if (hw->fc.requested_mode == e1000_fc_default)
1348                         hw->fc.requested_mode = e1000_fc_full;
1349                 break;
1350         default:
1351                 break;
1352         }
1353         return e1000_setup_link_generic(hw);
1354 }
1355
1356 /**
1357  *  e1000_setup_copper_link_82571 - Configure copper link settings
1358  *  @hw: pointer to the HW structure
1359  *
1360  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1361  *  for link, once link is established calls to configure collision distance
1362  *  and flow control are called.
1363  **/
1364 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1365 {
1366         u32 ctrl;
1367         s32  ret_val;
1368
1369         DEBUGFUNC("e1000_setup_copper_link_82571");
1370
1371         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1372         ctrl |= E1000_CTRL_SLU;
1373         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1374         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1375
1376         switch (hw->phy.type) {
1377         case e1000_phy_m88:
1378         case e1000_phy_bm:
1379                 ret_val = e1000_copper_link_setup_m88(hw);
1380                 break;
1381         case e1000_phy_igp_2:
1382                 ret_val = e1000_copper_link_setup_igp(hw);
1383                 break;
1384         default:
1385                 ret_val = -E1000_ERR_PHY;
1386                 break;
1387         }
1388
1389         if (ret_val)
1390                 goto out;
1391
1392         ret_val = e1000_setup_copper_link_generic(hw);
1393
1394 out:
1395         return ret_val;
1396 }
1397
1398 /**
1399  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1400  *  @hw: pointer to the HW structure
1401  *
1402  *  Configures collision distance and flow control for fiber and serdes links.
1403  *  Upon successful setup, poll for link.
1404  **/
1405 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1406 {
1407         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1408
1409         switch (hw->mac.type) {
1410         case e1000_82571:
1411         case e1000_82572:
1412                 /*
1413                  * If SerDes loopback mode is entered, there is no form
1414                  * of reset to take the adapter out of that mode.  So we
1415                  * have to explicitly take the adapter out of loopback
1416                  * mode.  This prevents drivers from twiddling their thumbs
1417                  * if another tool failed to take it out of loopback mode.
1418                  */
1419                 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1420                 break;
1421         default:
1422                 break;
1423         }
1424
1425         return e1000_setup_fiber_serdes_link_generic(hw);
1426 }
1427
1428 /**
1429  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1430  *  @hw: pointer to the HW structure
1431  *
1432  *  Reports the link state as up or down.
1433  *
1434  *  If autonegotiation is supported by the link partner, the link state is
1435  *  determined by the result of autonegotiation. This is the most likely case.
1436  *  If autonegotiation is not supported by the link partner, and the link
1437  *  has a valid signal, force the link up.
1438  *
1439  *  The link state is represented internally here by 4 states:
1440  *
1441  *  1) down
1442  *  2) autoneg_progress
1443  *  3) autoneg_complete (the link sucessfully autonegotiated)
1444  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1445  *
1446  **/
1447 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1448 {
1449         struct e1000_mac_info *mac = &hw->mac;
1450         u32 rxcw;
1451         u32 ctrl;
1452         u32 status;
1453         s32 ret_val = E1000_SUCCESS;
1454
1455         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1456
1457         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1458         status = E1000_READ_REG(hw, E1000_STATUS);
1459         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1460
1461         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1462
1463                 /* Receiver is synchronized with no invalid bits.  */
1464                 switch (mac->serdes_link_state) {
1465                 case e1000_serdes_link_autoneg_complete:
1466                         if (!(status & E1000_STATUS_LU)) {
1467                                 /*
1468                                  * We have lost link, retry autoneg before
1469                                  * reporting link failure
1470                                  */
1471                                 mac->serdes_link_state =
1472                                     e1000_serdes_link_autoneg_progress;
1473                                 mac->serdes_has_link = FALSE;
1474                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1475                         }
1476                 break;
1477
1478                 case e1000_serdes_link_forced_up:
1479                         /*
1480                          * If we are receiving /C/ ordered sets, re-enable
1481                          * auto-negotiation in the TXCW register and disable
1482                          * forced link in the Device Control register in an
1483                          * attempt to auto-negotiate with our link partner.
1484                          */
1485                         if (rxcw & E1000_RXCW_C) {
1486                                 /* Enable autoneg, and unforce link up */
1487                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1488                                 E1000_WRITE_REG(hw, E1000_CTRL,
1489                                     (ctrl & ~E1000_CTRL_SLU));
1490                                 mac->serdes_link_state =
1491                                     e1000_serdes_link_autoneg_progress;
1492                                 mac->serdes_has_link = FALSE;
1493                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1494                         }
1495                         break;
1496
1497                 case e1000_serdes_link_autoneg_progress:
1498                         if (rxcw & E1000_RXCW_C) {
1499                                 /*
1500                                  * We received /C/ ordered sets, meaning the
1501                                  * link partner has autonegotiated, and we can
1502                                  * trust the Link Up (LU) status bit.
1503                                  */
1504                                 if (status & E1000_STATUS_LU) {
1505                                         mac->serdes_link_state =
1506                                             e1000_serdes_link_autoneg_complete;
1507                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1508                                         mac->serdes_has_link = TRUE;
1509                                 } else {
1510                                         /* Autoneg completed, but failed. */
1511                                         mac->serdes_link_state =
1512                                             e1000_serdes_link_down;
1513                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1514                                 }
1515                         } else {
1516                                 /*
1517                                  * The link partner did not autoneg.
1518                                  * Force link up and full duplex, and change
1519                                  * state to forced.
1520                                  */
1521                                 E1000_WRITE_REG(hw, E1000_TXCW,
1522                                 (mac->txcw & ~E1000_TXCW_ANE));
1523                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1524                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1525
1526                                 /* Configure Flow Control after link up. */
1527                                 ret_val =
1528                                     e1000_config_fc_after_link_up_generic(hw);
1529                                 if (ret_val) {
1530                                         DEBUGOUT("Error config flow control\n");
1531                                         break;
1532                                 }
1533                                 mac->serdes_link_state =
1534                                 e1000_serdes_link_forced_up;
1535                                 mac->serdes_has_link = TRUE;
1536                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1537                         }
1538                         break;
1539
1540                 case e1000_serdes_link_down:
1541                 default:
1542                         /*
1543                          * The link was down but the receiver has now gained
1544                          * valid sync, so lets see if we can bring the link
1545                          * up.
1546                          */
1547                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1548                         E1000_WRITE_REG(hw, E1000_CTRL,
1549                             (ctrl & ~E1000_CTRL_SLU));
1550                         mac->serdes_link_state =
1551                             e1000_serdes_link_autoneg_progress;
1552                         DEBUGOUT("DOWN      -> AN_PROG\n");
1553                         break;
1554                 }
1555         } else {
1556                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1557                         mac->serdes_has_link = FALSE;
1558                         mac->serdes_link_state = e1000_serdes_link_down;
1559                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1560                 } else {
1561                         /*
1562                          * We have sync, and can tolerate one invalid (IV)
1563                          * codeword before declaring link down, so reread
1564                          * to look again.
1565                          */
1566                         usec_delay(10);
1567                         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1568                         if (rxcw & E1000_RXCW_IV) {
1569                                 mac->serdes_link_state = e1000_serdes_link_down;
1570                                 mac->serdes_has_link = FALSE;
1571                                 DEBUGOUT("ANYSTATE  -> DOWN\n");
1572                         }
1573                 }
1574         }
1575
1576         return ret_val;
1577 }
1578
1579 /**
1580  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1581  *  @hw: pointer to the HW structure
1582  *  @data: pointer to the NVM (EEPROM)
1583  *
1584  *  Read the EEPROM for the current default LED configuration.  If the
1585  *  LED configuration is not valid, set to a valid LED configuration.
1586  **/
1587 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1588 {
1589         s32 ret_val;
1590
1591         DEBUGFUNC("e1000_valid_led_default_82571");
1592
1593         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1594         if (ret_val) {
1595                 DEBUGOUT("NVM Read Error\n");
1596                 goto out;
1597         }
1598
1599         switch (hw->mac.type) {
1600         case e1000_82573:
1601         case e1000_82574:
1602         case e1000_82583:
1603                 if (*data == ID_LED_RESERVED_F746)
1604                         *data = ID_LED_DEFAULT_82573;
1605                 break;
1606         default:
1607                 if (*data == ID_LED_RESERVED_0000 ||
1608                     *data == ID_LED_RESERVED_FFFF)
1609                         *data = ID_LED_DEFAULT;
1610                 break;
1611         }
1612
1613 out:
1614         return ret_val;
1615 }
1616
1617 /**
1618  *  e1000_get_laa_state_82571 - Get locally administered address state
1619  *  @hw: pointer to the HW structure
1620  *
1621  *  Retrieve and return the current locally administered address state.
1622  **/
1623 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1624 {
1625         DEBUGFUNC("e1000_get_laa_state_82571");
1626
1627         if (hw->mac.type != e1000_82571)
1628                 return FALSE;
1629
1630         return hw->dev_spec._82571.laa_is_present;
1631 }
1632
1633 /**
1634  *  e1000_set_laa_state_82571 - Set locally administered address state
1635  *  @hw: pointer to the HW structure
1636  *  @state: enable/disable locally administered address
1637  *
1638  *  Enable/Disable the current locally administered address state.
1639  **/
1640 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1641 {
1642         DEBUGFUNC("e1000_set_laa_state_82571");
1643
1644         if (hw->mac.type != e1000_82571)
1645                 return;
1646
1647         hw->dev_spec._82571.laa_is_present = state;
1648
1649         /* If workaround is activated... */
1650         if (state)
1651                 /*
1652                  * Hold a copy of the LAA in RAR[14] This is done so that
1653                  * between the time RAR[0] gets clobbered and the time it
1654                  * gets fixed, the actual LAA is in one of the RARs and no
1655                  * incoming packets directed to this port are dropped.
1656                  * Eventually the LAA will be in RAR[0] and RAR[14].
1657                  */
1658                 e1000_rar_set_generic(hw, hw->mac.addr,
1659                                       hw->mac.rar_entry_count - 1);
1660         return;
1661 }
1662
1663 /**
1664  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1665  *  @hw: pointer to the HW structure
1666  *
1667  *  Verifies that the EEPROM has completed the update.  After updating the
1668  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1669  *  the checksum fix is not implemented, we need to set the bit and update
1670  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1671  *  we need to return bad checksum.
1672  **/
1673 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1674 {
1675         struct e1000_nvm_info *nvm = &hw->nvm;
1676         s32 ret_val = E1000_SUCCESS;
1677         u16 data;
1678
1679         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1680
1681         if (nvm->type != e1000_nvm_flash_hw)
1682                 goto out;
1683
1684         /*
1685          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1686          * 10h-12h.  Checksum may need to be fixed.
1687          */
1688         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1689         if (ret_val)
1690                 goto out;
1691
1692         if (!(data & 0x10)) {
1693                 /*
1694                  * Read 0x23 and check bit 15.  This bit is a 1
1695                  * when the checksum has already been fixed.  If
1696                  * the checksum is still wrong and this bit is a
1697                  * 1, we need to return bad checksum.  Otherwise,
1698                  * we need to set this bit to a 1 and update the
1699                  * checksum.
1700                  */
1701                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1702                 if (ret_val)
1703                         goto out;
1704
1705                 if (!(data & 0x8000)) {
1706                         data |= 0x8000;
1707                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1708                         if (ret_val)
1709                                 goto out;
1710                         ret_val = nvm->ops.update(hw);
1711                 }
1712         }
1713
1714 out:
1715         return ret_val;
1716 }
1717
1718
1719 /**
1720  *  e1000_read_mac_addr_82571 - Read device MAC address
1721  *  @hw: pointer to the HW structure
1722  **/
1723 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1724 {
1725         s32 ret_val = E1000_SUCCESS;
1726
1727         DEBUGFUNC("e1000_read_mac_addr_82571");
1728
1729         /*
1730          * If there's an alternate MAC address place it in RAR0
1731          * so that it will override the Si installed default perm
1732          * address.
1733          */
1734         ret_val = e1000_check_alt_mac_addr_generic(hw);
1735         if (ret_val)
1736                 goto out;
1737
1738         ret_val = e1000_read_mac_addr_generic(hw);
1739
1740 out:
1741         return ret_val;
1742 }
1743
1744 /**
1745  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1746  * @hw: pointer to the HW structure
1747  *
1748  * In the case of a PHY power down to save power, or to turn off link during a
1749  * driver unload, or wake on lan is not enabled, remove the link.
1750  **/
1751 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1752 {
1753         struct e1000_phy_info *phy = &hw->phy;
1754         struct e1000_mac_info *mac = &hw->mac;
1755
1756         if (!(phy->ops.check_reset_block))
1757                 return;
1758
1759         /* If the management interface is not enabled, then power down */
1760         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1761                 e1000_power_down_phy_copper(hw);
1762
1763         return;
1764 }
1765
1766 /**
1767  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1768  *  @hw: pointer to the HW structure
1769  *
1770  *  Clears the hardware counters by reading the counter registers.
1771  **/
1772 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1773 {
1774         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1775
1776         e1000_clear_hw_cntrs_base_generic(hw);
1777
1778         E1000_READ_REG(hw, E1000_PRC64);
1779         E1000_READ_REG(hw, E1000_PRC127);
1780         E1000_READ_REG(hw, E1000_PRC255);
1781         E1000_READ_REG(hw, E1000_PRC511);
1782         E1000_READ_REG(hw, E1000_PRC1023);
1783         E1000_READ_REG(hw, E1000_PRC1522);
1784         E1000_READ_REG(hw, E1000_PTC64);
1785         E1000_READ_REG(hw, E1000_PTC127);
1786         E1000_READ_REG(hw, E1000_PTC255);
1787         E1000_READ_REG(hw, E1000_PTC511);
1788         E1000_READ_REG(hw, E1000_PTC1023);
1789         E1000_READ_REG(hw, E1000_PTC1522);
1790
1791         E1000_READ_REG(hw, E1000_ALGNERRC);
1792         E1000_READ_REG(hw, E1000_RXERRC);
1793         E1000_READ_REG(hw, E1000_TNCRS);
1794         E1000_READ_REG(hw, E1000_CEXTERR);
1795         E1000_READ_REG(hw, E1000_TSCTC);
1796         E1000_READ_REG(hw, E1000_TSCTFC);
1797
1798         E1000_READ_REG(hw, E1000_MGTPRC);
1799         E1000_READ_REG(hw, E1000_MGTPDC);
1800         E1000_READ_REG(hw, E1000_MGTPTC);
1801
1802         E1000_READ_REG(hw, E1000_IAC);
1803         E1000_READ_REG(hw, E1000_ICRXOC);
1804
1805         E1000_READ_REG(hw, E1000_ICRXPTC);
1806         E1000_READ_REG(hw, E1000_ICRXATC);
1807         E1000_READ_REG(hw, E1000_ICTXPTC);
1808         E1000_READ_REG(hw, E1000_ICTXATC);
1809         E1000_READ_REG(hw, E1000_ICTXQEC);
1810         E1000_READ_REG(hw, E1000_ICTXQMTC);
1811         E1000_READ_REG(hw, E1000_ICRXDMTC);
1812 }