2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/i386/i386/Attic/identcpu.c,v 1.2 2003/06/17 04:28:35 dillon Exp $
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
52 #include <machine/asmacros.h>
53 #include <machine/clock.h>
54 #include <machine/cputypes.h>
55 #include <machine/segments.h>
56 #include <machine/specialreg.h>
57 #include <machine/md_var.h>
59 #include <i386/isa/intr_machdep.h>
61 #define IDENTBLUE_CYRIX486 0
62 #define IDENTBLUE_IBMCPU 1
63 #define IDENTBLUE_CYRIXM2 2
65 /* XXX - should be in header file: */
66 void printcpuinfo(void);
67 void finishidentcpu(void);
68 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
69 void enable_K5_wt_alloc(void);
70 void enable_K6_wt_alloc(void);
71 void enable_K6_2_wt_alloc(void);
73 void panicifcpuunsupported(void);
75 static void identifycyrix(void);
76 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
77 static void print_AMD_features(void);
79 static void print_AMD_info(void);
80 static void print_AMD_assoc(int i);
81 static void print_transmeta_info(void);
82 static void setup_tmx86_longrun(void);
84 int cpu_class = CPUCLASS_386;
85 u_int cpu_exthigh; /* Highest arg to extended CPUID */
86 u_int cyrix_did; /* Device ID of Cyrix CPU */
87 char machine[] = "i386";
88 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
89 machine, 0, "Machine class");
91 static char cpu_model[128];
92 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
93 cpu_model, 0, "Machine model");
95 static char cpu_brand[48];
97 #define MAX_BRAND_INDEX 8
99 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
103 "Intel Pentium III Xeon",
111 static struct cpu_nameclass i386_cpus[] = {
112 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
113 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
114 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
115 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
116 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
117 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
118 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
119 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
120 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
121 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
122 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
123 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
124 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
125 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
126 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
127 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
128 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
131 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
132 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
138 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
143 cpu_class = i386_cpus[cpu].cpu_class;
145 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
147 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
148 /* Check for extended CPUID information and a processor name. */
150 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
151 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
152 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
153 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
154 do_cpuid(0x80000000, regs);
155 if (regs[0] >= 0x80000000) {
156 cpu_exthigh = regs[0];
157 if (cpu_exthigh >= 0x80000004) {
159 for (i = 0x80000002; i < 0x80000005; i++) {
161 memcpy(brand, regs, sizeof(regs));
162 brand += sizeof(regs);
168 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
169 if ((cpu_id & 0xf00) > 0x300) {
174 switch (cpu_id & 0x3000) {
176 strcpy(cpu_model, "Overdrive ");
179 strcpy(cpu_model, "Dual ");
183 switch (cpu_id & 0xf00) {
185 strcat(cpu_model, "i486 ");
186 /* Check the particular flavor of 486 */
187 switch (cpu_id & 0xf0) {
190 strcat(cpu_model, "DX");
193 strcat(cpu_model, "SX");
196 strcat(cpu_model, "DX2");
199 strcat(cpu_model, "SL");
202 strcat(cpu_model, "SX2");
206 "DX2 Write-Back Enhanced");
209 strcat(cpu_model, "DX4");
214 /* Check the particular flavor of 586 */
215 strcat(cpu_model, "Pentium");
216 switch (cpu_id & 0xf0) {
218 strcat(cpu_model, " A-step");
221 strcat(cpu_model, "/P5");
224 strcat(cpu_model, "/P54C");
227 strcat(cpu_model, "/P54T Overdrive");
230 strcat(cpu_model, "/P55C");
233 strcat(cpu_model, "/P54C");
236 strcat(cpu_model, "/P55C (quarter-micron)");
242 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
244 * XXX - If/when Intel fixes the bug, this
245 * should also check the version of the
246 * CPU, not just that it's a Pentium.
252 /* Check the particular flavor of 686 */
253 switch (cpu_id & 0xf0) {
255 strcat(cpu_model, "Pentium Pro A-step");
258 strcat(cpu_model, "Pentium Pro");
264 "Pentium II/Pentium II Xeon/Celeron");
272 "Pentium III/Pentium III Xeon/Celeron");
276 strcat(cpu_model, "Unknown 80686");
281 strcat(cpu_model, "Pentium 4");
285 strcat(cpu_model, "unknown");
290 * If we didn't get a brand name from the extended
291 * CPUID, try to look it up in the brand table.
293 if (cpu_high > 0 && *cpu_brand == '\0') {
294 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
295 if (brand_index <= MAX_BRAND_INDEX &&
296 cpu_brandtable[brand_index] != NULL)
298 cpu_brandtable[brand_index]);
301 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
303 * Values taken from AMD Processor Recognition
304 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
305 * (also describes ``Features'' encodings.
307 strcpy(cpu_model, "AMD ");
308 switch (cpu_id & 0xFF0) {
310 strcat(cpu_model, "Standard Am486DX");
313 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
316 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
319 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
322 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
325 strcat(cpu_model, "Am5x86 Write-Through");
328 strcat(cpu_model, "Am5x86 Write-Back");
331 strcat(cpu_model, "K5 model 0");
335 strcat(cpu_model, "K5 model 1");
338 strcat(cpu_model, "K5 PR166 (model 2)");
341 strcat(cpu_model, "K5 PR200 (model 3)");
344 strcat(cpu_model, "K6");
347 strcat(cpu_model, "K6 266 (model 1)");
350 strcat(cpu_model, "K6-2");
353 strcat(cpu_model, "K6-III");
356 strcat(cpu_model, "Unknown");
359 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
360 if ((cpu_id & 0xf00) == 0x500) {
361 if (((cpu_id & 0x0f0) > 0)
362 && ((cpu_id & 0x0f0) < 0x60)
363 && ((cpu_id & 0x00f) > 3))
364 enable_K5_wt_alloc();
365 else if (((cpu_id & 0x0f0) > 0x80)
366 || (((cpu_id & 0x0f0) == 0x80)
367 && (cpu_id & 0x00f) > 0x07))
368 enable_K6_2_wt_alloc();
369 else if ((cpu_id & 0x0f0) > 0x50)
370 enable_K6_wt_alloc();
373 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
374 strcpy(cpu_model, "Cyrix ");
375 switch (cpu_id & 0xff0) {
377 strcat(cpu_model, "MediaGX");
380 strcat(cpu_model, "6x86");
383 cpu_class = CPUCLASS_586;
384 strcat(cpu_model, "GXm");
387 strcat(cpu_model, "6x86MX");
391 * Even though CPU supports the cpuid
392 * instruction, it can be disabled.
393 * Therefore, this routine supports all Cyrix
396 switch (cyrix_did & 0xf0) {
398 switch (cyrix_did & 0x0f) {
400 strcat(cpu_model, "486SLC");
403 strcat(cpu_model, "486DLC");
406 strcat(cpu_model, "486SLC2");
409 strcat(cpu_model, "486DLC2");
412 strcat(cpu_model, "486SRx");
415 strcat(cpu_model, "486DRx");
418 strcat(cpu_model, "486SRx2");
421 strcat(cpu_model, "486DRx2");
424 strcat(cpu_model, "486SRu");
427 strcat(cpu_model, "486DRu");
430 strcat(cpu_model, "486SRu2");
433 strcat(cpu_model, "486DRu2");
436 strcat(cpu_model, "Unknown");
441 switch (cyrix_did & 0x0f) {
443 strcat(cpu_model, "486S");
446 strcat(cpu_model, "486S2");
449 strcat(cpu_model, "486Se");
452 strcat(cpu_model, "486S2e");
455 strcat(cpu_model, "486DX");
458 strcat(cpu_model, "486DX2");
461 strcat(cpu_model, "486DX4");
464 strcat(cpu_model, "Unknown");
469 if ((cyrix_did & 0x0f) < 8)
470 strcat(cpu_model, "6x86"); /* Where did you get it? */
472 strcat(cpu_model, "5x86");
475 strcat(cpu_model, "6x86");
478 if ((cyrix_did & 0xf000) == 0x3000) {
479 cpu_class = CPUCLASS_586;
480 strcat(cpu_model, "GXm");
482 strcat(cpu_model, "MediaGX");
485 strcat(cpu_model, "6x86MX");
488 switch (cyrix_did & 0x0f) {
490 strcat(cpu_model, "Overdrive CPU");
492 strcpy(cpu_model, "Texas Instruments 486SXL");
495 strcat(cpu_model, "486SLC/DLC");
498 strcat(cpu_model, "Unknown");
503 strcat(cpu_model, "Unknown");
508 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
509 strcpy(cpu_model, "Rise ");
510 switch (cpu_id & 0xff0) {
512 strcat(cpu_model, "mP6");
515 strcat(cpu_model, "Unknown");
517 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
518 switch (cpu_id & 0xff0) {
520 strcpy(cpu_model, "IDT WinChip C6");
524 strcpy(cpu_model, "IDT WinChip 2");
527 strcpy(cpu_model, "VIA C3 Samuel 2");
530 strcpy(cpu_model, "VIA/IDT Unknown");
532 } else if (strcmp(cpu_vendor, "IBM") == 0) {
533 strcpy(cpu_model, "Blue Lightning CPU");
537 * Replace cpu_model with cpu_brand minus leading spaces if
541 while (*brand == ' ')
544 strcpy(cpu_model, brand);
548 printf("%s (", cpu_model);
553 #if defined(I386_CPU)
558 #if defined(I486_CPU)
564 #if defined(I586_CPU)
566 printf("%d.%02d-MHz ",
567 (tsc_freq + 4999) / 1000000,
568 ((tsc_freq + 4999) / 10000) % 100);
572 #if defined(I686_CPU)
574 printf("%d.%02d-MHz ",
575 (tsc_freq + 4999) / 1000000,
576 ((tsc_freq + 4999) / 10000) % 100);
581 printf("Unknown"); /* will panic below... */
583 printf("-class CPU)\n");
584 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
586 printf(" Origin = \"%s\"",cpu_vendor);
588 printf(" Id = 0x%x", cpu_id);
590 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
591 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
592 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
593 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
594 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
595 ((cpu_id & 0xf00) > 0x500))) {
596 printf(" Stepping = %u", cpu_id & 0xf);
597 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
598 printf(" DIR=0x%04x", cyrix_did);
601 * Here we should probably set up flags indicating
602 * whether or not various features are available.
603 * The interesting ones are probably VME, PSE, PAE,
604 * and PGE. The code already assumes without bothering
605 * to check that all CPUs >= Pentium have a TSC and
608 printf("\n Features=0x%b", cpu_feature,
610 "\001FPU" /* Integral FPU */
611 "\002VME" /* Extended VM86 mode support */
612 "\003DE" /* Debugging Extensions (CR4.DE) */
613 "\004PSE" /* 4MByte page tables */
614 "\005TSC" /* Timestamp counter */
615 "\006MSR" /* Machine specific registers */
616 "\007PAE" /* Physical address extension */
617 "\010MCE" /* Machine Check support */
618 "\011CX8" /* CMPEXCH8 instruction */
619 "\012APIC" /* SMP local APIC */
620 "\013oldMTRR" /* Previous implementation of MTRR */
621 "\014SEP" /* Fast System Call */
622 "\015MTRR" /* Memory Type Range Registers */
623 "\016PGE" /* PG_G (global bit) support */
624 "\017MCA" /* Machine Check Architecture */
625 "\020CMOV" /* CMOV instruction */
626 "\021PAT" /* Page attributes table */
627 "\022PSE36" /* 36 bit address space support */
628 "\023PN" /* Processor Serial number */
629 "\024CLFLUSH" /* Has the CLFLUSH instruction */
631 "\026DTS" /* Debug Trace Store */
632 "\027ACPI" /* ACPI support */
633 "\030MMX" /* MMX instructions */
634 "\031FXSR" /* FXSAVE/FXRSTOR */
635 "\032SSE" /* Streaming SIMD Extensions */
636 "\033SSE2" /* Streaming SIMD Extensions #2 */
637 "\034SS" /* Self snoop */
638 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
639 "\036TM" /* Thermal Monitor clock slowdown */
640 "\037IA64" /* CPU can execute IA64 instructions */
641 "\040PBE" /* Pending Break Enable */
645 * If this CPU supports hyperthreading then mention
646 * the number of logical CPU's it contains.
648 if (cpu_feature & CPUID_HTT &&
649 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
650 printf("\n Hyperthreading: %d logical CPUs",
651 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
653 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
654 cpu_exthigh >= 0x80000001)
655 print_AMD_features();
656 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
657 printf(" DIR=0x%04x", cyrix_did);
658 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
659 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
660 #ifndef CYRIX_CACHE_REALLY_WORKS
661 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
662 printf("\n CPU cache: write-through mode");
665 /* Avoid ugly blank lines: only print newline when we have to. */
666 if (*cpu_vendor || cpu_id)
670 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
671 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
672 setup_tmx86_longrun();
678 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
680 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
681 strcmp(cpu_vendor, "TransmetaCPU") == 0)
682 print_transmeta_info();
686 * XXX - Do PPro CPUID level=2 stuff here?
688 * No, but maybe in a print_Intel_info() function called from here.
694 panicifcpuunsupported(void)
697 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
698 #error This kernel is not configured for one of the supported CPUs
701 * Now that we have told the user what they have,
702 * let them know if that machine type isn't configured.
705 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
706 #if !defined(I386_CPU)
709 #if !defined(I486_CPU)
712 #if !defined(I586_CPU)
715 #if !defined(I686_CPU)
718 panic("CPU class not configured");
725 static volatile u_int trap_by_rdmsr;
728 * Special exception 6 handler.
729 * The rdmsr instruction generates invalid opcodes fault on 486-class
730 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
731 * function identblue() when this handler is called. Stacked eip should
739 .type " __XSTRING(CNAME(bluetrap6)) ",@function
740 " __XSTRING(CNAME(bluetrap6)) ":
742 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "
743 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
748 * Special exception 13 handler.
749 * Accessing non-existent MSR generates general protection fault.
751 inthand_t bluetrap13;
756 .type " __XSTRING(CNAME(bluetrap13)) ",@function
757 " __XSTRING(CNAME(bluetrap13)) ":
759 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "
760 popl %eax # discard errorcode.
761 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
766 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
767 * support cpuid instruction. This function should be called after
768 * loading interrupt descriptor table register.
770 * I don't like this method that handles fault, but I couldn't get
771 * information for any other methods. Does blue giant know?
780 * Cyrix 486-class CPU does not support rdmsr instruction.
781 * The rdmsr instruction generates invalid opcode fault, and exception
782 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
783 * bluetrap6() set the magic number to trap_by_rdmsr.
785 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
788 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
789 * In this case, rdmsr generates general protection fault, and
790 * exception will be trapped by bluetrap13().
792 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
794 rdmsr(0x1002); /* Cyrix CPU generates fault. */
796 if (trap_by_rdmsr == 0xa8c1d)
797 return IDENTBLUE_CYRIX486;
798 else if (trap_by_rdmsr == 0xa89c4)
799 return IDENTBLUE_CYRIXM2;
800 return IDENTBLUE_IBMCPU;
805 * identifycyrix() set lower 16 bits of cyrix_did as follows:
807 * F E D C B A 9 8 7 6 5 4 3 2 1 0
808 * +-------+-------+---------------+
809 * | SID | RID | Device ID |
810 * | (DIR 1) | (DIR 0) |
811 * +-------+-------+---------------+
817 int ccr2_test = 0, dir_test = 0;
820 eflags = read_eflags();
823 ccr2 = read_cyrix_reg(CCR2);
824 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
825 read_cyrix_reg(CCR2);
826 if (read_cyrix_reg(CCR2) != ccr2)
828 write_cyrix_reg(CCR2, ccr2);
830 ccr3 = read_cyrix_reg(CCR3);
831 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
832 read_cyrix_reg(CCR3);
833 if (read_cyrix_reg(CCR3) != ccr3)
834 dir_test = 1; /* CPU supports DIRs. */
835 write_cyrix_reg(CCR3, ccr3);
838 /* Device ID registers are available. */
839 cyrix_did = read_cyrix_reg(DIR1) << 8;
840 cyrix_did += read_cyrix_reg(DIR0);
841 } else if (ccr2_test)
842 cyrix_did = 0x0010; /* 486S A-step */
844 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
846 write_eflags(eflags);
850 * Final stage of CPU identification. -- Should I check TI?
859 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
860 if (cpu == CPU_486) {
862 * These conditions are equivalent to:
863 * - CPU does not support cpuid instruction.
864 * - Cyrix/IBM CPU is detected.
866 isblue = identblue();
867 if (isblue == IDENTBLUE_IBMCPU) {
868 strcpy(cpu_vendor, "IBM");
873 switch (cpu_id & 0xf00) {
876 * Cyrix's datasheet does not describe DIRs.
877 * Therefor, I assume it does not have them
878 * and use the result of the cpuid instruction.
879 * XXX they seem to have it for now at least. -Peter
887 * This routine contains a trick.
888 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
890 switch (cyrix_did & 0x00f0) {
899 if ((cyrix_did & 0x000f) < 8)
912 /* M2 and later CPUs are treated as M2. */
916 * enable cpuid instruction.
918 ccr3 = read_cyrix_reg(CCR3);
919 write_cyrix_reg(CCR3, CCR3_MAPEN0);
920 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
921 write_cyrix_reg(CCR3, ccr3);
924 cpu_high = regs[0]; /* eax */
926 cpu_id = regs[0]; /* eax */
927 cpu_feature = regs[3]; /* edx */
931 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
933 * There are BlueLightning CPUs that do not change
934 * undefined flags by dividing 5 by 2. In this case,
935 * the CPU identification routine in locore.s leaves
936 * cpu_vendor null string and puts CPU_486 into the
939 isblue = identblue();
940 if (isblue == IDENTBLUE_IBMCPU) {
941 strcpy(cpu_vendor, "IBM");
949 print_AMD_assoc(int i)
952 printf(", fully associative\n");
954 printf(", %d-way associative\n", i);
962 if (cpu_exthigh >= 0x80000005) {
965 do_cpuid(0x80000005, regs);
966 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
967 print_AMD_assoc(regs[1] >> 24);
968 printf("Instruction TLB: %d entries", regs[1] & 0xff);
969 print_AMD_assoc((regs[1] >> 8) & 0xff);
970 printf("L1 data cache: %d kbytes", regs[2] >> 24);
971 printf(", %d bytes/line", regs[2] & 0xff);
972 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
973 print_AMD_assoc((regs[2] >> 16) & 0xff);
974 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
975 printf(", %d bytes/line", regs[3] & 0xff);
976 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
977 print_AMD_assoc((regs[3] >> 16) & 0xff);
978 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
979 do_cpuid(0x80000006, regs);
980 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
981 printf(", %d bytes/line", regs[2] & 0xff);
982 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
983 print_AMD_assoc((regs[2] >> 12) & 0x0f);
986 if (((cpu_id & 0xf00) == 0x500)
987 && (((cpu_id & 0x0f0) > 0x80)
988 || (((cpu_id & 0x0f0) == 0x80)
989 && (cpu_id & 0x00f) > 0x07))) {
990 /* K6-2(new core [Stepping 8-F]), K6-III or later */
991 amd_whcr = rdmsr(0xc0000082);
992 if (!(amd_whcr & (0x3ff << 22))) {
993 printf("Write Allocate Disable\n");
995 printf("Write Allocate Enable Limit: %dM bytes\n",
996 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
997 printf("Write Allocate 15-16M bytes: %s\n",
998 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1000 } else if (((cpu_id & 0xf00) == 0x500)
1001 && ((cpu_id & 0x0f0) > 0x50)) {
1002 /* K6, K6-2(old core) */
1003 amd_whcr = rdmsr(0xc0000082);
1004 if (!(amd_whcr & (0x7f << 1))) {
1005 printf("Write Allocate Disable\n");
1007 printf("Write Allocate Enable Limit: %dM bytes\n",
1008 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1009 printf("Write Allocate 15-16M bytes: %s\n",
1010 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1011 printf("Hardware Write Allocate Control: %s\n",
1012 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1017 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1019 print_AMD_features(void)
1024 * Values taken from AMD Processor Recognition
1025 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1027 do_cpuid(0x80000001, regs);
1028 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1030 "\001FPU" /* Integral FPU */
1031 "\002VME" /* Extended VM86 mode support */
1032 "\003DE" /* Debug extensions */
1033 "\004PSE" /* 4MByte page tables */
1034 "\005TSC" /* Timestamp counter */
1035 "\006MSR" /* Machine specific registers */
1036 "\007PAE" /* Physical address extension */
1037 "\010MCE" /* Machine Check support */
1038 "\011CX8" /* CMPEXCH8 instruction */
1039 "\012APIC" /* SMP local APIC */
1041 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1042 "\015MTRR" /* Memory Type Range Registers */
1043 "\016PGE" /* PG_G (global bit) support */
1044 "\017MCA" /* Machine Check Architecture */
1045 "\020ICMOV" /* CMOV instruction */
1046 "\021PAT" /* Page attributes table */
1047 "\022PGE36" /* 36 bit address space support */
1048 "\023RSVD" /* Reserved, unknown */
1049 "\024MP" /* Multiprocessor Capable */
1052 "\027AMIE" /* AMD MMX Instruction Extensions */
1054 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1060 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1067 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1070 #define MSR_TMx86_LONGRUN 0x80868010
1071 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1073 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1074 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1075 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1077 #define LONGRUN_MODE_MINFREQUENCY 0x00
1078 #define LONGRUN_MODE_ECONOMY 0x01
1079 #define LONGRUN_MODE_PERFORMANCE 0x02
1080 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1081 #define LONGRUN_MODE_UNKNOWN 0x04
1082 #define LONGRUN_MODE_MAX 0x04
1089 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1090 /* MSR low, MSR high, flags bit0 */
1091 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1092 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1093 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1094 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1098 tmx86_get_longrun_mode(void)
1101 union msrinfo msrinfo;
1102 u_int low, high, flags, mode;
1104 eflags = read_eflags();
1107 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1108 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1109 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1110 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1112 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1113 if (low == longrun_modes[mode][0] &&
1114 high == longrun_modes[mode][1] &&
1115 flags == longrun_modes[mode][2]) {
1119 mode = LONGRUN_MODE_UNKNOWN;
1121 write_eflags(eflags);
1126 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1131 eflags = read_eflags();
1134 do_cpuid(0x80860007, regs);
1135 *frequency = regs[0];
1137 *percentage = regs[2];
1139 write_eflags(eflags);
1144 tmx86_set_longrun_mode(u_int mode)
1147 union msrinfo msrinfo;
1149 if (mode >= LONGRUN_MODE_UNKNOWN) {
1153 eflags = read_eflags();
1156 /* Write LongRun mode values to Model Specific Register. */
1157 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1158 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1159 longrun_modes[mode][0]);
1160 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1161 longrun_modes[mode][1]);
1162 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1164 /* Write LongRun mode flags to Model Specific Register. */
1165 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1166 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1167 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1169 write_eflags(eflags);
1173 static u_int crusoe_longrun;
1174 static u_int crusoe_frequency;
1175 static u_int crusoe_voltage;
1176 static u_int crusoe_percentage;
1177 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1178 static struct sysctl_oid *crusoe_sysctl_tree;
1181 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1186 crusoe_longrun = tmx86_get_longrun_mode();
1187 mode = crusoe_longrun;
1188 error = sysctl_handle_int(oidp, &mode, 0, req);
1189 if (error || !req->newptr) {
1192 if (mode >= LONGRUN_MODE_UNKNOWN) {
1196 if (crusoe_longrun != mode) {
1197 crusoe_longrun = mode;
1198 tmx86_set_longrun_mode(crusoe_longrun);
1205 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1210 tmx86_get_longrun_status(&crusoe_frequency,
1211 &crusoe_voltage, &crusoe_percentage);
1212 val = *(u_int *)oidp->oid_arg1;
1213 error = sysctl_handle_int(oidp, &val, 0, req);
1218 setup_tmx86_longrun(void)
1220 static int done = 0;
1226 sysctl_ctx_init(&crusoe_sysctl_ctx);
1227 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1228 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1229 "crusoe", CTLFLAG_RD, 0,
1230 "Transmeta Crusoe LongRun support");
1231 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1232 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1233 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1234 "LongRun mode [0-3]");
1235 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1236 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1237 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1238 "Current frequency (MHz)");
1239 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1240 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1241 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1242 "Current voltage (mV)");
1243 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1244 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1245 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1246 "Processing performance (%)");
1250 print_transmeta_info()
1252 u_int regs[4], nreg = 0;
1254 do_cpuid(0x80860000, regs);
1256 if (nreg >= 0x80860001) {
1257 do_cpuid(0x80860001, regs);
1258 printf(" Processor revision %u.%u.%u.%u\n",
1259 (regs[1] >> 24) & 0xff,
1260 (regs[1] >> 16) & 0xff,
1261 (regs[1] >> 8) & 0xff,
1264 if (nreg >= 0x80860002) {
1265 do_cpuid(0x80860002, regs);
1266 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1267 (regs[1] >> 24) & 0xff,
1268 (regs[1] >> 16) & 0xff,
1269 (regs[1] >> 8) & 0xff,
1273 if (nreg >= 0x80860006) {
1275 do_cpuid(0x80860003, (u_int*) &info[0]);
1276 do_cpuid(0x80860004, (u_int*) &info[16]);
1277 do_cpuid(0x80860005, (u_int*) &info[32]);
1278 do_cpuid(0x80860006, (u_int*) &info[48]);
1280 printf(" %s\n", info);
1283 crusoe_longrun = tmx86_get_longrun_mode();
1284 tmx86_get_longrun_status(&crusoe_frequency,
1285 &crusoe_voltage, &crusoe_percentage);
1286 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1287 crusoe_frequency, crusoe_voltage, crusoe_percentage);