2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
57 #include <machine/md_var.h>
60 #include <drm/i915_drm.h>
62 #include "i915_trace.h"
63 #include "intel_drv.h"
64 #include <linux/shmem_fs.h>
65 #include <linux/slab.h>
66 #include <linux/pci.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
70 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
72 bool map_and_fenceable,
74 static int i915_gem_phys_pwrite(struct drm_device *dev,
75 struct drm_i915_gem_object *obj,
76 struct drm_i915_gem_pwrite *args,
77 struct drm_file *file);
79 static void i915_gem_write_fence(struct drm_device *dev, int reg,
80 struct drm_i915_gem_object *obj);
81 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
82 struct drm_i915_fence_reg *fence,
85 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
86 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
88 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
91 i915_gem_release_mmap(obj);
93 /* As we do not have an associated fence register, we will force
94 * a tiling change if we ever need to acquire one.
96 obj->fence_dirty = false;
97 obj->fence_reg = I915_FENCE_REG_NONE;
100 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
101 static void i915_gem_lowmem(void *arg);
103 /* some bookkeeping */
104 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
107 dev_priv->mm.object_count++;
108 dev_priv->mm.object_memory += size;
111 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
114 dev_priv->mm.object_count--;
115 dev_priv->mm.object_memory -= size;
119 i915_gem_wait_for_error(struct i915_gpu_error *error)
123 #define EXIT_COND (!i915_reset_in_progress(error) || \
124 i915_terminally_wedged(error))
129 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
130 * userspace. If it takes that long something really bad is going on and
131 * we should simply try to bail out and fail as gracefully as possible.
133 ret = wait_event_interruptible_timeout(error->reset_queue,
137 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
139 } else if (ret < 0) {
147 int i915_mutex_lock_interruptible(struct drm_device *dev)
149 struct drm_i915_private *dev_priv = dev->dev_private;
152 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
156 ret = lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
160 WARN_ON(i915_verify_lists(dev));
165 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
171 i915_gem_init_ioctl(struct drm_device *dev, void *data,
172 struct drm_file *file)
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 struct drm_i915_gem_init *args = data;
177 if (drm_core_check_feature(dev, DRIVER_MODESET))
180 if (args->gtt_start >= args->gtt_end ||
181 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
184 /* GEM with user mode setting was never supported on ilk and later. */
185 if (INTEL_INFO(dev)->gen >= 5)
188 mutex_lock(&dev->struct_mutex);
189 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
191 dev_priv->gtt.mappable_end = args->gtt_end;
192 mutex_unlock(&dev->struct_mutex);
198 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
199 struct drm_file *file)
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct drm_i915_gem_get_aperture *args = data;
203 struct drm_i915_gem_object *obj;
207 mutex_lock(&dev->struct_mutex);
208 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
210 pinned += obj->gtt_space->size;
211 mutex_unlock(&dev->struct_mutex);
213 args->aper_size = dev_priv->gtt.total;
214 args->aper_available_size = args->aper_size - pinned;
219 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 i915_gem_create(struct drm_file *file,
226 struct drm_device *dev,
230 struct drm_i915_gem_object *obj;
234 size = roundup(size, PAGE_SIZE);
238 /* Allocate the new object */
239 obj = i915_gem_alloc_object(dev, size);
243 ret = drm_gem_handle_create(file, &obj->base, &handle);
245 drm_gem_object_release(&obj->base);
246 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
247 i915_gem_object_free(obj);
251 /* drop reference from allocate - handle holds it now */
252 drm_gem_object_unreference(&obj->base);
253 trace_i915_gem_object_create(obj);
260 i915_gem_dumb_create(struct drm_file *file,
261 struct drm_device *dev,
262 struct drm_mode_create_dumb *args)
265 /* have to work out size/pitch and return them */
266 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
267 args->size = args->pitch * args->height;
268 return i915_gem_create(file, dev,
269 args->size, &args->handle);
272 int i915_gem_dumb_destroy(struct drm_file *file,
273 struct drm_device *dev,
277 return drm_gem_handle_delete(file, handle);
281 * Creates a new mm object and returns a handle to it.
284 i915_gem_create_ioctl(struct drm_device *dev, void *data,
285 struct drm_file *file)
287 struct drm_i915_gem_create *args = data;
289 return i915_gem_create(file, dev,
290 args->size, &args->handle);
294 __copy_to_user_swizzled(char __user *cpu_vaddr,
295 const char *gpu_vaddr, int gpu_offset,
298 int ret, cpu_offset = 0;
301 int cacheline_end = ALIGN(gpu_offset + 1, 64);
302 int this_length = min(cacheline_end - gpu_offset, length);
303 int swizzled_gpu_offset = gpu_offset ^ 64;
305 ret = __copy_to_user(cpu_vaddr + cpu_offset,
306 gpu_vaddr + swizzled_gpu_offset,
311 cpu_offset += this_length;
312 gpu_offset += this_length;
313 length -= this_length;
320 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
321 const char __user *cpu_vaddr,
324 int ret, cpu_offset = 0;
327 int cacheline_end = ALIGN(gpu_offset + 1, 64);
328 int this_length = min(cacheline_end - gpu_offset, length);
329 int swizzled_gpu_offset = gpu_offset ^ 64;
331 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
332 cpu_vaddr + cpu_offset,
337 cpu_offset += this_length;
338 gpu_offset += this_length;
339 length -= this_length;
345 /* Per-page copy function for the shmem pread fastpath.
346 * Flushes invalid cachelines before reading the target if
347 * needs_clflush is set. */
349 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
350 char __user *user_data,
351 bool page_do_bit17_swizzling, bool needs_clflush)
356 if (unlikely(page_do_bit17_swizzling))
359 vaddr = kmap_atomic(page);
361 drm_clflush_virt_range(vaddr + shmem_page_offset,
363 ret = __copy_to_user_inatomic(user_data,
364 vaddr + shmem_page_offset,
366 kunmap_atomic(vaddr);
368 return ret ? -EFAULT : 0;
372 shmem_clflush_swizzled_range(char *addr, unsigned long length,
375 if (unlikely(swizzled)) {
376 unsigned long start = (unsigned long) addr;
377 unsigned long end = (unsigned long) addr + length;
379 /* For swizzling simply ensure that we always flush both
380 * channels. Lame, but simple and it works. Swizzled
381 * pwrite/pread is far from a hotpath - current userspace
382 * doesn't use it at all. */
383 start = round_down(start, 128);
384 end = round_up(end, 128);
386 drm_clflush_virt_range((void *)start, end - start);
388 drm_clflush_virt_range(addr, length);
393 /* Only difference to the fast-path function is that this can handle bit17
394 * and uses non-atomic copy and kmap functions. */
396 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
397 char __user *user_data,
398 bool page_do_bit17_swizzling, bool needs_clflush)
405 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
407 page_do_bit17_swizzling);
409 if (page_do_bit17_swizzling)
410 ret = __copy_to_user_swizzled(user_data,
411 vaddr, shmem_page_offset,
414 ret = __copy_to_user(user_data,
415 vaddr + shmem_page_offset,
419 return ret ? - EFAULT : 0;
422 static inline void vm_page_reference(vm_page_t m)
424 vm_page_flag_set(m, PG_REFERENCED);
428 i915_gem_shmem_pread(struct drm_device *dev,
429 struct drm_i915_gem_object *obj,
430 struct drm_i915_gem_pread *args,
431 struct drm_file *file)
433 char __user *user_data;
436 int shmem_page_offset, page_length, ret = 0;
437 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
438 int hit_slowpath = 0;
439 int needs_clflush = 0;
442 user_data = (char __user *) (uintptr_t) args->data_ptr;
445 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
447 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
448 /* If we're not in the cpu read domain, set ourself into the gtt
449 * read domain and manually flush cachelines (if required). This
450 * optimizes for the case when the gpu will dirty the data
451 * anyway again before the next pread happens. */
452 if (obj->cache_level == I915_CACHE_NONE)
454 if (obj->gtt_space) {
455 ret = i915_gem_object_set_to_gtt_domain(obj, false);
461 ret = i915_gem_object_get_pages(obj);
465 i915_gem_object_pin_pages(obj);
467 offset = args->offset;
469 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
470 struct vm_page *page;
472 if (i < offset >> PAGE_SHIFT)
478 /* Operation in this page
480 * shmem_page_offset = offset within page in shmem file
481 * page_length = bytes to copy for this page
483 shmem_page_offset = offset_in_page(offset);
484 page_length = remain;
485 if ((shmem_page_offset + page_length) > PAGE_SIZE)
486 page_length = PAGE_SIZE - shmem_page_offset;
490 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
491 (page_to_phys(page) & (1 << 17)) != 0;
493 page = obj->pages[i];
494 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
495 (VM_PAGE_TO_PHYS(page) & (1 << 17)) != 0;
498 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
499 user_data, page_do_bit17_swizzling,
505 mutex_unlock(&dev->struct_mutex);
509 ret = fault_in_multipages_writeable(user_data, remain);
510 /* Userspace is tricking us, but we've already clobbered
511 * its pages with the prefault and promised to write the
512 * data up to the first fault. Hence ignore any errors
513 * and just continue. */
519 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
520 user_data, page_do_bit17_swizzling,
523 mutex_lock(&dev->struct_mutex);
527 mark_page_accessed(page);
533 remain -= page_length;
534 user_data += page_length;
535 offset += page_length;
539 i915_gem_object_unpin_pages(obj);
542 /* Fixup: Kill any reinstated backing storage pages */
543 if (obj->madv == __I915_MADV_PURGED)
544 i915_gem_object_truncate(obj);
551 * Reads data from the object referenced by handle.
553 * On error, the contents of *data are undefined.
556 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
557 struct drm_file *file)
559 struct drm_i915_gem_pread *args = data;
560 struct drm_i915_gem_object *obj;
566 ret = i915_mutex_lock_interruptible(dev);
570 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
571 if (&obj->base == NULL) {
576 /* Bounds check source. */
577 if (args->offset > obj->base.size ||
578 args->size > obj->base.size - args->offset) {
583 ret = i915_gem_shmem_pread(dev, obj, args, file);
585 drm_gem_object_unreference(&obj->base);
587 mutex_unlock(&dev->struct_mutex);
592 /* This is the fast write path which cannot handle
593 * page faults in the source data
597 fast_user_write(struct io_mapping *mapping,
598 loff_t page_base, int page_offset,
599 char __user *user_data,
602 void __iomem *vaddr_atomic;
604 unsigned long unwritten;
606 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
607 /* We can use the cpu mem copy function because this is X86. */
608 vaddr = (void __force*)vaddr_atomic + page_offset;
609 unwritten = __copy_from_user_inatomic_nocache(vaddr,
611 io_mapping_unmap_atomic(vaddr_atomic);
616 * This is the fast pwrite path, where we copy the data directly from the
617 * user into the GTT, uncached.
620 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
621 struct drm_i915_gem_object *obj,
622 struct drm_i915_gem_pwrite *args,
623 struct drm_file *file)
625 drm_i915_private_t *dev_priv = dev->dev_private;
627 loff_t offset, page_base;
628 char __user *user_data;
629 int page_offset, page_length, ret;
631 ret = i915_gem_object_pin(obj, 0, true, true);
635 ret = i915_gem_object_set_to_gtt_domain(obj, true);
639 ret = i915_gem_object_put_fence(obj);
643 user_data = to_user_ptr(args->data_ptr);
646 offset = obj->gtt_offset + args->offset;
649 /* Operation in this page
651 * page_base = page offset within aperture
652 * page_offset = offset within page
653 * page_length = bytes to copy for this page
655 page_base = offset & PAGE_MASK;
656 page_offset = offset_in_page(offset);
657 page_length = remain;
658 if ((page_offset + remain) > PAGE_SIZE)
659 page_length = PAGE_SIZE - page_offset;
661 /* If we get a fault while copying data, then (presumably) our
662 * source page isn't available. Return the error and we'll
663 * retry in the slow path.
665 if (fast_user_write(dev_priv->gtt.mappable, page_base,
666 page_offset, user_data, page_length)) {
671 remain -= page_length;
672 user_data += page_length;
673 offset += page_length;
677 i915_gem_object_unpin(obj);
684 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
685 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
691 * Pass the unaligned physical address and size to pmap_mapdev_attr()
692 * so it can properly calculate whether an extra page needs to be
693 * mapped or not to cover the requested range. The function will
694 * add the page offset into the returned mkva for us.
696 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
697 offset, size, PAT_WRITE_COMBINING);
698 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
699 pmap_unmapdev(mkva, size);
704 /* Per-page copy function for the shmem pwrite fastpath.
705 * Flushes invalid cachelines before writing to the target if
706 * needs_clflush_before is set and flushes out any written cachelines after
707 * writing if needs_clflush is set. */
709 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
710 char __user *user_data,
711 bool page_do_bit17_swizzling,
712 bool needs_clflush_before,
713 bool needs_clflush_after)
718 if (unlikely(page_do_bit17_swizzling))
721 vaddr = kmap_atomic(page);
722 if (needs_clflush_before)
723 drm_clflush_virt_range(vaddr + shmem_page_offset,
725 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
728 if (needs_clflush_after)
729 drm_clflush_virt_range(vaddr + shmem_page_offset,
731 kunmap_atomic(vaddr);
733 return ret ? -EFAULT : 0;
736 /* Only difference to the fast-path function is that this can handle bit17
737 * and uses non-atomic copy and kmap functions. */
739 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
740 char __user *user_data,
741 bool page_do_bit17_swizzling,
742 bool needs_clflush_before,
743 bool needs_clflush_after)
749 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
750 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
752 page_do_bit17_swizzling);
753 if (page_do_bit17_swizzling)
754 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
758 ret = __copy_from_user(vaddr + shmem_page_offset,
761 if (needs_clflush_after)
762 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
764 page_do_bit17_swizzling);
767 return ret ? -EFAULT : 0;
772 i915_gem_shmem_pwrite(struct drm_device *dev,
773 struct drm_i915_gem_object *obj,
774 struct drm_i915_gem_pwrite *args,
775 struct drm_file *file)
782 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
784 do_bit17_swizzling = 0;
787 vm_obj = obj->base.vm_obj;
790 VM_OBJECT_LOCK(vm_obj);
791 vm_object_pip_add(vm_obj, 1);
792 while (args->size > 0) {
793 obj_pi = OFF_TO_IDX(args->offset);
794 obj_po = args->offset & PAGE_MASK;
796 m = shmem_read_mapping_page(vm_obj, obj_pi);
797 VM_OBJECT_UNLOCK(vm_obj);
799 sf = sf_buf_alloc(m);
800 mkva = sf_buf_kva(sf);
801 length = min(args->size, PAGE_SIZE - obj_po);
803 if (do_bit17_swizzling &&
804 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
805 cnt = roundup2(obj_po + 1, 64);
806 cnt = min(cnt - obj_po, length);
807 swizzled_po = obj_po ^ 64;
810 swizzled_po = obj_po;
812 ret = -copyin_nofault(
813 (void *)(uintptr_t)args->data_ptr,
814 (char *)mkva + swizzled_po, cnt);
817 args->data_ptr += cnt;
824 VM_OBJECT_LOCK(vm_obj);
826 vm_page_reference(m);
827 vm_page_busy_wait(m, FALSE, "i915gem");
828 vm_page_unwire(m, 1);
834 vm_object_pip_wakeup(vm_obj);
835 VM_OBJECT_UNLOCK(vm_obj);
841 * Writes data to the object referenced by handle.
843 * On error, the contents of the buffer that were to be modified are undefined.
846 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *file)
849 struct drm_i915_gem_pwrite *args = data;
850 struct drm_i915_gem_object *obj;
852 vm_offset_t start, end;
858 start = trunc_page(args->data_ptr);
859 end = round_page(args->data_ptr + args->size);
860 npages = howmany(end - start, PAGE_SIZE);
861 ma = kmalloc(npages * sizeof(vm_page_t), M_DRM, M_WAITOK |
863 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
864 (vm_offset_t)args->data_ptr, args->size,
865 VM_PROT_READ, ma, npages);
871 ret = i915_mutex_lock_interruptible(dev);
875 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
876 if (&obj->base == NULL) {
881 /* Bounds check destination. */
882 if (args->offset > obj->base.size ||
883 args->size > obj->base.size - args->offset) {
889 ret = i915_gem_phys_pwrite(dev, obj, args, file);
890 } else if (obj->gtt_space &&
891 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
892 ret = i915_gem_object_pin(obj, 0, true, false);
895 ret = i915_gem_object_set_to_gtt_domain(obj, true);
898 ret = i915_gem_object_put_fence(obj);
901 ret = i915_gem_gtt_write(dev, obj, args->data_ptr, args->size,
904 i915_gem_object_unpin(obj);
906 ret = i915_gem_object_set_to_cpu_domain(obj, true);
909 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
912 drm_gem_object_unreference(&obj->base);
914 mutex_unlock(&dev->struct_mutex);
916 vm_page_unhold_pages(ma, npages);
923 i915_gem_check_wedge(struct i915_gpu_error *error,
926 if (i915_reset_in_progress(error)) {
927 /* Non-interruptible callers can't handle -EAGAIN, hence return
928 * -EIO unconditionally for these. */
932 /* Recovery complete, but the reset failed ... */
933 if (i915_terminally_wedged(error))
943 * Compare seqno against outstanding lazy request. Emit a request if they are
947 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
951 DRM_LOCK_ASSERT(ring->dev);
954 if (seqno == ring->outstanding_lazy_request)
955 ret = i915_add_request(ring, NULL);
961 * __wait_seqno - wait until execution of seqno has finished
962 * @ring: the ring expected to report seqno
964 * @reset_counter: reset sequence associated with the given seqno
965 * @interruptible: do an interruptible wait (normally yes)
966 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
968 * Note: It is of utmost importance that the passed in seqno and reset_counter
969 * values have been read by the caller in an smp safe manner. Where read-side
970 * locks are involved, it is sufficient to read the reset_counter before
971 * unlocking the lock that protects the seqno. For lockless tricks, the
972 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
975 * Returns 0 if the seqno was found within the alloted time. Else returns the
976 * errno with remaining time filled in timeout argument.
978 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
979 unsigned reset_counter,
980 bool interruptible, struct timespec *timeout)
982 drm_i915_private_t *dev_priv = ring->dev->dev_private;
983 struct timespec before, now, wait_time={1,0};
984 unsigned long timeout_jiffies;
986 bool wait_forever = true;
989 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
992 if (timeout != NULL) {
993 wait_time = *timeout;
994 wait_forever = false;
997 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
999 if (WARN_ON(!ring->irq_get(ring)))
1002 /* Record current time in case interrupted by signal, or wedged * */
1003 getrawmonotonic(&before);
1006 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1007 i915_reset_in_progress(&dev_priv->gpu_error) || \
1008 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1011 end = wait_event_interruptible_timeout(ring->irq_queue,
1015 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1018 /* We need to check whether any gpu reset happened in between
1019 * the caller grabbing the seqno and now ... */
1020 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1023 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1025 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1028 } while (end == 0 && wait_forever);
1030 getrawmonotonic(&now);
1032 ring->irq_put(ring);
1036 struct timespec sleep_time = timespec_sub(now, before);
1037 *timeout = timespec_sub(*timeout, sleep_time);
1038 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1039 set_normalized_timespec(timeout, 0, 0);
1044 case -EAGAIN: /* Wedged */
1045 case -ERESTARTSYS: /* Signal */
1047 case 0: /* Timeout */
1048 return -ETIMEDOUT; /* -ETIME on Linux */
1049 default: /* Completed */
1050 WARN_ON(end < 0); /* We're not aware of other errors */
1056 * Waits for a sequence number to be signaled, and cleans up the
1057 * request and object lists appropriately for that event.
1060 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1062 struct drm_device *dev = ring->dev;
1063 struct drm_i915_private *dev_priv = dev->dev_private;
1064 bool interruptible = dev_priv->mm.interruptible;
1067 DRM_LOCK_ASSERT(dev);
1070 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1074 ret = i915_gem_check_olr(ring, seqno);
1078 return __wait_seqno(ring, seqno,
1079 atomic_read(&dev_priv->gpu_error.reset_counter),
1080 interruptible, NULL);
1084 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1085 struct intel_ring_buffer *ring)
1087 i915_gem_retire_requests_ring(ring);
1089 /* Manually manage the write flush as we may have not yet
1090 * retired the buffer.
1092 * Note that the last_write_seqno is always the earlier of
1093 * the two (read/write) seqno, so if we haved successfully waited,
1094 * we know we have passed the last write.
1096 obj->last_write_seqno = 0;
1097 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1103 * Ensures that all rendering to the object has completed and the object is
1104 * safe to unbind from the GTT or access from the CPU.
1106 static __must_check int
1107 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1110 struct intel_ring_buffer *ring = obj->ring;
1114 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1118 ret = i915_wait_seqno(ring, seqno);
1122 return i915_gem_object_wait_rendering__tail(obj, ring);
1125 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1126 * as the object state may change during this call.
1128 static __must_check int
1129 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1132 struct drm_device *dev = obj->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 struct intel_ring_buffer *ring = obj->ring;
1135 unsigned reset_counter;
1139 DRM_LOCK_ASSERT(dev);
1140 BUG_ON(!dev_priv->mm.interruptible);
1142 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1146 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1150 ret = i915_gem_check_olr(ring, seqno);
1154 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1155 mutex_unlock(&dev->struct_mutex);
1156 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1157 mutex_lock(&dev->struct_mutex);
1161 return i915_gem_object_wait_rendering__tail(obj, ring);
1165 * Called when user space prepares to use an object with the CPU, either
1166 * through the mmap ioctl's mapping or a GTT mapping.
1169 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1170 struct drm_file *file)
1172 struct drm_i915_gem_set_domain *args = data;
1173 struct drm_i915_gem_object *obj;
1174 uint32_t read_domains = args->read_domains;
1175 uint32_t write_domain = args->write_domain;
1178 /* Only handle setting domains to types used by the CPU. */
1179 if (write_domain & I915_GEM_GPU_DOMAINS)
1182 if (read_domains & I915_GEM_GPU_DOMAINS)
1185 /* Having something in the write domain implies it's in the read
1186 * domain, and only that read domain. Enforce that in the request.
1188 if (write_domain != 0 && read_domains != write_domain)
1191 ret = i915_mutex_lock_interruptible(dev);
1195 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1196 if (&obj->base == NULL) {
1201 /* Try to flush the object off the GPU without holding the lock.
1202 * We will repeat the flush holding the lock in the normal manner
1203 * to catch cases where we are gazumped.
1205 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1209 if (read_domains & I915_GEM_DOMAIN_GTT) {
1210 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1212 /* Silently promote "you're not bound, there was nothing to do"
1213 * to success, since the client was just asking us to
1214 * make sure everything was done.
1219 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1223 drm_gem_object_unreference(&obj->base);
1225 mutex_unlock(&dev->struct_mutex);
1230 * Called when user space has done writes to this buffer
1233 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1234 struct drm_file *file)
1236 struct drm_i915_gem_sw_finish *args = data;
1237 struct drm_i915_gem_object *obj;
1240 ret = i915_mutex_lock_interruptible(dev);
1243 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1244 if (&obj->base == NULL) {
1249 /* Pinned buffers may be scanout, so flush the cache */
1251 i915_gem_object_flush_cpu_write_domain(obj);
1253 drm_gem_object_unreference(&obj->base);
1255 mutex_unlock(&dev->struct_mutex);
1260 * Maps the contents of an object, returning the address it is mapped
1263 * While the mapping holds a reference on the contents of the object, it doesn't
1264 * imply a ref on the object itself.
1267 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1268 struct drm_file *file)
1270 struct drm_i915_gem_mmap *args = data;
1271 struct drm_gem_object *obj;
1272 struct proc *p = curproc;
1273 vm_map_t map = &p->p_vmspace->vm_map;
1278 obj = drm_gem_object_lookup(dev, file, args->handle);
1282 if (args->size == 0)
1285 size = round_page(args->size);
1286 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1292 vm_object_hold(obj->vm_obj);
1293 vm_object_reference_locked(obj->vm_obj);
1294 vm_object_drop(obj->vm_obj);
1295 rv = vm_map_find(map, obj->vm_obj, NULL,
1296 args->offset, &addr, args->size,
1297 PAGE_SIZE, /* align */
1299 VM_MAPTYPE_NORMAL, /* maptype */
1300 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1301 VM_PROT_READ | VM_PROT_WRITE, /* max */
1302 MAP_SHARED /* cow */);
1303 if (rv != KERN_SUCCESS) {
1304 vm_object_deallocate(obj->vm_obj);
1305 error = -vm_mmap_to_errno(rv);
1307 args->addr_ptr = (uint64_t)addr;
1310 drm_gem_object_unreference(obj);
1317 * i915_gem_fault - fault a page into the GTT
1318 * vma: VMA in question
1321 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1322 * from userspace. The fault handler takes care of binding the object to
1323 * the GTT (if needed), allocating and programming a fence register (again,
1324 * only if needed based on whether the old reg is still valid or the object
1325 * is tiled) and inserting a new PTE into the faulting process.
1327 * Note that the faulting process may involve evicting existing objects
1328 * from the GTT and/or fence registers to make room. So performance may
1329 * suffer if the GTT working set is large or there are few fence registers
1333 i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1336 struct drm_gem_object *gem_obj;
1337 struct drm_i915_gem_object *obj;
1338 struct drm_device *dev;
1339 drm_i915_private_t *dev_priv;
1344 gem_obj = vm_obj->handle;
1345 obj = to_intel_bo(gem_obj);
1346 dev = obj->base.dev;
1347 dev_priv = dev->dev_private;
1349 write = (prot & VM_PROT_WRITE) != 0;
1353 vm_object_pip_add(vm_obj, 1);
1356 * Remove the placeholder page inserted by vm_fault() from the
1357 * object before dropping the object lock. If
1358 * i915_gem_release_mmap() is active in parallel on this gem
1359 * object, then it owns the drm device sx and might find the
1360 * placeholder already. Then, since the page is busy,
1361 * i915_gem_release_mmap() sleeps waiting for the busy state
1362 * of the page cleared. We will be not able to acquire drm
1363 * device lock until i915_gem_release_mmap() is able to make a
1366 if (*mres != NULL) {
1368 vm_page_remove(oldm);
1373 VM_OBJECT_UNLOCK(vm_obj);
1379 ret = i915_mutex_lock_interruptible(dev);
1385 mutex_lock(&dev->struct_mutex);
1388 * Since the object lock was dropped, other thread might have
1389 * faulted on the same GTT address and instantiated the
1390 * mapping for the page. Recheck.
1392 VM_OBJECT_LOCK(vm_obj);
1393 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1395 if ((m->flags & PG_BUSY) != 0) {
1396 mutex_unlock(&dev->struct_mutex);
1398 vm_page_sleep(m, "915pee");
1404 VM_OBJECT_UNLOCK(vm_obj);
1406 /* Access to snoopable pages through the GTT is incoherent. */
1407 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1412 /* Now bind it into the GTT if needed */
1413 if (!obj->map_and_fenceable) {
1414 ret = i915_gem_object_unbind(obj);
1420 if (!obj->gtt_space) {
1421 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1427 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1434 if (obj->tiling_mode == I915_TILING_NONE)
1435 ret = i915_gem_object_put_fence(obj);
1437 ret = i915_gem_object_get_fence(obj);
1443 if (i915_gem_object_is_inactive(obj))
1444 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1446 obj->fault_mappable = true;
1447 VM_OBJECT_LOCK(vm_obj);
1448 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1455 KASSERT((m->flags & PG_FICTITIOUS) != 0,
1456 ("not fictitious %p", m));
1457 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1459 if ((m->flags & PG_BUSY) != 0) {
1460 mutex_unlock(&dev->struct_mutex);
1462 vm_page_sleep(m, "915pbs");
1466 m->valid = VM_PAGE_BITS_ALL;
1467 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1470 vm_page_busy_try(m, false);
1472 mutex_unlock(&dev->struct_mutex);
1476 vm_object_pip_wakeup(vm_obj);
1477 return (VM_PAGER_OK);
1480 mutex_unlock(&dev->struct_mutex);
1482 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1483 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1484 goto unlocked_vmobj;
1486 VM_OBJECT_LOCK(vm_obj);
1487 vm_object_pip_wakeup(vm_obj);
1488 return (VM_PAGER_ERROR);
1492 * i915_gem_release_mmap - remove physical page mappings
1493 * @obj: obj in question
1495 * Preserve the reservation of the mmapping with the DRM core code, but
1496 * relinquish ownership of the pages back to the system.
1498 * It is vital that we remove the page mapping if we have mapped a tiled
1499 * object through the GTT and then lose the fence register due to
1500 * resource pressure. Similarly if the object has been moved out of the
1501 * aperture, than pages mapped into userspace must be revoked. Removing the
1502 * mapping will then trigger a page fault on the next user access, allowing
1503 * fixup by i915_gem_fault().
1506 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1512 if (!obj->fault_mappable)
1515 devobj = cdev_pager_lookup(obj);
1516 if (devobj != NULL) {
1517 page_count = OFF_TO_IDX(obj->base.size);
1519 VM_OBJECT_LOCK(devobj);
1520 for (i = 0; i < page_count; i++) {
1521 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1524 cdev_pager_free_page(devobj, m);
1526 VM_OBJECT_UNLOCK(devobj);
1527 vm_object_deallocate(devobj);
1530 obj->fault_mappable = false;
1534 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1538 if (INTEL_INFO(dev)->gen >= 4 ||
1539 tiling_mode == I915_TILING_NONE)
1542 /* Previous chips need a power-of-two fence region when tiling */
1543 if (INTEL_INFO(dev)->gen == 3)
1544 gtt_size = 1024*1024;
1546 gtt_size = 512*1024;
1548 while (gtt_size < size)
1555 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1556 * @obj: object to check
1558 * Return the required GTT alignment for an object, taking into account
1559 * potential fence register mapping.
1562 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1563 int tiling_mode, bool fenced)
1567 * Minimum alignment is 4k (GTT page size), but might be greater
1568 * if a fence register is needed for the object.
1570 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1571 tiling_mode == I915_TILING_NONE)
1575 * Previous chips need to be aligned to the size of the smallest
1576 * fence register that can contain the object.
1578 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1582 i915_gem_mmap_gtt(struct drm_file *file,
1583 struct drm_device *dev,
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 struct drm_i915_gem_object *obj;
1591 ret = i915_mutex_lock_interruptible(dev);
1595 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1596 if (&obj->base == NULL) {
1601 if (obj->base.size > dev_priv->gtt.mappable_end) {
1606 if (obj->madv != I915_MADV_WILLNEED) {
1607 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1612 ret = drm_gem_create_mmap_offset(&obj->base);
1616 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1617 DRM_GEM_MAPPING_KEY;
1619 drm_gem_object_unreference(&obj->base);
1621 mutex_unlock(&dev->struct_mutex);
1626 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1628 * @data: GTT mapping ioctl data
1629 * @file: GEM object info
1631 * Simply returns the fake offset to userspace so it can mmap it.
1632 * The mmap call will end up in drm_gem_mmap(), which will set things
1633 * up so we can get faults in the handler above.
1635 * The fault handler will take care of binding the object into the GTT
1636 * (since it may have been evicted to make room for something), allocating
1637 * a fence register, and mapping the appropriate aperture address into
1641 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1642 struct drm_file *file)
1644 struct drm_i915_gem_mmap_gtt *args = data;
1646 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1649 /* Immediately discard the backing storage */
1651 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1655 vm_obj = obj->base.vm_obj;
1656 VM_OBJECT_LOCK(vm_obj);
1657 vm_object_page_remove(vm_obj, 0, 0, false);
1658 VM_OBJECT_UNLOCK(vm_obj);
1659 obj->madv = __I915_MADV_PURGED;
1663 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1665 return obj->madv == I915_MADV_DONTNEED;
1669 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1674 BUG_ON(obj->madv == __I915_MADV_PURGED);
1676 if (obj->tiling_mode != I915_TILING_NONE)
1677 i915_gem_object_save_bit_17_swizzle(obj);
1678 if (obj->madv == I915_MADV_DONTNEED)
1680 page_count = obj->base.size / PAGE_SIZE;
1681 VM_OBJECT_LOCK(obj->base.vm_obj);
1682 #if GEM_PARANOID_CHECK_GTT
1683 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
1685 for (i = 0; i < page_count; i++) {
1689 if (obj->madv == I915_MADV_WILLNEED)
1690 vm_page_reference(m);
1691 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1692 vm_page_unwire(obj->pages[i], 1);
1693 vm_page_wakeup(obj->pages[i]);
1695 VM_OBJECT_UNLOCK(obj->base.vm_obj);
1697 drm_free(obj->pages, M_DRM);
1702 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1704 const struct drm_i915_gem_object_ops *ops = obj->ops;
1706 if (obj->pages == NULL)
1709 BUG_ON(obj->gtt_space);
1711 if (obj->pages_pin_count)
1714 /* ->put_pages might need to allocate memory for the bit17 swizzle
1715 * array, hence protect them from being reaped by removing them from gtt
1717 list_del(&obj->global_list);
1719 ops->put_pages(obj);
1722 if (i915_gem_object_is_purgeable(obj))
1723 i915_gem_object_truncate(obj);
1729 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1731 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1732 struct drm_device *dev;
1734 int page_count, i, j;
1735 struct vm_page *page;
1737 dev = obj->base.dev;
1738 KASSERT(obj->pages == NULL, ("Obj already has pages"));
1739 page_count = obj->base.size / PAGE_SIZE;
1740 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1743 vm_obj = obj->base.vm_obj;
1744 VM_OBJECT_LOCK(vm_obj);
1746 for (i = 0; i < page_count; i++) {
1747 page = shmem_read_mapping_page(vm_obj, i);
1749 i915_gem_purge(dev_priv, page_count);
1753 obj->pages[i] = page;
1756 VM_OBJECT_UNLOCK(vm_obj);
1757 if (i915_gem_object_needs_bit17_swizzle(obj))
1758 i915_gem_object_do_bit_17_swizzle(obj);
1763 for (j = 0; j < i; j++) {
1764 page = obj->pages[j];
1765 vm_page_busy_wait(page, FALSE, "i915gem");
1766 vm_page_unwire(page, 0);
1767 vm_page_wakeup(page);
1769 VM_OBJECT_UNLOCK(vm_obj);
1770 drm_free(obj->pages, M_DRM);
1775 /* Ensure that the associated pages are gathered from the backing storage
1776 * and pinned into our object. i915_gem_object_get_pages() may be called
1777 * multiple times before they are released by a single call to
1778 * i915_gem_object_put_pages() - once the pages are no longer referenced
1779 * either as a result of memory pressure (reaping pages under the shrinker)
1780 * or as the object is itself released.
1783 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1785 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1786 const struct drm_i915_gem_object_ops *ops = obj->ops;
1792 if (obj->madv != I915_MADV_WILLNEED) {
1793 DRM_ERROR("Attempting to obtain a purgeable object\n");
1797 BUG_ON(obj->pages_pin_count);
1799 ret = ops->get_pages(obj);
1803 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1808 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1809 struct intel_ring_buffer *ring)
1811 struct drm_device *dev = obj->base.dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 u32 seqno = intel_ring_get_seqno(ring);
1815 BUG_ON(ring == NULL);
1816 if (obj->ring != ring && obj->last_write_seqno) {
1817 /* Keep the seqno relative to the current ring */
1818 obj->last_write_seqno = seqno;
1822 /* Add a reference if we're newly entering the active list. */
1824 drm_gem_object_reference(&obj->base);
1828 /* Move from whatever list we were on to the tail of execution. */
1829 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1830 list_move_tail(&obj->ring_list, &ring->active_list);
1832 obj->last_read_seqno = seqno;
1834 if (obj->fenced_gpu_access) {
1835 obj->last_fenced_seqno = seqno;
1837 /* Bump MRU to take account of the delayed flush */
1838 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1839 struct drm_i915_fence_reg *reg;
1841 reg = &dev_priv->fence_regs[obj->fence_reg];
1842 list_move_tail(®->lru_list,
1843 &dev_priv->mm.fence_list);
1849 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1851 struct drm_device *dev = obj->base.dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1854 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1855 BUG_ON(!obj->active);
1857 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1859 list_del_init(&obj->ring_list);
1862 obj->last_read_seqno = 0;
1863 obj->last_write_seqno = 0;
1864 obj->base.write_domain = 0;
1866 obj->last_fenced_seqno = 0;
1867 obj->fenced_gpu_access = false;
1870 drm_gem_object_unreference(&obj->base);
1872 WARN_ON(i915_verify_lists(dev));
1876 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_ring_buffer *ring;
1882 /* Carefully retire all requests without writing to the rings */
1883 for_each_ring(ring, dev_priv, i) {
1884 ret = intel_ring_idle(ring);
1888 i915_gem_retire_requests(dev);
1890 /* Finally reset hw state */
1891 for_each_ring(ring, dev_priv, i) {
1892 intel_ring_init_seqno(ring, seqno);
1894 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1895 ring->sync_seqno[j] = 0;
1901 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1909 /* HWS page needs to be set less than what we
1910 * will inject to ring
1912 ret = i915_gem_init_seqno(dev, seqno - 1);
1916 /* Carefully set the last_seqno value so that wrap
1917 * detection still works
1919 dev_priv->next_seqno = seqno;
1920 dev_priv->last_seqno = seqno - 1;
1921 if (dev_priv->last_seqno == 0)
1922 dev_priv->last_seqno--;
1928 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1930 struct drm_i915_private *dev_priv = dev->dev_private;
1932 /* reserve 0 for non-seqno */
1933 if (dev_priv->next_seqno == 0) {
1934 int ret = i915_gem_init_seqno(dev, 0);
1938 dev_priv->next_seqno = 1;
1941 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
1945 int __i915_add_request(struct intel_ring_buffer *ring,
1946 struct drm_file *file,
1947 struct drm_i915_gem_object *obj,
1950 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1951 struct drm_i915_gem_request *request;
1952 u32 request_ring_position, request_start;
1956 request_start = intel_ring_get_tail(ring);
1958 * Emit any outstanding flushes - execbuf can fail to emit the flush
1959 * after having emitted the batchbuffer command. Hence we need to fix
1960 * things up similar to emitting the lazy request. The difference here
1961 * is that the flush _must_ happen before the next request, no matter
1964 ret = intel_ring_flush_all_caches(ring);
1968 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK);
1969 if (request == NULL)
1973 /* Record the position of the start of the request so that
1974 * should we detect the updated seqno part-way through the
1975 * GPU processing the request, we never over-estimate the
1976 * position of the head.
1978 request_ring_position = intel_ring_get_tail(ring);
1980 ret = ring->add_request(ring);
1986 request->seqno = intel_ring_get_seqno(ring);
1987 request->ring = ring;
1988 request->head = request_start;
1989 request->tail = request_ring_position;
1990 request->ctx = ring->last_context;
1991 request->batch_obj = obj;
1993 /* Whilst this request exists, batch_obj will be on the
1994 * active_list, and so will hold the active reference. Only when this
1995 * request is retired will the the batch_obj be moved onto the
1996 * inactive_list and lose its active reference. Hence we do not need
1997 * to explicitly hold another reference here.
2001 i915_gem_context_reference(request->ctx);
2003 request->emitted_jiffies = jiffies;
2004 was_empty = list_empty(&ring->request_list);
2005 list_add_tail(&request->list, &ring->request_list);
2006 request->file_priv = NULL;
2009 struct drm_i915_file_private *file_priv = file->driver_priv;
2011 spin_lock(&file_priv->mm.lock);
2012 request->file_priv = file_priv;
2013 list_add_tail(&request->client_list,
2014 &file_priv->mm.request_list);
2015 spin_unlock(&file_priv->mm.lock);
2018 ring->outstanding_lazy_request = 0;
2020 if (!dev_priv->mm.suspended) {
2021 if (i915_enable_hangcheck) {
2022 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2023 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2026 queue_delayed_work(dev_priv->wq,
2027 &dev_priv->mm.retire_work,
2028 round_jiffies_up_relative(hz));
2029 intel_mark_busy(dev_priv->dev);
2034 *out_seqno = request->seqno;
2039 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2041 struct drm_i915_file_private *file_priv = request->file_priv;
2046 spin_lock(&file_priv->mm.lock);
2047 if (request->file_priv) {
2048 list_del(&request->client_list);
2049 request->file_priv = NULL;
2051 spin_unlock(&file_priv->mm.lock);
2054 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2056 if (acthd >= obj->gtt_offset &&
2057 acthd < obj->gtt_offset + obj->base.size)
2063 static bool i915_head_inside_request(const u32 acthd_unmasked,
2064 const u32 request_start,
2065 const u32 request_end)
2067 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2069 if (request_start < request_end) {
2070 if (acthd >= request_start && acthd < request_end)
2072 } else if (request_start > request_end) {
2073 if (acthd >= request_start || acthd < request_end)
2080 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2081 const u32 acthd, bool *inside)
2083 /* There is a possibility that unmasked head address
2084 * pointing inside the ring, matches the batch_obj address range.
2085 * However this is extremely unlikely.
2088 if (request->batch_obj) {
2089 if (i915_head_inside_object(acthd, request->batch_obj)) {
2095 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2103 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2104 struct drm_i915_gem_request *request,
2107 struct i915_ctx_hang_stats *hs = NULL;
2108 bool inside, guilty;
2110 /* Innocent until proven guilty */
2113 if (ring->hangcheck.action != wait &&
2114 i915_request_guilty(request, acthd, &inside)) {
2115 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2117 inside ? "inside" : "flushing",
2118 request->batch_obj ?
2119 request->batch_obj->gtt_offset : 0,
2120 request->ctx ? request->ctx->id : 0,
2126 /* If contexts are disabled or this is the default context, use
2127 * file_priv->reset_state
2129 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2130 hs = &request->ctx->hang_stats;
2131 else if (request->file_priv)
2132 hs = &request->file_priv->hang_stats;
2138 hs->batch_pending++;
2142 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2144 list_del(&request->list);
2145 i915_gem_request_remove_from_client(request);
2148 i915_gem_context_unreference(request->ctx);
2153 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2154 struct intel_ring_buffer *ring)
2156 u32 completed_seqno;
2159 acthd = intel_ring_get_active_head(ring);
2160 completed_seqno = ring->get_seqno(ring, false);
2162 while (!list_empty(&ring->request_list)) {
2163 struct drm_i915_gem_request *request;
2165 request = list_first_entry(&ring->request_list,
2166 struct drm_i915_gem_request,
2169 if (request->seqno > completed_seqno)
2170 i915_set_reset_status(ring, request, acthd);
2172 i915_gem_free_request(request);
2175 while (!list_empty(&ring->active_list)) {
2176 struct drm_i915_gem_object *obj;
2178 obj = list_first_entry(&ring->active_list,
2179 struct drm_i915_gem_object,
2182 i915_gem_object_move_to_inactive(obj);
2186 void i915_gem_restore_fences(struct drm_device *dev)
2188 struct drm_i915_private *dev_priv = dev->dev_private;
2191 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2192 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2195 * Commit delayed tiling changes if we have an object still
2196 * attached to the fence, otherwise just clear the fence.
2199 i915_gem_object_update_fence(reg->obj, reg,
2200 reg->obj->tiling_mode);
2202 i915_gem_write_fence(dev, i, NULL);
2207 void i915_gem_reset(struct drm_device *dev)
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 struct drm_i915_gem_object *obj;
2211 struct intel_ring_buffer *ring;
2214 for_each_ring(ring, dev_priv, i)
2215 i915_gem_reset_ring_lists(dev_priv, ring);
2217 /* Move everything out of the GPU domains to ensure we do any
2218 * necessary invalidation upon reuse.
2220 list_for_each_entry(obj,
2221 &dev_priv->mm.inactive_list,
2224 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2227 i915_gem_restore_fences(dev);
2231 * This function clears the request list as sequence numbers are passed.
2234 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2238 if (list_empty(&ring->request_list))
2241 WARN_ON(i915_verify_lists(ring->dev));
2243 seqno = ring->get_seqno(ring, true);
2245 while (!list_empty(&ring->request_list)) {
2246 struct drm_i915_gem_request *request;
2248 request = list_first_entry(&ring->request_list,
2249 struct drm_i915_gem_request,
2252 if (!i915_seqno_passed(seqno, request->seqno))
2255 /* We know the GPU must have read the request to have
2256 * sent us the seqno + interrupt, so use the position
2257 * of tail of the request to update the last known position
2260 ring->last_retired_head = request->tail;
2262 i915_gem_free_request(request);
2265 /* Move any buffers on the active list that are no longer referenced
2266 * by the ringbuffer to the flushing/inactive lists as appropriate.
2268 while (!list_empty(&ring->active_list)) {
2269 struct drm_i915_gem_object *obj;
2271 obj = list_first_entry(&ring->active_list,
2272 struct drm_i915_gem_object,
2275 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2278 i915_gem_object_move_to_inactive(obj);
2281 if (unlikely(ring->trace_irq_seqno &&
2282 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2283 ring->irq_put(ring);
2284 ring->trace_irq_seqno = 0;
2290 i915_gem_retire_requests(struct drm_device *dev)
2292 drm_i915_private_t *dev_priv = dev->dev_private;
2293 struct intel_ring_buffer *ring;
2296 for_each_ring(ring, dev_priv, i)
2297 i915_gem_retire_requests_ring(ring);
2301 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
2302 bool purgeable_only)
2304 struct drm_i915_gem_object *obj, *next;
2307 list_for_each_entry_safe(obj, next,
2308 &dev_priv->mm.unbound_list,
2311 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2312 i915_gem_object_put_pages(obj) == 0) {
2313 count += obj->base.size >> PAGE_SHIFT;
2314 if (count >= target)
2320 list_for_each_entry_safe(obj, next,
2321 &dev_priv->mm.inactive_list,
2324 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2325 i915_gem_object_unbind(obj) == 0 &&
2326 i915_gem_object_put_pages(obj) == 0) {
2327 count += obj->base.size >> PAGE_SHIFT;
2328 if (count >= target)
2338 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2340 return __i915_gem_shrink(dev_priv, target, true);
2344 i915_gem_retire_work_handler(struct work_struct *work)
2346 drm_i915_private_t *dev_priv;
2347 struct drm_device *dev;
2348 struct intel_ring_buffer *ring;
2352 dev_priv = container_of(work, drm_i915_private_t,
2353 mm.retire_work.work);
2354 dev = dev_priv->dev;
2356 /* Come back later if the device is busy... */
2357 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT)) {
2358 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2359 round_jiffies_up_relative(hz));
2363 i915_gem_retire_requests(dev);
2365 /* Send a periodic flush down the ring so we don't hold onto GEM
2366 * objects indefinitely.
2369 for_each_ring(ring, dev_priv, i) {
2370 if (ring->gpu_caches_dirty)
2371 i915_add_request(ring, NULL);
2373 idle &= list_empty(&ring->request_list);
2376 if (!dev_priv->mm.suspended && !idle)
2377 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2378 round_jiffies_up_relative(hz));
2380 intel_mark_idle(dev);
2382 mutex_unlock(&dev->struct_mutex);
2385 * Ensures that an object will eventually get non-busy by flushing any required
2386 * write domains, emitting any outstanding lazy request and retiring and
2387 * completed requests.
2390 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2395 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2399 i915_gem_retire_requests_ring(obj->ring);
2406 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2407 * @DRM_IOCTL_ARGS: standard ioctl arguments
2409 * Returns 0 if successful, else an error is returned with the remaining time in
2410 * the timeout parameter.
2411 * -ETIME: object is still busy after timeout
2412 * -ERESTARTSYS: signal interrupted the wait
2413 * -ENONENT: object doesn't exist
2414 * Also possible, but rare:
2415 * -EAGAIN: GPU wedged
2417 * -ENODEV: Internal IRQ fail
2418 * -E?: The add request failed
2420 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2421 * non-zero timeout parameter the wait ioctl will wait for the given number of
2422 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2423 * without holding struct_mutex the object may become re-busied before this
2424 * function completes. A similar but shorter * race condition exists in the busy
2428 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2430 drm_i915_private_t *dev_priv = dev->dev_private;
2431 struct drm_i915_gem_wait *args = data;
2432 struct drm_i915_gem_object *obj;
2433 struct intel_ring_buffer *ring = NULL;
2434 struct timespec timeout_stack, *timeout = NULL;
2435 unsigned reset_counter;
2439 if (args->timeout_ns >= 0) {
2440 timeout_stack = ns_to_timespec(args->timeout_ns);
2441 timeout = &timeout_stack;
2444 ret = i915_mutex_lock_interruptible(dev);
2448 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2449 if (&obj->base == NULL) {
2450 mutex_unlock(&dev->struct_mutex);
2454 /* Need to make sure the object gets inactive eventually. */
2455 ret = i915_gem_object_flush_active(obj);
2460 seqno = obj->last_read_seqno;
2467 /* Do this after OLR check to make sure we make forward progress polling
2468 * on this IOCTL with a 0 timeout (like busy ioctl)
2470 if (!args->timeout_ns) {
2475 drm_gem_object_unreference(&obj->base);
2476 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2477 mutex_unlock(&dev->struct_mutex);
2479 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2481 args->timeout_ns = timespec_to_ns(timeout);
2485 drm_gem_object_unreference(&obj->base);
2486 mutex_unlock(&dev->struct_mutex);
2491 * i915_gem_object_sync - sync an object to a ring.
2493 * @obj: object which may be in use on another ring.
2494 * @to: ring we wish to use the object on. May be NULL.
2496 * This code is meant to abstract object synchronization with the GPU.
2497 * Calling with NULL implies synchronizing the object with the CPU
2498 * rather than a particular GPU ring.
2500 * Returns 0 if successful, else propagates up the lower layer error.
2503 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2504 struct intel_ring_buffer *to)
2506 struct intel_ring_buffer *from = obj->ring;
2510 if (from == NULL || to == from)
2513 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2514 return i915_gem_object_wait_rendering(obj, false);
2516 idx = intel_ring_sync_index(from, to);
2518 seqno = obj->last_read_seqno;
2519 if (seqno <= from->sync_seqno[idx])
2522 ret = i915_gem_check_olr(obj->ring, seqno);
2526 ret = to->sync_to(to, from, seqno);
2528 /* We use last_read_seqno because sync_to()
2529 * might have just caused seqno wrap under
2532 from->sync_seqno[idx] = obj->last_read_seqno;
2537 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2539 u32 old_write_domain, old_read_domains;
2541 /* Force a pagefault for domain tracking on next user access */
2542 i915_gem_release_mmap(obj);
2544 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2547 /* Wait for any direct GTT access to complete */
2550 old_read_domains = obj->base.read_domains;
2551 old_write_domain = obj->base.write_domain;
2553 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2554 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2559 * Unbinds an object from the GTT aperture.
2562 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2564 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2567 if (obj->gtt_space == NULL)
2573 BUG_ON(obj->pages == NULL);
2575 ret = i915_gem_object_finish_gpu(obj);
2578 /* Continue on if we fail due to EIO, the GPU is hung so we
2579 * should be safe and we need to cleanup or else we might
2580 * cause memory corruption through use-after-free.
2583 i915_gem_object_finish_gtt(obj);
2585 /* Move the object to the CPU domain to ensure that
2586 * any possible CPU writes while it's not in the GTT
2587 * are flushed when we go to remap it.
2590 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2591 if (ret == -ERESTARTSYS)
2594 /* In the event of a disaster, abandon all caches and
2595 * hope for the best.
2597 i915_gem_clflush_object(obj);
2598 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2601 /* release the fence reg _after_ flushing */
2602 ret = i915_gem_object_put_fence(obj);
2606 if (obj->has_global_gtt_mapping)
2607 i915_gem_gtt_unbind_object(obj);
2608 if (obj->has_aliasing_ppgtt_mapping) {
2609 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2610 obj->has_aliasing_ppgtt_mapping = 0;
2612 i915_gem_gtt_finish_object(obj);
2614 i915_gem_object_put_pages_gtt(obj);
2616 list_del_init(&obj->global_list);
2617 list_del_init(&obj->mm_list);
2618 /* Avoid an unnecessary call to unbind on rebind. */
2619 obj->map_and_fenceable = true;
2621 drm_mm_put_block(obj->gtt_space);
2622 obj->gtt_space = NULL;
2623 obj->gtt_offset = 0;
2625 if (i915_gem_object_is_purgeable(obj))
2626 i915_gem_object_truncate(obj);
2631 int i915_gpu_idle(struct drm_device *dev)
2633 drm_i915_private_t *dev_priv = dev->dev_private;
2634 struct intel_ring_buffer *ring;
2637 /* Flush everything onto the inactive list. */
2638 for_each_ring(ring, dev_priv, i) {
2639 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2643 ret = intel_ring_idle(ring);
2651 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2652 struct drm_i915_gem_object *obj)
2654 drm_i915_private_t *dev_priv = dev->dev_private;
2656 int fence_pitch_shift;
2658 if (INTEL_INFO(dev)->gen >= 6) {
2659 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2660 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2662 fence_reg = FENCE_REG_965_0;
2663 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2666 fence_reg += reg * 8;
2668 /* To w/a incoherency with non-atomic 64-bit register updates,
2669 * we split the 64-bit update into two 32-bit writes. In order
2670 * for a partial fence not to be evaluated between writes, we
2671 * precede the update with write to turn off the fence register,
2672 * and only enable the fence as the last step.
2674 * For extra levels of paranoia, we make sure each step lands
2675 * before applying the next step.
2677 I915_WRITE(fence_reg, 0);
2678 POSTING_READ(fence_reg);
2681 u32 size = obj->gtt_space->size;
2684 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2686 val |= obj->gtt_offset & 0xfffff000;
2687 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2688 if (obj->tiling_mode == I915_TILING_Y)
2689 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2690 val |= I965_FENCE_REG_VALID;
2692 I915_WRITE(fence_reg + 4, val >> 32);
2693 POSTING_READ(fence_reg + 4);
2695 I915_WRITE(fence_reg + 0, val);
2696 POSTING_READ(fence_reg);
2698 I915_WRITE(fence_reg + 4, 0);
2699 POSTING_READ(fence_reg + 4);
2703 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2704 struct drm_i915_gem_object *obj)
2706 drm_i915_private_t *dev_priv = dev->dev_private;
2710 u32 size = obj->gtt_space->size;
2714 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2715 (size & -size) != size ||
2716 (obj->gtt_offset & (size - 1)),
2717 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2718 obj->gtt_offset, obj->map_and_fenceable, size);
2720 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2725 /* Note: pitch better be a power of two tile widths */
2726 pitch_val = obj->stride / tile_width;
2727 pitch_val = ffs(pitch_val) - 1;
2729 val = obj->gtt_offset;
2730 if (obj->tiling_mode == I915_TILING_Y)
2731 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2732 val |= I915_FENCE_SIZE_BITS(size);
2733 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2734 val |= I830_FENCE_REG_VALID;
2739 reg = FENCE_REG_830_0 + reg * 4;
2741 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2743 I915_WRITE(reg, val);
2747 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2748 struct drm_i915_gem_object *obj)
2750 drm_i915_private_t *dev_priv = dev->dev_private;
2754 u32 size = obj->gtt_space->size;
2757 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2758 (size & -size) != size ||
2759 (obj->gtt_offset & (size - 1)),
2760 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2761 obj->gtt_offset, size);
2763 pitch_val = obj->stride / 128;
2764 pitch_val = ffs(pitch_val) - 1;
2766 val = obj->gtt_offset;
2767 if (obj->tiling_mode == I915_TILING_Y)
2768 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2769 val |= I830_FENCE_SIZE_BITS(size);
2770 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2771 val |= I830_FENCE_REG_VALID;
2775 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2776 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2779 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2781 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2784 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2785 struct drm_i915_gem_object *obj)
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2789 /* Ensure that all CPU reads are completed before installing a fence
2790 * and all writes before removing the fence.
2792 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2795 WARN(obj && (!obj->stride || !obj->tiling_mode),
2796 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2797 obj->stride, obj->tiling_mode);
2799 switch (INTEL_INFO(dev)->gen) {
2803 case 4: i965_write_fence_reg(dev, reg, obj); break;
2804 case 3: i915_write_fence_reg(dev, reg, obj); break;
2805 case 2: i830_write_fence_reg(dev, reg, obj); break;
2809 /* And similarly be paranoid that no direct access to this region
2810 * is reordered to before the fence is installed.
2812 if (i915_gem_object_needs_mb(obj))
2816 static inline int fence_number(struct drm_i915_private *dev_priv,
2817 struct drm_i915_fence_reg *fence)
2819 return fence - dev_priv->fence_regs;
2822 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2823 struct drm_i915_fence_reg *fence,
2826 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2827 int reg = fence_number(dev_priv, fence);
2829 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2832 obj->fence_reg = reg;
2834 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2836 obj->fence_reg = I915_FENCE_REG_NONE;
2838 list_del_init(&fence->lru_list);
2840 obj->fence_dirty = false;
2844 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2846 if (obj->last_fenced_seqno) {
2847 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2851 obj->last_fenced_seqno = 0;
2854 obj->fenced_gpu_access = false;
2859 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2861 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2862 struct drm_i915_fence_reg *fence;
2865 ret = i915_gem_object_wait_fence(obj);
2869 if (obj->fence_reg == I915_FENCE_REG_NONE)
2872 fence = &dev_priv->fence_regs[obj->fence_reg];
2874 i915_gem_object_fence_lost(obj);
2875 i915_gem_object_update_fence(obj, fence, false);
2880 static struct drm_i915_fence_reg *
2881 i915_find_fence_reg(struct drm_device *dev)
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct drm_i915_fence_reg *reg, *avail;
2887 /* First try to find a free reg */
2889 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2890 reg = &dev_priv->fence_regs[i];
2894 if (!reg->pin_count)
2901 /* None available, try to steal one or wait for a user to finish */
2902 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2913 * i915_gem_object_get_fence - set up fencing for an object
2914 * @obj: object to map through a fence reg
2916 * When mapping objects through the GTT, userspace wants to be able to write
2917 * to them without having to worry about swizzling if the object is tiled.
2918 * This function walks the fence regs looking for a free one for @obj,
2919 * stealing one if it can't find any.
2921 * It then sets up the reg based on the object's properties: address, pitch
2922 * and tiling format.
2924 * For an untiled surface, this removes any existing fence.
2927 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2929 struct drm_device *dev = obj->base.dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 bool enable = obj->tiling_mode != I915_TILING_NONE;
2932 struct drm_i915_fence_reg *reg;
2935 /* Have we updated the tiling parameters upon the object and so
2936 * will need to serialise the write to the associated fence register?
2938 if (obj->fence_dirty) {
2939 ret = i915_gem_object_wait_fence(obj);
2944 /* Just update our place in the LRU if our fence is getting reused. */
2945 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2946 reg = &dev_priv->fence_regs[obj->fence_reg];
2947 if (!obj->fence_dirty) {
2948 list_move_tail(®->lru_list,
2949 &dev_priv->mm.fence_list);
2952 } else if (enable) {
2953 reg = i915_find_fence_reg(dev);
2958 struct drm_i915_gem_object *old = reg->obj;
2960 ret = i915_gem_object_wait_fence(old);
2964 i915_gem_object_fence_lost(old);
2969 i915_gem_object_update_fence(obj, reg, enable);
2974 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2975 struct drm_mm_node *gtt_space,
2976 unsigned long cache_level)
2978 struct drm_mm_node *other;
2980 /* On non-LLC machines we have to be careful when putting differing
2981 * types of snoopable memory together to avoid the prefetcher
2982 * crossing memory domains and dying.
2987 if (gtt_space == NULL)
2990 if (list_empty(>t_space->node_list))
2993 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2994 if (other->allocated && !other->hole_follows && other->color != cache_level)
2997 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2998 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3004 static void i915_gem_verify_gtt(struct drm_device *dev)
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 struct drm_i915_gem_object *obj;
3011 list_for_each_entry(obj, &dev_priv->mm.global_list, global_list) {
3012 if (obj->gtt_space == NULL) {
3013 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3018 if (obj->cache_level != obj->gtt_space->color) {
3019 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3020 obj->gtt_space->start,
3021 obj->gtt_space->start + obj->gtt_space->size,
3023 obj->gtt_space->color);
3028 if (!i915_gem_valid_gtt_space(dev,
3030 obj->cache_level)) {
3031 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3032 obj->gtt_space->start,
3033 obj->gtt_space->start + obj->gtt_space->size,
3045 * Finds free space in the GTT aperture and binds the object there.
3048 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3050 bool map_and_fenceable,
3053 struct drm_device *dev = obj->base.dev;
3054 drm_i915_private_t *dev_priv = dev->dev_private;
3055 struct drm_mm_node *node;
3056 u32 size, fence_size, fence_alignment, unfenced_alignment;
3057 bool mappable, fenceable;
3058 size_t gtt_max = map_and_fenceable ?
3059 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3062 fence_size = i915_gem_get_gtt_size(dev,
3065 fence_alignment = i915_gem_get_gtt_alignment(dev,
3067 obj->tiling_mode, true);
3068 unfenced_alignment =
3069 i915_gem_get_gtt_alignment(dev,
3071 obj->tiling_mode, false);
3074 alignment = map_and_fenceable ? fence_alignment :
3076 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3077 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3081 size = map_and_fenceable ? fence_size : obj->base.size;
3083 /* If the object is bigger than the entire aperture, reject it early
3084 * before evicting everything in a vain attempt to find space.
3086 if (obj->base.size > gtt_max) {
3087 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3089 map_and_fenceable ? "mappable" : "total",
3095 if (map_and_fenceable)
3096 node = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
3097 size, alignment, obj->cache_level,
3098 0, dev_priv->gtt.mappable_end,
3101 node = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
3102 size, alignment, obj->cache_level,
3105 if (map_and_fenceable)
3107 drm_mm_get_block_range_generic(node,
3108 size, alignment, obj->cache_level,
3109 0, dev_priv->gtt.mappable_end,
3113 drm_mm_get_block_generic(node,
3114 size, alignment, obj->cache_level,
3117 if (obj->gtt_space == NULL) {
3118 ret = i915_gem_evict_something(dev, size, alignment,
3129 * NOTE: i915_gem_object_get_pages_gtt() cannot
3130 * return ENOMEM, since we used VM_ALLOC_RETRY.
3132 ret = i915_gem_object_get_pages_gtt(obj);
3134 drm_mm_put_block(obj->gtt_space);
3135 obj->gtt_space = NULL;
3139 i915_gem_gtt_bind_object(obj, obj->cache_level);
3141 i915_gem_object_put_pages_gtt(obj);
3142 drm_mm_put_block(obj->gtt_space);
3143 obj->gtt_space = NULL;
3144 if (i915_gem_evict_everything(dev))
3149 list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
3150 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3152 obj->gtt_offset = obj->gtt_space->start;
3155 obj->gtt_space->size == fence_size &&
3156 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
3159 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3161 obj->map_and_fenceable = mappable && fenceable;
3163 trace_i915_gem_object_bind(obj, map_and_fenceable);
3164 i915_gem_verify_gtt(dev);
3169 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3172 /* If we don't have a page list set up, then we're not pinned
3173 * to GPU, and we can ignore the cache flush because it'll happen
3174 * again at bind time.
3176 if (obj->pages == NULL)
3180 * Stolen memory is always coherent with the GPU as it is explicitly
3181 * marked as wc by the system, or the system is cache-coherent.
3186 /* If the GPU is snooping the contents of the CPU cache,
3187 * we do not need to manually clear the CPU cache lines. However,
3188 * the caches are only snooped when the render cache is
3189 * flushed/invalidated. As we always have to emit invalidations
3190 * and flushes when moving into and out of the RENDER domain, correct
3191 * snooping behaviour occurs naturally as the result of our domain
3194 if (obj->cache_level != I915_CACHE_NONE)
3197 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3200 /** Flushes the GTT write domain for the object if it's dirty. */
3202 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3204 uint32_t old_write_domain;
3206 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3209 /* No actual flushing is required for the GTT write domain. Writes
3210 * to it immediately go to main memory as far as we know, so there's
3211 * no chipset flush. It also doesn't land in render cache.
3213 * However, we do have to enforce the order so that all writes through
3214 * the GTT land before any writes to the device, such as updates to
3219 old_write_domain = obj->base.write_domain;
3220 obj->base.write_domain = 0;
3223 /** Flushes the CPU write domain for the object if it's dirty. */
3225 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3227 uint32_t old_write_domain;
3229 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3232 i915_gem_clflush_object(obj);
3233 i915_gem_chipset_flush(obj->base.dev);
3234 old_write_domain = obj->base.write_domain;
3235 obj->base.write_domain = 0;
3239 * Moves a single object to the GTT read, and possibly write domain.
3241 * This function returns when the move is complete, including waiting on
3245 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3247 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3248 uint32_t old_write_domain, old_read_domains;
3251 /* Not valid to be called on unbound objects. */
3252 if (obj->gtt_space == NULL)
3255 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3258 ret = i915_gem_object_wait_rendering(obj, !write);
3262 i915_gem_object_flush_cpu_write_domain(obj);
3264 /* Serialise direct access to this object with the barriers for
3265 * coherent writes from the GPU, by effectively invalidating the
3266 * GTT domain upon first access.
3268 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3271 old_write_domain = obj->base.write_domain;
3272 old_read_domains = obj->base.read_domains;
3274 /* It should now be out of any other write domains, and we can update
3275 * the domain values for our changes.
3277 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3278 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3280 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3281 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3285 /* And bump the LRU for this access */
3286 if (i915_gem_object_is_inactive(obj))
3287 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3292 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3293 enum i915_cache_level cache_level)
3295 struct drm_device *dev = obj->base.dev;
3296 drm_i915_private_t *dev_priv = dev->dev_private;
3299 if (obj->cache_level == cache_level)
3302 if (obj->pin_count) {
3303 DRM_DEBUG("can not change the cache level of pinned objects\n");
3307 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3308 ret = i915_gem_object_unbind(obj);
3313 if (obj->gtt_space) {
3314 ret = i915_gem_object_finish_gpu(obj);
3318 i915_gem_object_finish_gtt(obj);
3320 /* Before SandyBridge, you could not use tiling or fence
3321 * registers with snooped memory, so relinquish any fences
3322 * currently pointing to our region in the aperture.
3324 if (INTEL_INFO(dev)->gen < 6) {
3325 ret = i915_gem_object_put_fence(obj);
3330 if (obj->has_global_gtt_mapping)
3331 i915_gem_gtt_bind_object(obj, cache_level);
3332 if (obj->has_aliasing_ppgtt_mapping)
3333 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3336 obj->gtt_space->color = cache_level;
3339 if (cache_level == I915_CACHE_NONE) {
3340 u32 old_read_domains, old_write_domain;
3342 /* If we're coming from LLC cached, then we haven't
3343 * actually been tracking whether the data is in the
3344 * CPU cache or not, since we only allow one bit set
3345 * in obj->write_domain and have been skipping the clflushes.
3346 * Just set it to the CPU cache for now.
3348 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3349 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3351 old_read_domains = obj->base.read_domains;
3352 old_write_domain = obj->base.write_domain;
3354 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3355 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3359 obj->cache_level = cache_level;
3360 i915_gem_verify_gtt(dev);
3364 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3365 struct drm_file *file)
3367 struct drm_i915_gem_caching *args = data;
3368 struct drm_i915_gem_object *obj;
3371 ret = i915_mutex_lock_interruptible(dev);
3375 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3376 if (&obj->base == NULL) {
3381 args->caching = obj->cache_level != I915_CACHE_NONE;
3383 drm_gem_object_unreference(&obj->base);
3385 mutex_unlock(&dev->struct_mutex);
3389 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3390 struct drm_file *file)
3392 struct drm_i915_gem_caching *args = data;
3393 struct drm_i915_gem_object *obj;
3394 enum i915_cache_level level;
3397 switch (args->caching) {
3398 case I915_CACHING_NONE:
3399 level = I915_CACHE_NONE;
3401 case I915_CACHING_CACHED:
3402 level = I915_CACHE_LLC;
3408 ret = i915_mutex_lock_interruptible(dev);
3412 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3413 if (&obj->base == NULL) {
3418 ret = i915_gem_object_set_cache_level(obj, level);
3420 drm_gem_object_unreference(&obj->base);
3422 mutex_unlock(&dev->struct_mutex);
3427 * Prepare buffer for display plane (scanout, cursors, etc).
3428 * Can be called from an uninterruptible phase (modesetting) and allows
3429 * any flushes to be pipelined (for pageflips).
3432 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3434 struct intel_ring_buffer *pipelined)
3436 u32 old_read_domains, old_write_domain;
3439 if (pipelined != obj->ring) {
3440 ret = i915_gem_object_sync(obj, pipelined);
3445 /* The display engine is not coherent with the LLC cache on gen6. As
3446 * a result, we make sure that the pinning that is about to occur is
3447 * done with uncached PTEs. This is lowest common denominator for all
3450 * However for gen6+, we could do better by using the GFDT bit instead
3451 * of uncaching, which would allow us to flush all the LLC-cached data
3452 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3454 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3458 /* As the user may map the buffer once pinned in the display plane
3459 * (e.g. libkms for the bootup splash), we have to ensure that we
3460 * always use map_and_fenceable for all scanout buffers.
3462 ret = i915_gem_object_pin(obj, alignment, true, false);
3466 i915_gem_object_flush_cpu_write_domain(obj);
3468 old_write_domain = obj->base.write_domain;
3469 old_read_domains = obj->base.read_domains;
3471 /* It should now be out of any other write domains, and we can update
3472 * the domain values for our changes.
3474 obj->base.write_domain = 0;
3475 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3481 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3485 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3488 ret = i915_gem_object_wait_rendering(obj, false);
3492 /* Ensure that we invalidate the GPU's caches and TLBs. */
3493 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3498 * Moves a single object to the CPU read, and possibly write domain.
3500 * This function returns when the move is complete, including waiting on
3504 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3506 uint32_t old_write_domain, old_read_domains;
3509 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3512 ret = i915_gem_object_wait_rendering(obj, !write);
3516 i915_gem_object_flush_gtt_write_domain(obj);
3518 old_write_domain = obj->base.write_domain;
3519 old_read_domains = obj->base.read_domains;
3521 /* Flush the CPU cache if it's still invalid. */
3522 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3523 i915_gem_clflush_object(obj);
3525 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3528 /* It should now be out of any other write domains, and we can update
3529 * the domain values for our changes.
3531 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3533 /* If we're writing through the CPU, then the GPU read domains will
3534 * need to be invalidated at next use.
3537 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3538 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3544 /* Throttle our rendering by waiting until the ring has completed our requests
3545 * emitted over 20 msec ago.
3547 * Note that if we were to use the current jiffies each time around the loop,
3548 * we wouldn't escape the function with any frames outstanding if the time to
3549 * render a frame was over 20ms.
3551 * This should get us reasonable parallelism between CPU and GPU but also
3552 * relatively low latency when blocking on a particular request to finish.
3555 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 struct drm_i915_file_private *file_priv = file->driver_priv;
3559 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3560 struct drm_i915_gem_request *request;
3561 struct intel_ring_buffer *ring = NULL;
3562 unsigned reset_counter;
3566 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3570 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3574 spin_lock(&file_priv->mm.lock);
3575 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3576 if (time_after_eq(request->emitted_jiffies, recent_enough))
3579 ring = request->ring;
3580 seqno = request->seqno;
3582 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3583 spin_unlock(&file_priv->mm.lock);
3588 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3590 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3596 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3598 bool map_and_fenceable,
3603 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3606 if (obj->gtt_space != NULL) {
3607 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3608 (map_and_fenceable && !obj->map_and_fenceable)) {
3609 WARN(obj->pin_count,
3610 "bo is already pinned with incorrect alignment:"
3611 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3612 " obj->map_and_fenceable=%d\n",
3613 obj->gtt_offset, alignment,
3615 obj->map_and_fenceable);
3616 ret = i915_gem_object_unbind(obj);
3622 if (obj->gtt_space == NULL) {
3623 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3625 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3631 if (!dev_priv->mm.aliasing_ppgtt)
3632 i915_gem_gtt_bind_object(obj, obj->cache_level);
3635 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3636 i915_gem_gtt_bind_object(obj, obj->cache_level);
3639 obj->pin_mappable |= map_and_fenceable;
3645 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3647 BUG_ON(obj->pin_count == 0);
3648 BUG_ON(obj->gtt_space == NULL);
3650 if (--obj->pin_count == 0)
3651 obj->pin_mappable = false;
3655 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3656 struct drm_file *file)
3658 struct drm_i915_gem_pin *args = data;
3659 struct drm_i915_gem_object *obj;
3662 ret = i915_mutex_lock_interruptible(dev);
3666 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3667 if (&obj->base == NULL) {
3672 if (obj->madv != I915_MADV_WILLNEED) {
3673 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3678 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3679 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3685 if (obj->user_pin_count == 0) {
3686 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3691 obj->user_pin_count++;
3692 obj->pin_filp = file;
3694 /* XXX - flush the CPU caches for pinned objects
3695 * as the X server doesn't manage domains yet
3697 i915_gem_object_flush_cpu_write_domain(obj);
3698 args->offset = obj->gtt_offset;
3700 drm_gem_object_unreference(&obj->base);
3702 mutex_unlock(&dev->struct_mutex);
3707 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3708 struct drm_file *file)
3710 struct drm_i915_gem_pin *args = data;
3711 struct drm_i915_gem_object *obj;
3714 ret = i915_mutex_lock_interruptible(dev);
3718 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3719 if (&obj->base == NULL) {
3724 if (obj->pin_filp != file) {
3725 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3730 obj->user_pin_count--;
3731 if (obj->user_pin_count == 0) {
3732 obj->pin_filp = NULL;
3733 i915_gem_object_unpin(obj);
3737 drm_gem_object_unreference(&obj->base);
3739 mutex_unlock(&dev->struct_mutex);
3744 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3745 struct drm_file *file)
3747 struct drm_i915_gem_busy *args = data;
3748 struct drm_i915_gem_object *obj;
3751 ret = i915_mutex_lock_interruptible(dev);
3755 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3756 if (&obj->base == NULL) {
3761 /* Count all active objects as busy, even if they are currently not used
3762 * by the gpu. Users of this interface expect objects to eventually
3763 * become non-busy without any further actions, therefore emit any
3764 * necessary flushes here.
3766 ret = i915_gem_object_flush_active(obj);
3768 args->busy = obj->active;
3770 args->busy |= intel_ring_flag(obj->ring) << 16;
3773 drm_gem_object_unreference(&obj->base);
3775 mutex_unlock(&dev->struct_mutex);
3780 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3781 struct drm_file *file_priv)
3783 return i915_gem_ring_throttle(dev, file_priv);
3787 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3788 struct drm_file *file_priv)
3790 struct drm_i915_gem_madvise *args = data;
3791 struct drm_i915_gem_object *obj;
3794 switch (args->madv) {
3795 case I915_MADV_DONTNEED:
3796 case I915_MADV_WILLNEED:
3802 ret = i915_mutex_lock_interruptible(dev);
3806 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3807 if (&obj->base == NULL) {
3812 if (obj->pin_count) {
3817 if (obj->madv != __I915_MADV_PURGED)
3818 obj->madv = args->madv;
3820 /* if the object is no longer attached, discard its backing storage */
3821 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3822 i915_gem_object_truncate(obj);
3824 args->retained = obj->madv != __I915_MADV_PURGED;
3827 drm_gem_object_unreference(&obj->base);
3829 mutex_unlock(&dev->struct_mutex);
3833 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3834 const struct drm_i915_gem_object_ops *ops)
3836 INIT_LIST_HEAD(&obj->mm_list);
3837 INIT_LIST_HEAD(&obj->global_list);
3838 INIT_LIST_HEAD(&obj->ring_list);
3839 INIT_LIST_HEAD(&obj->exec_list);
3843 obj->fence_reg = I915_FENCE_REG_NONE;
3844 obj->madv = I915_MADV_WILLNEED;
3845 /* Avoid an unnecessary call to unbind on the first bind. */
3846 obj->map_and_fenceable = true;
3848 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3851 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3852 .get_pages = i915_gem_object_get_pages_gtt,
3853 .put_pages = i915_gem_object_put_pages_gtt,
3856 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3859 struct drm_i915_gem_object *obj;
3861 struct address_space *mapping;
3865 obj = kmalloc(sizeof(*obj), M_DRM, M_WAITOK | M_ZERO);
3869 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3875 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3876 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3877 /* 965gm cannot relocate objects above 4GiB. */
3878 mask &= ~__GFP_HIGHMEM;
3879 mask |= __GFP_DMA32;
3882 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3883 mapping_set_gfp_mask(mapping, mask);
3886 i915_gem_object_init(obj, &i915_gem_object_ops);
3888 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3889 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3892 /* On some devices, we can have the GPU use the LLC (the CPU
3893 * cache) for about a 10% performance improvement
3894 * compared to uncached. Graphics requests other than
3895 * display scanout are coherent with the CPU in
3896 * accessing this cache. This means in this mode we
3897 * don't need to clflush on the CPU side, and on the
3898 * GPU side we only need to flush internal caches to
3899 * get data visible to the CPU.
3901 * However, we maintain the display planes as UC, and so
3902 * need to rebind when first used as such.
3904 obj->cache_level = I915_CACHE_LLC;
3906 obj->cache_level = I915_CACHE_NONE;
3911 int i915_gem_init_object(struct drm_gem_object *obj)
3918 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3920 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3921 struct drm_device *dev = obj->base.dev;
3922 drm_i915_private_t *dev_priv = dev->dev_private;
3925 i915_gem_detach_phys_object(dev, obj);
3928 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3929 bool was_interruptible;
3931 was_interruptible = dev_priv->mm.interruptible;
3932 dev_priv->mm.interruptible = false;
3934 WARN_ON(i915_gem_object_unbind(obj));
3936 dev_priv->mm.interruptible = was_interruptible;
3939 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3940 * before progressing. */
3942 i915_gem_object_unpin_pages(obj);
3944 if (WARN_ON(obj->pages_pin_count))
3945 obj->pages_pin_count = 0;
3946 i915_gem_object_put_pages(obj);
3947 drm_gem_free_mmap_offset(&obj->base);
3951 drm_gem_object_release(&obj->base);
3952 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3955 i915_gem_object_free(obj);
3959 i915_gem_idle(struct drm_device *dev)
3961 drm_i915_private_t *dev_priv = dev->dev_private;
3964 mutex_lock(&dev->struct_mutex);
3966 if (dev_priv->mm.suspended) {
3967 mutex_unlock(&dev->struct_mutex);
3971 ret = i915_gpu_idle(dev);
3973 mutex_unlock(&dev->struct_mutex);
3976 i915_gem_retire_requests(dev);
3978 /* Under UMS, be paranoid and evict. */
3979 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3980 i915_gem_evict_everything(dev);
3982 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3983 * We need to replace this with a semaphore, or something.
3984 * And not confound mm.suspended!
3986 dev_priv->mm.suspended = 1;
3987 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
3989 i915_kernel_lost_context(dev);
3990 i915_gem_cleanup_ringbuffer(dev);
3992 mutex_unlock(&dev->struct_mutex);
3994 /* Cancel the retire work handler, which should be idle now. */
3995 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4000 void i915_gem_l3_remap(struct drm_device *dev)
4002 drm_i915_private_t *dev_priv = dev->dev_private;
4006 if (!HAS_L3_GPU_CACHE(dev))
4009 if (!dev_priv->l3_parity.remap_info)
4012 misccpctl = I915_READ(GEN7_MISCCPCTL);
4013 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4014 POSTING_READ(GEN7_MISCCPCTL);
4016 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4017 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4018 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4019 DRM_DEBUG("0x%x was already programmed to %x\n",
4020 GEN7_L3LOG_BASE + i, remap);
4021 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4022 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4023 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4026 /* Make sure all the writes land before disabling dop clock gating */
4027 POSTING_READ(GEN7_L3LOG_BASE);
4029 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4032 void i915_gem_init_swizzling(struct drm_device *dev)
4034 drm_i915_private_t *dev_priv = dev->dev_private;
4036 if (INTEL_INFO(dev)->gen < 5 ||
4037 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4040 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4041 DISP_TILE_SURFACE_SWIZZLING);
4046 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4048 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4049 else if (IS_GEN7(dev))
4050 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4056 intel_enable_blt(struct drm_device *dev)
4063 /* The blitter was dysfunctional on early prototypes */
4064 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
4065 if (IS_GEN6(dev) && revision < 8) {
4066 DRM_INFO("BLT not supported on this pre-production hardware;"
4067 " graphics performance will be degraded.\n");
4074 static int i915_gem_init_rings(struct drm_device *dev)
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4079 ret = intel_init_render_ring_buffer(dev);
4084 ret = intel_init_bsd_ring_buffer(dev);
4086 goto cleanup_render_ring;
4089 if (intel_enable_blt(dev)) {
4090 ret = intel_init_blt_ring_buffer(dev);
4092 goto cleanup_bsd_ring;
4095 if (HAS_VEBOX(dev)) {
4096 ret = intel_init_vebox_ring_buffer(dev);
4098 goto cleanup_blt_ring;
4102 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4104 goto cleanup_vebox_ring;
4109 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4111 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4113 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4114 cleanup_render_ring:
4115 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4121 i915_gem_init_hw(struct drm_device *dev)
4123 drm_i915_private_t *dev_priv = dev->dev_private;
4127 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4131 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4132 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4134 if (HAS_PCH_NOP(dev)) {
4135 u32 temp = I915_READ(GEN7_MSG_CTL);
4136 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4137 I915_WRITE(GEN7_MSG_CTL, temp);
4140 i915_gem_l3_remap(dev);
4142 i915_gem_init_swizzling(dev);
4144 ret = i915_gem_init_rings(dev);
4149 * XXX: There was some w/a described somewhere suggesting loading
4150 * contexts before PPGTT.
4152 i915_gem_context_init(dev);
4153 if (dev_priv->mm.aliasing_ppgtt) {
4154 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4156 i915_gem_cleanup_aliasing_ppgtt(dev);
4157 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4164 int i915_gem_init(struct drm_device *dev)
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4169 mutex_lock(&dev->struct_mutex);
4171 if (IS_VALLEYVIEW(dev)) {
4172 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4173 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4174 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4175 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4178 i915_gem_init_global_gtt(dev);
4180 ret = i915_gem_init_hw(dev);
4181 mutex_unlock(&dev->struct_mutex);
4183 i915_gem_cleanup_aliasing_ppgtt(dev);
4187 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4188 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4189 dev_priv->dri1.allow_batchbuffer = 1;
4194 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4196 drm_i915_private_t *dev_priv = dev->dev_private;
4197 struct intel_ring_buffer *ring;
4200 for_each_ring(ring, dev_priv, i)
4201 intel_cleanup_ring_buffer(ring);
4205 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4206 struct drm_file *file_priv)
4208 drm_i915_private_t *dev_priv = dev->dev_private;
4211 if (drm_core_check_feature(dev, DRIVER_MODESET))
4214 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4215 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4216 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4219 mutex_lock(&dev->struct_mutex);
4220 dev_priv->mm.suspended = 0;
4222 ret = i915_gem_init_hw(dev);
4224 mutex_unlock(&dev->struct_mutex);
4228 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
4229 mutex_unlock(&dev->struct_mutex);
4231 ret = drm_irq_install(dev);
4233 goto cleanup_ringbuffer;
4238 mutex_lock(&dev->struct_mutex);
4239 i915_gem_cleanup_ringbuffer(dev);
4240 dev_priv->mm.suspended = 1;
4241 mutex_unlock(&dev->struct_mutex);
4247 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4248 struct drm_file *file_priv)
4250 if (drm_core_check_feature(dev, DRIVER_MODESET))
4253 drm_irq_uninstall(dev);
4254 return i915_gem_idle(dev);
4258 i915_gem_lastclose(struct drm_device *dev)
4262 if (drm_core_check_feature(dev, DRIVER_MODESET))
4265 ret = i915_gem_idle(dev);
4267 DRM_ERROR("failed to idle hardware: %d\n", ret);
4271 init_ring_lists(struct intel_ring_buffer *ring)
4273 INIT_LIST_HEAD(&ring->active_list);
4274 INIT_LIST_HEAD(&ring->request_list);
4278 i915_gem_load(struct drm_device *dev)
4281 drm_i915_private_t *dev_priv = dev->dev_private;
4283 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4284 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4285 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4286 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4287 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4288 for (i = 0; i < I915_NUM_RINGS; i++)
4289 init_ring_lists(&dev_priv->ring[i]);
4290 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4291 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4292 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4293 i915_gem_retire_work_handler);
4294 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4296 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4298 I915_WRITE(MI_ARB_STATE,
4299 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4302 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4304 /* Old X drivers will take 0-2 for front, back, depth buffers */
4305 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4306 dev_priv->fence_reg_start = 3;
4308 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4309 dev_priv->num_fence_regs = 32;
4310 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4311 dev_priv->num_fence_regs = 16;
4313 dev_priv->num_fence_regs = 8;
4315 /* Initialize fence registers to zero */
4316 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4317 i915_gem_restore_fences(dev);
4319 i915_gem_detect_bit_6_swizzle(dev);
4320 init_waitqueue_head(&dev_priv->pending_flip_queue);
4322 dev_priv->mm.interruptible = true;
4325 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4326 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4327 register_shrinker(&dev_priv->mm.inactive_shrinker);
4329 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4330 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
4335 * Create a physically contiguous memory object for this object
4336 * e.g. for cursor + overlay regs
4338 static int i915_gem_init_phys_object(struct drm_device *dev,
4339 int id, int size, int align)
4341 drm_i915_private_t *dev_priv = dev->dev_private;
4342 struct drm_i915_gem_phys_object *phys_obj;
4345 if (dev_priv->mm.phys_objs[id - 1] || !size)
4348 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4354 phys_obj->handle = drm_pci_alloc(dev, size, align);
4355 if (!phys_obj->handle) {
4359 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4360 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4362 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4371 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4373 drm_i915_private_t *dev_priv = dev->dev_private;
4374 struct drm_i915_gem_phys_object *phys_obj;
4376 if (!dev_priv->mm.phys_objs[id - 1])
4379 phys_obj = dev_priv->mm.phys_objs[id - 1];
4380 if (phys_obj->cur_obj) {
4381 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4384 drm_pci_free(dev, phys_obj->handle);
4386 dev_priv->mm.phys_objs[id - 1] = NULL;
4389 void i915_gem_free_all_phys_object(struct drm_device *dev)
4393 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4394 i915_gem_free_phys_object(dev, i);
4397 void i915_gem_detach_phys_object(struct drm_device *dev,
4398 struct drm_i915_gem_object *obj)
4400 struct vm_object *mapping = obj->base.vm_obj;
4407 vaddr = obj->phys_obj->handle->vaddr;
4409 page_count = obj->base.size / PAGE_SIZE;
4410 VM_OBJECT_LOCK(obj->base.vm_obj);
4411 for (i = 0; i < page_count; i++) {
4412 struct vm_page *page = shmem_read_mapping_page(mapping, i);
4413 if (!IS_ERR(page)) {
4414 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4415 char *dst = kmap_atomic(page);
4416 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4419 drm_clflush_pages(&page, 1);
4422 set_page_dirty(page);
4423 mark_page_accessed(page);
4424 page_cache_release(page);
4426 VM_OBJECT_LOCK(obj->base.vm_obj);
4427 vm_page_reference(page);
4428 vm_page_dirty(page);
4429 vm_page_busy_wait(page, FALSE, "i915gem");
4430 vm_page_unwire(page, 0);
4431 vm_page_wakeup(page);
4434 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4435 intel_gtt_chipset_flush();
4437 obj->phys_obj->cur_obj = NULL;
4438 obj->phys_obj = NULL;
4442 i915_gem_attach_phys_object(struct drm_device *dev,
4443 struct drm_i915_gem_object *obj,
4447 struct vm_object *mapping = obj->base.vm_obj;
4448 drm_i915_private_t *dev_priv = dev->dev_private;
4453 if (id > I915_MAX_PHYS_OBJECT)
4456 if (obj->phys_obj) {
4457 if (obj->phys_obj->id == id)
4459 i915_gem_detach_phys_object(dev, obj);
4462 /* create a new object */
4463 if (!dev_priv->mm.phys_objs[id - 1]) {
4464 ret = i915_gem_init_phys_object(dev, id,
4465 obj->base.size, align);
4467 DRM_ERROR("failed to init phys object %d size: %zu\n",
4468 id, obj->base.size);
4473 /* bind to the object */
4474 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4475 obj->phys_obj->cur_obj = obj;
4477 page_count = obj->base.size / PAGE_SIZE;
4479 VM_OBJECT_LOCK(obj->base.vm_obj);
4480 for (i = 0; i < page_count; i++) {
4481 struct vm_page *page;
4484 page = shmem_read_mapping_page(mapping, i);
4485 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4487 return PTR_ERR(page);
4489 src = kmap_atomic(page);
4490 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4491 memcpy(dst, src, PAGE_SIZE);
4495 mark_page_accessed(page);
4496 page_cache_release(page);
4498 VM_OBJECT_LOCK(obj->base.vm_obj);
4499 vm_page_reference(page);
4500 vm_page_busy_wait(page, FALSE, "i915gem");
4501 vm_page_unwire(page, 0);
4502 vm_page_wakeup(page);
4504 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4510 i915_gem_phys_pwrite(struct drm_device *dev,
4511 struct drm_i915_gem_object *obj,
4512 struct drm_i915_gem_pwrite *args,
4513 struct drm_file *file_priv)
4515 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4516 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4518 if (copyin_nofault(user_data, vaddr, args->size) != 0) {
4519 unsigned long unwritten;
4521 /* The physical object once assigned is fixed for the lifetime
4522 * of the obj, so we can safely drop the lock and continue
4525 mutex_unlock(&dev->struct_mutex);
4526 unwritten = copy_from_user(vaddr, user_data, args->size);
4527 mutex_lock(&dev->struct_mutex);
4532 i915_gem_chipset_flush(dev);
4536 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4538 struct drm_i915_file_private *file_priv = file->driver_priv;
4540 /* Clean up our request list when the client is going away, so that
4541 * later retire_requests won't dereference our soon-to-be-gone
4544 spin_lock(&file_priv->mm.lock);
4545 while (!list_empty(&file_priv->mm.request_list)) {
4546 struct drm_i915_gem_request *request;
4548 request = list_first_entry(&file_priv->mm.request_list,
4549 struct drm_i915_gem_request,
4551 list_del(&request->client_list);
4552 request->file_priv = NULL;
4554 spin_unlock(&file_priv->mm.lock);
4558 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
4559 vm_ooffset_t foff, struct ucred *cred, u_short *color)
4562 *color = 0; /* XXXKIB */
4567 i915_gem_pager_dtor(void *handle)
4569 struct drm_gem_object *obj;
4570 struct drm_device *dev;
4575 mutex_lock(&dev->struct_mutex);
4576 drm_gem_free_mmap_offset(obj);
4577 i915_gem_release_mmap(to_intel_bo(obj));
4578 drm_gem_object_unreference(obj);
4579 mutex_unlock(&dev->struct_mutex);
4582 #define GEM_PARANOID_CHECK_GTT 0
4583 #if GEM_PARANOID_CHECK_GTT
4585 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
4588 struct drm_i915_private *dev_priv;
4590 unsigned long start, end;
4594 dev_priv = dev->dev_private;
4595 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
4596 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
4597 for (i = start; i < end; i++) {
4598 pa = intel_gtt_read_pte_paddr(i);
4599 for (j = 0; j < page_count; j++) {
4600 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
4601 panic("Page %p in GTT pte index %d pte %x",
4602 ma[i], i, intel_gtt_read_pte(i));
4606 obj->fence_dirty = false;
4611 i915_gpu_is_active(struct drm_device *dev)
4613 drm_i915_private_t *dev_priv = dev->dev_private;
4615 return !list_empty(&dev_priv->mm.active_list);
4619 i915_gem_lowmem(void *arg)
4621 struct drm_device *dev;
4622 struct drm_i915_private *dev_priv;
4623 struct drm_i915_gem_object *obj, *next;
4624 int cnt, cnt_fail, cnt_total;
4627 dev_priv = dev->dev_private;
4629 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT))
4633 /* first scan for clean buffers */
4634 i915_gem_retire_requests(dev);
4636 cnt_total = cnt_fail = cnt = 0;
4638 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4640 if (i915_gem_object_is_purgeable(obj)) {
4641 if (i915_gem_object_unbind(obj) != 0)
4647 /* second pass, evict/count anything still on the inactive list */
4648 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4650 if (i915_gem_object_unbind(obj) == 0)
4656 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4658 * We are desperate for pages, so as a last resort, wait
4659 * for the GPU to finish and discard whatever we can.
4660 * This has a dramatic impact to reduce the number of
4661 * OOM-killer events whilst running the GPU aggressively.
4663 if (i915_gpu_idle(dev) == 0)
4666 mutex_unlock(&dev->struct_mutex);