2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.36 2006/10/25 20:55:59 dillon Exp $
37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
38 * available from http://www.sis.com.tw.
40 * This driver also supports the NatSemi DP83815. Datasheets are
41 * available from http://www.national.com.
43 * Written by Bill Paul <wpaul@ee.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #include "opt_polling.h"
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/sysctl.h>
71 #include <sys/serialize.h>
72 #include <sys/thread2.h>
77 #include <net/ifq_var.h>
78 #include <net/if_arp.h>
79 #include <net/ethernet.h>
80 #include <net/if_dl.h>
81 #include <net/if_media.h>
82 #include <net/if_types.h>
83 #include <net/vlan/if_vlan_var.h>
87 #include <dev/netif/mii_layer/mii.h>
88 #include <dev/netif/mii_layer/miivar.h>
90 #include <bus/pci/pcidevs.h>
91 #include <bus/pci/pcireg.h>
92 #include <bus/pci/pcivar.h>
94 #define SIS_USEIOSPACE
96 #include "if_sisreg.h"
98 /* "controller miibus0" required. See GENERIC if you get errors here. */
99 #include "miibus_if.h"
102 * Various supported device vendors/types and their names.
104 static struct sis_type sis_devs[] = {
105 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" },
106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" },
107 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
111 static int sis_probe(device_t);
112 static int sis_attach(device_t);
113 static int sis_detach(device_t);
115 static int sis_newbuf(struct sis_softc *, struct sis_desc *,
117 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
118 static void sis_rxeof(struct sis_softc *);
119 static void sis_rxeoc(struct sis_softc *);
120 static void sis_txeof(struct sis_softc *);
121 static void sis_intr(void *);
122 static void sis_tick(void *);
123 static void sis_start(struct ifnet *);
124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
125 static void sis_init(void *);
126 static void sis_stop(struct sis_softc *);
127 static void sis_watchdog(struct ifnet *);
128 static void sis_shutdown(device_t);
129 static int sis_ifmedia_upd(struct ifnet *);
130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
132 static uint16_t sis_reverse(uint16_t);
133 static void sis_delay(struct sis_softc *);
134 static void sis_eeprom_idle(struct sis_softc *);
135 static void sis_eeprom_putbyte(struct sis_softc *, int);
136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
141 static device_t sis_find_bridge(device_t);
144 static void sis_mii_sync(struct sis_softc *);
145 static void sis_mii_send(struct sis_softc *, uint32_t, int);
146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_miibus_readreg(device_t, int, int);
149 static int sis_miibus_writereg(device_t, int, int, int);
150 static void sis_miibus_statchg(device_t);
152 static void sis_setmulti_sis(struct sis_softc *);
153 static void sis_setmulti_ns(struct sis_softc *);
154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
155 static void sis_reset(struct sis_softc *);
156 static int sis_list_rx_init(struct sis_softc *);
157 static int sis_list_tx_init(struct sis_softc *);
159 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
160 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
161 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
162 #ifdef DEVICE_POLLING
163 static poll_handler_t sis_poll;
165 #ifdef SIS_USEIOSPACE
166 #define SIS_RES SYS_RES_IOPORT
167 #define SIS_RID SIS_PCI_LOIO
169 #define SIS_RES SYS_RES_MEMORY
170 #define SIS_RID SIS_PCI_LOMEM
173 static device_method_t sis_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, sis_probe),
176 DEVMETHOD(device_attach, sis_attach),
177 DEVMETHOD(device_detach, sis_detach),
178 DEVMETHOD(device_shutdown, sis_shutdown),
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
186 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
187 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
192 static driver_t sis_driver = {
195 sizeof(struct sis_softc)
198 static devclass_t sis_devclass;
200 DECLARE_DUMMY_MODULE(if_sis);
201 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
202 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
204 #define SIS_SETBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
207 #define SIS_CLRBIT(sc, reg, x) \
208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
217 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
222 r->sis_next = segs->ds_addr;
226 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
231 r->sis_ptr = segs->ds_addr;
235 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
244 * Routine to reverse the bits in a word. Stolen almost
245 * verbatim from /usr/games/fortune.
248 sis_reverse(uint16_t n)
250 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
251 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
252 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
253 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
259 sis_delay(struct sis_softc *sc)
263 for (idx = (300 / 33) + 1; idx > 0; idx--)
264 CSR_READ_4(sc, SIS_CSR);
268 sis_eeprom_idle(struct sis_softc *sc)
272 SIO_SET(SIS_EECTL_CSEL);
274 SIO_SET(SIS_EECTL_CLK);
277 for (i = 0; i < 25; i++) {
278 SIO_CLR(SIS_EECTL_CLK);
280 SIO_SET(SIS_EECTL_CLK);
284 SIO_CLR(SIS_EECTL_CLK);
286 SIO_CLR(SIS_EECTL_CSEL);
288 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
292 * Send a read command and address to the EEPROM, check for ACK.
295 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
299 d = addr | SIS_EECMD_READ;
302 * Feed in each bit and stobe the clock.
304 for (i = 0x400; i; i >>= 1) {
306 SIO_SET(SIS_EECTL_DIN);
308 SIO_CLR(SIS_EECTL_DIN);
310 SIO_SET(SIS_EECTL_CLK);
312 SIO_CLR(SIS_EECTL_CLK);
318 * Read a word of data stored in the EEPROM at address 'addr.'
321 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
326 /* Force EEPROM to idle state. */
329 /* Enter EEPROM access mode. */
331 SIO_CLR(SIS_EECTL_CLK);
333 SIO_SET(SIS_EECTL_CSEL);
337 * Send address of word we want to read.
339 sis_eeprom_putbyte(sc, addr);
342 * Start reading bits from EEPROM.
344 for (i = 0x8000; i; i >>= 1) {
345 SIO_SET(SIS_EECTL_CLK);
347 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
350 SIO_CLR(SIS_EECTL_CLK);
354 /* Turn off EEPROM access mode. */
361 * Read a sequence of words from the EEPROM.
364 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
367 uint16_t word = 0, *ptr;
369 for (i = 0; i < cnt; i++) {
370 sis_eeprom_getword(sc, off + i, &word);
371 ptr = (uint16_t *)(dest + (i * 2));
381 sis_find_bridge(device_t dev)
383 devclass_t pci_devclass;
384 device_t *pci_devices;
386 device_t *pci_children;
387 int pci_childcount = 0;
388 device_t *busp, *childp;
389 device_t child = NULL;
392 if ((pci_devclass = devclass_find("pci")) == NULL)
395 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
397 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
399 device_get_children(*busp, &pci_children, &pci_childcount);
400 for (j = 0, childp = pci_children; j < pci_childcount;
402 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS &&
403 pci_get_device(*childp) == 0x0008) {
411 kfree(pci_devices, M_TEMP);
412 kfree(pci_children, M_TEMP);
417 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
423 bus_space_tag_t btag;
425 bridge = sis_find_bridge(dev);
428 reg = pci_read_config(bridge, 0x48, 1);
429 pci_write_config(bridge, 0x48, reg|0x40, 1);
432 btag = I386_BUS_SPACE_IO;
434 for (i = 0; i < cnt; i++) {
435 bus_space_write_1(btag, 0x0, 0x70, i + off);
436 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
439 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
443 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
445 uint32_t filtsave, csrsave;
447 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
448 csrsave = CSR_READ_4(sc, SIS_CSR);
450 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
451 CSR_WRITE_4(sc, SIS_CSR, 0);
453 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
455 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
456 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
457 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
458 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
460 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
462 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
463 CSR_WRITE_4(sc, SIS_CSR, csrsave);
468 * Sync the PHYs by setting data bit and strobing the clock 32 times.
471 sis_mii_sync(struct sis_softc *sc)
475 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
477 for (i = 0; i < 32; i++) {
478 SIO_SET(SIS_MII_CLK);
480 SIO_CLR(SIS_MII_CLK);
486 * Clock a series of bits through the MII.
489 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
493 SIO_CLR(SIS_MII_CLK);
495 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
497 SIO_SET(SIS_MII_DATA);
499 SIO_CLR(SIS_MII_DATA);
501 SIO_CLR(SIS_MII_CLK);
503 SIO_SET(SIS_MII_CLK);
508 * Read an PHY register through the MII.
511 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
516 * Set up frame for RX.
518 frame->mii_stdelim = SIS_MII_STARTDELIM;
519 frame->mii_opcode = SIS_MII_READOP;
520 frame->mii_turnaround = 0;
526 SIO_SET(SIS_MII_DIR);
531 * Send command/address info.
533 sis_mii_send(sc, frame->mii_stdelim, 2);
534 sis_mii_send(sc, frame->mii_opcode, 2);
535 sis_mii_send(sc, frame->mii_phyaddr, 5);
536 sis_mii_send(sc, frame->mii_regaddr, 5);
539 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
541 SIO_SET(SIS_MII_CLK);
545 SIO_CLR(SIS_MII_DIR);
548 SIO_CLR(SIS_MII_CLK);
550 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
551 SIO_SET(SIS_MII_CLK);
555 * Now try reading data bits. If the ack failed, we still
556 * need to clock through 16 cycles to keep the PHY(s) in sync.
559 for(i = 0; i < 16; i++) {
560 SIO_CLR(SIS_MII_CLK);
562 SIO_SET(SIS_MII_CLK);
568 for (i = 0x8000; i; i >>= 1) {
569 SIO_CLR(SIS_MII_CLK);
572 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
573 frame->mii_data |= i;
576 SIO_SET(SIS_MII_CLK);
582 SIO_CLR(SIS_MII_CLK);
584 SIO_SET(SIS_MII_CLK);
593 * Write to a PHY register through the MII.
596 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
599 * Set up frame for TX.
602 frame->mii_stdelim = SIS_MII_STARTDELIM;
603 frame->mii_opcode = SIS_MII_WRITEOP;
604 frame->mii_turnaround = SIS_MII_TURNAROUND;
607 * Turn on data output.
609 SIO_SET(SIS_MII_DIR);
613 sis_mii_send(sc, frame->mii_stdelim, 2);
614 sis_mii_send(sc, frame->mii_opcode, 2);
615 sis_mii_send(sc, frame->mii_phyaddr, 5);
616 sis_mii_send(sc, frame->mii_regaddr, 5);
617 sis_mii_send(sc, frame->mii_turnaround, 2);
618 sis_mii_send(sc, frame->mii_data, 16);
621 SIO_SET(SIS_MII_CLK);
623 SIO_CLR(SIS_MII_CLK);
629 SIO_CLR(SIS_MII_DIR);
635 sis_miibus_readreg(device_t dev, int phy, int reg)
637 struct sis_softc *sc;
638 struct sis_mii_frame frame;
640 sc = device_get_softc(dev);
642 if (sc->sis_type == SIS_TYPE_83815) {
646 * The NatSemi chip can take a while after
647 * a reset to come ready, during which the BMSR
648 * returns a value of 0. This is *never* supposed
649 * to happen: some of the BMSR bits are meant to
650 * be hardwired in the on position, and this can
651 * confuse the miibus code a bit during the probe
652 * and attach phase. So we make an effort to check
653 * for this condition and wait for it to clear.
655 if (!CSR_READ_4(sc, NS_BMSR))
657 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
660 * Chipsets < SIS_635 seem not to be able to read/write
661 * through mdio. Use the enhanced PHY access register
664 if (sc->sis_type == SIS_TYPE_900 &&
665 sc->sis_rev < SIS_REV_635) {
671 CSR_WRITE_4(sc, SIS_PHYCTL,
672 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
673 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
675 for (i = 0; i < SIS_TIMEOUT; i++) {
676 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
680 if (i == SIS_TIMEOUT) {
681 device_printf(dev, "PHY failed to come ready\n");
685 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
692 bzero((char *)&frame, sizeof(frame));
694 frame.mii_phyaddr = phy;
695 frame.mii_regaddr = reg;
696 sis_mii_readreg(sc, &frame);
698 return(frame.mii_data);
703 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
705 struct sis_softc *sc;
706 struct sis_mii_frame frame;
708 sc = device_get_softc(dev);
710 if (sc->sis_type == SIS_TYPE_83815) {
713 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
717 if (sc->sis_type == SIS_TYPE_900 &&
718 sc->sis_rev < SIS_REV_635) {
724 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
725 (reg << 6) | SIS_PHYOP_WRITE);
726 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
728 for (i = 0; i < SIS_TIMEOUT; i++) {
729 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
733 if (i == SIS_TIMEOUT)
734 device_printf(dev, "PHY failed to come ready\n");
736 bzero((char *)&frame, sizeof(frame));
738 frame.mii_phyaddr = phy;
739 frame.mii_regaddr = reg;
740 frame.mii_data = data;
741 sis_mii_writereg(sc, &frame);
747 sis_miibus_statchg(device_t dev)
749 struct sis_softc *sc;
751 sc = device_get_softc(dev);
756 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
762 /* Compute CRC for the address value. */
763 crc = 0xFFFFFFFF; /* initial value */
765 for (i = 0; i < 6; i++) {
767 for (j = 0; j < 8; j++) {
768 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
772 crc = (crc ^ 0x04c11db6) | carry;
777 * return the filter bit position
779 * The NatSemi chip has a 512-bit filter, which is
780 * different than the SiS, so we special-case it.
782 if (sc->sis_type == SIS_TYPE_83815)
784 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
791 sis_setmulti_ns(struct sis_softc *sc)
794 struct ifmultiaddr *ifma;
795 uint32_t h = 0, i, filtsave;
798 ifp = &sc->arpcom.ac_if;
800 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
801 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
802 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
807 * We have to explicitly enable the multicast hash table
808 * on the NatSemi chip if we want to use it, which we do.
810 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
811 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
813 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
815 /* first, zot all the existing hash bits */
816 for (i = 0; i < 32; i++) {
817 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
818 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
821 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
822 if (ifma->ifma_addr->sa_family != AF_LINK)
825 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
828 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
831 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
838 sis_setmulti_sis(struct sis_softc *sc)
841 struct ifmultiaddr *ifma;
842 uint32_t h, i, n, ctl;
845 ifp = &sc->arpcom.ac_if;
847 /* hash table size */
848 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
853 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
855 if (ifp->if_flags & IFF_BROADCAST)
856 ctl |= SIS_RXFILTCTL_BROAD;
858 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
859 ctl |= SIS_RXFILTCTL_ALLMULTI;
860 if (ifp->if_flags & IFF_PROMISC)
861 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
862 for (i = 0; i < n; i++)
865 for (i = 0; i < n; i++)
868 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
869 if (ifma->ifma_addr->sa_family != AF_LINK)
872 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
873 hashes[h >> 4] |= 1 << (h & 0xf);
877 ctl |= SIS_RXFILTCTL_ALLMULTI;
878 for (i = 0; i < n; i++)
883 for (i = 0; i < n; i++) {
884 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
885 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
888 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
892 sis_reset(struct sis_softc *sc)
894 struct ifnet *ifp = &sc->arpcom.ac_if;
897 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
899 for (i = 0; i < SIS_TIMEOUT; i++) {
900 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
904 if (i == SIS_TIMEOUT)
905 if_printf(ifp, "reset never completed\n");
907 /* Wait a little while for the chip to get its brains in order. */
911 * If this is a NetSemi chip, make sure to clear
914 if (sc->sis_type == SIS_TYPE_83815) {
915 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
916 CSR_WRITE_4(sc, NS_CLKRUN, 0);
921 * Probe for an SiS chip. Check the PCI vendor and device
922 * IDs against our list and return a device name if we find a match.
925 sis_probe(device_t dev)
931 while(t->sis_name != NULL) {
932 if ((pci_get_vendor(dev) == t->sis_vid) &&
933 (pci_get_device(dev) == t->sis_did)) {
934 device_set_desc(dev, t->sis_name);
944 * Attach the interface. Allocate softc structures, do ifmedia
945 * setup and ethernet/BPF attach.
948 sis_attach(device_t dev)
950 uint8_t eaddr[ETHER_ADDR_LEN];
952 struct sis_softc *sc;
954 int error, rid, waittime;
956 error = waittime = 0;
957 sc = device_get_softc(dev);
959 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900)
960 sc->sis_type = SIS_TYPE_900;
961 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016)
962 sc->sis_type = SIS_TYPE_7016;
963 if (pci_get_vendor(dev) == PCI_VENDOR_NS)
964 sc->sis_type = SIS_TYPE_83815;
966 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
969 * Handle power management nonsense.
972 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
973 if (command == 0x01) {
975 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
976 if (command & SIS_PSTATE_MASK) {
977 uint32_t iobase, membase, irq;
979 /* Save important PCI config data. */
980 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
981 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
982 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
984 /* Reset the power state. */
985 device_printf(dev, "chip is in D%d power mode "
986 "-- setting to D0\n", command & SIS_PSTATE_MASK);
987 command &= 0xFFFFFFFC;
988 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
990 /* Restore PCI config data. */
991 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
992 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
993 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
998 * Map control/status registers.
1000 command = pci_read_config(dev, PCIR_COMMAND, 4);
1001 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1002 pci_write_config(dev, PCIR_COMMAND, command, 4);
1003 command = pci_read_config(dev, PCIR_COMMAND, 4);
1005 #ifdef SIS_USEIOSPACE
1006 if (!(command & PCIM_CMD_PORTEN)) {
1007 device_printf(dev, "failed to enable I/O ports!\n");
1012 if (!(command & PCIM_CMD_MEMEN)) {
1013 device_printf(dev, "failed to enable memory mapping!\n");
1020 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
1022 if (sc->sis_res == NULL) {
1023 device_printf(dev, "couldn't map ports/memory\n");
1028 sc->sis_btag = rman_get_bustag(sc->sis_res);
1029 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1031 /* Allocate interrupt */
1033 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1034 RF_SHAREABLE | RF_ACTIVE);
1036 if (sc->sis_irq == NULL) {
1037 device_printf(dev, "couldn't map interrupt\n");
1042 /* Reset the adapter. */
1045 if (sc->sis_type == SIS_TYPE_900 &&
1046 (sc->sis_rev == SIS_REV_635 ||
1047 sc->sis_rev == SIS_REV_900B)) {
1048 SIO_SET(SIS_CFG_RND_CNT);
1049 SIO_SET(SIS_CFG_PERR_DETECT);
1053 * Get station address from the EEPROM.
1055 switch (pci_get_vendor(dev)) {
1058 * Reading the MAC address out of the EEPROM on
1059 * the NatSemi chip takes a bit more work than
1060 * you'd expect. The address spans 4 16-bit words,
1061 * with the first word containing only a single bit.
1062 * You have to shift everything over one bit to
1063 * get it aligned properly. Also, the bits are
1064 * stored backwards (the LSB is really the MSB,
1065 * and so on) so you have to reverse them in order
1066 * to get the MAC address into the form we want.
1067 * Why? Who the hell knows.
1072 sis_read_eeprom(sc, (caddr_t)&tmp,
1073 NS_EE_NODEADDR, 4, 0);
1075 /* Shift everything over one bit. */
1076 tmp[3] = tmp[3] >> 1;
1077 tmp[3] |= tmp[2] << 15;
1078 tmp[2] = tmp[2] >> 1;
1079 tmp[2] |= tmp[1] << 15;
1080 tmp[1] = tmp[1] >> 1;
1081 tmp[1] |= tmp[0] << 15;
1083 /* Now reverse all the bits. */
1084 tmp[3] = sis_reverse(tmp[3]);
1085 tmp[2] = sis_reverse(tmp[2]);
1086 tmp[1] = sis_reverse(tmp[1]);
1088 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1091 case PCI_VENDOR_SIS:
1095 * If this is a SiS 630E chipset with an embedded
1096 * SiS 900 controller, we have to read the MAC address
1097 * from the APC CMOS RAM. Our method for doing this
1098 * is very ugly since we have to reach out and grab
1099 * ahold of hardware for which we cannot properly
1100 * allocate resources. This code is only compiled on
1101 * the i386 architecture since the SiS 630E chipset
1102 * is for x86 motherboards only. Note that there are
1103 * a lot of magic numbers in this hack. These are
1104 * taken from SiS's Linux driver. I'd like to replace
1105 * them with proper symbolic definitions, but that
1106 * requires some datasheets that I don't have access
1109 if (sc->sis_rev == SIS_REV_630S ||
1110 sc->sis_rev == SIS_REV_630E ||
1111 sc->sis_rev == SIS_REV_630EA1)
1112 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1114 else if (sc->sis_rev == SIS_REV_635 ||
1115 sc->sis_rev == SIS_REV_630ET)
1116 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1117 else if (sc->sis_rev == SIS_REV_96x) {
1119 * Allow to read EEPROM from LAN. It is shared
1120 * between a 1394 controller and the NIC and each
1121 * time we access it, we need to set SIS_EECMD_REQ.
1123 SIO_SET(SIS_EECMD_REQ);
1124 for (waittime = 0; waittime < SIS_TIMEOUT;
1126 /* Force EEPROM to idle state. */
1127 sis_eeprom_idle(sc);
1128 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1129 sis_read_eeprom(sc, (caddr_t)&eaddr,
1130 SIS_EE_NODEADDR, 3, 0);
1136 * Set SIS_EECTL_CLK to high, so a other master
1137 * can operate on the i2c bus.
1139 SIO_SET(SIS_EECTL_CLK);
1140 /* Refuse EEPROM access by LAN */
1141 SIO_SET(SIS_EECMD_DONE);
1144 sis_read_eeprom(sc, (caddr_t)&eaddr,
1145 SIS_EE_NODEADDR, 3, 0);
1149 callout_init(&sc->sis_timer);
1152 * Allocate the parent bus DMA tag appropriate for PCI.
1154 #define SIS_NSEG_NEW 32
1155 error = bus_dma_tag_create(NULL, /* parent */
1156 1, 0, /* alignment, boundary */
1157 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1158 BUS_SPACE_MAXADDR, /* highaddr */
1159 NULL, NULL, /* filter, filterarg */
1160 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1161 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1162 BUS_DMA_ALLOCNOW, /* flags */
1163 &sc->sis_parent_tag);
1168 * Now allocate a tag for the DMA descriptor lists and a chunk
1169 * of DMA-able memory based on the tag. Also obtain the physical
1170 * addresses of the RX and TX ring, which we'll need later.
1171 * All of our lists are allocated as a contiguous block of memory.
1173 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1174 1, 0, /* alignment, boundary */
1175 BUS_SPACE_MAXADDR, /* lowaddr */
1176 BUS_SPACE_MAXADDR, /* highaddr */
1177 NULL, NULL, /* filter, filterarg */
1178 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1179 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1181 &sc->sis_ldata.sis_rx_tag);
1185 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1186 (void **)&sc->sis_ldata.sis_rx_list,
1187 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1188 &sc->sis_ldata.sis_rx_dmamap);
1191 device_printf(dev, "no memory for rx list buffers!\n");
1192 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1193 sc->sis_ldata.sis_rx_tag = NULL;
1197 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1198 sc->sis_ldata.sis_rx_dmamap,
1199 sc->sis_ldata.sis_rx_list,
1200 sizeof(struct sis_desc), sis_dma_map_ring,
1201 &sc->sis_cdata.sis_rx_paddr, 0);
1204 device_printf(dev, "cannot get address of the rx ring!\n");
1205 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1206 sc->sis_ldata.sis_rx_list,
1207 sc->sis_ldata.sis_rx_dmamap);
1208 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1209 sc->sis_ldata.sis_rx_tag = NULL;
1213 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1214 1, 0, /* alignment, boundary */
1215 BUS_SPACE_MAXADDR, /* lowaddr */
1216 BUS_SPACE_MAXADDR, /* highaddr */
1217 NULL, NULL, /* filter, filterarg */
1218 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1219 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1221 &sc->sis_ldata.sis_tx_tag);
1225 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1226 (void **)&sc->sis_ldata.sis_tx_list,
1227 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1228 &sc->sis_ldata.sis_tx_dmamap);
1231 device_printf(dev, "no memory for tx list buffers!\n");
1232 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1233 sc->sis_ldata.sis_tx_tag = NULL;
1237 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1238 sc->sis_ldata.sis_tx_dmamap,
1239 sc->sis_ldata.sis_tx_list,
1240 sizeof(struct sis_desc), sis_dma_map_ring,
1241 &sc->sis_cdata.sis_tx_paddr, 0);
1244 device_printf(dev, "cannot get address of the tx ring!\n");
1245 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1246 sc->sis_ldata.sis_tx_list,
1247 sc->sis_ldata.sis_tx_dmamap);
1248 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1249 sc->sis_ldata.sis_tx_tag = NULL;
1253 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1254 1, 0, /* alignment, boundary */
1255 BUS_SPACE_MAXADDR, /* lowaddr */
1256 BUS_SPACE_MAXADDR, /* highaddr */
1257 NULL, NULL, /* filter, filterarg */
1258 MCLBYTES, 1, /* maxsize, nsegments */
1259 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1265 ifp = &sc->arpcom.ac_if;
1267 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1268 ifp->if_mtu = ETHERMTU;
1269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1270 ifp->if_ioctl = sis_ioctl;
1271 ifp->if_start = sis_start;
1272 ifp->if_watchdog = sis_watchdog;
1273 ifp->if_init = sis_init;
1274 ifp->if_baudrate = 10000000;
1275 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1276 ifq_set_ready(&ifp->if_snd);
1277 #ifdef DEVICE_POLLING
1278 ifp->if_poll = sis_poll;
1280 ifp->if_capenable = ifp->if_capabilities;
1285 if (mii_phy_probe(dev, &sc->sis_miibus,
1286 sis_ifmedia_upd, sis_ifmedia_sts)) {
1287 device_printf(dev, "MII without any PHY!\n");
1293 * Call MI attach routine.
1295 ether_ifattach(ifp, eaddr, NULL);
1298 * Tell the upper layer(s) we support long frames.
1300 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1302 error = bus_setup_intr(dev, sc->sis_irq, INTR_NETSAFE,
1305 ifp->if_serializer);
1308 device_printf(dev, "couldn't set up irq\n");
1309 ether_ifdetach(ifp);
1321 * Shutdown hardware and free up resources. It is called in both the error case
1322 * and the normal detach case so it needs to be careful about only freeing
1323 * resources that have actually been allocated.
1326 sis_detach(device_t dev)
1328 struct sis_softc *sc = device_get_softc(dev);
1329 struct ifnet *ifp = &sc->arpcom.ac_if;
1332 if (device_is_attached(dev)) {
1333 lwkt_serialize_enter(ifp->if_serializer);
1336 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1337 lwkt_serialize_exit(ifp->if_serializer);
1339 ether_ifdetach(ifp);
1342 device_delete_child(dev, sc->sis_miibus);
1343 bus_generic_detach(dev);
1346 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1348 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1350 if (sc->sis_ldata.sis_rx_tag) {
1351 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1352 sc->sis_ldata.sis_rx_dmamap);
1353 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1354 sc->sis_ldata.sis_rx_list,
1355 sc->sis_ldata.sis_rx_dmamap);
1356 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1359 if (sc->sis_ldata.sis_tx_tag) {
1360 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1361 sc->sis_ldata.sis_tx_dmamap);
1362 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1363 sc->sis_ldata.sis_tx_list,
1364 sc->sis_ldata.sis_tx_dmamap);
1365 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1368 bus_dma_tag_destroy(sc->sis_tag);
1369 if (sc->sis_parent_tag)
1370 bus_dma_tag_destroy(sc->sis_parent_tag);
1376 * Initialize the transmit descriptors.
1379 sis_list_tx_init(struct sis_softc *sc)
1381 struct sis_list_data *ld;
1382 struct sis_ring_data *cd;
1385 cd = &sc->sis_cdata;
1386 ld = &sc->sis_ldata;
1388 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1389 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1390 ld->sis_tx_list[i].sis_nextdesc =
1391 &ld->sis_tx_list[nexti];
1392 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1393 sc->sis_ldata.sis_tx_dmamap,
1394 &ld->sis_tx_list[nexti],
1395 sizeof(struct sis_desc), sis_dma_map_desc_next,
1396 &ld->sis_tx_list[i], 0);
1397 ld->sis_tx_list[i].sis_mbuf = NULL;
1398 ld->sis_tx_list[i].sis_ptr = 0;
1399 ld->sis_tx_list[i].sis_ctl = 0;
1402 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1404 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1405 BUS_DMASYNC_PREWRITE);
1411 * Initialize the RX descriptors and allocate mbufs for them. Note that
1412 * we arrange the descriptors in a closed ring, so that the last descriptor
1413 * points back to the first.
1416 sis_list_rx_init(struct sis_softc *sc)
1418 struct sis_list_data *ld;
1419 struct sis_ring_data *cd;
1422 ld = &sc->sis_ldata;
1423 cd = &sc->sis_cdata;
1425 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1426 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1428 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1429 ld->sis_rx_list[i].sis_nextdesc =
1430 &ld->sis_rx_list[nexti];
1431 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1432 sc->sis_ldata.sis_rx_dmamap,
1433 &ld->sis_rx_list[nexti],
1434 sizeof(struct sis_desc), sis_dma_map_desc_next,
1435 &ld->sis_rx_list[i], 0);
1438 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1439 BUS_DMASYNC_PREWRITE);
1441 cd->sis_rx_prod = 0;
1447 * Initialize an RX descriptor and attach an MBUF cluster.
1450 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1453 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1457 m->m_data = m->m_ext.ext_buf;
1461 c->sis_ctl = SIS_RXLEN;
1463 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1464 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1465 sis_dma_map_desc_ptr, c, 0);
1466 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1472 * A frame has been uploaded: pass the resulting mbuf chain up to
1473 * the higher level protocols.
1476 sis_rxeof(struct sis_softc *sc)
1480 struct sis_desc *cur_rx;
1481 int i, total_len = 0;
1484 ifp = &sc->arpcom.ac_if;
1485 i = sc->sis_cdata.sis_rx_prod;
1487 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1489 #ifdef DEVICE_POLLING
1490 if (ifp->if_flags & IFF_POLLING) {
1491 if (sc->rxcycles <= 0)
1495 #endif /* DEVICE_POLLING */
1496 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1497 rxstat = cur_rx->sis_rxstat;
1498 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1499 BUS_DMASYNC_POSTWRITE);
1500 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1501 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1502 m = cur_rx->sis_mbuf;
1503 cur_rx->sis_mbuf = NULL;
1504 total_len = SIS_RXBYTES(cur_rx);
1505 SIS_INC(i, SIS_RX_LIST_CNT);
1508 * If an error occurs, update stats, clear the
1509 * status word and leave the mbuf cluster in place:
1510 * it should simply get re-used next time this descriptor
1511 * comes up in the ring.
1513 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1515 if (rxstat & SIS_RXSTAT_COLL)
1516 ifp->if_collisions++;
1517 sis_newbuf(sc, cur_rx, m);
1521 /* No errors; receive the packet. */
1524 * On the x86 we do not have alignment problems, so try to
1525 * allocate a new buffer for the receive ring, and pass up
1526 * the one where the packet is already, saving the expensive
1527 * copy done in m_devget().
1528 * If we are on an architecture with alignment problems, or
1529 * if the allocation fails, then use m_devget and leave the
1530 * existing buffer in the receive ring.
1532 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1533 m->m_pkthdr.len = m->m_len = total_len;
1538 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1539 total_len + ETHER_ALIGN, 0, ifp, NULL);
1540 sis_newbuf(sc, cur_rx, m);
1545 m_adj(m0, ETHER_ALIGN);
1550 ifp->if_input(ifp, m);
1553 sc->sis_cdata.sis_rx_prod = i;
1557 sis_rxeoc(struct sis_softc *sc)
1564 * A frame was downloaded to the chip. It's safe for us to clean up
1569 sis_txeof(struct sis_softc *sc)
1571 struct sis_desc *cur_tx;
1575 ifp = &sc->arpcom.ac_if;
1578 * Go through our tx list and free mbufs for those
1579 * frames that have been transmitted.
1581 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1582 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1583 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1585 if (SIS_OWNDESC(cur_tx))
1588 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1591 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1593 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1594 ifp->if_collisions++;
1595 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1596 ifp->if_collisions++;
1599 ifp->if_collisions +=
1600 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1603 if (cur_tx->sis_mbuf != NULL) {
1604 m_freem(cur_tx->sis_mbuf);
1605 cur_tx->sis_mbuf = NULL;
1606 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1607 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1611 if (idx != sc->sis_cdata.sis_tx_cons) {
1612 /* we freed up some buffers */
1613 sc->sis_cdata.sis_tx_cons = idx;
1614 ifp->if_flags &= ~IFF_OACTIVE;
1617 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1623 struct sis_softc *sc = xsc;
1624 struct mii_data *mii;
1625 struct ifnet *ifp = &sc->arpcom.ac_if;
1627 lwkt_serialize_enter(ifp->if_serializer);
1629 mii = device_get_softc(sc->sis_miibus);
1632 if (!sc->sis_link) {
1634 if (mii->mii_media_status & IFM_ACTIVE &&
1635 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1637 if (!ifq_is_empty(&ifp->if_snd))
1641 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1642 lwkt_serialize_exit(ifp->if_serializer);
1645 #ifdef DEVICE_POLLING
1648 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1650 struct sis_softc *sc = ifp->if_softc;
1654 /* disable interrupts */
1655 CSR_WRITE_4(sc, SIS_IER, 0);
1657 case POLL_DEREGISTER:
1658 /* enable interrupts */
1659 CSR_WRITE_4(sc, SIS_IER, 1);
1663 * On the sis, reading the status register also clears it.
1664 * So before returning to intr mode we must make sure that all
1665 * possible pending sources of interrupts have been served.
1666 * In practice this means run to completion the *eof routines,
1667 * and then call the interrupt routine
1669 sc->rxcycles = count;
1672 if (!ifq_is_empty(&ifp->if_snd))
1675 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1678 /* Reading the ISR register clears all interrupts. */
1679 status = CSR_READ_4(sc, SIS_ISR);
1681 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1684 if (status & (SIS_ISR_RX_IDLE))
1685 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1687 if (status & SIS_ISR_SYSERR) {
1695 #endif /* DEVICE_POLLING */
1700 struct sis_softc *sc;
1705 ifp = &sc->arpcom.ac_if;
1707 /* Supress unwanted interrupts */
1708 if (!(ifp->if_flags & IFF_UP)) {
1713 /* Disable interrupts. */
1714 CSR_WRITE_4(sc, SIS_IER, 0);
1717 /* Reading the ISR register clears all interrupts. */
1718 status = CSR_READ_4(sc, SIS_ISR);
1720 if ((status & SIS_INTRS) == 0)
1724 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1729 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1732 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1735 if (status & (SIS_ISR_RX_IDLE))
1736 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1738 if (status & SIS_ISR_SYSERR) {
1744 /* Re-enable interrupts. */
1745 CSR_WRITE_4(sc, SIS_IER, 1);
1747 if (!ifq_is_empty(&ifp->if_snd))
1752 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1753 * pointers to the fragment pointers.
1756 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1758 struct sis_desc *f = NULL;
1760 int frag, cur, cnt = 0;
1763 * If there's no way we can send any packets, return now.
1765 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1769 * Start packing the mbufs in this chain into
1770 * the fragment pointers. Stop when we run out
1771 * of fragments or hit the end of the mbuf chain.
1774 cur = frag = *txidx;
1776 for (m = m_head; m != NULL; m = m->m_next) {
1777 if (m->m_len != 0) {
1778 if ((SIS_TX_LIST_CNT -
1779 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1781 f = &sc->sis_ldata.sis_tx_list[frag];
1782 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1783 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1784 bus_dmamap_load(sc->sis_tag, f->sis_map,
1785 mtod(m, void *), m->m_len,
1786 sis_dma_map_desc_ptr, f, 0);
1787 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1788 BUS_DMASYNC_PREREAD);
1790 f->sis_ctl |= SIS_CMDSTS_OWN;
1792 SIS_INC(frag, SIS_TX_LIST_CNT);
1800 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1801 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1802 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1803 sc->sis_cdata.sis_tx_cnt += cnt;
1810 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1811 * to the mbuf data regions directly in the transmit lists. We also save a
1812 * copy of the pointers since the transmit list fragment pointers are
1813 * physical addresses.
1817 sis_start(struct ifnet *ifp)
1819 struct sis_softc *sc;
1820 struct mbuf *m_head = NULL;
1829 idx = sc->sis_cdata.sis_tx_prod;
1831 if (ifp->if_flags & IFF_OACTIVE)
1835 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1836 m_head = ifq_poll(&ifp->if_snd);
1840 if (sis_encap(sc, m_head, &idx)) {
1841 ifp->if_flags |= IFF_OACTIVE;
1844 ifq_dequeue(&ifp->if_snd, m_head);
1848 * If there's a BPF listener, bounce a copy of this frame
1851 BPF_MTAP(ifp, m_head);
1858 sc->sis_cdata.sis_tx_prod = idx;
1859 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1862 * Set a timeout in case the chip goes out to lunch.
1870 struct sis_softc *sc = xsc;
1871 struct ifnet *ifp = &sc->arpcom.ac_if;
1872 struct mii_data *mii;
1875 * Cancel pending I/O and free all RX/TX buffers.
1879 mii = device_get_softc(sc->sis_miibus);
1881 /* Set MAC address */
1882 if (sc->sis_type == SIS_TYPE_83815) {
1883 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1884 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1885 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1886 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1887 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1888 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1890 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1891 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1894 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1895 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1896 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1897 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1898 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1899 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1900 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1901 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1904 /* Init circular RX list. */
1905 if (sis_list_rx_init(sc) == ENOBUFS) {
1906 if_printf(ifp, "initialization failed: "
1907 "no memory for rx buffers\n");
1913 * Init tx descriptors.
1915 sis_list_tx_init(sc);
1918 * For the NatSemi chip, we have to explicitly enable the
1919 * reception of ARP frames, as well as turn on the 'perfect
1920 * match' filter where we store the station address, otherwise
1921 * we won't receive unicasts meant for this host.
1923 if (sc->sis_type == SIS_TYPE_83815) {
1924 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1925 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1928 /* If we want promiscuous mode, set the allframes bit. */
1929 if (ifp->if_flags & IFF_PROMISC)
1930 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1932 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1935 * Set the capture broadcast bit to capture broadcast frames.
1937 if (ifp->if_flags & IFF_BROADCAST)
1938 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1940 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1943 * Load the multicast filter.
1945 if (sc->sis_type == SIS_TYPE_83815)
1946 sis_setmulti_ns(sc);
1948 sis_setmulti_sis(sc);
1950 /* Turn the receive filter on */
1951 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1954 * Load the address of the RX and TX lists.
1956 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1957 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
1959 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1960 * the PCI bus. When this bit is set, the Max DMA Burst Size
1961 * for TX/RX DMA should be no larger than 16 double words.
1963 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1964 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1966 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1968 /* Accept Long Packets for VLAN support */
1969 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1971 /* Set TX configuration */
1972 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1973 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1975 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1977 /* Set full/half duplex mode. */
1978 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1979 SIS_SETBIT(sc, SIS_TX_CFG,
1980 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1981 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1983 SIS_CLRBIT(sc, SIS_TX_CFG,
1984 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1985 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1989 * Enable interrupts.
1991 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1992 #ifdef DEVICE_POLLING
1994 * ... only enable interrupts if we are not polling, make sure
1995 * they are off otherwise.
1997 if (ifp->if_flags & IFF_POLLING)
1998 CSR_WRITE_4(sc, SIS_IER, 0);
2000 #endif /* DEVICE_POLLING */
2001 CSR_WRITE_4(sc, SIS_IER, 1);
2003 /* Enable receiver and transmitter. */
2004 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2005 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2012 * Page 75 of the DP83815 manual recommends the
2013 * following register settings "for optimum
2014 * performance." Note however that at least three
2015 * of the registers are listed as "reserved" in
2016 * the register map, so who knows what they do.
2018 if (sc->sis_type == SIS_TYPE_83815) {
2019 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2020 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2021 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2022 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2023 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2026 ifp->if_flags |= IFF_RUNNING;
2027 ifp->if_flags &= ~IFF_OACTIVE;
2029 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
2033 * Set media options.
2036 sis_ifmedia_upd(struct ifnet *ifp)
2038 struct sis_softc *sc;
2039 struct mii_data *mii;
2043 mii = device_get_softc(sc->sis_miibus);
2045 if (mii->mii_instance) {
2046 struct mii_softc *miisc;
2047 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2048 mii_phy_reset(miisc);
2056 * Report current media status.
2059 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2061 struct sis_softc *sc;
2062 struct mii_data *mii;
2066 mii = device_get_softc(sc->sis_miibus);
2068 ifmr->ifm_active = mii->mii_media_active;
2069 ifmr->ifm_status = mii->mii_media_status;
2073 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2075 struct sis_softc *sc = ifp->if_softc;
2076 struct ifreq *ifr = (struct ifreq *) data;
2077 struct mii_data *mii;
2082 if (ifp->if_flags & IFF_UP) {
2085 if (ifp->if_flags & IFF_RUNNING)
2092 if (sc->sis_type == SIS_TYPE_83815)
2093 sis_setmulti_ns(sc);
2095 sis_setmulti_sis(sc);
2100 mii = device_get_softc(sc->sis_miibus);
2101 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2104 error = ether_ioctl(ifp, command, data);
2111 sis_watchdog(struct ifnet *ifp)
2113 struct sis_softc *sc;
2118 if_printf(ifp, "watchdog timeout\n");
2124 if (!ifq_is_empty(&ifp->if_snd))
2129 * Stop the adapter and free any mbufs allocated to the
2133 sis_stop(struct sis_softc *sc)
2138 ifp = &sc->arpcom.ac_if;
2141 callout_stop(&sc->sis_timer);
2143 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2144 CSR_WRITE_4(sc, SIS_IER, 0);
2145 CSR_WRITE_4(sc, SIS_IMR, 0);
2146 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2148 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2149 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2154 * Free data in the RX lists.
2156 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2157 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2158 bus_dmamap_unload(sc->sis_tag,
2159 sc->sis_ldata.sis_rx_list[i].sis_map);
2160 bus_dmamap_destroy(sc->sis_tag,
2161 sc->sis_ldata.sis_rx_list[i].sis_map);
2162 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2163 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2166 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
2169 * Free the TX list buffers.
2171 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2172 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2173 bus_dmamap_unload(sc->sis_tag,
2174 sc->sis_ldata.sis_tx_list[i].sis_map);
2175 bus_dmamap_destroy(sc->sis_tag,
2176 sc->sis_ldata.sis_tx_list[i].sis_map);
2177 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2178 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2182 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
2186 * Stop all chip I/O so that the kernel's probe routines don't
2187 * get confused by errant DMAs when rebooting.
2190 sis_shutdown(device_t dev)
2192 struct sis_softc *sc;
2195 sc = device_get_softc(dev);
2196 ifp = &sc->arpcom.ac_if;
2197 lwkt_serialize_enter(ifp->if_serializer);
2200 lwkt_serialize_exit(ifp->if_serializer);