sys/dev/drm/radeon/radeon_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  *
  32  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $
  33  */
  34 #include <ttm/ttm_bo_api.h>
  35 #include <ttm/ttm_bo_driver.h>
  36 #include <ttm/ttm_placement.h>
  37 #include <ttm/ttm_module.h>
  38 #include <ttm/ttm_page_alloc.h>
  39 #include <drm/drmP.h>
  40 #include <drm/radeon_drm.h>
  41 #include <linux/seq_file.h>
  42 #include <linux/slab.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include "radeon_reg.h"
  46 #include "radeon.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  51 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  52
  53 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  54 {
  55         struct radeon_mman *mman;
  56         struct radeon_device *rdev;
  57
  58         mman = container_of(bdev, struct radeon_mman, bdev);
  59         rdev = container_of(mman, struct radeon_device, mman);
  60         return rdev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int radeon_ttm_global_init(struct radeon_device *rdev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         int r;
  81
  82         rdev->mman.mem_global_referenced = false;
  83         global_ref = &rdev->mman.mem_global_ref;
  84         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85         global_ref->size = sizeof(struct ttm_mem_global);
  86         global_ref->init = &radeon_ttm_mem_global_init;
  87         global_ref->release = &radeon_ttm_mem_global_release;
  88         r = drm_global_item_ref(global_ref);
  89         if (r != 0) {
  90                 DRM_ERROR("Failed setting up TTM memory accounting "
  91                           "subsystem.\n");
  92                 return r;
  93         }
  94
  95         rdev->mman.bo_global_ref.mem_glob =
  96                 rdev->mman.mem_global_ref.object;
  97         global_ref = &rdev->mman.bo_global_ref.ref;
  98         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99         global_ref->size = sizeof(struct ttm_bo_global);
 100         global_ref->init = &ttm_bo_global_init;
 101         global_ref->release = &ttm_bo_global_release;
 102         r = drm_global_item_ref(global_ref);
 103         if (r != 0) {
 104                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 106                 return r;
 107         }
 108
 109         rdev->mman.mem_global_referenced = true;
 110         return 0;
 111 }
 112
 113 static void radeon_ttm_global_fini(struct radeon_device *rdev)
 114 {
 115         if (rdev->mman.mem_global_referenced) {
 116                 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
 117                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 118                 rdev->mman.mem_global_referenced = false;
 119         }
 120 }
 121
 122 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 123 {
 124         return 0;
 125 }
 126
 127 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 128                                 struct ttm_mem_type_manager *man)
 129 {
 130         struct radeon_device *rdev;
 131
 132         rdev = radeon_get_rdev(bdev);
 133
 134         switch (type) {
 135         case TTM_PL_SYSTEM:
 136                 /* System memory */
 137                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 138                 man->available_caching = TTM_PL_MASK_CACHING;
 139                 man->default_caching = TTM_PL_FLAG_CACHED;
 140                 break;
 141         case TTM_PL_TT:
 142                 man->func = &ttm_bo_manager_func;
 143                 man->gpu_offset = rdev->mc.gtt_start;
 144                 man->available_caching = TTM_PL_MASK_CACHING;
 145                 man->default_caching = TTM_PL_FLAG_CACHED;
 146                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 147 #if IS_ENABLED(CONFIG_AGP)
 148                 if (rdev->flags & RADEON_IS_AGP) {
 149                         if (!rdev->ddev->agp) {
 150                                 DRM_ERROR("AGP is not enabled for memory type %u\n",
 151                                           (unsigned)type);
 152                                 return -EINVAL;
 153                         }
 154                         if (!rdev->ddev->agp->cant_use_aperture)
 155                                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 156                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 157                                                  TTM_PL_FLAG_WC;
 158                         man->default_caching = TTM_PL_FLAG_WC;
 159                 }
 160 #endif
 161                 break;
 162         case TTM_PL_VRAM:
 163                 /* "On-card" video ram */
 164                 man->func = &ttm_bo_manager_func;
 165                 man->gpu_offset = rdev->mc.vram_start;
 166                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 167                              TTM_MEMTYPE_FLAG_MAPPABLE;
 168                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 169                 man->default_caching = TTM_PL_FLAG_WC;
 170                 break;
 171         default:
 172                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 173                 return -EINVAL;
 174         }
 175         return 0;
 176 }
 177
 178 static void radeon_evict_flags(struct ttm_buffer_object *bo,
 179                                 struct ttm_placement *placement)
 180 {
 181         static struct ttm_place placements = {
 182                 .fpfn = 0,
 183                 .lpfn = 0,
 184                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 185         };
 186
 187         struct radeon_bo *rbo;
 188
 189         if (!radeon_ttm_bo_is_radeon_bo(bo)) {
 190                 placement->placement = &placements;
 191                 placement->busy_placement = &placements;
 192                 placement->num_placement = 1;
 193                 placement->num_busy_placement = 1;
 194                 return;
 195         }
 196         rbo = container_of(bo, struct radeon_bo, tbo);
 197         switch (bo->mem.mem_type) {
 198         case TTM_PL_VRAM:
 199                 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
 200                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 201                 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
 202                          bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
 203                         unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 204                         int i;
 205
 206                         /* Try evicting to the CPU inaccessible part of VRAM
 207                          * first, but only set GTT as busy placement, so this
 208                          * BO will be evicted to GTT rather than causing other
 209                          * BOs to be evicted from VRAM
 210                          */
 211                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
 212                                                          RADEON_GEM_DOMAIN_GTT);
 213                         rbo->placement.num_busy_placement = 0;
 214                         for (i = 0; i < rbo->placement.num_placement; i++) {
 215                                 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
 216                                         if (rbo->placements[i].fpfn < fpfn)
 217                                                 rbo->placements[i].fpfn = fpfn;
 218                                 } else {
 219                                         rbo->placement.busy_placement =
 220                                                 &rbo->placements[i];
 221                                         rbo->placement.num_busy_placement = 1;
 222                                 }
 223                         }
 224                 } else
 225                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 226                 break;
 227         case TTM_PL_TT:
 228         default:
 229                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 230         }
 231         *placement = rbo->placement;
 232 }
 233
 234 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 235 {
 236 #if 0
 237         struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 238 #endif
 239
 240         if (radeon_ttm_tt_has_userptr(bo->ttm))
 241                 return -EPERM;
 242
 243         return 0;
 244 }
 245
 246 static void radeon_move_null(struct ttm_buffer_object *bo,
 247                              struct ttm_mem_reg *new_mem)
 248 {
 249         struct ttm_mem_reg *old_mem = &bo->mem;
 250
 251         BUG_ON(old_mem->mm_node != NULL);
 252         *old_mem = *new_mem;
 253         new_mem->mm_node = NULL;
 254 }
 255
 256 static int radeon_move_blit(struct ttm_buffer_object *bo,
 257                         bool evict, bool no_wait_gpu,
 258                         struct ttm_mem_reg *new_mem,
 259                         struct ttm_mem_reg *old_mem)
 260 {
 261         struct radeon_device *rdev;
 262         uint64_t old_start, new_start;
 263         struct radeon_fence *fence;
 264         unsigned num_pages;
 265         int r, ridx;
 266
 267         rdev = radeon_get_rdev(bo->bdev);
 268         ridx = radeon_copy_ring_index(rdev);
 269         old_start = (u64)old_mem->start << PAGE_SHIFT;
 270         new_start = (u64)new_mem->start << PAGE_SHIFT;
 271
 272         switch (old_mem->mem_type) {
 273         case TTM_PL_VRAM:
 274                 old_start += rdev->mc.vram_start;
 275                 break;
 276         case TTM_PL_TT:
 277                 old_start += rdev->mc.gtt_start;
 278                 break;
 279         default:
 280                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 281                 return -EINVAL;
 282         }
 283         switch (new_mem->mem_type) {
 284         case TTM_PL_VRAM:
 285                 new_start += rdev->mc.vram_start;
 286                 break;
 287         case TTM_PL_TT:
 288                 new_start += rdev->mc.gtt_start;
 289                 break;
 290         default:
 291                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 292                 return -EINVAL;
 293         }
 294         if (!rdev->ring[ridx].ready) {
 295                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 296                 return -EINVAL;
 297         }
 298
 299         BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
 300
 301         num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
 302         fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
 303         if (IS_ERR(fence))
 304                 return PTR_ERR(fence);
 305
 306         r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem);
 307         radeon_fence_unref(&fence);
 308         return r;
 309 }
 310
 311 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
 312                                 bool evict, bool interruptible,
 313                                 bool no_wait_gpu,
 314                                 struct ttm_mem_reg *new_mem)
 315 {
 316         struct radeon_device *rdev;
 317         struct ttm_mem_reg *old_mem = &bo->mem;
 318         struct ttm_mem_reg tmp_mem;
 319         struct ttm_place placements;
 320         struct ttm_placement placement;
 321         int r;
 322
 323         rdev = radeon_get_rdev(bo->bdev);
 324         tmp_mem = *new_mem;
 325         tmp_mem.mm_node = NULL;
 326         placement.num_placement = 1;
 327         placement.placement = &placements;
 328         placement.num_busy_placement = 1;
 329         placement.busy_placement = &placements;
 330         placements.fpfn = 0;
 331         placements.lpfn = 0;
 332         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 333         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 334                              interruptible, no_wait_gpu);
 335         if (unlikely(r)) {
 336                 return r;
 337         }
 338
 339         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 340         if (unlikely(r)) {
 341                 goto out_cleanup;
 342         }
 343
 344         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 345         if (unlikely(r)) {
 346                 goto out_cleanup;
 347         }
 348         r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 349         if (unlikely(r)) {
 350                 goto out_cleanup;
 351         }
 352         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 353 out_cleanup:
 354         ttm_bo_mem_put(bo, &tmp_mem);
 355         return r;
 356 }
 357
 358 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
 359                                 bool evict, bool interruptible,
 360                                 bool no_wait_gpu,
 361                                 struct ttm_mem_reg *new_mem)
 362 {
 363         struct radeon_device *rdev;
 364         struct ttm_mem_reg *old_mem = &bo->mem;
 365         struct ttm_mem_reg tmp_mem;
 366         struct ttm_placement placement;
 367         struct ttm_place placements;
 368         int r;
 369
 370         rdev = radeon_get_rdev(bo->bdev);
 371         tmp_mem = *new_mem;
 372         tmp_mem.mm_node = NULL;
 373         placement.num_placement = 1;
 374         placement.placement = &placements;
 375         placement.num_busy_placement = 1;
 376         placement.busy_placement = &placements;
 377         placements.fpfn = 0;
 378         placements.lpfn = 0;
 379         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 380         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 381                              interruptible, no_wait_gpu);
 382         if (unlikely(r)) {
 383                 return r;
 384         }
 385         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 386         if (unlikely(r)) {
 387                 goto out_cleanup;
 388         }
 389         r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 390         if (unlikely(r)) {
 391                 goto out_cleanup;
 392         }
 393 out_cleanup:
 394         ttm_bo_mem_put(bo, &tmp_mem);
 395         return r;
 396 }
 397
 398 static int radeon_bo_move(struct ttm_buffer_object *bo,
 399                         bool evict, bool interruptible,
 400                         bool no_wait_gpu,
 401                         struct ttm_mem_reg *new_mem)
 402 {
 403         struct radeon_device *rdev;
 404         struct radeon_bo *rbo;
 405         struct ttm_mem_reg *old_mem = &bo->mem;
 406         int r;
 407
 408         r = ttm_bo_wait(bo, interruptible, no_wait_gpu);
 409         if (r)
 410                 return r;
 411
 412         /* Can't move a pinned BO */
 413         rbo = container_of(bo, struct radeon_bo, tbo);
 414         if (WARN_ON_ONCE(rbo->pin_count > 0))
 415                 return -EINVAL;
 416
 417         rdev = radeon_get_rdev(bo->bdev);
 418         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 419                 radeon_move_null(bo, new_mem);
 420                 return 0;
 421         }
 422         if ((old_mem->mem_type == TTM_PL_TT &&
 423              new_mem->mem_type == TTM_PL_SYSTEM) ||
 424             (old_mem->mem_type == TTM_PL_SYSTEM &&
 425              new_mem->mem_type == TTM_PL_TT)) {
 426                 /* bind is enough */
 427                 radeon_move_null(bo, new_mem);
 428                 return 0;
 429         }
 430         if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
 431             rdev->asic->copy.copy == NULL) {
 432                 /* use memcpy */
 433                 goto memcpy;
 434         }
 435
 436         if (old_mem->mem_type == TTM_PL_VRAM &&
 437             new_mem->mem_type == TTM_PL_SYSTEM) {
 438                 r = radeon_move_vram_ram(bo, evict, interruptible,
 439                                         no_wait_gpu, new_mem);
 440         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 441                    new_mem->mem_type == TTM_PL_VRAM) {
 442                 r = radeon_move_ram_vram(bo, evict, interruptible,
 443                                             no_wait_gpu, new_mem);
 444         } else {
 445                 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 446         }
 447
 448         if (r) {
 449 memcpy:
 450                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 451                 if (r) {
 452                         return r;
 453                 }
 454         }
 455
 456         /* update statistics */
 457         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
 458         return 0;
 459 }
 460
 461 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 462 {
 463         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 464         struct radeon_device *rdev = radeon_get_rdev(bdev);
 465
 466         mem->bus.addr = NULL;
 467         mem->bus.offset = 0;
 468         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 469         mem->bus.base = 0;
 470         mem->bus.is_iomem = false;
 471         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 472                 return -EINVAL;
 473         switch (mem->mem_type) {
 474         case TTM_PL_SYSTEM:
 475                 /* system memory */
 476                 return 0;
 477         case TTM_PL_TT:
 478 #if IS_ENABLED(CONFIG_AGP)
 479                 if (rdev->flags & RADEON_IS_AGP) {
 480                         /* RADEON_IS_AGP is set only if AGP is active */
 481                         mem->bus.offset = mem->start << PAGE_SHIFT;
 482                         mem->bus.base = rdev->mc.agp_base;
 483                         mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
 484                 }
 485 #endif
 486                 break;
 487         case TTM_PL_VRAM:
 488                 mem->bus.offset = mem->start << PAGE_SHIFT;
 489                 /* check if it's visible */
 490                 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
 491                         return -EINVAL;
 492                 mem->bus.base = rdev->mc.aper_base;
 493                 mem->bus.is_iomem = true;
 494 #ifdef __alpha__
 495                 /*
 496                  * Alpha: use bus.addr to hold the ioremap() return,
 497                  * so we can modify bus.base below.
 498                  */
 499                 if (mem->placement & TTM_PL_FLAG_WC)
 500                         mem->bus.addr =
 501                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 502                                            mem->bus.size);
 503                 else
 504                         mem->bus.addr =
 505                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 506                                                 mem->bus.size);
 507
 508                 /*
 509                  * Alpha: Use just the bus offset plus
 510                  * the hose/domain memory base for bus.base.
 511                  * It then can be used to build PTEs for VRAM
 512                  * access, as done in ttm_bo_vm_fault().
 513                  */
 514                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 515                         rdev->ddev->hose->dense_mem_base;
 516 #endif
 517                 break;
 518         default:
 519                 return -EINVAL;
 520         }
 521         return 0;
 522 }
 523
 524 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 525 {
 526 }
 527
 528 /*
 529  * TTM backend functions.
 530  */
 531 struct radeon_ttm_tt {
 532         struct ttm_dma_tt               ttm;
 533         struct radeon_device            *rdev;
 534         u64                             offset;
 535
 536         uint64_t                        userptr;
 537         struct mm_struct                *usermm;
 538         uint32_t                        userflags;
 539 };
 540
 541 #if 0
 542 /* prepare the sg table with the user pages */
 543 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 544 {
 545         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 546         struct radeon_ttm_tt *gtt = (void *)ttm;
 547         unsigned pinned = 0, nents;
 548         int r;
 549
 550         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 551         enum dma_data_direction direction = write ?
 552                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 553
 554         if (current->mm != gtt->usermm)
 555                 return -EPERM;
 556
 557         if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
 558                 /* check that we only pin down anonymous memory
 559                    to prevent problems with writeback */
 560                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 561                 struct vm_area_struct *vma;
 562                 vma = find_vma(gtt->usermm, gtt->userptr);
 563                 if (!vma || vma->vm_file || vma->vm_end < end)
 564                         return -EPERM;
 565         }
 566
 567         do {
 568                 unsigned num_pages = ttm->num_pages - pinned;
 569                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 570                 struct page **pages = ttm->pages + pinned;
 571
 572                 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
 573                                    pages, NULL);
 574                 if (r < 0)
 575                         goto release_pages;
 576
 577                 pinned += r;
 578
 579         } while (pinned < ttm->num_pages);
 580
 581         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 582                                       ttm->num_pages << PAGE_SHIFT,
 583                                       GFP_KERNEL);
 584         if (r)
 585                 goto release_sg;
 586
 587         r = -ENOMEM;
 588         nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 589         if (nents != ttm->sg->nents)
 590                 goto release_sg;
 591
 592         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 593                                          gtt->ttm.dma_address, ttm->num_pages);
 594
 595         return 0;
 596
 597 release_sg:
 598         kfree(ttm->sg);
 599
 600 release_pages:
 601         release_pages(ttm->pages, pinned, 0);
 602         return r;
 603 }
 604
 605 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 606 {
 607         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 608         struct radeon_ttm_tt *gtt = (void *)ttm;
 609         struct sg_page_iter sg_iter;
 610
 611         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 612         enum dma_data_direction direction = write ?
 613                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 614
 615         /* double check that we don't free the table twice */
 616         if (!ttm->sg->sgl)
 617                 return;
 618
 619         /* free the sg table and pages again */
 620         dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 621
 622         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 623                 struct page *page = sg_page_iter_page(&sg_iter);
 624                 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
 625                         set_page_dirty(page);
 626
 627                 mark_page_accessed(page);
 628                 put_page(page);
 629         }
 630
 631         sg_free_table(ttm->sg);
 632 }
 633 #endif
 634
 635 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
 636                                    struct ttm_mem_reg *bo_mem)
 637 {
 638         struct radeon_ttm_tt *gtt = (void*)ttm;
 639         uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
 640                 RADEON_GART_PAGE_WRITE;
 641         int r;
 642
 643 #if 0
 644         if (gtt->userptr) {
 645                 radeon_ttm_tt_pin_userptr(ttm);
 646                 flags &= ~RADEON_GART_PAGE_WRITE;
 647         }
 648 #endif
 649
 650         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 651         if (!ttm->num_pages) {
 652                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 653                      ttm->num_pages, bo_mem, ttm);
 654         }
 655         if (ttm->caching_state == tt_cached)
 656                 flags |= RADEON_GART_PAGE_SNOOP;
 657         r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
 658                              ttm->pages, gtt->ttm.dma_address, flags);
 659         if (r) {
 660                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 661                           ttm->num_pages, (unsigned)gtt->offset);
 662                 return r;
 663         }
 664         return 0;
 665 }
 666
 667 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
 668 {
 669         struct radeon_ttm_tt *gtt = (void *)ttm;
 670
 671         radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
 672 #if 0
 673         if (gtt->userptr)
 674                 radeon_ttm_tt_unpin_userptr(ttm);
 675 #endif
 676
 677         return 0;
 678 }
 679
 680 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
 681 {
 682         struct radeon_ttm_tt *gtt = (void *)ttm;
 683
 684         ttm_dma_tt_fini(&gtt->ttm);
 685         kfree(gtt);
 686 }
 687
 688 static struct ttm_backend_func radeon_backend_func = {
 689         .bind = &radeon_ttm_backend_bind,
 690         .unbind = &radeon_ttm_backend_unbind,
 691         .destroy = &radeon_ttm_backend_destroy,
 692 };
 693
 694 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
 695                                     unsigned long size, uint32_t page_flags,
 696                                     struct page *dummy_read_page)
 697 {
 698         struct radeon_device *rdev;
 699         struct radeon_ttm_tt *gtt;
 700
 701         rdev = radeon_get_rdev(bdev);
 702 #if IS_ENABLED(CONFIG_AGP)
 703         if (rdev->flags & RADEON_IS_AGP) {
 704                 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev,
 705                                          size, page_flags, dummy_read_page);
 706         }
 707 #endif
 708
 709         gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
 710         if (gtt == NULL) {
 711                 return NULL;
 712         }
 713         gtt->ttm.ttm.func = &radeon_backend_func;
 714         gtt->rdev = rdev;
 715         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 716                 kfree(gtt);
 717                 return NULL;
 718         }
 719         return &gtt->ttm.ttm;
 720 }
 721
 722 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
 723 {
 724         if (!ttm || ttm->func != &radeon_backend_func)
 725                 return NULL;
 726         return (struct radeon_ttm_tt *)ttm;
 727 }
 728
 729 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
 730 {
 731         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 732         struct radeon_device *rdev;
 733         unsigned i;
 734         int r;
 735 #ifdef DUMBBELL_WIP
 736         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 737 #endif /* DUMBBELL_WIP */
 738
 739         if (ttm->state != tt_unpopulated)
 740                 return 0;
 741
 742 #if 0
 743         if (gtt && gtt->userptr) {
 744                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 745                 if (!ttm->sg)
 746                         return -ENOMEM;
 747
 748                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 749                 ttm->state = tt_unbound;
 750                 return 0;
 751         }
 752 #endif
 753
 754 #ifdef DUMBBELL_WIP
 755         /*
 756          * Maybe unneeded on FreeBSD.
 757          *   -- dumbbell@
 758          */
 759         if (slave && ttm->sg) {
 760                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 761                                                  gtt->ttm.dma_address, ttm->num_pages);
 762                 ttm->state = tt_unbound;
 763                 return 0;
 764         }
 765 #endif /* DUMBBELL_WIP */
 766
 767         rdev = radeon_get_rdev(ttm->bdev);
 768 #if IS_ENABLED(CONFIG_AGP)
 769         if (rdev->flags & RADEON_IS_AGP) {
 770                 return ttm_agp_tt_populate(ttm);
 771         }
 772 #endif
 773
 774 #ifdef CONFIG_SWIOTLB
 775         if (swiotlb_nr_tbl()) {
 776                 return ttm_dma_populate(&gtt->ttm, rdev->dev);
 777         }
 778 #endif
 779
 780         r = ttm_pool_populate(ttm);
 781         if (r) {
 782                 return r;
 783         }
 784
 785         for (i = 0; i < ttm->num_pages; i++) {
 786                 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
 787                                                        0, PAGE_SIZE,
 788                                                        PCI_DMA_BIDIRECTIONAL);
 789 #ifdef DUMBBELL_WIP
 790                 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
 791                         while (i--) {
 792                                 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 793                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 794                                 gtt->ttm.dma_address[i] = 0;
 795                         }
 796                         ttm_pool_unpopulate(ttm);
 797                         return -EFAULT;
 798                 }
 799 #endif /* DUMBBELL_WIP */
 800         }
 801         return 0;
 802 }
 803
 804 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
 805 {
 806         struct radeon_device *rdev;
 807         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 808         unsigned i;
 809         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 810
 811 #if 0
 812         if (gtt && gtt->userptr) {
 813                 kfree(ttm->sg);
 814                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 815                 return;
 816         }
 817 #endif
 818
 819         if (slave)
 820                 return;
 821
 822         rdev = radeon_get_rdev(ttm->bdev);
 823 #if IS_ENABLED(CONFIG_AGP)
 824         if (rdev->flags & RADEON_IS_AGP) {
 825                 ttm_agp_tt_unpopulate(ttm);
 826                 return;
 827         }
 828 #endif
 829
 830 #ifdef CONFIG_SWIOTLB
 831         if (swiotlb_nr_tbl()) {
 832                 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
 833                 return;
 834         }
 835 #endif
 836
 837         for (i = 0; i < ttm->num_pages; i++) {
 838                 if (gtt->ttm.dma_address[i]) {
 839                         gtt->ttm.dma_address[i] = 0;
 840 #ifdef DUMBBELL_WIP
 841                         pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 842                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 843 #endif /* DUMBBELL_WIP */
 844                 }
 845         }
 846
 847         ttm_pool_unpopulate(ttm);
 848 }
 849
 850 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
 851 {
 852 #if 0
 853         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 854
 855         if (gtt == NULL)
 856 #endif
 857                 return false;
 858
 859 #if 0
 860         return !!gtt->userptr;
 861 #endif
 862 }
 863
 864 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
 865 {
 866         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 867
 868         if (gtt == NULL)
 869                 return false;
 870
 871         return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 872 }
 873
 874 static struct ttm_bo_driver radeon_bo_driver = {
 875         .ttm_tt_create = &radeon_ttm_tt_create,
 876         .ttm_tt_populate = &radeon_ttm_tt_populate,
 877         .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
 878         .invalidate_caches = &radeon_invalidate_caches,
 879         .init_mem_type = &radeon_init_mem_type,
 880         .evict_flags = &radeon_evict_flags,
 881         .move = &radeon_bo_move,
 882         .verify_access = &radeon_verify_access,
 883         .move_notify = &radeon_bo_move_notify,
 884         .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
 885         .io_mem_reserve = &radeon_ttm_io_mem_reserve,
 886         .io_mem_free = &radeon_ttm_io_mem_free,
 887         .lru_tail = &ttm_bo_default_lru_tail,
 888         .swap_lru_tail = &ttm_bo_default_swap_lru_tail,
 889 };
 890
 891 int radeon_ttm_init(struct radeon_device *rdev)
 892 {
 893         int r;
 894
 895         r = radeon_ttm_global_init(rdev);
 896         if (r) {
 897                 return r;
 898         }
 899         /* No others user of address space so set it to 0 */
 900         r = ttm_bo_device_init(&rdev->mman.bdev,
 901                                rdev->mman.bo_global_ref.ref.object,
 902                                &radeon_bo_driver,
 903 #ifdef __DragonFly__
 904                                NULL,
 905 #else
 906                                rdev->ddev->anon_inode->i_mapping,
 907 #endif
 908                                DRM_FILE_PAGE_OFFSET,
 909                                rdev->need_dma32);
 910         if (r) {
 911                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 912                 return r;
 913         }
 914         rdev->mman.initialized = true;
 915         rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev;
 916         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
 917                                 rdev->mc.real_vram_size >> PAGE_SHIFT);
 918         if (r) {
 919                 DRM_ERROR("Failed initializing VRAM heap.\n");
 920                 return r;
 921         }
 922         /* Change the size here instead of the init above so only lpfn is affected */
 923         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 924
 925         r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
 926                              RADEON_GEM_DOMAIN_VRAM, 0, NULL,
 927                              NULL, &rdev->stollen_vga_memory);
 928         if (r) {
 929                 return r;
 930         }
 931         r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 932         if (r)
 933                 return r;
 934         r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
 935         radeon_bo_unreserve(rdev->stollen_vga_memory);
 936         if (r) {
 937                 radeon_bo_unref(&rdev->stollen_vga_memory);
 938                 return r;
 939         }
 940         DRM_INFO("radeon: %uM of VRAM memory ready\n",
 941                  (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
 942         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
 943                                 rdev->mc.gtt_size >> PAGE_SHIFT);
 944         if (r) {
 945                 DRM_ERROR("Failed initializing GTT heap.\n");
 946                 return r;
 947         }
 948         DRM_INFO("radeon: %uM of GTT memory ready.\n",
 949                  (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
 950
 951         r = radeon_ttm_debugfs_init(rdev);
 952         if (r) {
 953                 DRM_ERROR("Failed to init debugfs\n");
 954                 return r;
 955         }
 956         return 0;
 957 }
 958
 959 void radeon_ttm_fini(struct radeon_device *rdev)
 960 {
 961         int r;
 962
 963         if (!rdev->mman.initialized)
 964                 return;
 965         radeon_ttm_debugfs_fini(rdev);
 966         if (rdev->stollen_vga_memory) {
 967                 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 968                 if (r == 0) {
 969                         radeon_bo_unpin(rdev->stollen_vga_memory);
 970                         radeon_bo_unreserve(rdev->stollen_vga_memory);
 971                 }
 972                 radeon_bo_unref(&rdev->stollen_vga_memory);
 973         }
 974         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 975         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
 976         ttm_bo_device_release(&rdev->mman.bdev);
 977         radeon_gart_fini(rdev);
 978         radeon_ttm_global_fini(rdev);
 979         rdev->mman.initialized = false;
 980         DRM_INFO("radeon: ttm finalized\n");
 981 }
 982
 983 /* this should only be called at bootup or when userspace
 984  * isn't running */
 985 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
 986 {
 987         struct ttm_mem_type_manager *man;
 988
 989         if (!rdev->mman.initialized)
 990                 return;
 991
 992         man = &rdev->mman.bdev.man[TTM_PL_VRAM];
 993         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
 994         man->size = size >> PAGE_SHIFT;
 995 }
 996
 997 #ifdef DUMBBELL_WIP
 998 static struct vm_operations_struct radeon_ttm_vm_ops;
 999 static const struct vm_operations_struct *ttm_vm_ops = NULL;
1000
1001 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1002 {
1003         struct ttm_buffer_object *bo;
1004         struct radeon_device *rdev;
1005         int r;
1006
1007         bo = (struct ttm_buffer_object *)vma->vm_private_data;
1008         if (bo == NULL) {
1009                 return VM_FAULT_NOPAGE;
1010         }
1011         rdev = radeon_get_rdev(bo->bdev);
1012         down_read(&rdev->pm.mclk_lock);
1013         r = ttm_vm_ops->fault(vma, vmf);
1014         up_read(&rdev->pm.mclk_lock);
1015         return r;
1016 }
1017
1018 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
1019 {
1020         struct drm_file *file_priv;
1021         struct radeon_device *rdev;
1022         int r;
1023
1024         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
1025                 return -EINVAL;
1026         }
1027
1028         file_priv = filp->private_data;
1029         rdev = file_priv->minor->dev->dev_private;
1030         if (rdev == NULL) {
1031                 return -EINVAL;
1032         }
1033         r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1034         if (unlikely(r != 0)) {
1035                 return r;
1036         }
1037         if (unlikely(ttm_vm_ops == NULL)) {
1038                 ttm_vm_ops = vma->vm_ops;
1039                 radeon_ttm_vm_ops = *ttm_vm_ops;
1040                 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1041         }
1042         vma->vm_ops = &radeon_ttm_vm_ops;
1043         return 0;
1044 }
1045 #endif /* DUMBBELL_WIP */
1046
1047 #if defined(CONFIG_DEBUG_FS)
1048
1049 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1050 {
1051         struct drm_info_node *node = (struct drm_info_node *)m->private;
1052         unsigned ttm_pl = *(int *)node->info_ent->data;
1053         struct drm_device *dev = node->minor->dev;
1054         struct radeon_device *rdev = dev->dev_private;
1055         struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
1056         int ret;
1057         struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1058
1059         lockmgr(&glob->lru_lock, LK_EXCLUSIVE);
1060         ret = drm_mm_dump_table(m, mm);
1061         lockmgr(&glob->lru_lock, LK_RELEASE);
1062         return ret;
1063 }
1064
1065 static int ttm_pl_vram = TTM_PL_VRAM;
1066 static int ttm_pl_tt = TTM_PL_TT;
1067
1068 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1069         {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1070         {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1071         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1072 #ifdef CONFIG_SWIOTLB
1073         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1074 #endif
1075 };
1076
1077 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1078 {
1079         struct radeon_device *rdev = inode->i_private;
1080         i_size_write(inode, rdev->mc.mc_vram_size);
1081         filep->private_data = inode->i_private;
1082         return 0;
1083 }
1084
1085 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1086                                     size_t size, loff_t *pos)
1087 {
1088         struct radeon_device *rdev = f->private_data;
1089         ssize_t result = 0;
1090         int r;
1091
1092         if (size & 0x3 || *pos & 0x3)
1093                 return -EINVAL;
1094
1095         while (size) {
1096                 unsigned long flags;
1097                 uint32_t value;
1098
1099                 if (*pos >= rdev->mc.mc_vram_size)
1100                         return result;
1101
1102                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1103                 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1104                 if (rdev->family >= CHIP_CEDAR)
1105                         WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1106                 value = RREG32(RADEON_MM_DATA);
1107                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1108
1109                 r = put_user(value, (uint32_t *)buf);
1110                 if (r)
1111                         return r;
1112
1113                 result += 4;
1114                 buf += 4;
1115                 *pos += 4;
1116                 size -= 4;
1117         }
1118
1119         return result;
1120 }
1121
1122 static const struct file_operations radeon_ttm_vram_fops = {
1123         .owner = THIS_MODULE,
1124         .open = radeon_ttm_vram_open,
1125         .read = radeon_ttm_vram_read,
1126         .llseek = default_llseek
1127 };
1128
1129 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1130 {
1131         struct radeon_device *rdev = inode->i_private;
1132         i_size_write(inode, rdev->mc.gtt_size);
1133         filep->private_data = inode->i_private;
1134         return 0;
1135 }
1136
1137 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1138                                    size_t size, loff_t *pos)
1139 {
1140         struct radeon_device *rdev = f->private_data;
1141         ssize_t result = 0;
1142         int r;
1143
1144         while (size) {
1145                 loff_t p = *pos / PAGE_SIZE;
1146                 unsigned off = *pos & ~LINUX_PAGE_MASK;
1147                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1148                 struct page *page;
1149                 void *ptr;
1150
1151                 if (p >= rdev->gart.num_cpu_pages)
1152                         return result;
1153
1154                 page = rdev->gart.pages[p];
1155                 if (page) {
1156                         ptr = kmap(page);
1157                         ptr += off;
1158
1159                         r = copy_to_user(buf, ptr, cur_size);
1160                         kunmap(rdev->gart.pages[p]);
1161                 } else
1162                         r = clear_user(buf, cur_size);
1163
1164                 if (r)
1165                         return -EFAULT;
1166
1167                 result += cur_size;
1168                 buf += cur_size;
1169                 *pos += cur_size;
1170                 size -= cur_size;
1171         }
1172
1173         return result;
1174 }
1175
1176 static const struct file_operations radeon_ttm_gtt_fops = {
1177         .owner = THIS_MODULE,
1178         .open = radeon_ttm_gtt_open,
1179         .read = radeon_ttm_gtt_read,
1180         .llseek = default_llseek
1181 };
1182
1183 #endif
1184
1185 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1186 {
1187 #if defined(CONFIG_DEBUG_FS)
1188         unsigned count;
1189
1190         struct drm_minor *minor = rdev->ddev->primary;
1191         struct dentry *ent, *root = minor->debugfs_root;
1192
1193         ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1194                                   rdev, &radeon_ttm_vram_fops);
1195         if (IS_ERR(ent))
1196                 return PTR_ERR(ent);
1197         rdev->mman.vram = ent;
1198
1199         ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1200                                   rdev, &radeon_ttm_gtt_fops);
1201         if (IS_ERR(ent))
1202                 return PTR_ERR(ent);
1203         rdev->mman.gtt = ent;
1204
1205         count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1206
1207 #ifdef CONFIG_SWIOTLB
1208         if (!swiotlb_nr_tbl())
1209                 --count;
1210 #endif
1211
1212         return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1213 #else
1214
1215         return 0;
1216 #endif
1217 }
1218
1219 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1220 {
1221 #if defined(CONFIG_DEBUG_FS)
1222
1223         debugfs_remove(rdev->mman.vram);
1224         rdev->mman.vram = NULL;
1225
1226         debugfs_remove(rdev->mman.gtt);
1227         rdev->mman.gtt = NULL;
1228 #endif
1229 }