sys/dev/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/rs690.c 254885 2013-08-25 19:37:15Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "atom.h"
  35 #include "rs690d.h"
  36
  37 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  38 {
  39         unsigned i;
  40         uint32_t tmp;
  41
  42         for (i = 0; i < rdev->usec_timeout; i++) {
  43                 /* read MC_STATUS */
  44                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  45                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  46                         return 0;
  47                 DRM_UDELAY(1);
  48         }
  49         return -1;
  50 }
  51
  52 static void rs690_gpu_init(struct radeon_device *rdev)
  53 {
  54         /* FIXME: is this correct ? */
  55         r420_pipes_init(rdev);
  56         if (rs690_mc_wait_for_idle(rdev)) {
  57                 DRM_ERROR("Failed to wait MC idle while "
  58                        "programming pipes. Bad things might happen.\n");
  59         }
  60 }
  61
  62 union igp_info {
  63         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  64         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
  65 };
  66
  67 void rs690_pm_info(struct radeon_device *rdev)
  68 {
  69         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  70         union igp_info *info;
  71         uint16_t data_offset;
  72         uint8_t frev, crev;
  73         fixed20_12 tmp;
  74
  75         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  76                                    &frev, &crev, &data_offset)) {
  77                 info = (union igp_info *)((uintptr_t)rdev->mode_info.atom_context->bios + data_offset);
  78
  79                 /* Get various system informations from bios */
  80                 switch (crev) {
  81                 case 1:
  82                         tmp.full = dfixed_const(100);
  83                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
  84                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  85                         if (le16_to_cpu(info->info.usK8MemoryClock))
  86                                 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
  87                         else if (rdev->clock.default_mclk) {
  88                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
  89                                 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
  90                         } else
  91                                 rdev->pm.igp_system_mclk.full = dfixed_const(400);
  92                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
  93                         rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
  94                         break;
  95                 case 2:
  96                         tmp.full = dfixed_const(100);
  97                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
  98                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  99                         if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
 100                                 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
 101                         else if (rdev->clock.default_mclk)
 102                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
 103                         else
 104                                 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
 105                         rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
 106                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
 107                         rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
 108                         rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
 109                         break;
 110                 default:
 111                         /* We assume the slower possible clock ie worst case */
 112                         rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 113                         rdev->pm.igp_system_mclk.full = dfixed_const(200);
 114                         rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 115                         rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 116                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 117                         break;
 118                 }
 119         } else {
 120                 /* We assume the slower possible clock ie worst case */
 121                 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 122                 rdev->pm.igp_system_mclk.full = dfixed_const(200);
 123                 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 124                 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 125                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 126         }
 127         /* Compute various bandwidth */
 128         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 129         tmp.full = dfixed_const(4);
 130         rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
 131         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 132          *              = ht_clk * ht_width / 5
 133          */
 134         tmp.full = dfixed_const(5);
 135         rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
 136                                                 rdev->pm.igp_ht_link_width);
 137         rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
 138         if (tmp.full < rdev->pm.max_bandwidth.full) {
 139                 /* HT link is a limiting factor */
 140                 rdev->pm.max_bandwidth.full = tmp.full;
 141         }
 142         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 143          *                    = (sideport_clk * 14) / 10
 144          */
 145         tmp.full = dfixed_const(14);
 146         rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 147         tmp.full = dfixed_const(10);
 148         rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
 149 }
 150
 151 static void rs690_mc_init(struct radeon_device *rdev)
 152 {
 153         u64 base;
 154         uint32_t h_addr, l_addr;
 155         unsigned long long k8_addr;
 156
 157         rs400_gart_adjust_size(rdev);
 158         rdev->mc.vram_is_ddr = true;
 159         rdev->mc.vram_width = 128;
 160         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 161         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 162         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 163         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 164         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 165         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
 166         base = G_000100_MC_FB_START(base) << 16;
 167         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 168
 169         /* Use K8 direct mapping for fast fb access. */
 170         rdev->fastfb_working = false;
 171         h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
 172         l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
 173         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
 174 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
 175         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
 176 #endif
 177         {
 178                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
 179                  * memory is present.
 180                  */
 181                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
 182                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
 183                                         (unsigned long long)rdev->mc.aper_base, k8_addr);
 184                         rdev->mc.aper_base = (resource_size_t)k8_addr;
 185                         rdev->fastfb_working = true;
 186                 }
 187         }
 188
 189         rs690_pm_info(rdev);
 190         radeon_vram_location(rdev, &rdev->mc, base);
 191         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 192         radeon_gtt_location(rdev, &rdev->mc);
 193         radeon_update_bandwidth_info(rdev);
 194 }
 195
 196 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 197                               struct drm_display_mode *mode1,
 198                               struct drm_display_mode *mode2)
 199 {
 200         u32 tmp;
 201
 202         /*
 203          * Line Buffer Setup
 204          * There is a single line buffer shared by both display controllers.
 205          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 206          * the display controllers.  The paritioning can either be done
 207          * manually or via one of four preset allocations specified in bits 1:0:
 208          *  0 - line buffer is divided in half and shared between crtc
 209          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 210          *  2 - D1 gets the whole buffer
 211          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 212          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 213          * allocation mode. In manual allocation mode, D1 always starts at 0,
 214          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 215          */
 216         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 217         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 218         /* auto */
 219         if (mode1 && mode2) {
 220                 if (mode1->hdisplay > mode2->hdisplay) {
 221                         if (mode1->hdisplay > 2560)
 222                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 223                         else
 224                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 225                 } else if (mode2->hdisplay > mode1->hdisplay) {
 226                         if (mode2->hdisplay > 2560)
 227                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 228                         else
 229                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 230                 } else
 231                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 232         } else if (mode1) {
 233                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 234         } else if (mode2) {
 235                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 236         }
 237         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 238 }
 239
 240 struct rs690_watermark {
 241         u32        lb_request_fifo_depth;
 242         fixed20_12 num_line_pair;
 243         fixed20_12 estimated_width;
 244         fixed20_12 worst_case_latency;
 245         fixed20_12 consumption_rate;
 246         fixed20_12 active_time;
 247         fixed20_12 dbpp;
 248         fixed20_12 priority_mark_max;
 249         fixed20_12 priority_mark;
 250         fixed20_12 sclk;
 251 };
 252
 253 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 254                                   struct radeon_crtc *crtc,
 255                                   struct rs690_watermark *wm)
 256 {
 257         struct drm_display_mode *mode = &crtc->base.mode;
 258         fixed20_12 a, b, c;
 259         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 260         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 261
 262         if (!crtc->base.enabled) {
 263                 /* FIXME: wouldn't it better to set priority mark to maximum */
 264                 wm->lb_request_fifo_depth = 4;
 265                 return;
 266         }
 267
 268         if (crtc->vsc.full > dfixed_const(2))
 269                 wm->num_line_pair.full = dfixed_const(2);
 270         else
 271                 wm->num_line_pair.full = dfixed_const(1);
 272
 273         b.full = dfixed_const(mode->crtc_hdisplay);
 274         c.full = dfixed_const(256);
 275         a.full = dfixed_div(b, c);
 276         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 277         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 278         if (a.full < dfixed_const(4)) {
 279                 wm->lb_request_fifo_depth = 4;
 280         } else {
 281                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 282         }
 283
 284         /* Determine consumption rate
 285          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 286          *  vtaps = number of vertical taps,
 287          *  vsc = vertical scaling ratio, defined as source/destination
 288          *  hsc = horizontal scaling ration, defined as source/destination
 289          */
 290         a.full = dfixed_const(mode->clock);
 291         b.full = dfixed_const(1000);
 292         a.full = dfixed_div(a, b);
 293         pclk.full = dfixed_div(b, a);
 294         if (crtc->rmx_type != RMX_OFF) {
 295                 b.full = dfixed_const(2);
 296                 if (crtc->vsc.full > b.full)
 297                         b.full = crtc->vsc.full;
 298                 b.full = dfixed_mul(b, crtc->hsc);
 299                 c.full = dfixed_const(2);
 300                 b.full = dfixed_div(b, c);
 301                 consumption_time.full = dfixed_div(pclk, b);
 302         } else {
 303                 consumption_time.full = pclk.full;
 304         }
 305         a.full = dfixed_const(1);
 306         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 307
 308
 309         /* Determine line time
 310          *  LineTime = total time for one line of displayhtotal
 311          *  LineTime = total number of horizontal pixels
 312          *  pclk = pixel clock period(ns)
 313          */
 314         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 315         line_time.full = dfixed_mul(a, pclk);
 316
 317         /* Determine active time
 318          *  ActiveTime = time of active region of display within one line,
 319          *  hactive = total number of horizontal active pixels
 320          *  htotal = total number of horizontal pixels
 321          */
 322         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 323         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 324         wm->active_time.full = dfixed_mul(line_time, b);
 325         wm->active_time.full = dfixed_div(wm->active_time, a);
 326
 327         /* Maximun bandwidth is the minimun bandwidth of all component */
 328         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 329         if (rdev->mc.igp_sideport_enabled) {
 330                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 331                         rdev->pm.sideport_bandwidth.full)
 332                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 333 #ifdef DUMBBELL_WIP
 334                 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
 335 #endif /* DUMBBELL_WIP */
 336                 read_delay_latency.full = UINT_MAX;
 337                 read_delay_latency.full = dfixed_div(read_delay_latency,
 338                         rdev->pm.igp_sideport_mclk);
 339         } else {
 340                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 341                         rdev->pm.k8_bandwidth.full)
 342                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 343                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 344                         rdev->pm.ht_bandwidth.full)
 345                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 346                 read_delay_latency.full = dfixed_const(5000);
 347         }
 348
 349         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 350         a.full = dfixed_const(16);
 351         rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
 352         a.full = dfixed_const(1000);
 353         rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
 354         /* Determine chunk time
 355          * ChunkTime = the time it takes the DCP to send one chunk of data
 356          * to the LB which consists of pipeline delay and inter chunk gap
 357          * sclk = system clock(ns)
 358          */
 359         a.full = dfixed_const(256 * 13);
 360         chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
 361         a.full = dfixed_const(10);
 362         chunk_time.full = dfixed_div(chunk_time, a);
 363
 364         /* Determine the worst case latency
 365          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 366          * WorstCaseLatency = worst case time from urgent to when the MC starts
 367          *                    to return data
 368          * READ_DELAY_IDLE_MAX = constant of 1us
 369          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 370          *             which consists of pipeline delay and inter chunk gap
 371          */
 372         if (dfixed_trunc(wm->num_line_pair) > 1) {
 373                 a.full = dfixed_const(3);
 374                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 375                 wm->worst_case_latency.full += read_delay_latency.full;
 376         } else {
 377                 a.full = dfixed_const(2);
 378                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 379                 wm->worst_case_latency.full += read_delay_latency.full;
 380         }
 381
 382         /* Determine the tolerable latency
 383          * TolerableLatency = Any given request has only 1 line time
 384          *                    for the data to be returned
 385          * LBRequestFifoDepth = Number of chunk requests the LB can
 386          *                      put into the request FIFO for a display
 387          *  LineTime = total time for one line of display
 388          *  ChunkTime = the time it takes the DCP to send one chunk
 389          *              of data to the LB which consists of
 390          *  pipeline delay and inter chunk gap
 391          */
 392         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
 393                 tolerable_latency.full = line_time.full;
 394         } else {
 395                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
 396                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 397                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
 398                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 399         }
 400         /* We assume worst case 32bits (4 bytes) */
 401         wm->dbpp.full = dfixed_const(4 * 8);
 402
 403         /* Determine the maximum priority mark
 404          *  width = viewport width in pixels
 405          */
 406         a.full = dfixed_const(16);
 407         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 408         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
 409         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
 410
 411         /* Determine estimated width */
 412         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 413         estimated_width.full = dfixed_div(estimated_width, consumption_time);
 414         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 415                 wm->priority_mark.full = dfixed_const(10);
 416         } else {
 417                 a.full = dfixed_const(16);
 418                 wm->priority_mark.full = dfixed_div(estimated_width, a);
 419                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
 420                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 421         }
 422 }
 423
 424 void rs690_bandwidth_update(struct radeon_device *rdev)
 425 {
 426         struct drm_display_mode *mode0 = NULL;
 427         struct drm_display_mode *mode1 = NULL;
 428         struct rs690_watermark wm0;
 429         struct rs690_watermark wm1;
 430         u32 tmp;
 431         u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 432         u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 433         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 434         fixed20_12 a, b;
 435
 436         radeon_update_display_priority(rdev);
 437
 438         if (rdev->mode_info.crtcs[0]->base.enabled)
 439                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 440         if (rdev->mode_info.crtcs[1]->base.enabled)
 441                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 442         /*
 443          * Set display0/1 priority up in the memory controller for
 444          * modes if the user specifies HIGH for displaypriority
 445          * option.
 446          */
 447         if ((rdev->disp_priority == 2) &&
 448             ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
 449                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 450                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 451                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 452                 if (mode0)
 453                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 454                 if (mode1)
 455                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 456                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 457         }
 458         rs690_line_buffer_adjust(rdev, mode0, mode1);
 459
 460         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 461                 WREG32(R_006C9C_DCP_CONTROL, 0);
 462         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 463                 WREG32(R_006C9C_DCP_CONTROL, 2);
 464
 465         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 466         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 467
 468         tmp = (wm0.lb_request_fifo_depth - 1);
 469         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 470         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 471
 472         if (mode0 && mode1) {
 473                 if (dfixed_trunc(wm0.dbpp) > 64)
 474                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 475                 else
 476                         a.full = wm0.num_line_pair.full;
 477                 if (dfixed_trunc(wm1.dbpp) > 64)
 478                         b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 479                 else
 480                         b.full = wm1.num_line_pair.full;
 481                 a.full += b.full;
 482                 fill_rate.full = dfixed_div(wm0.sclk, a);
 483                 if (wm0.consumption_rate.full > fill_rate.full) {
 484                         b.full = wm0.consumption_rate.full - fill_rate.full;
 485                         b.full = dfixed_mul(b, wm0.active_time);
 486                         a.full = dfixed_mul(wm0.worst_case_latency,
 487                                                 wm0.consumption_rate);
 488                         a.full = a.full + b.full;
 489                         b.full = dfixed_const(16 * 1000);
 490                         priority_mark02.full = dfixed_div(a, b);
 491                 } else {
 492                         a.full = dfixed_mul(wm0.worst_case_latency,
 493                                                 wm0.consumption_rate);
 494                         b.full = dfixed_const(16 * 1000);
 495                         priority_mark02.full = dfixed_div(a, b);
 496                 }
 497                 if (wm1.consumption_rate.full > fill_rate.full) {
 498                         b.full = wm1.consumption_rate.full - fill_rate.full;
 499                         b.full = dfixed_mul(b, wm1.active_time);
 500                         a.full = dfixed_mul(wm1.worst_case_latency,
 501                                                 wm1.consumption_rate);
 502                         a.full = a.full + b.full;
 503                         b.full = dfixed_const(16 * 1000);
 504                         priority_mark12.full = dfixed_div(a, b);
 505                 } else {
 506                         a.full = dfixed_mul(wm1.worst_case_latency,
 507                                                 wm1.consumption_rate);
 508                         b.full = dfixed_const(16 * 1000);
 509                         priority_mark12.full = dfixed_div(a, b);
 510                 }
 511                 if (wm0.priority_mark.full > priority_mark02.full)
 512                         priority_mark02.full = wm0.priority_mark.full;
 513                 if (dfixed_trunc(priority_mark02) < 0)
 514                         priority_mark02.full = 0;
 515                 if (wm0.priority_mark_max.full > priority_mark02.full)
 516                         priority_mark02.full = wm0.priority_mark_max.full;
 517                 if (wm1.priority_mark.full > priority_mark12.full)
 518                         priority_mark12.full = wm1.priority_mark.full;
 519                 if (dfixed_trunc(priority_mark12) < 0)
 520                         priority_mark12.full = 0;
 521                 if (wm1.priority_mark_max.full > priority_mark12.full)
 522                         priority_mark12.full = wm1.priority_mark_max.full;
 523                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 524                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 525                 if (rdev->disp_priority == 2) {
 526                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 527                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 528                 }
 529         } else if (mode0) {
 530                 if (dfixed_trunc(wm0.dbpp) > 64)
 531                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 532                 else
 533                         a.full = wm0.num_line_pair.full;
 534                 fill_rate.full = dfixed_div(wm0.sclk, a);
 535                 if (wm0.consumption_rate.full > fill_rate.full) {
 536                         b.full = wm0.consumption_rate.full - fill_rate.full;
 537                         b.full = dfixed_mul(b, wm0.active_time);
 538                         a.full = dfixed_mul(wm0.worst_case_latency,
 539                                                 wm0.consumption_rate);
 540                         a.full = a.full + b.full;
 541                         b.full = dfixed_const(16 * 1000);
 542                         priority_mark02.full = dfixed_div(a, b);
 543                 } else {
 544                         a.full = dfixed_mul(wm0.worst_case_latency,
 545                                                 wm0.consumption_rate);
 546                         b.full = dfixed_const(16 * 1000);
 547                         priority_mark02.full = dfixed_div(a, b);
 548                 }
 549                 if (wm0.priority_mark.full > priority_mark02.full)
 550                         priority_mark02.full = wm0.priority_mark.full;
 551                 if (dfixed_trunc(priority_mark02) < 0)
 552                         priority_mark02.full = 0;
 553                 if (wm0.priority_mark_max.full > priority_mark02.full)
 554                         priority_mark02.full = wm0.priority_mark_max.full;
 555                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 556                 if (rdev->disp_priority == 2)
 557                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 558         } else if (mode1) {
 559                 if (dfixed_trunc(wm1.dbpp) > 64)
 560                         a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 561                 else
 562                         a.full = wm1.num_line_pair.full;
 563                 fill_rate.full = dfixed_div(wm1.sclk, a);
 564                 if (wm1.consumption_rate.full > fill_rate.full) {
 565                         b.full = wm1.consumption_rate.full - fill_rate.full;
 566                         b.full = dfixed_mul(b, wm1.active_time);
 567                         a.full = dfixed_mul(wm1.worst_case_latency,
 568                                                 wm1.consumption_rate);
 569                         a.full = a.full + b.full;
 570                         b.full = dfixed_const(16 * 1000);
 571                         priority_mark12.full = dfixed_div(a, b);
 572                 } else {
 573                         a.full = dfixed_mul(wm1.worst_case_latency,
 574                                                 wm1.consumption_rate);
 575                         b.full = dfixed_const(16 * 1000);
 576                         priority_mark12.full = dfixed_div(a, b);
 577                 }
 578                 if (wm1.priority_mark.full > priority_mark12.full)
 579                         priority_mark12.full = wm1.priority_mark.full;
 580                 if (dfixed_trunc(priority_mark12) < 0)
 581                         priority_mark12.full = 0;
 582                 if (wm1.priority_mark_max.full > priority_mark12.full)
 583                         priority_mark12.full = wm1.priority_mark_max.full;
 584                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 585                 if (rdev->disp_priority == 2)
 586                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 587         }
 588
 589         WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 590         WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 591         WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 592         WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 593 }
 594
 595 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 596 {
 597         uint32_t r;
 598
 599         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 600         r = RREG32(R_00007C_MC_DATA);
 601         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 602         return r;
 603 }
 604
 605 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 606 {
 607         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 608                 S_000078_MC_IND_WR_EN(1));
 609         WREG32(R_00007C_MC_DATA, v);
 610         WREG32(R_000078_MC_INDEX, 0x7F);
 611 }
 612
 613 static void rs690_mc_program(struct radeon_device *rdev)
 614 {
 615         struct rv515_mc_save save;
 616
 617         /* Stops all mc clients */
 618         rv515_mc_stop(rdev, &save);
 619
 620         /* Wait for mc idle */
 621         if (rs690_mc_wait_for_idle(rdev))
 622                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 623         /* Program MC, should be a 32bits limited address space */
 624         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 625                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 626                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 627         WREG32(R_000134_HDP_FB_LOCATION,
 628                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 629
 630         rv515_mc_resume(rdev, &save);
 631 }
 632
 633 static int rs690_startup(struct radeon_device *rdev)
 634 {
 635         int r;
 636
 637         rs690_mc_program(rdev);
 638         /* Resume clock */
 639         rv515_clock_startup(rdev);
 640         /* Initialize GPU configuration (# pipes, ...) */
 641         rs690_gpu_init(rdev);
 642         /* Initialize GART (initialize after TTM so we can allocate
 643          * memory through TTM but finalize after TTM) */
 644         r = rs400_gart_enable(rdev);
 645         if (r)
 646                 return r;
 647
 648         /* allocate wb buffer */
 649         r = radeon_wb_init(rdev);
 650         if (r)
 651                 return r;
 652
 653         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 654         if (r) {
 655                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 656                 return r;
 657         }
 658
 659         /* Enable IRQ */
 660         if (!rdev->irq.installed) {
 661                 r = radeon_irq_kms_init(rdev);
 662                 if (r)
 663                         return r;
 664         }
 665
 666         rs600_irq_set(rdev);
 667         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 668         /* 1M ring buffer */
 669         r = r100_cp_init(rdev, 1024 * 1024);
 670         if (r) {
 671                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 672                 return r;
 673         }
 674
 675         r = radeon_ib_pool_init(rdev);
 676         if (r) {
 677                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 678                 return r;
 679         }
 680
 681         r = r600_audio_init(rdev);
 682         if (r) {
 683                 dev_err(rdev->dev, "failed initializing audio\n");
 684                 return r;
 685         }
 686
 687         return 0;
 688 }
 689
 690 int rs690_resume(struct radeon_device *rdev)
 691 {
 692         int r;
 693
 694         /* Make sur GART are not working */
 695         rs400_gart_disable(rdev);
 696         /* Resume clock before doing reset */
 697         rv515_clock_startup(rdev);
 698         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 699         if (radeon_asic_reset(rdev)) {
 700                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 701                         RREG32(R_000E40_RBBM_STATUS),
 702                         RREG32(R_0007C0_CP_STAT));
 703         }
 704         /* post */
 705         atom_asic_init(rdev->mode_info.atom_context);
 706         /* Resume clock after posting */
 707         rv515_clock_startup(rdev);
 708         /* Initialize surface registers */
 709         radeon_surface_init(rdev);
 710
 711         rdev->accel_working = true;
 712         r = rs690_startup(rdev);
 713         if (r) {
 714                 rdev->accel_working = false;
 715         }
 716         return r;
 717 }
 718
 719 int rs690_suspend(struct radeon_device *rdev)
 720 {
 721         r600_audio_fini(rdev);
 722         r100_cp_disable(rdev);
 723         radeon_wb_disable(rdev);
 724         rs600_irq_disable(rdev);
 725         rs400_gart_disable(rdev);
 726         return 0;
 727 }
 728
 729 void rs690_fini(struct radeon_device *rdev)
 730 {
 731         r600_audio_fini(rdev);
 732         r100_cp_fini(rdev);
 733         radeon_wb_fini(rdev);
 734         radeon_ib_pool_fini(rdev);
 735         radeon_gem_fini(rdev);
 736         rs400_gart_fini(rdev);
 737         radeon_irq_kms_fini(rdev);
 738         radeon_fence_driver_fini(rdev);
 739         radeon_bo_fini(rdev);
 740         radeon_atombios_fini(rdev);
 741         drm_free(rdev->bios, M_DRM);
 742         rdev->bios = NULL;
 743 }
 744
 745 int rs690_init(struct radeon_device *rdev)
 746 {
 747         int r;
 748
 749         /* Disable VGA */
 750         rv515_vga_render_disable(rdev);
 751         /* Initialize scratch registers */
 752         radeon_scratch_init(rdev);
 753         /* Initialize surface registers */
 754         radeon_surface_init(rdev);
 755         /* restore some register to sane defaults */
 756         r100_restore_sanity(rdev);
 757         /* TODO: disable VGA need to use VGA request */
 758         /* BIOS*/
 759         if (!radeon_get_bios(rdev)) {
 760                 if (ASIC_IS_AVIVO(rdev))
 761                         return -EINVAL;
 762         }
 763         if (rdev->is_atom_bios) {
 764                 r = radeon_atombios_init(rdev);
 765                 if (r)
 766                         return r;
 767         } else {
 768                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 769                 return -EINVAL;
 770         }
 771         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 772         if (radeon_asic_reset(rdev)) {
 773                 dev_warn(rdev->dev,
 774                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 775                         RREG32(R_000E40_RBBM_STATUS),
 776                         RREG32(R_0007C0_CP_STAT));
 777         }
 778         /* check if cards are posted or not */
 779         if (radeon_boot_test_post_card(rdev) == false)
 780                 return -EINVAL;
 781
 782         /* Initialize clocks */
 783         radeon_get_clock_info(rdev->ddev);
 784         /* initialize memory controller */
 785         rs690_mc_init(rdev);
 786         rv515_debugfs(rdev);
 787         /* Fence driver */
 788         r = radeon_fence_driver_init(rdev);
 789         if (r)
 790                 return r;
 791         /* Memory manager */
 792         r = radeon_bo_init(rdev);
 793         if (r)
 794                 return r;
 795         r = rs400_gart_init(rdev);
 796         if (r)
 797                 return r;
 798         rs600_set_safe_registers(rdev);
 799
 800         rdev->accel_working = true;
 801         r = rs690_startup(rdev);
 802         if (r) {
 803                 /* Somethings want wront with the accel init stop accel */
 804                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 805                 r100_cp_fini(rdev);
 806                 radeon_wb_fini(rdev);
 807                 radeon_ib_pool_fini(rdev);
 808                 rs400_gart_fini(rdev);
 809                 radeon_irq_kms_fini(rdev);
 810                 rdev->accel_working = false;
 811         }
 812         return 0;
 813 }