sys/dev/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int
 321 gen7_render_ring_flush(struct intel_engine_cs *ring,
 322                        u32 invalidate_domains, u32 flush_domains)
 323 {
 324         u32 flags = 0;
 325         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 326         int ret;
 327
 328         /*
 329          * Ensure that any following seqno writes only happen when the render
 330          * cache is indeed flushed.
 331          *
 332          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 333          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 334          * don't try to be clever and just set it unconditionally.
 335          */
 336         flags |= PIPE_CONTROL_CS_STALL;
 337
 338         /* Just flush everything.  Experiments have shown that reducing the
 339          * number of bits based on the write domains has little performance
 340          * impact.
 341          */
 342         if (flush_domains) {
 343                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 344                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 345         }
 346         if (invalidate_domains) {
 347                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 348                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 349                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 350                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 351                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 352                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 353                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 354                 /*
 355                  * TLB invalidate requires a post-sync write.
 356                  */
 357                 flags |= PIPE_CONTROL_QW_WRITE;
 358                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 359
 360                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 361
 362                 /* Workaround: we must issue a pipe_control with CS-stall bit
 363                  * set before a pipe_control command that has the state cache
 364                  * invalidate bit set. */
 365                 gen7_render_ring_cs_stall_wa(ring);
 366         }
 367
 368         ret = intel_ring_begin(ring, 4);
 369         if (ret)
 370                 return ret;
 371
 372         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 373         intel_ring_emit(ring, flags);
 374         intel_ring_emit(ring, scratch_addr);
 375         intel_ring_emit(ring, 0);
 376         intel_ring_advance(ring);
 377
 378         return 0;
 379 }
 380
 381 static int
 382 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 383                        u32 flags, u32 scratch_addr)
 384 {
 385         int ret;
 386
 387         ret = intel_ring_begin(ring, 6);
 388         if (ret)
 389                 return ret;
 390
 391         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 392         intel_ring_emit(ring, flags);
 393         intel_ring_emit(ring, scratch_addr);
 394         intel_ring_emit(ring, 0);
 395         intel_ring_emit(ring, 0);
 396         intel_ring_emit(ring, 0);
 397         intel_ring_advance(ring);
 398
 399         return 0;
 400 }
 401
 402 static int
 403 gen8_render_ring_flush(struct intel_engine_cs *ring,
 404                        u32 invalidate_domains, u32 flush_domains)
 405 {
 406         u32 flags = 0;
 407         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 408         int ret;
 409
 410         flags |= PIPE_CONTROL_CS_STALL;
 411
 412         if (flush_domains) {
 413                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 414                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 415         }
 416         if (invalidate_domains) {
 417                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 418                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 419                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 420                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 421                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 422                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 423                 flags |= PIPE_CONTROL_QW_WRITE;
 424                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 425
 426                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 427                 ret = gen8_emit_pipe_control(ring,
 428                                              PIPE_CONTROL_CS_STALL |
 429                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 430                                              0);
 431                 if (ret)
 432                         return ret;
 433         }
 434
 435         return gen8_emit_pipe_control(ring, flags, scratch_addr);
 436 }
 437
 438 static void ring_write_tail(struct intel_engine_cs *ring,
 439                             u32 value)
 440 {
 441         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 442         I915_WRITE_TAIL(ring, value);
 443 }
 444
 445 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 446 {
 447         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 448         u64 acthd;
 449
 450         if (INTEL_INFO(ring->dev)->gen >= 8)
 451                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 452                                          RING_ACTHD_UDW(ring->mmio_base));
 453         else if (INTEL_INFO(ring->dev)->gen >= 4)
 454                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 455         else
 456                 acthd = I915_READ(ACTHD);
 457
 458         return acthd;
 459 }
 460
 461 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 462 {
 463         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 464         u32 addr;
 465
 466         addr = dev_priv->status_page_dmah->busaddr;
 467         if (INTEL_INFO(ring->dev)->gen >= 4)
 468                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 469         I915_WRITE(HWS_PGA, addr);
 470 }
 471
 472 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 473 {
 474         struct drm_device *dev = ring->dev;
 475         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 476         u32 mmio = 0;
 477
 478         /* The ring status page addresses are no longer next to the rest of
 479          * the ring registers as of gen7.
 480          */
 481         if (IS_GEN7(dev)) {
 482                 switch (ring->id) {
 483                 case RCS:
 484                         mmio = RENDER_HWS_PGA_GEN7;
 485                         break;
 486                 case BCS:
 487                         mmio = BLT_HWS_PGA_GEN7;
 488                         break;
 489                 /*
 490                  * VCS2 actually doesn't exist on Gen7. Only shut up
 491                  * gcc switch check warning
 492                  */
 493                 case VCS2:
 494                 case VCS:
 495                         mmio = BSD_HWS_PGA_GEN7;
 496                         break;
 497                 case VECS:
 498                         mmio = VEBOX_HWS_PGA_GEN7;
 499                         break;
 500                 }
 501         } else if (IS_GEN6(ring->dev)) {
 502                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 503         } else {
 504                 /* XXX: gen8 returns to sanity */
 505                 mmio = RING_HWS_PGA(ring->mmio_base);
 506         }
 507
 508         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 509         POSTING_READ(mmio);
 510
 511         /*
 512          * Flush the TLB for this page
 513          *
 514          * FIXME: These two bits have disappeared on gen8, so a question
 515          * arises: do we still need this and if so how should we go about
 516          * invalidating the TLB?
 517          */
 518         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 519                 u32 reg = RING_INSTPM(ring->mmio_base);
 520
 521                 /* ring should be idle before issuing a sync flush*/
 522                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 523
 524                 I915_WRITE(reg,
 525                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 526                                               INSTPM_SYNC_FLUSH));
 527                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 528                              1000))
 529                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 530                                   ring->name);
 531         }
 532 }
 533
 534 static bool stop_ring(struct intel_engine_cs *ring)
 535 {
 536         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 537
 538         if (!IS_GEN2(ring->dev)) {
 539                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 540                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 541                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 542                         /* Sometimes we observe that the idle flag is not
 543                          * set even though the ring is empty. So double
 544                          * check before giving up.
 545                          */
 546                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 547                                 return false;
 548                 }
 549         }
 550
 551         I915_WRITE_CTL(ring, 0);
 552         I915_WRITE_HEAD(ring, 0);
 553         ring->write_tail(ring, 0);
 554
 555         if (!IS_GEN2(ring->dev)) {
 556                 (void)I915_READ_CTL(ring);
 557                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 558         }
 559
 560         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 561 }
 562
 563 static int init_ring_common(struct intel_engine_cs *ring)
 564 {
 565         struct drm_device *dev = ring->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_ringbuffer *ringbuf = ring->buffer;
 568         struct drm_i915_gem_object *obj = ringbuf->obj;
 569         int ret = 0;
 570
 571         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 572
 573         if (!stop_ring(ring)) {
 574                 /* G45 ring initialization often fails to reset head to zero */
 575                 DRM_DEBUG_KMS("%s head not reset to zero "
 576                               "ctl %08x head %08x tail %08x start %08x\n",
 577                               ring->name,
 578                               I915_READ_CTL(ring),
 579                               I915_READ_HEAD(ring),
 580                               I915_READ_TAIL(ring),
 581                               I915_READ_START(ring));
 582
 583                 if (!stop_ring(ring)) {
 584                         DRM_ERROR("failed to set %s head to zero "
 585                                   "ctl %08x head %08x tail %08x start %08x\n",
 586                                   ring->name,
 587                                   I915_READ_CTL(ring),
 588                                   I915_READ_HEAD(ring),
 589                                   I915_READ_TAIL(ring),
 590                                   I915_READ_START(ring));
 591                         ret = -EIO;
 592                         goto out;
 593                 }
 594         }
 595
 596         if (I915_NEED_GFX_HWS(dev))
 597                 intel_ring_setup_status_page(ring);
 598         else
 599                 ring_setup_phys_status_page(ring);
 600
 601         /* Enforce ordering by reading HEAD register back */
 602         I915_READ_HEAD(ring);
 603
 604         /* Initialize the ring. This must happen _after_ we've cleared the ring
 605          * registers with the above sequence (the readback of the HEAD registers
 606          * also enforces ordering), otherwise the hw might lose the new ring
 607          * register values. */
 608         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 609
 610         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 611         if (I915_READ_HEAD(ring))
 612                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 613                           ring->name, I915_READ_HEAD(ring));
 614         I915_WRITE_HEAD(ring, 0);
 615         (void)I915_READ_HEAD(ring);
 616
 617         I915_WRITE_CTL(ring,
 618                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 619                         | RING_VALID);
 620
 621         /* If the head is still not zero, the ring is dead */
 622         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 623                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 624                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 625                 DRM_ERROR("%s initialization failed "
 626                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 627                           ring->name,
 628                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 629                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 630                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 631                 ret = -EIO;
 632                 goto out;
 633         }
 634
 635         ringbuf->last_retired_head = -1;
 636         ringbuf->head = I915_READ_HEAD(ring);
 637         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 638         intel_ring_update_space(ringbuf);
 639
 640         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 641
 642 out:
 643         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 644
 645         return ret;
 646 }
 647
 648 void
 649 intel_fini_pipe_control(struct intel_engine_cs *ring)
 650 {
 651         struct drm_device *dev = ring->dev;
 652
 653         if (ring->scratch.obj == NULL)
 654                 return;
 655
 656         if (INTEL_INFO(dev)->gen >= 5) {
 657                 kunmap(ring->scratch.obj->pages[0]);
 658                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 659         }
 660
 661         drm_gem_object_unreference(&ring->scratch.obj->base);
 662         ring->scratch.obj = NULL;
 663 }
 664
 665 int
 666 intel_init_pipe_control(struct intel_engine_cs *ring)
 667 {
 668         int ret;
 669
 670         WARN_ON(ring->scratch.obj);
 671
 672         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 673         if (ring->scratch.obj == NULL) {
 674                 DRM_ERROR("Failed to allocate seqno page\n");
 675                 ret = -ENOMEM;
 676                 goto err;
 677         }
 678
 679         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 680         if (ret)
 681                 goto err_unref;
 682
 683         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 684         if (ret)
 685                 goto err_unref;
 686
 687         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 688         ring->scratch.cpu_page = kmap(ring->scratch.obj->pages[0]);
 689         if (ring->scratch.cpu_page == NULL) {
 690                 ret = -ENOMEM;
 691                 goto err_unpin;
 692         }
 693
 694         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 695                          ring->name, ring->scratch.gtt_offset);
 696         return 0;
 697
 698 err_unpin:
 699         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 700 err_unref:
 701         drm_gem_object_unreference(&ring->scratch.obj->base);
 702 err:
 703         return ret;
 704 }
 705
 706 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 707                                        struct intel_context *ctx)
 708 {
 709         int ret, i;
 710         struct drm_device *dev = ring->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct i915_workarounds *w = &dev_priv->workarounds;
 713
 714         if (WARN_ON_ONCE(w->count == 0))
 715                 return 0;
 716
 717         ring->gpu_caches_dirty = true;
 718         ret = intel_ring_flush_all_caches(ring);
 719         if (ret)
 720                 return ret;
 721
 722         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 723         if (ret)
 724                 return ret;
 725
 726         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 727         for (i = 0; i < w->count; i++) {
 728                 intel_ring_emit(ring, w->reg[i].addr);
 729                 intel_ring_emit(ring, w->reg[i].value);
 730         }
 731         intel_ring_emit(ring, MI_NOOP);
 732
 733         intel_ring_advance(ring);
 734
 735         ring->gpu_caches_dirty = true;
 736         ret = intel_ring_flush_all_caches(ring);
 737         if (ret)
 738                 return ret;
 739
 740         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 741
 742         return 0;
 743 }
 744
 745 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 746                               struct intel_context *ctx)
 747 {
 748         int ret;
 749
 750         ret = intel_ring_workarounds_emit(ring, ctx);
 751         if (ret != 0)
 752                 return ret;
 753
 754         ret = i915_gem_render_state_init(ring);
 755         if (ret)
 756                 DRM_ERROR("init render state: %d\n", ret);
 757
 758         return ret;
 759 }
 760
 761 static int wa_add(struct drm_i915_private *dev_priv,
 762                   const u32 addr, const u32 mask, const u32 val)
 763 {
 764         const u32 idx = dev_priv->workarounds.count;
 765
 766         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 767                 return -ENOSPC;
 768
 769         dev_priv->workarounds.reg[idx].addr = addr;
 770         dev_priv->workarounds.reg[idx].value = val;
 771         dev_priv->workarounds.reg[idx].mask = mask;
 772
 773         dev_priv->workarounds.count++;
 774
 775         return 0;
 776 }
 777
 778 #define WA_REG(addr, mask, val) { \
 779                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 780                 if (r) \
 781                         return r; \
 782         }
 783
 784 #define WA_SET_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 786
 787 #define WA_CLR_BIT_MASKED(addr, mask) \
 788         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 789
 790 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 791         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 792
 793 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 794 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 795
 796 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 797
 798 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 799 {
 800         struct drm_device *dev = ring->dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802
 803         /* WaDisablePartialInstShootdown:bdw */
 804         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 805         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 806                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 807                           STALL_DOP_GATING_DISABLE);
 808
 809         /* WaDisableDopClockGating:bdw */
 810         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 811                           DOP_CLOCK_GATING_DISABLE);
 812
 813         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 814                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 815
 816         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 817          * workaround for for a possible hang in the unlikely event a TLB
 818          * invalidation occurs during a PSD flush.
 819          */
 820         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 821                           /* WaForceEnableNonCoherent:bdw */
 822                           HDC_FORCE_NON_COHERENT |
 823                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 824                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 825                           /* WaHdcDisableFetchWhenMasked:bdw */
 826                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 827                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 828                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 829
 830         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 831          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 832          *  polygons in the same 8x4 pixel/sample area to be processed without
 833          *  stalling waiting for the earlier ones to write to Hierarchical Z
 834          *  buffer."
 835          *
 836          * This optimization is off by default for Broadwell; turn it on.
 837          */
 838         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 839
 840         /* Wa4x4STCOptimizationDisable:bdw */
 841         WA_SET_BIT_MASKED(CACHE_MODE_1,
 842                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 843
 844         /*
 845          * BSpec recommends 8x4 when MSAA is used,
 846          * however in practice 16x4 seems fastest.
 847          *
 848          * Note that PS/WM thread counts depend on the WIZ hashing
 849          * disable bit, which we don't touch here, but it's good
 850          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 851          */
 852         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 853                             GEN6_WIZ_HASHING_MASK,
 854                             GEN6_WIZ_HASHING_16x4);
 855
 856         return 0;
 857 }
 858
 859 static int chv_init_workarounds(struct intel_engine_cs *ring)
 860 {
 861         struct drm_device *dev = ring->dev;
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863
 864         /* WaDisablePartialInstShootdown:chv */
 865         /* WaDisableThreadStallDopClockGating:chv */
 866         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 867                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 868                           STALL_DOP_GATING_DISABLE);
 869
 870         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 871          * workaround for a possible hang in the unlikely event a TLB
 872          * invalidation occurs during a PSD flush.
 873          */
 874         /* WaForceEnableNonCoherent:chv */
 875         /* WaHdcDisableFetchWhenMasked:chv */
 876         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 877                           HDC_FORCE_NON_COHERENT |
 878                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 879
 880         /* According to the CACHE_MODE_0 default value documentation, some
 881          * CHV platforms disable this optimization by default.  Turn it on.
 882          */
 883         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 884
 885         /* Wa4x4STCOptimizationDisable:chv */
 886         WA_SET_BIT_MASKED(CACHE_MODE_1,
 887                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 888
 889         /* Improve HiZ throughput on CHV. */
 890         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 891
 892         /*
 893          * BSpec recommends 8x4 when MSAA is used,
 894          * however in practice 16x4 seems fastest.
 895          *
 896          * Note that PS/WM thread counts depend on the WIZ hashing
 897          * disable bit, which we don't touch here, but it's good
 898          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 899          */
 900         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 901                             GEN6_WIZ_HASHING_MASK,
 902                             GEN6_WIZ_HASHING_16x4);
 903
 904         return 0;
 905 }
 906
 907 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 908 {
 909         struct drm_device *dev = ring->dev;
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911
 912         /* WaDisablePartialInstShootdown:skl */
 913         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 914                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 915
 916         /* Syncing dependencies between camera and graphics */
 917         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 918                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 919
 920         if (INTEL_REVID(dev) == SKL_REVID_A0 ||
 921             INTEL_REVID(dev) == SKL_REVID_B0) {
 922                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
 923                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 924                                   GEN9_DG_MIRROR_FIX_ENABLE);
 925         }
 926
 927         if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
 928                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
 929                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 930                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 931                 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
 932                                   DISABLE_PIXEL_MASK_CAMMING);
 933         }
 934
 935         if (INTEL_REVID(dev) >= SKL_REVID_C0) {
 936                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
 937                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 938                                   GEN9_ENABLE_YV12_BUGFIX);
 939         }
 940
 941         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
 942                 /*
 943                  *Use Force Non-Coherent whenever executing a 3D context. This
 944                  * is a workaround for a possible hang in the unlikely event
 945                  * a TLB invalidation occurs during a PSD flush.
 946                  */
 947                 /* WaForceEnableNonCoherent:skl */
 948                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
 949                                   HDC_FORCE_NON_COHERENT);
 950         }
 951
 952         /* Wa4x4STCOptimizationDisable:skl */
 953         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 954
 955         /* WaDisablePartialResolveInVc:skl */
 956         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 957
 958         /* WaCcsTlbPrefetchDisable:skl */
 959         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 960                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 961
 962         return 0;
 963 }
 964
 965 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 966 {
 967         struct drm_device *dev = ring->dev;
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         u8 vals[3] = { 0, 0, 0 };
 970         unsigned int i;
 971
 972         for (i = 0; i < 3; i++) {
 973                 u8 ss;
 974
 975                 /*
 976                  * Only consider slices where one, and only one, subslice has 7
 977                  * EUs
 978                  */
 979                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
 980                         continue;
 981
 982                 /*
 983                  * subslice_7eu[i] != 0 (because of the check above) and
 984                  * ss_max == 4 (maximum number of subslices possible per slice)
 985                  *
 986                  * ->    0 <= ss <= 3;
 987                  */
 988                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
 989                 vals[i] = 3 - ss;
 990         }
 991
 992         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 993                 return 0;
 994
 995         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 996         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 997                             GEN9_IZ_HASHING_MASK(2) |
 998                             GEN9_IZ_HASHING_MASK(1) |
 999                             GEN9_IZ_HASHING_MASK(0),
1000                             GEN9_IZ_HASHING(2, vals[2]) |
1001                             GEN9_IZ_HASHING(1, vals[1]) |
1002                             GEN9_IZ_HASHING(0, vals[0]));
1003
1004         return 0;
1005 }
1006
1007
1008 static int skl_init_workarounds(struct intel_engine_cs *ring)
1009 {
1010         struct drm_device *dev = ring->dev;
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012
1013         gen9_init_workarounds(ring);
1014
1015         /* WaDisablePowerCompilerClockGating:skl */
1016         if (INTEL_REVID(dev) == SKL_REVID_B0)
1017                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1018                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1019
1020         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1021             INTEL_REVID(dev) == SKL_REVID_D0)
1022                 /* WaBarrierPerformanceFixDisable:skl */
1023                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1024                                   HDC_FENCE_DEST_SLM_DISABLE |
1025                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1026
1027         return skl_tune_iz_hashing(ring);
1028 }
1029
1030 int init_workarounds_ring(struct intel_engine_cs *ring)
1031 {
1032         struct drm_device *dev = ring->dev;
1033         struct drm_i915_private *dev_priv = dev->dev_private;
1034
1035         WARN_ON(ring->id != RCS);
1036
1037         dev_priv->workarounds.count = 0;
1038
1039         if (IS_BROADWELL(dev))
1040                 return bdw_init_workarounds(ring);
1041
1042         if (IS_CHERRYVIEW(dev))
1043                 return chv_init_workarounds(ring);
1044
1045         if (IS_SKYLAKE(dev))
1046                 return skl_init_workarounds(ring);
1047         else if (IS_GEN9(dev))
1048                 return gen9_init_workarounds(ring);
1049
1050         return 0;
1051 }
1052
1053 static int init_render_ring(struct intel_engine_cs *ring)
1054 {
1055         struct drm_device *dev = ring->dev;
1056         struct drm_i915_private *dev_priv = dev->dev_private;
1057         int ret = init_ring_common(ring);
1058         if (ret)
1059                 return ret;
1060
1061         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1062         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1063                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1064
1065         /* We need to disable the AsyncFlip performance optimisations in order
1066          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1067          * programmed to '1' on all products.
1068          *
1069          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1070          */
1071         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1072                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1073
1074         /* Required for the hardware to program scanline values for waiting */
1075         /* WaEnableFlushTlbInvalidationMode:snb */
1076         if (INTEL_INFO(dev)->gen == 6)
1077                 I915_WRITE(GFX_MODE,
1078                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1079
1080         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1081         if (IS_GEN7(dev))
1082                 I915_WRITE(GFX_MODE_GEN7,
1083                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1084                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1085
1086         if (IS_GEN6(dev)) {
1087                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1088                  * "If this bit is set, STCunit will have LRA as replacement
1089                  *  policy. [...] This bit must be reset.  LRA replacement
1090                  *  policy is not supported."
1091                  */
1092                 I915_WRITE(CACHE_MODE_0,
1093                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1094         }
1095
1096         if (INTEL_INFO(dev)->gen >= 6)
1097                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1098
1099         if (HAS_L3_DPF(dev))
1100                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1101
1102         return init_workarounds_ring(ring);
1103 }
1104
1105 static void render_ring_cleanup(struct intel_engine_cs *ring)
1106 {
1107         struct drm_device *dev = ring->dev;
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109
1110         if (dev_priv->semaphore_obj) {
1111                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1112                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1113                 dev_priv->semaphore_obj = NULL;
1114         }
1115
1116         intel_fini_pipe_control(ring);
1117 }
1118
1119 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1120                            unsigned int num_dwords)
1121 {
1122 #define MBOX_UPDATE_DWORDS 8
1123         struct drm_device *dev = signaller->dev;
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125         struct intel_engine_cs *waiter;
1126         int i, ret, num_rings;
1127
1128         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1129         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1130 #undef MBOX_UPDATE_DWORDS
1131
1132         ret = intel_ring_begin(signaller, num_dwords);
1133         if (ret)
1134                 return ret;
1135
1136         for_each_ring(waiter, dev_priv, i) {
1137                 u32 seqno;
1138                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1139                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1140                         continue;
1141
1142                 seqno = i915_gem_request_get_seqno(
1143                                            signaller->outstanding_lazy_request);
1144                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1145                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1146                                            PIPE_CONTROL_QW_WRITE |
1147                                            PIPE_CONTROL_FLUSH_ENABLE);
1148                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1149                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1150                 intel_ring_emit(signaller, seqno);
1151                 intel_ring_emit(signaller, 0);
1152                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1153                                            MI_SEMAPHORE_TARGET(waiter->id));
1154                 intel_ring_emit(signaller, 0);
1155         }
1156
1157         return 0;
1158 }
1159
1160 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1161                            unsigned int num_dwords)
1162 {
1163 #define MBOX_UPDATE_DWORDS 6
1164         struct drm_device *dev = signaller->dev;
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         struct intel_engine_cs *waiter;
1167         int i, ret, num_rings;
1168
1169         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1170         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1171 #undef MBOX_UPDATE_DWORDS
1172
1173         ret = intel_ring_begin(signaller, num_dwords);
1174         if (ret)
1175                 return ret;
1176
1177         for_each_ring(waiter, dev_priv, i) {
1178                 u32 seqno;
1179                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1180                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1181                         continue;
1182
1183                 seqno = i915_gem_request_get_seqno(
1184                                            signaller->outstanding_lazy_request);
1185                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1186                                            MI_FLUSH_DW_OP_STOREDW);
1187                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1188                                            MI_FLUSH_DW_USE_GTT);
1189                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1190                 intel_ring_emit(signaller, seqno);
1191                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1192                                            MI_SEMAPHORE_TARGET(waiter->id));
1193                 intel_ring_emit(signaller, 0);
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int gen6_signal(struct intel_engine_cs *signaller,
1200                        unsigned int num_dwords)
1201 {
1202         struct drm_device *dev = signaller->dev;
1203         struct drm_i915_private *dev_priv = dev->dev_private;
1204         struct intel_engine_cs *useless;
1205         int i, ret, num_rings;
1206
1207 #define MBOX_UPDATE_DWORDS 3
1208         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1209         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1210 #undef MBOX_UPDATE_DWORDS
1211
1212         ret = intel_ring_begin(signaller, num_dwords);
1213         if (ret)
1214                 return ret;
1215
1216         for_each_ring(useless, dev_priv, i) {
1217                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1218                 if (mbox_reg != GEN6_NOSYNC) {
1219                         u32 seqno = i915_gem_request_get_seqno(
1220                                            signaller->outstanding_lazy_request);
1221                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1222                         intel_ring_emit(signaller, mbox_reg);
1223                         intel_ring_emit(signaller, seqno);
1224                 }
1225         }
1226
1227         /* If num_dwords was rounded, make sure the tail pointer is correct */
1228         if (num_rings % 2 == 0)
1229                 intel_ring_emit(signaller, MI_NOOP);
1230
1231         return 0;
1232 }
1233
1234 /**
1235  * gen6_add_request - Update the semaphore mailbox registers
1236  *
1237  * @ring - ring that is adding a request
1238  * @seqno - return seqno stuck into the ring
1239  *
1240  * Update the mailbox registers in the *other* rings with the current seqno.
1241  * This acts like a signal in the canonical semaphore.
1242  */
1243 static int
1244 gen6_add_request(struct intel_engine_cs *ring)
1245 {
1246         int ret;
1247
1248         if (ring->semaphore.signal)
1249                 ret = ring->semaphore.signal(ring, 4);
1250         else
1251                 ret = intel_ring_begin(ring, 4);
1252
1253         if (ret)
1254                 return ret;
1255
1256         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1257         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1258         intel_ring_emit(ring,
1259                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1260         intel_ring_emit(ring, MI_USER_INTERRUPT);
1261         __intel_ring_advance(ring);
1262
1263         return 0;
1264 }
1265
1266 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1267                                               u32 seqno)
1268 {
1269         struct drm_i915_private *dev_priv = dev->dev_private;
1270         return dev_priv->last_seqno < seqno;
1271 }
1272
1273 /**
1274  * intel_ring_sync - sync the waiter to the signaller on seqno
1275  *
1276  * @waiter - ring that is waiting
1277  * @signaller - ring which has, or will signal
1278  * @seqno - seqno which the waiter will block on
1279  */
1280
1281 static int
1282 gen8_ring_sync(struct intel_engine_cs *waiter,
1283                struct intel_engine_cs *signaller,
1284                u32 seqno)
1285 {
1286         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1287         int ret;
1288
1289         ret = intel_ring_begin(waiter, 4);
1290         if (ret)
1291                 return ret;
1292
1293         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1294                                 MI_SEMAPHORE_GLOBAL_GTT |
1295                                 MI_SEMAPHORE_POLL |
1296                                 MI_SEMAPHORE_SAD_GTE_SDD);
1297         intel_ring_emit(waiter, seqno);
1298         intel_ring_emit(waiter,
1299                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1300         intel_ring_emit(waiter,
1301                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1302         intel_ring_advance(waiter);
1303         return 0;
1304 }
1305
1306 static int
1307 gen6_ring_sync(struct intel_engine_cs *waiter,
1308                struct intel_engine_cs *signaller,
1309                u32 seqno)
1310 {
1311         u32 dw1 = MI_SEMAPHORE_MBOX |
1312                   MI_SEMAPHORE_COMPARE |
1313                   MI_SEMAPHORE_REGISTER;
1314         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1315         int ret;
1316
1317         /* Throughout all of the GEM code, seqno passed implies our current
1318          * seqno is >= the last seqno executed. However for hardware the
1319          * comparison is strictly greater than.
1320          */
1321         seqno -= 1;
1322
1323         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1324
1325         ret = intel_ring_begin(waiter, 4);
1326         if (ret)
1327                 return ret;
1328
1329         /* If seqno wrap happened, omit the wait with no-ops */
1330         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1331                 intel_ring_emit(waiter, dw1 | wait_mbox);
1332                 intel_ring_emit(waiter, seqno);
1333                 intel_ring_emit(waiter, 0);
1334                 intel_ring_emit(waiter, MI_NOOP);
1335         } else {
1336                 intel_ring_emit(waiter, MI_NOOP);
1337                 intel_ring_emit(waiter, MI_NOOP);
1338                 intel_ring_emit(waiter, MI_NOOP);
1339                 intel_ring_emit(waiter, MI_NOOP);
1340         }
1341         intel_ring_advance(waiter);
1342
1343         return 0;
1344 }
1345
1346 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1347 do {                                                                    \
1348         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1349                  PIPE_CONTROL_DEPTH_STALL);                             \
1350         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1351         intel_ring_emit(ring__, 0);                                                     \
1352         intel_ring_emit(ring__, 0);                                                     \
1353 } while (0)
1354
1355 static int
1356 pc_render_add_request(struct intel_engine_cs *ring)
1357 {
1358         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1359         int ret;
1360
1361         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1362          * incoherent with writes to memory, i.e. completely fubar,
1363          * so we need to use PIPE_NOTIFY instead.
1364          *
1365          * However, we also need to workaround the qword write
1366          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1367          * memory before requesting an interrupt.
1368          */
1369         ret = intel_ring_begin(ring, 32);
1370         if (ret)
1371                 return ret;
1372
1373         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1374                         PIPE_CONTROL_WRITE_FLUSH |
1375                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1376         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1377         intel_ring_emit(ring,
1378                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1379         intel_ring_emit(ring, 0);
1380         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1381         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1382         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1383         scratch_addr += 2 * CACHELINE_BYTES;
1384         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1385         scratch_addr += 2 * CACHELINE_BYTES;
1386         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1387         scratch_addr += 2 * CACHELINE_BYTES;
1388         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1389         scratch_addr += 2 * CACHELINE_BYTES;
1390         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1391
1392         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1393                         PIPE_CONTROL_WRITE_FLUSH |
1394                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1395                         PIPE_CONTROL_NOTIFY);
1396         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1397         intel_ring_emit(ring,
1398                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1399         intel_ring_emit(ring, 0);
1400         __intel_ring_advance(ring);
1401
1402         return 0;
1403 }
1404
1405 static u32
1406 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1407 {
1408         /* Workaround to force correct ordering between irq and seqno writes on
1409          * ivb (and maybe also on snb) by reading from a CS register (like
1410          * ACTHD) before reading the status page. */
1411         if (!lazy_coherency) {
1412                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1413                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1414         }
1415
1416         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1417 }
1418
1419 static u32
1420 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1421 {
1422         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1423 }
1424
1425 static void
1426 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1427 {
1428         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1429 }
1430
1431 static u32
1432 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1433 {
1434         return ring->scratch.cpu_page[0];
1435 }
1436
1437 static void
1438 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1439 {
1440         ring->scratch.cpu_page[0] = seqno;
1441 }
1442
1443 static bool
1444 gen5_ring_get_irq(struct intel_engine_cs *ring)
1445 {
1446         struct drm_device *dev = ring->dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448
1449         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1450                 return false;
1451
1452         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1453         if (ring->irq_refcount++ == 0)
1454                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1455         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1456
1457         return true;
1458 }
1459
1460 static void
1461 gen5_ring_put_irq(struct intel_engine_cs *ring)
1462 {
1463         struct drm_device *dev = ring->dev;
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465
1466         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1467         if (--ring->irq_refcount == 0)
1468                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1469         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1470 }
1471
1472 static bool
1473 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1474 {
1475         struct drm_device *dev = ring->dev;
1476         struct drm_i915_private *dev_priv = dev->dev_private;
1477
1478         if (!intel_irqs_enabled(dev_priv))
1479                 return false;
1480
1481         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1482         if (ring->irq_refcount++ == 0) {
1483                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1484                 I915_WRITE(IMR, dev_priv->irq_mask);
1485                 POSTING_READ(IMR);
1486         }
1487         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1488
1489         return true;
1490 }
1491
1492 static void
1493 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1494 {
1495         struct drm_device *dev = ring->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497
1498         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1499         if (--ring->irq_refcount == 0) {
1500                 dev_priv->irq_mask |= ring->irq_enable_mask;
1501                 I915_WRITE(IMR, dev_priv->irq_mask);
1502                 POSTING_READ(IMR);
1503         }
1504         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1505 }
1506
1507 static bool
1508 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1509 {
1510         struct drm_device *dev = ring->dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512
1513         if (!intel_irqs_enabled(dev_priv))
1514                 return false;
1515
1516         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1517         if (ring->irq_refcount++ == 0) {
1518                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1519                 I915_WRITE16(IMR, dev_priv->irq_mask);
1520                 POSTING_READ16(IMR);
1521         }
1522         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1523
1524         return true;
1525 }
1526
1527 static void
1528 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1529 {
1530         struct drm_device *dev = ring->dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532
1533         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1534         if (--ring->irq_refcount == 0) {
1535                 dev_priv->irq_mask |= ring->irq_enable_mask;
1536                 I915_WRITE16(IMR, dev_priv->irq_mask);
1537                 POSTING_READ16(IMR);
1538         }
1539         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1540 }
1541
1542 static int
1543 bsd_ring_flush(struct intel_engine_cs *ring,
1544                u32     invalidate_domains,
1545                u32     flush_domains)
1546 {
1547         int ret;
1548
1549         ret = intel_ring_begin(ring, 2);
1550         if (ret)
1551                 return ret;
1552
1553         intel_ring_emit(ring, MI_FLUSH);
1554         intel_ring_emit(ring, MI_NOOP);
1555         intel_ring_advance(ring);
1556         return 0;
1557 }
1558
1559 static int
1560 i9xx_add_request(struct intel_engine_cs *ring)
1561 {
1562         int ret;
1563
1564         ret = intel_ring_begin(ring, 4);
1565         if (ret)
1566                 return ret;
1567
1568         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1569         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1570         intel_ring_emit(ring,
1571                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1572         intel_ring_emit(ring, MI_USER_INTERRUPT);
1573         __intel_ring_advance(ring);
1574
1575         return 0;
1576 }
1577
1578 static bool
1579 gen6_ring_get_irq(struct intel_engine_cs *ring)
1580 {
1581         struct drm_device *dev = ring->dev;
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583
1584         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1585                 return false;
1586
1587         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1588         if (ring->irq_refcount++ == 0) {
1589                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1590                         I915_WRITE_IMR(ring,
1591                                        ~(ring->irq_enable_mask |
1592                                          GT_PARITY_ERROR(dev)));
1593                 else
1594                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1595                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1596         }
1597         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1598
1599         return true;
1600 }
1601
1602 static void
1603 gen6_ring_put_irq(struct intel_engine_cs *ring)
1604 {
1605         struct drm_device *dev = ring->dev;
1606         struct drm_i915_private *dev_priv = dev->dev_private;
1607
1608         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1609         if (--ring->irq_refcount == 0) {
1610                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1611                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1612                 else
1613                         I915_WRITE_IMR(ring, ~0);
1614                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1615         }
1616         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1617 }
1618
1619 static bool
1620 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1621 {
1622         struct drm_device *dev = ring->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624
1625         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1626                 return false;
1627
1628         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1629         if (ring->irq_refcount++ == 0) {
1630                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1631                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1632         }
1633         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1634
1635         return true;
1636 }
1637
1638 static void
1639 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1640 {
1641         struct drm_device *dev = ring->dev;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643
1644         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1645         if (--ring->irq_refcount == 0) {
1646                 I915_WRITE_IMR(ring, ~0);
1647                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1648         }
1649         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1650 }
1651
1652 static bool
1653 gen8_ring_get_irq(struct intel_engine_cs *ring)
1654 {
1655         struct drm_device *dev = ring->dev;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1659                 return false;
1660
1661         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1662         if (ring->irq_refcount++ == 0) {
1663                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1664                         I915_WRITE_IMR(ring,
1665                                        ~(ring->irq_enable_mask |
1666                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1667                 } else {
1668                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1669                 }
1670                 POSTING_READ(RING_IMR(ring->mmio_base));
1671         }
1672         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1673
1674         return true;
1675 }
1676
1677 static void
1678 gen8_ring_put_irq(struct intel_engine_cs *ring)
1679 {
1680         struct drm_device *dev = ring->dev;
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682
1683         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1684         if (--ring->irq_refcount == 0) {
1685                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1686                         I915_WRITE_IMR(ring,
1687                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1688                 } else {
1689                         I915_WRITE_IMR(ring, ~0);
1690                 }
1691                 POSTING_READ(RING_IMR(ring->mmio_base));
1692         }
1693         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1694 }
1695
1696 static int
1697 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1698                          u64 offset, u32 length,
1699                          unsigned dispatch_flags)
1700 {
1701         int ret;
1702
1703         ret = intel_ring_begin(ring, 2);
1704         if (ret)
1705                 return ret;
1706
1707         intel_ring_emit(ring,
1708                         MI_BATCH_BUFFER_START |
1709                         MI_BATCH_GTT |
1710                         (dispatch_flags & I915_DISPATCH_SECURE ?
1711                          0 : MI_BATCH_NON_SECURE_I965));
1712         intel_ring_emit(ring, offset);
1713         intel_ring_advance(ring);
1714
1715         return 0;
1716 }
1717
1718 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1719 #define I830_BATCH_LIMIT (256*1024)
1720 #define I830_TLB_ENTRIES (2)
1721 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1722 static int
1723 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1724                          u64 offset, u32 len,
1725                          unsigned dispatch_flags)
1726 {
1727         u32 cs_offset = ring->scratch.gtt_offset;
1728         int ret;
1729
1730         ret = intel_ring_begin(ring, 6);
1731         if (ret)
1732                 return ret;
1733
1734         /* Evict the invalid PTE TLBs */
1735         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1736         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1737         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1738         intel_ring_emit(ring, cs_offset);
1739         intel_ring_emit(ring, 0xdeadbeef);
1740         intel_ring_emit(ring, MI_NOOP);
1741         intel_ring_advance(ring);
1742
1743         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1744                 if (len > I830_BATCH_LIMIT)
1745                         return -ENOSPC;
1746
1747                 ret = intel_ring_begin(ring, 6 + 2);
1748                 if (ret)
1749                         return ret;
1750
1751                 /* Blit the batch (which has now all relocs applied) to the
1752                  * stable batch scratch bo area (so that the CS never
1753                  * stumbles over its tlb invalidation bug) ...
1754                  */
1755                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1756                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1757                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1758                 intel_ring_emit(ring, cs_offset);
1759                 intel_ring_emit(ring, 4096);
1760                 intel_ring_emit(ring, offset);
1761
1762                 intel_ring_emit(ring, MI_FLUSH);
1763                 intel_ring_emit(ring, MI_NOOP);
1764                 intel_ring_advance(ring);
1765
1766                 /* ... and execute it. */
1767                 offset = cs_offset;
1768         }
1769
1770         ret = intel_ring_begin(ring, 4);
1771         if (ret)
1772                 return ret;
1773
1774         intel_ring_emit(ring, MI_BATCH_BUFFER);
1775         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1776                                         0 : MI_BATCH_NON_SECURE));
1777         intel_ring_emit(ring, offset + len - 8);
1778         intel_ring_emit(ring, MI_NOOP);
1779         intel_ring_advance(ring);
1780
1781         return 0;
1782 }
1783
1784 static int
1785 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1786                          u64 offset, u32 len,
1787                          unsigned dispatch_flags)
1788 {
1789         int ret;
1790
1791         ret = intel_ring_begin(ring, 2);
1792         if (ret)
1793                 return ret;
1794
1795         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1796         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1797                                         0 : MI_BATCH_NON_SECURE));
1798         intel_ring_advance(ring);
1799
1800         return 0;
1801 }
1802
1803 static void cleanup_status_page(struct intel_engine_cs *ring)
1804 {
1805         struct drm_i915_gem_object *obj;
1806
1807         obj = ring->status_page.obj;
1808         if (obj == NULL)
1809                 return;
1810
1811         kunmap(obj->pages[0]);
1812         i915_gem_object_ggtt_unpin(obj);
1813         drm_gem_object_unreference(&obj->base);
1814         ring->status_page.obj = NULL;
1815 }
1816
1817 static int init_status_page(struct intel_engine_cs *ring)
1818 {
1819         struct drm_i915_gem_object *obj;
1820
1821         if ((obj = ring->status_page.obj) == NULL) {
1822                 unsigned flags;
1823                 int ret;
1824
1825                 obj = i915_gem_alloc_object(ring->dev, 4096);
1826                 if (obj == NULL) {
1827                         DRM_ERROR("Failed to allocate status page\n");
1828                         return -ENOMEM;
1829                 }
1830
1831                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1832                 if (ret)
1833                         goto err_unref;
1834
1835                 flags = 0;
1836                 if (!HAS_LLC(ring->dev))
1837                         /* On g33, we cannot place HWS above 256MiB, so
1838                          * restrict its pinning to the low mappable arena.
1839                          * Though this restriction is not documented for
1840                          * gen4, gen5, or byt, they also behave similarly
1841                          * and hang if the HWS is placed at the top of the
1842                          * GTT. To generalise, it appears that all !llc
1843                          * platforms have issues with us placing the HWS
1844                          * above the mappable region (even though we never
1845                          * actualy map it).
1846                          */
1847                         flags |= PIN_MAPPABLE;
1848                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1849                 if (ret) {
1850 err_unref:
1851                         drm_gem_object_unreference(&obj->base);
1852                         return ret;
1853                 }
1854
1855                 ring->status_page.obj = obj;
1856         }
1857
1858         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1859         ring->status_page.page_addr = kmap(obj->pages[0]);
1860         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1861
1862         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1863                         ring->name, ring->status_page.gfx_addr);
1864
1865         return 0;
1866 }
1867
1868 static int init_phys_status_page(struct intel_engine_cs *ring)
1869 {
1870         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1871
1872         if (!dev_priv->status_page_dmah) {
1873                 dev_priv->status_page_dmah =
1874                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1875                 if (!dev_priv->status_page_dmah)
1876                         return -ENOMEM;
1877         }
1878
1879         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1880         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1881
1882         return 0;
1883 }
1884
1885 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1886 {
1887         iounmap(ringbuf->virtual_start, ringbuf->size);
1888         ringbuf->virtual_start = NULL;
1889         i915_gem_object_ggtt_unpin(ringbuf->obj);
1890 }
1891
1892 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1893                                      struct intel_ringbuffer *ringbuf)
1894 {
1895         struct drm_i915_private *dev_priv = to_i915(dev);
1896         struct drm_i915_gem_object *obj = ringbuf->obj;
1897         int ret;
1898
1899         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1900         if (ret)
1901                 return ret;
1902
1903         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1904         if (ret) {
1905                 i915_gem_object_ggtt_unpin(obj);
1906                 return ret;
1907         }
1908
1909         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1910                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1911         if (ringbuf->virtual_start == NULL) {
1912                 i915_gem_object_ggtt_unpin(obj);
1913                 return -EINVAL;
1914         }
1915
1916         return 0;
1917 }
1918
1919 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1920 {
1921         drm_gem_object_unreference(&ringbuf->obj->base);
1922         ringbuf->obj = NULL;
1923 }
1924
1925 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1926                                struct intel_ringbuffer *ringbuf)
1927 {
1928         struct drm_i915_gem_object *obj;
1929
1930         obj = NULL;
1931         if (!HAS_LLC(dev))
1932                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1933         if (obj == NULL)
1934                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1935         if (obj == NULL)
1936                 return -ENOMEM;
1937
1938         /* mark ring buffers as read-only from GPU side by default */
1939         obj->gt_ro = 1;
1940
1941         ringbuf->obj = obj;
1942
1943         return 0;
1944 }
1945
1946 static int intel_init_ring_buffer(struct drm_device *dev,
1947                                   struct intel_engine_cs *ring)
1948 {
1949         struct intel_ringbuffer *ringbuf;
1950         int ret;
1951
1952         WARN_ON(ring->buffer);
1953
1954         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1955         if (!ringbuf)
1956                 return -ENOMEM;
1957         ring->buffer = ringbuf;
1958
1959         ring->dev = dev;
1960         INIT_LIST_HEAD(&ring->active_list);
1961         INIT_LIST_HEAD(&ring->request_list);
1962         INIT_LIST_HEAD(&ring->execlist_queue);
1963         ringbuf->size = 32 * PAGE_SIZE;
1964         ringbuf->ring = ring;
1965         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1966
1967         init_waitqueue_head(&ring->irq_queue);
1968
1969         if (I915_NEED_GFX_HWS(dev)) {
1970                 ret = init_status_page(ring);
1971                 if (ret)
1972                         goto error;
1973         } else {
1974                 BUG_ON(ring->id != RCS);
1975                 ret = init_phys_status_page(ring);
1976                 if (ret)
1977                         goto error;
1978         }
1979
1980         WARN_ON(ringbuf->obj);
1981
1982         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1983         if (ret) {
1984                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1985                                 ring->name, ret);
1986                 goto error;
1987         }
1988
1989         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1990         if (ret) {
1991                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1992                                 ring->name, ret);
1993                 intel_destroy_ringbuffer_obj(ringbuf);
1994                 goto error;
1995         }
1996
1997         /* Workaround an erratum on the i830 which causes a hang if
1998          * the TAIL pointer points to within the last 2 cachelines
1999          * of the buffer.
2000          */
2001         ringbuf->effective_size = ringbuf->size;
2002         if (IS_I830(dev) || IS_845G(dev))
2003                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2004
2005         ret = i915_cmd_parser_init_ring(ring);
2006         if (ret)
2007                 goto error;
2008
2009         return 0;
2010
2011 error:
2012         kfree(ringbuf);
2013         ring->buffer = NULL;
2014         return ret;
2015 }
2016
2017 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2018 {
2019         struct drm_i915_private *dev_priv;
2020         struct intel_ringbuffer *ringbuf;
2021
2022         if (!intel_ring_initialized(ring))
2023                 return;
2024
2025         dev_priv = to_i915(ring->dev);
2026         ringbuf = ring->buffer;
2027
2028         intel_stop_ring_buffer(ring);
2029         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2030
2031         intel_unpin_ringbuffer_obj(ringbuf);
2032         intel_destroy_ringbuffer_obj(ringbuf);
2033         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2034
2035         if (ring->cleanup)
2036                 ring->cleanup(ring);
2037
2038         cleanup_status_page(ring);
2039
2040         i915_cmd_parser_fini_ring(ring);
2041
2042         kfree(ringbuf);
2043         ring->buffer = NULL;
2044 }
2045
2046 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
2047 {
2048         struct intel_ringbuffer *ringbuf = ring->buffer;
2049         struct drm_i915_gem_request *request;
2050         int ret;
2051
2052         if (intel_ring_space(ringbuf) >= n)
2053                 return 0;
2054
2055         list_for_each_entry(request, &ring->request_list, list) {
2056                 if (__intel_ring_space(request->postfix, ringbuf->tail,
2057                                        ringbuf->size) >= n) {
2058                         break;
2059                 }
2060         }
2061
2062         if (&request->list == &ring->request_list)
2063                 return -ENOSPC;
2064
2065         ret = i915_wait_request(request);
2066         if (ret)
2067                 return ret;
2068
2069         i915_gem_retire_requests_ring(ring);
2070
2071         return 0;
2072 }
2073
2074 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2075 {
2076         struct drm_device *dev = ring->dev;
2077         struct drm_i915_private *dev_priv = dev->dev_private;
2078         struct intel_ringbuffer *ringbuf = ring->buffer;
2079         unsigned long end;
2080         int ret;
2081
2082         ret = intel_ring_wait_request(ring, n);
2083         if (ret != -ENOSPC)
2084                 return ret;
2085
2086         /* force the tail write in case we have been skipping them */
2087         __intel_ring_advance(ring);
2088
2089         /* With GEM the hangcheck timer should kick us out of the loop,
2090          * leaving it early runs the risk of corrupting GEM state (due
2091          * to running on almost untested codepaths). But on resume
2092          * timers don't work yet, so prevent a complete hang in that
2093          * case by choosing an insanely large timeout. */
2094         end = jiffies + 60 * HZ;
2095
2096         ret = 0;
2097         trace_i915_ring_wait_begin(ring);
2098         do {
2099                 if (intel_ring_space(ringbuf) >= n)
2100                         break;
2101                 ringbuf->head = I915_READ_HEAD(ring);
2102                 if (intel_ring_space(ringbuf) >= n)
2103                         break;
2104
2105                 msleep(1);
2106
2107                 if (dev_priv->mm.interruptible && signal_pending(curthread->td_lwp)) {
2108                         ret = -ERESTARTSYS;
2109                         break;
2110                 }
2111
2112                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2113                                            dev_priv->mm.interruptible);
2114                 if (ret)
2115                         break;
2116
2117                 if (time_after(jiffies, end)) {
2118                         ret = -EBUSY;
2119                         break;
2120                 }
2121         } while (1);
2122         trace_i915_ring_wait_end(ring);
2123         return ret;
2124 }
2125
2126 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2127 {
2128         uint32_t __iomem *virt;
2129         struct intel_ringbuffer *ringbuf = ring->buffer;
2130         int rem = ringbuf->size - ringbuf->tail;
2131
2132         if (ringbuf->space < rem) {
2133                 int ret = ring_wait_for_space(ring, rem);
2134                 if (ret)
2135                         return ret;
2136         }
2137
2138         virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail);
2139         rem /= 4;
2140         while (rem--)
2141                 iowrite32(MI_NOOP, virt++);
2142
2143         ringbuf->tail = 0;
2144         intel_ring_update_space(ringbuf);
2145
2146         return 0;
2147 }
2148
2149 int intel_ring_idle(struct intel_engine_cs *ring)
2150 {
2151         struct drm_i915_gem_request *req;
2152         int ret;
2153
2154         /* We need to add any requests required to flush the objects and ring */
2155         if (ring->outstanding_lazy_request) {
2156                 ret = i915_add_request(ring);
2157                 if (ret)
2158                         return ret;
2159         }
2160
2161         /* Wait upon the last request to be completed */
2162         if (list_empty(&ring->request_list))
2163                 return 0;
2164
2165         req = list_entry(ring->request_list.prev,
2166                            struct drm_i915_gem_request,
2167                            list);
2168
2169         return i915_wait_request(req);
2170 }
2171
2172 static int
2173 intel_ring_alloc_request(struct intel_engine_cs *ring)
2174 {
2175         int ret;
2176         struct drm_i915_gem_request *request;
2177         struct drm_i915_private *dev_private = ring->dev->dev_private;
2178
2179         if (ring->outstanding_lazy_request)
2180                 return 0;
2181
2182         request = kzalloc(sizeof(*request), GFP_KERNEL);
2183         if (request == NULL)
2184                 return -ENOMEM;
2185
2186         kref_init(&request->ref);
2187         request->ring = ring;
2188         request->ringbuf = ring->buffer;
2189         request->uniq = dev_private->request_uniq++;
2190
2191         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2192         if (ret) {
2193                 kfree(request);
2194                 return ret;
2195         }
2196
2197         ring->outstanding_lazy_request = request;
2198         return 0;
2199 }
2200
2201 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2202                                 int bytes)
2203 {
2204         struct intel_ringbuffer *ringbuf = ring->buffer;
2205         int ret;
2206
2207         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2208                 ret = intel_wrap_ring_buffer(ring);
2209                 if (unlikely(ret))
2210                         return ret;
2211         }
2212
2213         if (unlikely(ringbuf->space < bytes)) {
2214                 ret = ring_wait_for_space(ring, bytes);
2215                 if (unlikely(ret))
2216                         return ret;
2217         }
2218
2219         return 0;
2220 }
2221
2222 int intel_ring_begin(struct intel_engine_cs *ring,
2223                      int num_dwords)
2224 {
2225         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2226         int ret;
2227
2228         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2229                                    dev_priv->mm.interruptible);
2230         if (ret)
2231                 return ret;
2232
2233         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2234         if (ret)
2235                 return ret;
2236
2237         /* Preallocate the olr before touching the ring */
2238         ret = intel_ring_alloc_request(ring);
2239         if (ret)
2240                 return ret;
2241
2242         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2243         return 0;
2244 }
2245
2246 /* Align the ring tail to a cacheline boundary */
2247 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2248 {
2249         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2250         int ret;
2251
2252         if (num_dwords == 0)
2253                 return 0;
2254
2255         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2256         ret = intel_ring_begin(ring, num_dwords);
2257         if (ret)
2258                 return ret;
2259
2260         while (num_dwords--)
2261                 intel_ring_emit(ring, MI_NOOP);
2262
2263         intel_ring_advance(ring);
2264
2265         return 0;
2266 }
2267
2268 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2269 {
2270         struct drm_device *dev = ring->dev;
2271         struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273         BUG_ON(ring->outstanding_lazy_request);
2274
2275         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2276                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2277                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2278                 if (HAS_VEBOX(dev))
2279                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2280         }
2281
2282         ring->set_seqno(ring, seqno);
2283         ring->hangcheck.seqno = seqno;
2284 }
2285
2286 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2287                                      u32 value)
2288 {
2289         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2290
2291        /* Every tail move must follow the sequence below */
2292
2293         /* Disable notification that the ring is IDLE. The GT
2294          * will then assume that it is busy and bring it out of rc6.
2295          */
2296         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2297                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2298
2299         /* Clear the context id. Here be magic! */
2300         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2301
2302         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2303         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2304                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2305                      50))
2306                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2307
2308         /* Now that the ring is fully powered up, update the tail */
2309         I915_WRITE_TAIL(ring, value);
2310         POSTING_READ(RING_TAIL(ring->mmio_base));
2311
2312         /* Let the ring send IDLE messages to the GT again,
2313          * and so let it sleep to conserve power when idle.
2314          */
2315         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2316                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2317 }
2318
2319 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2320                                u32 invalidate, u32 flush)
2321 {
2322         uint32_t cmd;
2323         int ret;
2324
2325         ret = intel_ring_begin(ring, 4);
2326         if (ret)
2327                 return ret;
2328
2329         cmd = MI_FLUSH_DW;
2330         if (INTEL_INFO(ring->dev)->gen >= 8)
2331                 cmd += 1;
2332
2333         /* We always require a command barrier so that subsequent
2334          * commands, such as breadcrumb interrupts, are strictly ordered
2335          * wrt the contents of the write cache being flushed to memory
2336          * (and thus being coherent from the CPU).
2337          */
2338         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2339
2340         /*
2341          * Bspec vol 1c.5 - video engine command streamer:
2342          * "If ENABLED, all TLBs will be invalidated once the flush
2343          * operation is complete. This bit is only valid when the
2344          * Post-Sync Operation field is a value of 1h or 3h."
2345          */
2346         if (invalidate & I915_GEM_GPU_DOMAINS)
2347                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2348
2349         intel_ring_emit(ring, cmd);
2350         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2351         if (INTEL_INFO(ring->dev)->gen >= 8) {
2352                 intel_ring_emit(ring, 0); /* upper addr */
2353                 intel_ring_emit(ring, 0); /* value */
2354         } else  {
2355                 intel_ring_emit(ring, 0);
2356                 intel_ring_emit(ring, MI_NOOP);
2357         }
2358         intel_ring_advance(ring);
2359         return 0;
2360 }
2361
2362 static int
2363 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2364                               u64 offset, u32 len,
2365                               unsigned dispatch_flags)
2366 {
2367         bool ppgtt = USES_PPGTT(ring->dev) &&
2368                         !(dispatch_flags & I915_DISPATCH_SECURE);
2369         int ret;
2370
2371         ret = intel_ring_begin(ring, 4);
2372         if (ret)
2373                 return ret;
2374
2375         /* FIXME(BDW): Address space and security selectors. */
2376         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2377         intel_ring_emit(ring, lower_32_bits(offset));
2378         intel_ring_emit(ring, upper_32_bits(offset));
2379         intel_ring_emit(ring, MI_NOOP);
2380         intel_ring_advance(ring);
2381
2382         return 0;
2383 }
2384
2385 static int
2386 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2387                              u64 offset, u32 len,
2388                              unsigned dispatch_flags)
2389 {
2390         int ret;
2391
2392         ret = intel_ring_begin(ring, 2);
2393         if (ret)
2394                 return ret;
2395
2396         intel_ring_emit(ring,
2397                         MI_BATCH_BUFFER_START |
2398                         (dispatch_flags & I915_DISPATCH_SECURE ?
2399                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2400         /* bit0-7 is the length on GEN6+ */
2401         intel_ring_emit(ring, offset);
2402         intel_ring_advance(ring);
2403
2404         return 0;
2405 }
2406
2407 static int
2408 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2409                               u64 offset, u32 len,
2410                               unsigned dispatch_flags)
2411 {
2412         int ret;
2413
2414         ret = intel_ring_begin(ring, 2);
2415         if (ret)
2416                 return ret;
2417
2418         intel_ring_emit(ring,
2419                         MI_BATCH_BUFFER_START |
2420                         (dispatch_flags & I915_DISPATCH_SECURE ?
2421                          0 : MI_BATCH_NON_SECURE_I965));
2422         /* bit0-7 is the length on GEN6+ */
2423         intel_ring_emit(ring, offset);
2424         intel_ring_advance(ring);
2425
2426         return 0;
2427 }
2428
2429 /* Blitter support (SandyBridge+) */
2430
2431 static int gen6_ring_flush(struct intel_engine_cs *ring,
2432                            u32 invalidate, u32 flush)
2433 {
2434         struct drm_device *dev = ring->dev;
2435         uint32_t cmd;
2436         int ret;
2437
2438         ret = intel_ring_begin(ring, 4);
2439         if (ret)
2440                 return ret;
2441
2442         cmd = MI_FLUSH_DW;
2443         if (INTEL_INFO(dev)->gen >= 8)
2444                 cmd += 1;
2445
2446         /* We always require a command barrier so that subsequent
2447          * commands, such as breadcrumb interrupts, are strictly ordered
2448          * wrt the contents of the write cache being flushed to memory
2449          * (and thus being coherent from the CPU).
2450          */
2451         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2452
2453         /*
2454          * Bspec vol 1c.3 - blitter engine command streamer:
2455          * "If ENABLED, all TLBs will be invalidated once the flush
2456          * operation is complete. This bit is only valid when the
2457          * Post-Sync Operation field is a value of 1h or 3h."
2458          */
2459         if (invalidate & I915_GEM_DOMAIN_RENDER)
2460                 cmd |= MI_INVALIDATE_TLB;
2461         intel_ring_emit(ring, cmd);
2462         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2463         if (INTEL_INFO(dev)->gen >= 8) {
2464                 intel_ring_emit(ring, 0); /* upper addr */
2465                 intel_ring_emit(ring, 0); /* value */
2466         } else  {
2467                 intel_ring_emit(ring, 0);
2468                 intel_ring_emit(ring, MI_NOOP);
2469         }
2470         intel_ring_advance(ring);
2471
2472         return 0;
2473 }
2474
2475 int intel_init_render_ring_buffer(struct drm_device *dev)
2476 {
2477         struct drm_i915_private *dev_priv = dev->dev_private;
2478         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2479         struct drm_i915_gem_object *obj;
2480         int ret;
2481
2482         ring->name = "render ring";
2483         ring->id = RCS;
2484         ring->mmio_base = RENDER_RING_BASE;
2485
2486         if (INTEL_INFO(dev)->gen >= 8) {
2487                 if (i915_semaphore_is_enabled(dev)) {
2488                         obj = i915_gem_alloc_object(dev, 4096);
2489                         if (obj == NULL) {
2490                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2491                                 i915.semaphores = 0;
2492                         } else {
2493                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2494                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2495                                 if (ret != 0) {
2496                                         drm_gem_object_unreference(&obj->base);
2497                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2498                                         i915.semaphores = 0;
2499                                 } else
2500                                         dev_priv->semaphore_obj = obj;
2501                         }
2502                 }
2503
2504                 ring->init_context = intel_rcs_ctx_init;
2505                 ring->add_request = gen6_add_request;
2506                 ring->flush = gen8_render_ring_flush;
2507                 ring->irq_get = gen8_ring_get_irq;
2508                 ring->irq_put = gen8_ring_put_irq;
2509                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2510                 ring->get_seqno = gen6_ring_get_seqno;
2511                 ring->set_seqno = ring_set_seqno;
2512                 if (i915_semaphore_is_enabled(dev)) {
2513                         WARN_ON(!dev_priv->semaphore_obj);
2514                         ring->semaphore.sync_to = gen8_ring_sync;
2515                         ring->semaphore.signal = gen8_rcs_signal;
2516                         GEN8_RING_SEMAPHORE_INIT;
2517                 }
2518         } else if (INTEL_INFO(dev)->gen >= 6) {
2519                 ring->add_request = gen6_add_request;
2520                 ring->flush = gen7_render_ring_flush;
2521                 if (INTEL_INFO(dev)->gen == 6)
2522                         ring->flush = gen6_render_ring_flush;
2523                 ring->irq_get = gen6_ring_get_irq;
2524                 ring->irq_put = gen6_ring_put_irq;
2525                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2526                 ring->get_seqno = gen6_ring_get_seqno;
2527                 ring->set_seqno = ring_set_seqno;
2528                 if (i915_semaphore_is_enabled(dev)) {
2529                         ring->semaphore.sync_to = gen6_ring_sync;
2530                         ring->semaphore.signal = gen6_signal;
2531                         /*
2532                          * The current semaphore is only applied on pre-gen8
2533                          * platform.  And there is no VCS2 ring on the pre-gen8
2534                          * platform. So the semaphore between RCS and VCS2 is
2535                          * initialized as INVALID.  Gen8 will initialize the
2536                          * sema between VCS2 and RCS later.
2537                          */
2538                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2539                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2540                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2541                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2542                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2543                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2544                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2545                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2546                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2547                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2548                 }
2549         } else if (IS_GEN5(dev)) {
2550                 ring->add_request = pc_render_add_request;
2551                 ring->flush = gen4_render_ring_flush;
2552                 ring->get_seqno = pc_render_get_seqno;
2553                 ring->set_seqno = pc_render_set_seqno;
2554                 ring->irq_get = gen5_ring_get_irq;
2555                 ring->irq_put = gen5_ring_put_irq;
2556                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2557                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2558         } else {
2559                 ring->add_request = i9xx_add_request;
2560                 if (INTEL_INFO(dev)->gen < 4)
2561                         ring->flush = gen2_render_ring_flush;
2562                 else
2563                         ring->flush = gen4_render_ring_flush;
2564                 ring->get_seqno = ring_get_seqno;
2565                 ring->set_seqno = ring_set_seqno;
2566                 if (IS_GEN2(dev)) {
2567                         ring->irq_get = i8xx_ring_get_irq;
2568                         ring->irq_put = i8xx_ring_put_irq;
2569                 } else {
2570                         ring->irq_get = i9xx_ring_get_irq;
2571                         ring->irq_put = i9xx_ring_put_irq;
2572                 }
2573                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2574         }
2575         ring->write_tail = ring_write_tail;
2576
2577         if (IS_HASWELL(dev))
2578                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2579         else if (IS_GEN8(dev))
2580                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2581         else if (INTEL_INFO(dev)->gen >= 6)
2582                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2583         else if (INTEL_INFO(dev)->gen >= 4)
2584                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2585         else if (IS_I830(dev) || IS_845G(dev))
2586                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2587         else
2588                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2589         ring->init_hw = init_render_ring;
2590         ring->cleanup = render_ring_cleanup;
2591
2592         /* Workaround batchbuffer to combat CS tlb bug. */
2593         if (HAS_BROKEN_CS_TLB(dev)) {
2594                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2595                 if (obj == NULL) {
2596                         DRM_ERROR("Failed to allocate batch bo\n");
2597                         return -ENOMEM;
2598                 }
2599
2600                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2601                 if (ret != 0) {
2602                         drm_gem_object_unreference(&obj->base);
2603                         DRM_ERROR("Failed to ping batch bo\n");
2604                         return ret;
2605                 }
2606
2607                 ring->scratch.obj = obj;
2608                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2609         }
2610
2611         ret = intel_init_ring_buffer(dev, ring);
2612         if (ret)
2613                 return ret;
2614
2615         if (INTEL_INFO(dev)->gen >= 5) {
2616                 ret = intel_init_pipe_control(ring);
2617                 if (ret)
2618                         return ret;
2619         }
2620
2621         return 0;
2622 }
2623
2624 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2625 {
2626         struct drm_i915_private *dev_priv = dev->dev_private;
2627         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2628
2629         ring->name = "bsd ring";
2630         ring->id = VCS;
2631
2632         ring->write_tail = ring_write_tail;
2633         if (INTEL_INFO(dev)->gen >= 6) {
2634                 ring->mmio_base = GEN6_BSD_RING_BASE;
2635                 /* gen6 bsd needs a special wa for tail updates */
2636                 if (IS_GEN6(dev))
2637                         ring->write_tail = gen6_bsd_ring_write_tail;
2638                 ring->flush = gen6_bsd_ring_flush;
2639                 ring->add_request = gen6_add_request;
2640                 ring->get_seqno = gen6_ring_get_seqno;
2641                 ring->set_seqno = ring_set_seqno;
2642                 if (INTEL_INFO(dev)->gen >= 8) {
2643                         ring->irq_enable_mask =
2644                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2645                         ring->irq_get = gen8_ring_get_irq;
2646                         ring->irq_put = gen8_ring_put_irq;
2647                         ring->dispatch_execbuffer =
2648                                 gen8_ring_dispatch_execbuffer;
2649                         if (i915_semaphore_is_enabled(dev)) {
2650                                 ring->semaphore.sync_to = gen8_ring_sync;
2651                                 ring->semaphore.signal = gen8_xcs_signal;
2652                                 GEN8_RING_SEMAPHORE_INIT;
2653                         }
2654                 } else {
2655                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2656                         ring->irq_get = gen6_ring_get_irq;
2657                         ring->irq_put = gen6_ring_put_irq;
2658                         ring->dispatch_execbuffer =
2659                                 gen6_ring_dispatch_execbuffer;
2660                         if (i915_semaphore_is_enabled(dev)) {
2661                                 ring->semaphore.sync_to = gen6_ring_sync;
2662                                 ring->semaphore.signal = gen6_signal;
2663                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2664                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2665                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2666                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2667                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2668                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2669                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2670                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2671                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2672                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2673                         }
2674                 }
2675         } else {
2676                 ring->mmio_base = BSD_RING_BASE;
2677                 ring->flush = bsd_ring_flush;
2678                 ring->add_request = i9xx_add_request;
2679                 ring->get_seqno = ring_get_seqno;
2680                 ring->set_seqno = ring_set_seqno;
2681                 if (IS_GEN5(dev)) {
2682                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2683                         ring->irq_get = gen5_ring_get_irq;
2684                         ring->irq_put = gen5_ring_put_irq;
2685                 } else {
2686                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2687                         ring->irq_get = i9xx_ring_get_irq;
2688                         ring->irq_put = i9xx_ring_put_irq;
2689                 }
2690                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2691         }
2692         ring->init_hw = init_ring_common;
2693
2694         return intel_init_ring_buffer(dev, ring);
2695 }
2696
2697 /**
2698  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2699  */
2700 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2701 {
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2704
2705         ring->name = "bsd2 ring";
2706         ring->id = VCS2;
2707
2708         ring->write_tail = ring_write_tail;
2709         ring->mmio_base = GEN8_BSD2_RING_BASE;
2710         ring->flush = gen6_bsd_ring_flush;
2711         ring->add_request = gen6_add_request;
2712         ring->get_seqno = gen6_ring_get_seqno;
2713         ring->set_seqno = ring_set_seqno;
2714         ring->irq_enable_mask =
2715                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2716         ring->irq_get = gen8_ring_get_irq;
2717         ring->irq_put = gen8_ring_put_irq;
2718         ring->dispatch_execbuffer =
2719                         gen8_ring_dispatch_execbuffer;
2720         if (i915_semaphore_is_enabled(dev)) {
2721                 ring->semaphore.sync_to = gen8_ring_sync;
2722                 ring->semaphore.signal = gen8_xcs_signal;
2723                 GEN8_RING_SEMAPHORE_INIT;
2724         }
2725         ring->init_hw = init_ring_common;
2726
2727         return intel_init_ring_buffer(dev, ring);
2728 }
2729
2730 int intel_init_blt_ring_buffer(struct drm_device *dev)
2731 {
2732         struct drm_i915_private *dev_priv = dev->dev_private;
2733         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2734
2735         ring->name = "blitter ring";
2736         ring->id = BCS;
2737
2738         ring->mmio_base = BLT_RING_BASE;
2739         ring->write_tail = ring_write_tail;
2740         ring->flush = gen6_ring_flush;
2741         ring->add_request = gen6_add_request;
2742         ring->get_seqno = gen6_ring_get_seqno;
2743         ring->set_seqno = ring_set_seqno;
2744         if (INTEL_INFO(dev)->gen >= 8) {
2745                 ring->irq_enable_mask =
2746                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2747                 ring->irq_get = gen8_ring_get_irq;
2748                 ring->irq_put = gen8_ring_put_irq;
2749                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2750                 if (i915_semaphore_is_enabled(dev)) {
2751                         ring->semaphore.sync_to = gen8_ring_sync;
2752                         ring->semaphore.signal = gen8_xcs_signal;
2753                         GEN8_RING_SEMAPHORE_INIT;
2754                 }
2755         } else {
2756                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2757                 ring->irq_get = gen6_ring_get_irq;
2758                 ring->irq_put = gen6_ring_put_irq;
2759                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2760                 if (i915_semaphore_is_enabled(dev)) {
2761                         ring->semaphore.signal = gen6_signal;
2762                         ring->semaphore.sync_to = gen6_ring_sync;
2763                         /*
2764                          * The current semaphore is only applied on pre-gen8
2765                          * platform.  And there is no VCS2 ring on the pre-gen8
2766                          * platform. So the semaphore between BCS and VCS2 is
2767                          * initialized as INVALID.  Gen8 will initialize the
2768                          * sema between BCS and VCS2 later.
2769                          */
2770                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2771                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2772                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2773                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2774                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2775                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2776                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2777                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2778                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2779                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2780                 }
2781         }
2782         ring->init_hw = init_ring_common;
2783
2784         return intel_init_ring_buffer(dev, ring);
2785 }
2786
2787 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2788 {
2789         struct drm_i915_private *dev_priv = dev->dev_private;
2790         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2791
2792         ring->name = "video enhancement ring";
2793         ring->id = VECS;
2794
2795         ring->mmio_base = VEBOX_RING_BASE;
2796         ring->write_tail = ring_write_tail;
2797         ring->flush = gen6_ring_flush;
2798         ring->add_request = gen6_add_request;
2799         ring->get_seqno = gen6_ring_get_seqno;
2800         ring->set_seqno = ring_set_seqno;
2801
2802         if (INTEL_INFO(dev)->gen >= 8) {
2803                 ring->irq_enable_mask =
2804                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2805                 ring->irq_get = gen8_ring_get_irq;
2806                 ring->irq_put = gen8_ring_put_irq;
2807                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2808                 if (i915_semaphore_is_enabled(dev)) {
2809                         ring->semaphore.sync_to = gen8_ring_sync;
2810                         ring->semaphore.signal = gen8_xcs_signal;
2811                         GEN8_RING_SEMAPHORE_INIT;
2812                 }
2813         } else {
2814                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2815                 ring->irq_get = hsw_vebox_get_irq;
2816                 ring->irq_put = hsw_vebox_put_irq;
2817                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2818                 if (i915_semaphore_is_enabled(dev)) {
2819                         ring->semaphore.sync_to = gen6_ring_sync;
2820                         ring->semaphore.signal = gen6_signal;
2821                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2822                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2823                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2824                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2825                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2826                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2827                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2828                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2829                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2830                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2831                 }
2832         }
2833         ring->init_hw = init_ring_common;
2834
2835         return intel_init_ring_buffer(dev, ring);
2836 }
2837
2838 int
2839 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2840 {
2841         int ret;
2842
2843         if (!ring->gpu_caches_dirty)
2844                 return 0;
2845
2846         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2847         if (ret)
2848                 return ret;
2849
2850         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2851
2852         ring->gpu_caches_dirty = false;
2853         return 0;
2854 }
2855
2856 int
2857 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2858 {
2859         uint32_t flush_domains;
2860         int ret;
2861
2862         flush_domains = 0;
2863         if (ring->gpu_caches_dirty)
2864                 flush_domains = I915_GEM_GPU_DOMAINS;
2865
2866         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2867         if (ret)
2868                 return ret;
2869
2870         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2871
2872         ring->gpu_caches_dirty = false;
2873         return 0;
2874 }
2875
2876 void
2877 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2878 {
2879         int ret;
2880
2881         if (!intel_ring_initialized(ring))
2882                 return;
2883
2884         ret = intel_ring_idle(ring);
2885         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2886                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2887                           ring->name, ret);
2888
2889         stop_ring(ring);
2890 }