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34 .Nd Architecture-specific details
36 Differences between CPU architectures and platforms supported by
39 This document is a quick reference of key ABI details of
42 For full details consult the processor-specific ABI supplement
45 If not explicitly mentioned, sizes are in bytes.
46 The architecture details in this document apply to
48 and later, unless otherwise noted.
51 uses a flat address space.
57 and pointers all have the same representation.
59 In order to maximize compatibility with future pointer integrity mechanisms,
60 manipulations of pointers as integers should be performed via
71 On some architectures, e.g.,
76 the kernel uses a separate address space.
77 On other architectures, kernel and a user mode process share a
79 The kernel is located at the highest addresses.
81 On each architecture, the main user mode thread's stack starts near
82 the highest user address and grows down.
85 architecture support varies by release.
86 This table shows the first
88 release to support each architecture, and, for discontinued
89 architectures, the final release.
91 .Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release"
92 .It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
93 .It alpha Ta 3.2 Ta 6.4
99 .It ia64 Ta 5.0 Ta 10.x
108 .It mips64elhf Ta 12.0
110 .It pc98 Ta 2.2 Ta 11.x
112 .It powerpcspe Ta 12.0
115 .It riscv64sf Ta 12.0
121 architectures use some variant of the ELF (see
123 .Sy Application Binary Interface
124 (ABI) for the machine processor.
125 All supported ABIs can be divided into two groups:
126 .Bl -tag -width "Dv ILP32"
131 types machine representations all have 4-byte size.
134 type machine representation uses 4 bytes,
143 symbol when compiling for an
147 Some machines support more that one
150 Typically these are 64-bit machines, where the
153 execution environment is accompanied by the
156 environment, which was historical 32-bit predecessor for 64-bit evolution.
158 .Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart"
159 .It Sy LP64 Ta Sy ILP32 counterpart
160 .It Dv amd64 Ta Dv i386
161 .It Dv powerpc64 Ta Dv powerpc
162 .It Dv mips64* Ta Dv mips*
165 currently does not support execution of
167 binaries, even if the CPU implements
171 On all supported architectures:
172 .Bl -column -offset -indent "long long" "Size"
173 .It Sy Type Ta Sy Size
176 .It long Ta sizeof(void*)
181 Integers are represented in two's complement.
182 Alignment of integer and pointer types is natural, that is,
183 the address of the variable must be congruent to zero modulo the type size.
184 Most ILP32 ABIs, except
186 require only 4-byte alignment for 64-bit integers.
188 Machine-dependent type sizes:
189 .Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t"
190 .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
191 .It amd64 Ta 8 Ta 16 Ta 8
192 .It arm Ta 4 Ta 8 Ta 8
193 .It armeb Ta 4 Ta 8 Ta 8
194 .It armv6 Ta 4 Ta 8 Ta 8
195 .It arm64 Ta 8 Ta 16 Ta 8
196 .It i386 Ta 4 Ta 12 Ta 4
197 .It mips Ta 4 Ta 8 Ta 8
198 .It mipsel Ta 4 Ta 8 Ta 8
199 .It mipselhf Ta 4 Ta 8 Ta 8
200 .It mipshf Ta 4 Ta 8 Ta 8
201 .It mipsn32 Ta 4 Ta 8 Ta 8
202 .It mips64 Ta 8 Ta 8 Ta 8
203 .It mips64el Ta 8 Ta 8 Ta 8
204 .It mips64elhf Ta 8 Ta 8 Ta 8
205 .It mips64hf Ta 8 Ta 8 Ta 8
206 .It powerpc Ta 4 Ta 8 Ta 8
207 .It powerpcspe Ta 4 Ta 8 Ta 8
208 .It powerpc64 Ta 8 Ta 8 Ta 8
209 .It riscv64 Ta 8 Ta 16 Ta 8
210 .It riscv64sf Ta 8 Ta 16 Ta 8
211 .It sparc64 Ta 8 Ta 16 Ta 8
215 is 8 bytes on all supported architectures except i386.
216 .Ss Endianness and Char Signedness
217 .Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness"
218 .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
219 .It amd64 Ta little Ta signed
220 .It arm Ta little Ta unsigned
221 .It armeb Ta big Ta unsigned
222 .It armv6 Ta little Ta unsigned
223 .It arm64 Ta little Ta unsigned
224 .It i386 Ta little Ta signed
225 .It mips Ta big Ta signed
226 .It mipsel Ta little Ta signed
227 .It mipselhf Ta little Ta signed
228 .It mipshf Ta big Ta signed
229 .It mipsn32 Ta big Ta signed
230 .It mips64 Ta big Ta signed
231 .It mips64el Ta little Ta signed
232 .It mips64elhf Ta little Ta signed
233 .It mips64hf Ta big Ta signed
234 .It powerpc Ta big Ta unsigned
235 .It powerpcspe Ta big Ta unsigned
236 .It powerpc64 Ta big Ta unsigned
237 .It riscv64 Ta little Ta signed
238 .It riscv64sf Ta little Ta signed
239 .It sparc64 Ta big Ta signed
242 .Bl -column -offset indent "Sy Architecture" "Sy Page Sizes"
243 .It Sy Architecture Ta Sy Page Sizes
244 .It amd64 Ta 4K, 2M, 1G
248 .It arm64 Ta 4K, 2M, 1G
249 .It i386 Ta 4K, 2M (PAE), 4M
267 .Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double"
268 .It Sy Architecture Ta Sy float, double Ta Sy long double
269 .It amd64 Ta hard Ta hard, 80 bit
270 .It arm Ta soft Ta soft, double precision
271 .It armeb Ta soft Ta soft, double precision
272 .It armv6 Ta hard(1) Ta hard, double precision
273 .It arm64 Ta hard Ta soft, quad precision
274 .It i386 Ta hard Ta hard, 80 bit
275 .It mips Ta soft Ta identical to double
276 .It mipsel Ta soft Ta identical to double
277 .It mipselhf Ta hard Ta identical to double
278 .It mipshf Ta hard Ta identical to double
279 .It mipsn32 Ta soft Ta identical to double
280 .It mips64 Ta soft Ta identical to double
281 .It mips64el Ta soft Ta identical to double
282 .It mips64elhf Ta hard Ta identical to double
283 .It mips64hf Ta hard Ta identical to double
284 .It powerpc Ta hard Ta hard, double precision
285 .It powerpcspe Ta hard Ta hard, double precision
286 .It powerpc64 Ta hard Ta hard, double precision
287 .It riscv64 Ta hard Ta hard, double precision
288 .It riscv64sf Ta soft Ta soft, double precision
289 .It sparc64 Ta hard Ta hard, quad precision
294 armv6 used the softfp ABI even though it supported only processors
295 with a floating point unit.
296 .Ss Predefined Macros
297 The compiler provides a number of predefined macros.
298 Some of these provide architecture-specific details and are explained below.
299 Other macros, including those required by the language standard, are not
302 The full set of predefined macros can be obtained with this command:
303 .Bd -literal -offset indent
304 cc -x c -dM -E /dev/null
307 Common type size and endianness macros:
308 .Bl -column -offset indent "BYTE_ORDER" "Sy Meaning"
309 .It Sy Macro Ta Sy Meaning
310 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
311 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
312 .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
318 Architecture-specific macros:
319 .Bl -column -offset indent "Sy Architecture" "Sy Predefined macros"
320 .It Sy Architecture Ta Sy Predefined macros
321 .It amd64 Ta Dv __amd64__, Dv __x86_64__
322 .It arm Ta Dv __arm__
323 .It armeb Ta Dv __arm__
324 .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
325 .It arm64 Ta Dv __aarch64__
326 .It i386 Ta Dv __i386__
327 .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
328 .It mipsel Ta Dv __mips__, Dv __mips_o32
329 .It mipselhf Ta Dv __mips__, Dv __mips_o32
330 .It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
331 .It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
332 .It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
333 .It mips64el Ta Dv __mips__, Dv __mips_n64
334 .It mips64elhf Ta Dv __mips__, Dv __mips_n64
335 .It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
336 .It powerpc Ta Dv __powerpc__
337 .It powerpcspe Ta Dv __powerpc__, Dv __SPE__
338 .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
339 .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
340 .It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
341 .It sparc64 Ta Dv __sparc64__
343 .Ss Important Xr make 1 variables
344 Most of the externally settable variables are defined in the
347 These variables are not otherwise documented and are used extensively
349 .Bl -column -offset indent "Sy Variable" "Sy Meaning and usage"
350 .It Dv MACHINE Represent the hardware platform.
351 This is the same as the native platform's
355 It defines both the userland / kernel interface, as well as the
356 bootloader / kernel interface.
357 It should only be used in these contexts.
358 Each CPU architecture may have multiple hardware platforms it supports
362 It is used to collect together all the files from
365 It is often the same as
367 just as one CPU architecture can be implemented by many different
368 hardware platforms, one hardware platform may support multiple CPU
369 architecture family members, though with different binaries.
372 of i386 supported the IBM-AT hardware platform while the
374 of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
376 Both of these hardware platforms supported only the
378 of i386 where they shared a common ABI, except for certain kernel /
379 userland interfaces relating to underlying hardware platform
380 differences in bus architecture, device enumeration and boot interface.
383 should only be used in src/sys and src/stand or in system imagers or
385 .It Dv MACHINE_ARCH Represents the CPU processor architecture.
386 This is the same as the native platforms
390 It defines the CPU instruction family supported.
391 It may also encode a variation in the byte ordering of multi-byte
393 It may also encode a variation in the size of the integer or pointer.
394 It may also encode a ISA revision.
395 It may also encode hard versus soft floating point ABI and usage.
396 It may also encode a variant ABI when the other factors do not
397 uniquely define the ABI (e.g., MIPS' n32 ABI).
400 defines the ABI used by the system.
401 For example, the MIPS CPU processor family supports 9 different
402 combinations encoding pointer size, endian and hard versus soft float (for
403 8 combinations) as well as N32 (which only ever had one variation of
405 Generally, the plain CPU name specifies the most common (or at least
406 first) variant of the CPU.
407 This is why mips and mips64 imply 'big endian' while 'arm' and 'armv7'
409 If we ever were to support the so-called x32 ABI (using 32-bit
410 pointers on the amd64 architecture), it would most likely be encoded
412 It is unfortunate that amd64 speifies the 64-bit evolution of the x86
413 platform (it matches the 'first rule') as everybody else uses x86_64.
414 There is no standard name for the processor: each OS selects its own
416 .It Dv MACHINE_CPUARCH Represents the source location for a given
420 is defined to be mips for all the flavors of mips that we support
421 since we support them all with a shared set of sources.
422 While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
424 The FreeBSD source base supports amd64 and i386 with two
425 distinct source bases living in subdirectories named amd64 and i386
426 (though behind the scenes there's some sharing that fits into this
428 .It Dv CPUTYPE Sets the flavor of
431 It is used to optimize the build for a specific CPU / core that the
433 Generally, this does not change the ABI, though it can be a fine line
434 between optimization for specific cases.
435 .It Dv TARGET Used to set
437 in the top level Makefile for cross building.
438 Unused outside of that scope.
439 It is not passed down to the rest of the build.
440 Makefiles outside of the top level should not use it at all (though
441 some have their own private copy for hysterical raisons).
442 .It Dv TARGET_ARCH Used to set
444 by the top level Makefile for cross building.
446 .Dv TARGET , it is unused outside of that scope.
454 manual page appeared in