1 //===----------------------------- Registers.hpp --------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is dual licensed under the MIT and the University of Illinois Open
6 // Source Licenses. See LICENSE.TXT for details.
9 // Models register sets for supported processors.
11 //===----------------------------------------------------------------------===//
13 #ifndef __REGISTERS_HPP__
14 #define __REGISTERS_HPP__
19 #include "libunwind.h"
24 // For emulating 128-bit registers
25 struct v128 { uint32_t vec[4]; };
28 #if defined(_LIBUNWIND_TARGET_I386)
29 /// Registers_x86 holds the register state of a thread in a 32-bit intel
31 class _LIBUNWIND_HIDDEN Registers_x86 {
34 Registers_x86(const void *registers);
36 bool validRegister(int num) const;
37 uint32_t getRegister(int num) const;
38 void setRegister(int num, uint32_t value);
39 bool validFloatRegister(int) const { return false; }
40 double getFloatRegister(int num) const;
41 void setFloatRegister(int num, double value);
42 bool validVectorRegister(int) const { return false; }
43 v128 getVectorRegister(int num) const;
44 void setVectorRegister(int num, v128 value);
45 const char *getRegisterName(int num);
47 static int lastDwarfRegNum() { return 8; }
49 uint32_t getSP() const { return _registers.__esp; }
50 void setSP(uint32_t value) { _registers.__esp = value; }
51 uint32_t getIP() const { return _registers.__eip; }
52 void setIP(uint32_t value) { _registers.__eip = value; }
53 uint32_t getEBP() const { return _registers.__ebp; }
54 void setEBP(uint32_t value) { _registers.__ebp = value; }
55 uint32_t getEBX() const { return _registers.__ebx; }
56 void setEBX(uint32_t value) { _registers.__ebx = value; }
57 uint32_t getECX() const { return _registers.__ecx; }
58 void setECX(uint32_t value) { _registers.__ecx = value; }
59 uint32_t getEDX() const { return _registers.__edx; }
60 void setEDX(uint32_t value) { _registers.__edx = value; }
61 uint32_t getESI() const { return _registers.__esi; }
62 void setESI(uint32_t value) { _registers.__esi = value; }
63 uint32_t getEDI() const { return _registers.__edi; }
64 void setEDI(uint32_t value) { _registers.__edi = value; }
77 unsigned int __eflags;
89 inline Registers_x86::Registers_x86(const void *registers) {
90 static_assert((check_fit<Registers_x86, unw_context_t>::does_fit),
91 "x86 registers do not fit into unw_context_t");
92 memcpy(&_registers, registers, sizeof(_registers));
95 inline Registers_x86::Registers_x86() {
96 memset(&_registers, 0, sizeof(_registers));
99 inline bool Registers_x86::validRegister(int regNum) const {
100 if (regNum == UNW_REG_IP)
102 if (regNum == UNW_REG_SP)
111 inline uint32_t Registers_x86::getRegister(int regNum) const {
114 return _registers.__eip;
116 return _registers.__esp;
118 return _registers.__eax;
120 return _registers.__ecx;
122 return _registers.__edx;
124 return _registers.__ebx;
126 return _registers.__ebp;
128 return _registers.__esp;
130 return _registers.__esi;
132 return _registers.__edi;
134 _LIBUNWIND_ABORT("unsupported x86 register");
137 inline void Registers_x86::setRegister(int regNum, uint32_t value) {
140 _registers.__eip = value;
143 _registers.__esp = value;
146 _registers.__eax = value;
149 _registers.__ecx = value;
152 _registers.__edx = value;
155 _registers.__ebx = value;
158 _registers.__ebp = value;
161 _registers.__esp = value;
164 _registers.__esi = value;
167 _registers.__edi = value;
170 _LIBUNWIND_ABORT("unsupported x86 register");
173 inline const char *Registers_x86::getRegisterName(int regNum) {
196 return "unknown register";
200 inline double Registers_x86::getFloatRegister(int) const {
201 _LIBUNWIND_ABORT("no x86 float registers");
204 inline void Registers_x86::setFloatRegister(int, double) {
205 _LIBUNWIND_ABORT("no x86 float registers");
208 inline v128 Registers_x86::getVectorRegister(int) const {
209 _LIBUNWIND_ABORT("no x86 vector registers");
212 inline void Registers_x86::setVectorRegister(int, v128) {
213 _LIBUNWIND_ABORT("no x86 vector registers");
215 #endif // _LIBUNWIND_TARGET_I386
218 #if defined(_LIBUNWIND_TARGET_X86_64)
219 /// Registers_x86_64 holds the register state of a thread in a 64-bit intel
221 class _LIBUNWIND_HIDDEN Registers_x86_64 {
224 Registers_x86_64(const void *registers);
226 bool validRegister(int num) const;
227 uint64_t getRegister(int num) const;
228 void setRegister(int num, uint64_t value);
229 bool validFloatRegister(int) const { return false; }
230 double getFloatRegister(int num) const;
231 void setFloatRegister(int num, double value);
232 bool validVectorRegister(int) const { return false; }
233 v128 getVectorRegister(int num) const;
234 void setVectorRegister(int num, v128 value);
235 const char *getRegisterName(int num);
237 static int lastDwarfRegNum() { return 16; }
239 uint64_t getSP() const { return _registers.__rsp; }
240 void setSP(uint64_t value) { _registers.__rsp = value; }
241 uint64_t getIP() const { return _registers.__rip; }
242 void setIP(uint64_t value) { _registers.__rip = value; }
243 uint64_t getRBP() const { return _registers.__rbp; }
244 void setRBP(uint64_t value) { _registers.__rbp = value; }
245 uint64_t getRBX() const { return _registers.__rbx; }
246 void setRBX(uint64_t value) { _registers.__rbx = value; }
247 uint64_t getR12() const { return _registers.__r12; }
248 void setR12(uint64_t value) { _registers.__r12 = value; }
249 uint64_t getR13() const { return _registers.__r13; }
250 void setR13(uint64_t value) { _registers.__r13 = value; }
251 uint64_t getR14() const { return _registers.__r14; }
252 void setR14(uint64_t value) { _registers.__r14 = value; }
253 uint64_t getR15() const { return _registers.__r15; }
254 void setR15(uint64_t value) { _registers.__r15 = value; }
283 inline Registers_x86_64::Registers_x86_64(const void *registers) {
284 static_assert((check_fit<Registers_x86_64, unw_context_t>::does_fit),
285 "x86_64 registers do not fit into unw_context_t");
286 memcpy(&_registers, registers, sizeof(_registers));
289 inline Registers_x86_64::Registers_x86_64() {
290 memset(&_registers, 0, sizeof(_registers));
293 inline bool Registers_x86_64::validRegister(int regNum) const {
294 if (regNum == UNW_REG_IP)
296 if (regNum == UNW_REG_SP)
305 inline uint64_t Registers_x86_64::getRegister(int regNum) const {
308 return _registers.__rip;
310 return _registers.__rsp;
312 return _registers.__rax;
314 return _registers.__rdx;
316 return _registers.__rcx;
318 return _registers.__rbx;
320 return _registers.__rsi;
322 return _registers.__rdi;
324 return _registers.__rbp;
326 return _registers.__rsp;
328 return _registers.__r8;
330 return _registers.__r9;
332 return _registers.__r10;
334 return _registers.__r11;
336 return _registers.__r12;
338 return _registers.__r13;
340 return _registers.__r14;
342 return _registers.__r15;
344 _LIBUNWIND_ABORT("unsupported x86_64 register");
347 inline void Registers_x86_64::setRegister(int regNum, uint64_t value) {
350 _registers.__rip = value;
353 _registers.__rsp = value;
356 _registers.__rax = value;
359 _registers.__rdx = value;
362 _registers.__rcx = value;
365 _registers.__rbx = value;
368 _registers.__rsi = value;
371 _registers.__rdi = value;
374 _registers.__rbp = value;
377 _registers.__rsp = value;
380 _registers.__r8 = value;
383 _registers.__r9 = value;
386 _registers.__r10 = value;
389 _registers.__r11 = value;
392 _registers.__r12 = value;
395 _registers.__r13 = value;
398 _registers.__r14 = value;
401 _registers.__r15 = value;
404 _LIBUNWIND_ABORT("unsupported x86_64 register");
407 inline const char *Registers_x86_64::getRegisterName(int regNum) {
446 return "unknown register";
450 inline double Registers_x86_64::getFloatRegister(int) const {
451 _LIBUNWIND_ABORT("no x86_64 float registers");
454 inline void Registers_x86_64::setFloatRegister(int, double) {
455 _LIBUNWIND_ABORT("no x86_64 float registers");
458 inline v128 Registers_x86_64::getVectorRegister(int) const {
459 _LIBUNWIND_ABORT("no x86_64 vector registers");
462 inline void Registers_x86_64::setVectorRegister(int, v128) {
463 _LIBUNWIND_ABORT("no x86_64 vector registers");
465 #endif // _LIBUNWIND_TARGET_X86_64
468 #if defined(_LIBUNWIND_TARGET_PPC)
469 /// Registers_ppc holds the register state of a thread in a 32-bit PowerPC
471 class _LIBUNWIND_HIDDEN Registers_ppc {
474 Registers_ppc(const void *registers);
476 bool validRegister(int num) const;
477 uint32_t getRegister(int num) const;
478 void setRegister(int num, uint32_t value);
479 bool validFloatRegister(int num) const;
480 double getFloatRegister(int num) const;
481 void setFloatRegister(int num, double value);
482 bool validVectorRegister(int num) const;
483 v128 getVectorRegister(int num) const;
484 void setVectorRegister(int num, v128 value);
485 const char *getRegisterName(int num);
487 static int lastDwarfRegNum() { return 112; }
489 uint64_t getSP() const { return _registers.__r1; }
490 void setSP(uint32_t value) { _registers.__r1 = value; }
491 uint64_t getIP() const { return _registers.__srr0; }
492 void setIP(uint32_t value) { _registers.__srr0 = value; }
495 struct ppc_thread_state_t {
496 unsigned int __srr0; /* Instruction address register (PC) */
497 unsigned int __srr1; /* Machine state register (supervisor) */
530 unsigned int __cr; /* Condition register */
531 unsigned int __xer; /* User's integer exception register */
532 unsigned int __lr; /* Link register */
533 unsigned int __ctr; /* Count register */
534 unsigned int __mq; /* MQ register (601 only) */
535 unsigned int __vrsave; /* Vector Save Register */
538 struct ppc_float_state_t {
541 unsigned int __fpscr_pad; /* fpscr is 64 bits, 32 bits of rubbish */
542 unsigned int __fpscr; /* floating point status register */
545 ppc_thread_state_t _registers;
546 ppc_float_state_t _floatRegisters;
547 v128 _vectorRegisters[32]; // offset 424
550 inline Registers_ppc::Registers_ppc(const void *registers) {
551 static_assert((check_fit<Registers_ppc, unw_context_t>::does_fit),
552 "ppc registers do not fit into unw_context_t");
553 memcpy(&_registers, static_cast<const uint8_t *>(registers),
555 static_assert(sizeof(ppc_thread_state_t) == 160,
556 "expected float register offset to be 160");
557 memcpy(&_floatRegisters,
558 static_cast<const uint8_t *>(registers) + sizeof(ppc_thread_state_t),
559 sizeof(_floatRegisters));
560 static_assert(sizeof(ppc_thread_state_t) + sizeof(ppc_float_state_t) == 424,
561 "expected vector register offset to be 424 bytes");
562 memcpy(_vectorRegisters,
563 static_cast<const uint8_t *>(registers) + sizeof(ppc_thread_state_t) +
564 sizeof(ppc_float_state_t),
565 sizeof(_vectorRegisters));
568 inline Registers_ppc::Registers_ppc() {
569 memset(&_registers, 0, sizeof(_registers));
570 memset(&_floatRegisters, 0, sizeof(_floatRegisters));
571 memset(&_vectorRegisters, 0, sizeof(_vectorRegisters));
574 inline bool Registers_ppc::validRegister(int regNum) const {
575 if (regNum == UNW_REG_IP)
577 if (regNum == UNW_REG_SP)
579 if (regNum == UNW_PPC_VRSAVE)
583 if (regNum <= UNW_PPC_R31)
585 if (regNum == UNW_PPC_MQ)
587 if (regNum == UNW_PPC_LR)
589 if (regNum == UNW_PPC_CTR)
591 if ((UNW_PPC_CR0 <= regNum) && (regNum <= UNW_PPC_CR7))
596 inline uint32_t Registers_ppc::getRegister(int regNum) const {
599 return _registers.__srr0;
601 return _registers.__r1;
603 return _registers.__r0;
605 return _registers.__r1;
607 return _registers.__r2;
609 return _registers.__r3;
611 return _registers.__r4;
613 return _registers.__r5;
615 return _registers.__r6;
617 return _registers.__r7;
619 return _registers.__r8;
621 return _registers.__r9;
623 return _registers.__r10;
625 return _registers.__r11;
627 return _registers.__r12;
629 return _registers.__r13;
631 return _registers.__r14;
633 return _registers.__r15;
635 return _registers.__r16;
637 return _registers.__r17;
639 return _registers.__r18;
641 return _registers.__r19;
643 return _registers.__r20;
645 return _registers.__r21;
647 return _registers.__r22;
649 return _registers.__r23;
651 return _registers.__r24;
653 return _registers.__r25;
655 return _registers.__r26;
657 return _registers.__r27;
659 return _registers.__r28;
661 return _registers.__r29;
663 return _registers.__r30;
665 return _registers.__r31;
667 return _registers.__lr;
669 return (_registers.__cr & 0xF0000000);
671 return (_registers.__cr & 0x0F000000);
673 return (_registers.__cr & 0x00F00000);
675 return (_registers.__cr & 0x000F0000);
677 return (_registers.__cr & 0x0000F000);
679 return (_registers.__cr & 0x00000F00);
681 return (_registers.__cr & 0x000000F0);
683 return (_registers.__cr & 0x0000000F);
685 return _registers.__vrsave;
687 _LIBUNWIND_ABORT("unsupported ppc register");
690 inline void Registers_ppc::setRegister(int regNum, uint32_t value) {
691 //fprintf(stderr, "Registers_ppc::setRegister(%d, 0x%08X)\n", regNum, value);
694 _registers.__srr0 = value;
697 _registers.__r1 = value;
700 _registers.__r0 = value;
703 _registers.__r1 = value;
706 _registers.__r2 = value;
709 _registers.__r3 = value;
712 _registers.__r4 = value;
715 _registers.__r5 = value;
718 _registers.__r6 = value;
721 _registers.__r7 = value;
724 _registers.__r8 = value;
727 _registers.__r9 = value;
730 _registers.__r10 = value;
733 _registers.__r11 = value;
736 _registers.__r12 = value;
739 _registers.__r13 = value;
742 _registers.__r14 = value;
745 _registers.__r15 = value;
748 _registers.__r16 = value;
751 _registers.__r17 = value;
754 _registers.__r18 = value;
757 _registers.__r19 = value;
760 _registers.__r20 = value;
763 _registers.__r21 = value;
766 _registers.__r22 = value;
769 _registers.__r23 = value;
772 _registers.__r24 = value;
775 _registers.__r25 = value;
778 _registers.__r26 = value;
781 _registers.__r27 = value;
784 _registers.__r28 = value;
787 _registers.__r29 = value;
790 _registers.__r30 = value;
793 _registers.__r31 = value;
796 _registers.__mq = value;
799 _registers.__lr = value;
802 _registers.__ctr = value;
805 _registers.__cr &= 0x0FFFFFFF;
806 _registers.__cr |= (value & 0xF0000000);
809 _registers.__cr &= 0xF0FFFFFF;
810 _registers.__cr |= (value & 0x0F000000);
813 _registers.__cr &= 0xFF0FFFFF;
814 _registers.__cr |= (value & 0x00F00000);
817 _registers.__cr &= 0xFFF0FFFF;
818 _registers.__cr |= (value & 0x000F0000);
821 _registers.__cr &= 0xFFFF0FFF;
822 _registers.__cr |= (value & 0x0000F000);
825 _registers.__cr &= 0xFFFFF0FF;
826 _registers.__cr |= (value & 0x00000F00);
829 _registers.__cr &= 0xFFFFFF0F;
830 _registers.__cr |= (value & 0x000000F0);
833 _registers.__cr &= 0xFFFFFFF0;
834 _registers.__cr |= (value & 0x0000000F);
837 _registers.__vrsave = value;
842 _registers.__xer = value;
846 case UNW_PPC_SPEFSCR:
850 _LIBUNWIND_ABORT("unsupported ppc register");
853 inline bool Registers_ppc::validFloatRegister(int regNum) const {
854 if (regNum < UNW_PPC_F0)
856 if (regNum > UNW_PPC_F31)
861 inline double Registers_ppc::getFloatRegister(int regNum) const {
862 assert(validFloatRegister(regNum));
863 return _floatRegisters.__fpregs[regNum - UNW_PPC_F0];
866 inline void Registers_ppc::setFloatRegister(int regNum, double value) {
867 assert(validFloatRegister(regNum));
868 _floatRegisters.__fpregs[regNum - UNW_PPC_F0] = value;
871 inline bool Registers_ppc::validVectorRegister(int regNum) const {
872 if (regNum < UNW_PPC_V0)
874 if (regNum > UNW_PPC_V31)
879 inline v128 Registers_ppc::getVectorRegister(int regNum) const {
880 assert(validVectorRegister(regNum));
881 v128 result = _vectorRegisters[regNum - UNW_PPC_V0];
885 inline void Registers_ppc::setVectorRegister(int regNum, v128 value) {
886 assert(validVectorRegister(regNum));
887 _vectorRegisters[regNum - UNW_PPC_V0] = value;
890 inline const char *Registers_ppc::getRegisterName(int regNum) {
1027 return "unknown register";
1031 #endif // _LIBUNWIND_TARGET_PPC
1034 #if defined(_LIBUNWIND_TARGET_AARCH64)
1035 /// Registers_arm64 holds the register state of a thread in a 64-bit arm
1037 class _LIBUNWIND_HIDDEN Registers_arm64 {
1040 Registers_arm64(const void *registers);
1042 bool validRegister(int num) const;
1043 uint64_t getRegister(int num) const;
1044 void setRegister(int num, uint64_t value);
1045 bool validFloatRegister(int num) const;
1046 double getFloatRegister(int num) const;
1047 void setFloatRegister(int num, double value);
1048 bool validVectorRegister(int num) const;
1049 v128 getVectorRegister(int num) const;
1050 void setVectorRegister(int num, v128 value);
1051 const char *getRegisterName(int num);
1053 static int lastDwarfRegNum() { return 95; }
1055 uint64_t getSP() const { return _registers.__sp; }
1056 void setSP(uint64_t value) { _registers.__sp = value; }
1057 uint64_t getIP() const { return _registers.__pc; }
1058 void setIP(uint64_t value) { _registers.__pc = value; }
1059 uint64_t getFP() const { return _registers.__fp; }
1060 void setFP(uint64_t value) { _registers.__fp = value; }
1064 uint64_t __x[29]; // x0-x28
1065 uint64_t __fp; // Frame pointer x29
1066 uint64_t __lr; // Link register x30
1067 uint64_t __sp; // Stack pointer x31
1068 uint64_t __pc; // Program counter
1069 uint64_t padding; // 16-byte align
1073 double _vectorHalfRegisters[32];
1074 // Currently only the lower double in 128-bit vectore registers
1075 // is perserved during unwinding. We could define new register
1076 // numbers (> 96) which mean whole vector registers, then this
1077 // struct would need to change to contain whole vector registers.
1080 inline Registers_arm64::Registers_arm64(const void *registers) {
1081 static_assert((check_fit<Registers_arm64, unw_context_t>::does_fit),
1082 "arm64 registers do not fit into unw_context_t");
1083 memcpy(&_registers, registers, sizeof(_registers));
1084 static_assert(sizeof(GPRs) == 0x110,
1085 "expected VFP registers to be at offset 272");
1086 memcpy(_vectorHalfRegisters,
1087 static_cast<const uint8_t *>(registers) + sizeof(GPRs),
1088 sizeof(_vectorHalfRegisters));
1091 inline Registers_arm64::Registers_arm64() {
1092 memset(&_registers, 0, sizeof(_registers));
1093 memset(&_vectorHalfRegisters, 0, sizeof(_vectorHalfRegisters));
1096 inline bool Registers_arm64::validRegister(int regNum) const {
1097 if (regNum == UNW_REG_IP)
1099 if (regNum == UNW_REG_SP)
1105 if ((regNum > 31) && (regNum < 64))
1110 inline uint64_t Registers_arm64::getRegister(int regNum) const {
1111 if (regNum == UNW_REG_IP)
1112 return _registers.__pc;
1113 if (regNum == UNW_REG_SP)
1114 return _registers.__sp;
1115 if ((regNum >= 0) && (regNum < 32))
1116 return _registers.__x[regNum];
1117 _LIBUNWIND_ABORT("unsupported arm64 register");
1120 inline void Registers_arm64::setRegister(int regNum, uint64_t value) {
1121 if (regNum == UNW_REG_IP)
1122 _registers.__pc = value;
1123 else if (regNum == UNW_REG_SP)
1124 _registers.__sp = value;
1125 else if ((regNum >= 0) && (regNum < 32))
1126 _registers.__x[regNum] = value;
1128 _LIBUNWIND_ABORT("unsupported arm64 register");
1131 inline const char *Registers_arm64::getRegisterName(int regNum) {
1266 return "unknown register";
1270 inline bool Registers_arm64::validFloatRegister(int regNum) const {
1271 if (regNum < UNW_ARM64_D0)
1273 if (regNum > UNW_ARM64_D31)
1278 inline double Registers_arm64::getFloatRegister(int regNum) const {
1279 assert(validFloatRegister(regNum));
1280 return _vectorHalfRegisters[regNum - UNW_ARM64_D0];
1283 inline void Registers_arm64::setFloatRegister(int regNum, double value) {
1284 assert(validFloatRegister(regNum));
1285 _vectorHalfRegisters[regNum - UNW_ARM64_D0] = value;
1288 inline bool Registers_arm64::validVectorRegister(int) const {
1292 inline v128 Registers_arm64::getVectorRegister(int) const {
1293 _LIBUNWIND_ABORT("no arm64 vector register support yet");
1296 inline void Registers_arm64::setVectorRegister(int, v128) {
1297 _LIBUNWIND_ABORT("no arm64 vector register support yet");
1299 #endif // _LIBUNWIND_TARGET_AARCH64
1301 #if defined(_LIBUNWIND_TARGET_ARM)
1302 /// Registers_arm holds the register state of a thread in a 32-bit arm
1305 /// NOTE: Assumes VFPv3. On ARM processors without a floating point unit,
1306 /// this uses more memory than required.
1307 class _LIBUNWIND_HIDDEN Registers_arm {
1310 Registers_arm(const void *registers);
1312 bool validRegister(int num) const;
1313 uint32_t getRegister(int num);
1314 void setRegister(int num, uint32_t value);
1315 bool validFloatRegister(int num) const;
1316 unw_fpreg_t getFloatRegister(int num);
1317 void setFloatRegister(int num, unw_fpreg_t value);
1318 bool validVectorRegister(int num) const;
1319 v128 getVectorRegister(int num) const;
1320 void setVectorRegister(int num, v128 value);
1321 const char *getRegisterName(int num);
1323 restoreSavedFloatRegisters();
1324 restoreCoreAndJumpTo();
1327 uint32_t getSP() const { return _registers.__sp; }
1328 void setSP(uint32_t value) { _registers.__sp = value; }
1329 uint32_t getIP() const { return _registers.__pc; }
1330 void setIP(uint32_t value) { _registers.__pc = value; }
1333 assert(_use_X_for_vfp_save || !_saved_vfp_d0_d15);
1334 _use_X_for_vfp_save = true;
1337 void restoreSavedFloatRegisters() {
1338 if (_saved_vfp_d0_d15) {
1339 if (_use_X_for_vfp_save)
1340 restoreVFPWithFLDMX(_vfp_d0_d15_pad);
1342 restoreVFPWithFLDMD(_vfp_d0_d15_pad);
1344 if (_saved_vfp_d16_d31)
1345 restoreVFPv3(_vfp_d16_d31);
1347 restoreiWMMX(_iwmmx);
1348 if (_saved_iwmmx_control)
1349 restoreiWMMXControl(_iwmmx_control);
1354 uint32_t __r[13]; // r0-r12
1355 uint32_t __sp; // Stack pointer r13
1356 uint32_t __lr; // Link register r14
1357 uint32_t __pc; // Program counter r15
1360 static void saveVFPWithFSTMD(unw_fpreg_t*);
1361 static void saveVFPWithFSTMX(unw_fpreg_t*);
1362 static void saveVFPv3(unw_fpreg_t*);
1363 static void saveiWMMX(unw_fpreg_t*);
1364 static void saveiWMMXControl(uint32_t*);
1365 static void restoreVFPWithFLDMD(unw_fpreg_t*);
1366 static void restoreVFPWithFLDMX(unw_fpreg_t*);
1367 static void restoreVFPv3(unw_fpreg_t*);
1368 static void restoreiWMMX(unw_fpreg_t*);
1369 static void restoreiWMMXControl(uint32_t*);
1370 void restoreCoreAndJumpTo();
1375 // We save floating point registers lazily because we can't know ahead of
1376 // time which ones are used. See EHABI #4.7.
1378 // Whether D0-D15 are saved in the FTSMX instead of FSTMD format.
1380 // See EHABI #7.5 that explains how matching instruction sequences for load
1381 // and store need to be used to correctly restore the exact register bits.
1382 bool _use_X_for_vfp_save;
1383 // Whether VFP D0-D15 are saved.
1384 bool _saved_vfp_d0_d15;
1385 // Whether VFPv3 D16-D31 are saved.
1386 bool _saved_vfp_d16_d31;
1387 // Whether iWMMX data registers are saved.
1389 // Whether iWMMX control registers are saved.
1390 bool _saved_iwmmx_control;
1391 // VFP registers D0-D15, + padding if saved using FSTMX
1392 unw_fpreg_t _vfp_d0_d15_pad[17];
1393 // VFPv3 registers D16-D31, always saved using FSTMD
1394 unw_fpreg_t _vfp_d16_d31[16];
1396 unw_fpreg_t _iwmmx[16];
1397 // iWMMX control registers
1398 uint32_t _iwmmx_control[4];
1401 inline Registers_arm::Registers_arm(const void *registers)
1402 : _use_X_for_vfp_save(false),
1403 _saved_vfp_d0_d15(false),
1404 _saved_vfp_d16_d31(false),
1405 _saved_iwmmx(false),
1406 _saved_iwmmx_control(false) {
1407 static_assert((check_fit<Registers_arm, unw_context_t>::does_fit),
1408 "arm registers do not fit into unw_context_t");
1409 // See unw_getcontext() note about data.
1410 memcpy(&_registers, registers, sizeof(_registers));
1411 memset(&_vfp_d0_d15_pad, 0, sizeof(_vfp_d0_d15_pad));
1412 memset(&_vfp_d16_d31, 0, sizeof(_vfp_d16_d31));
1413 memset(&_iwmmx, 0, sizeof(_iwmmx));
1414 memset(&_iwmmx_control, 0, sizeof(_iwmmx_control));
1417 inline Registers_arm::Registers_arm()
1418 : _use_X_for_vfp_save(false),
1419 _saved_vfp_d0_d15(false),
1420 _saved_vfp_d16_d31(false),
1421 _saved_iwmmx(false),
1422 _saved_iwmmx_control(false) {
1423 memset(&_registers, 0, sizeof(_registers));
1424 memset(&_vfp_d0_d15_pad, 0, sizeof(_vfp_d0_d15_pad));
1425 memset(&_vfp_d16_d31, 0, sizeof(_vfp_d16_d31));
1426 memset(&_iwmmx, 0, sizeof(_iwmmx));
1427 memset(&_iwmmx_control, 0, sizeof(_iwmmx_control));
1430 inline bool Registers_arm::validRegister(int regNum) const {
1431 // Returns true for all non-VFP registers supported by the EHABI
1432 // virtual register set (VRS).
1433 if (regNum == UNW_REG_IP)
1435 if (regNum == UNW_REG_SP)
1437 if (regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15)
1439 if (regNum >= UNW_ARM_WC0 && regNum <= UNW_ARM_WC3)
1444 inline uint32_t Registers_arm::getRegister(int regNum) {
1445 if (regNum == UNW_REG_SP || regNum == UNW_ARM_SP)
1446 return _registers.__sp;
1447 if (regNum == UNW_ARM_LR)
1448 return _registers.__lr;
1449 if (regNum == UNW_REG_IP || regNum == UNW_ARM_IP)
1450 return _registers.__pc;
1451 if (regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R12)
1452 return _registers.__r[regNum];
1453 if (regNum >= UNW_ARM_WC0 && regNum <= UNW_ARM_WC3) {
1454 if (!_saved_iwmmx_control) {
1455 _saved_iwmmx_control = true;
1456 saveiWMMXControl(_iwmmx_control);
1458 return _iwmmx_control[regNum - UNW_ARM_WC0];
1460 _LIBUNWIND_ABORT("unsupported arm register");
1463 inline void Registers_arm::setRegister(int regNum, uint32_t value) {
1464 if (regNum == UNW_REG_SP || regNum == UNW_ARM_SP)
1465 _registers.__sp = value;
1466 else if (regNum == UNW_ARM_LR)
1467 _registers.__lr = value;
1468 else if (regNum == UNW_REG_IP || regNum == UNW_ARM_IP)
1469 _registers.__pc = value;
1470 else if (regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R12)
1471 _registers.__r[regNum] = value;
1472 else if (regNum >= UNW_ARM_WC0 && regNum <= UNW_ARM_WC3) {
1473 if (!_saved_iwmmx_control) {
1474 _saved_iwmmx_control = true;
1475 saveiWMMXControl(_iwmmx_control);
1477 _iwmmx_control[regNum - UNW_ARM_WC0] = value;
1479 _LIBUNWIND_ABORT("unsupported arm register");
1482 inline const char *Registers_arm::getRegisterName(int regNum) {
1485 case UNW_ARM_IP: // UNW_ARM_R15 is alias
1487 case UNW_ARM_LR: // UNW_ARM_R14 is alias
1490 case UNW_ARM_SP: // UNW_ARM_R13 is alias
1647 return "unknown register";
1651 inline bool Registers_arm::validFloatRegister(int regNum) const {
1652 // NOTE: Consider the intel MMX registers floating points so the
1653 // unw_get_fpreg can be used to transmit the 64-bit data back.
1654 return ((regNum >= UNW_ARM_D0) && (regNum <= UNW_ARM_D31))
1655 || ((regNum >= UNW_ARM_WR0) && (regNum <= UNW_ARM_WR15));
1658 inline unw_fpreg_t Registers_arm::getFloatRegister(int regNum) {
1659 if (regNum >= UNW_ARM_D0 && regNum <= UNW_ARM_D15) {
1660 if (!_saved_vfp_d0_d15) {
1661 _saved_vfp_d0_d15 = true;
1662 if (_use_X_for_vfp_save)
1663 saveVFPWithFSTMX(_vfp_d0_d15_pad);
1665 saveVFPWithFSTMD(_vfp_d0_d15_pad);
1667 return _vfp_d0_d15_pad[regNum - UNW_ARM_D0];
1668 } else if (regNum >= UNW_ARM_D16 && regNum <= UNW_ARM_D31) {
1669 if (!_saved_vfp_d16_d31) {
1670 _saved_vfp_d16_d31 = true;
1671 saveVFPv3(_vfp_d16_d31);
1673 return _vfp_d16_d31[regNum - UNW_ARM_D16];
1674 } else if (regNum >= UNW_ARM_WR0 && regNum <= UNW_ARM_WR15) {
1675 if (!_saved_iwmmx) {
1676 _saved_iwmmx = true;
1679 return _iwmmx[regNum - UNW_ARM_WR0];
1681 _LIBUNWIND_ABORT("Unknown ARM float register");
1685 inline void Registers_arm::setFloatRegister(int regNum, unw_fpreg_t value) {
1686 if (regNum >= UNW_ARM_D0 && regNum <= UNW_ARM_D15) {
1687 if (!_saved_vfp_d0_d15) {
1688 _saved_vfp_d0_d15 = true;
1689 if (_use_X_for_vfp_save)
1690 saveVFPWithFSTMX(_vfp_d0_d15_pad);
1692 saveVFPWithFSTMD(_vfp_d0_d15_pad);
1694 _vfp_d0_d15_pad[regNum - UNW_ARM_D0] = value;
1695 } else if (regNum >= UNW_ARM_D16 && regNum <= UNW_ARM_D31) {
1696 if (!_saved_vfp_d16_d31) {
1697 _saved_vfp_d16_d31 = true;
1698 saveVFPv3(_vfp_d16_d31);
1700 _vfp_d16_d31[regNum - UNW_ARM_D16] = value;
1701 } else if (regNum >= UNW_ARM_WR0 && regNum <= UNW_ARM_WR15) {
1702 if (!_saved_iwmmx) {
1703 _saved_iwmmx = true;
1706 _iwmmx[regNum - UNW_ARM_WR0] = value;
1708 _LIBUNWIND_ABORT("Unknown ARM float register");
1712 inline bool Registers_arm::validVectorRegister(int) const {
1716 inline v128 Registers_arm::getVectorRegister(int) const {
1717 _LIBUNWIND_ABORT("ARM vector support not implemented");
1720 inline void Registers_arm::setVectorRegister(int, v128) {
1721 _LIBUNWIND_ABORT("ARM vector support not implemented");
1723 #endif // _LIBUNWIND_TARGET_ARM
1726 #if defined(_LIBUNWIND_TARGET_OR1K)
1727 /// Registers_or1k holds the register state of a thread in an OpenRISC1000
1729 class _LIBUNWIND_HIDDEN Registers_or1k {
1732 Registers_or1k(const void *registers);
1734 bool validRegister(int num) const;
1735 uint32_t getRegister(int num) const;
1736 void setRegister(int num, uint32_t value);
1737 bool validFloatRegister(int num) const;
1738 double getFloatRegister(int num) const;
1739 void setFloatRegister(int num, double value);
1740 bool validVectorRegister(int num) const;
1741 v128 getVectorRegister(int num) const;
1742 void setVectorRegister(int num, v128 value);
1743 const char *getRegisterName(int num);
1745 static int lastDwarfRegNum() { return 31; }
1747 uint64_t getSP() const { return _registers.__r[1]; }
1748 void setSP(uint32_t value) { _registers.__r[1] = value; }
1749 uint64_t getIP() const { return _registers.__r[9]; }
1750 void setIP(uint32_t value) { _registers.__r[9] = value; }
1753 struct or1k_thread_state_t {
1754 unsigned int __r[32];
1757 or1k_thread_state_t _registers;
1760 inline Registers_or1k::Registers_or1k(const void *registers) {
1761 static_assert((check_fit<Registers_or1k, unw_context_t>::does_fit),
1762 "or1k registers do not fit into unw_context_t");
1763 memcpy(&_registers, static_cast<const uint8_t *>(registers),
1764 sizeof(_registers));
1767 inline Registers_or1k::Registers_or1k() {
1768 memset(&_registers, 0, sizeof(_registers));
1771 inline bool Registers_or1k::validRegister(int regNum) const {
1772 if (regNum == UNW_REG_IP)
1774 if (regNum == UNW_REG_SP)
1778 if (regNum <= UNW_OR1K_R31)
1783 inline uint32_t Registers_or1k::getRegister(int regNum) const {
1784 if (regNum >= UNW_OR1K_R0 && regNum <= UNW_OR1K_R31)
1785 return _registers.__r[regNum - UNW_OR1K_R0];
1789 return _registers.__r[9];
1791 return _registers.__r[1];
1793 _LIBUNWIND_ABORT("unsupported or1k register");
1796 inline void Registers_or1k::setRegister(int regNum, uint32_t value) {
1797 if (regNum >= UNW_OR1K_R0 && regNum <= UNW_OR1K_R31) {
1798 _registers.__r[regNum - UNW_OR1K_R0] = value;
1804 _registers.__r[9] = value;
1807 _registers.__r[1] = value;
1810 _LIBUNWIND_ABORT("unsupported or1k register");
1813 inline bool Registers_or1k::validFloatRegister(int /* regNum */) const {
1817 inline double Registers_or1k::getFloatRegister(int /* regNum */) const {
1818 _LIBUNWIND_ABORT("or1k float support not implemented");
1821 inline void Registers_or1k::setFloatRegister(int /* regNum */,
1822 double /* value */) {
1823 _LIBUNWIND_ABORT("or1k float support not implemented");
1826 inline bool Registers_or1k::validVectorRegister(int /* regNum */) const {
1830 inline v128 Registers_or1k::getVectorRegister(int /* regNum */) const {
1831 _LIBUNWIND_ABORT("or1k vector support not implemented");
1834 inline void Registers_or1k::setVectorRegister(int /* regNum */, v128 /* value */) {
1835 _LIBUNWIND_ABORT("or1k vector support not implemented");
1838 inline const char *Registers_or1k::getRegisterName(int regNum) {
1905 return "unknown register";
1909 #endif // _LIBUNWIND_TARGET_OR1K
1912 #if defined(_LIBUNWIND_TARGET_RISCV)
1913 /// Registers_riscv holds the register state of a thread in a 64-bit RISC-V
1915 class _LIBUNWIND_HIDDEN Registers_riscv {
1918 Registers_riscv(const void *registers);
1920 bool validRegister(int num) const;
1921 uint64_t getRegister(int num) const;
1922 void setRegister(int num, uint64_t value);
1923 bool validFloatRegister(int num) const;
1924 double getFloatRegister(int num) const;
1925 void setFloatRegister(int num, double value);
1926 bool validVectorRegister(int num) const;
1927 v128 getVectorRegister(int num) const;
1928 void setVectorRegister(int num, v128 value);
1929 const char *getRegisterName(int num);
1931 static int lastDwarfRegNum() { return 95; }
1933 uint64_t getSP() const { return _registers.__x[2]; }
1934 void setSP(uint64_t value) { _registers.__x[2] = value; }
1935 uint64_t getIP() const { return _registers.__x[1]; }
1936 void setIP(uint64_t value) { _registers.__x[1] = value; }
1940 uint64_t __x[32]; // x0-x31
1944 double _vectorHalfRegisters[32];
1945 // Currently only the lower double in 128-bit vectore registers
1946 // is perserved during unwinding. We could define new register
1947 // numbers (> 96) which mean whole vector registers, then this
1948 // struct would need to change to contain whole vector registers.
1951 inline Registers_riscv::Registers_riscv(const void *registers) {
1952 static_assert((check_fit<Registers_riscv, unw_context_t>::does_fit),
1953 "riscv registers do not fit into unw_context_t");
1954 memcpy(&_registers, registers, sizeof(_registers));
1955 static_assert(sizeof(GPRs) == 0x100,
1956 "expected VFP registers to be at offset 256");
1957 memcpy(_vectorHalfRegisters,
1958 static_cast<const uint8_t *>(registers) + sizeof(GPRs),
1959 sizeof(_vectorHalfRegisters));
1962 inline Registers_riscv::Registers_riscv() {
1963 memset(&_registers, 0, sizeof(_registers));
1964 memset(&_vectorHalfRegisters, 0, sizeof(_vectorHalfRegisters));
1967 inline bool Registers_riscv::validRegister(int regNum) const {
1968 if (regNum == UNW_REG_IP)
1970 if (regNum == UNW_REG_SP)
1976 if ((regNum > 31) && (regNum < 64))
1981 inline uint64_t Registers_riscv::getRegister(int regNum) const {
1982 if (regNum == UNW_REG_IP)
1983 return _registers.__x[1];
1984 if (regNum == UNW_REG_SP)
1985 return _registers.__x[2];
1986 if ((regNum >= 0) && (regNum < 32))
1987 return _registers.__x[regNum];
1988 _LIBUNWIND_ABORT("unsupported riscv register");
1991 inline void Registers_riscv::setRegister(int regNum, uint64_t value) {
1992 if (regNum == UNW_REG_IP)
1993 _registers.__x[1] = value;
1994 else if (regNum == UNW_REG_SP)
1995 _registers.__x[2] = value;
1996 else if ((regNum >= 0) && (regNum < 32))
1997 _registers.__x[regNum] = value;
1999 _LIBUNWIND_ABORT("unsupported riscv register");
2002 inline const char *Registers_riscv::getRegisterName(int regNum) {
2137 return "unknown register";
2141 inline bool Registers_riscv::validFloatRegister(int regNum) const {
2142 if (regNum < UNW_RISCV_D0)
2144 if (regNum > UNW_RISCV_D31)
2149 inline double Registers_riscv::getFloatRegister(int regNum) const {
2150 assert(validFloatRegister(regNum));
2151 return _vectorHalfRegisters[regNum - UNW_RISCV_D0];
2154 inline void Registers_riscv::setFloatRegister(int regNum, double value) {
2155 assert(validFloatRegister(regNum));
2156 _vectorHalfRegisters[regNum - UNW_RISCV_D0] = value;
2159 inline bool Registers_riscv::validVectorRegister(int) const {
2163 inline v128 Registers_riscv::getVectorRegister(int) const {
2164 _LIBUNWIND_ABORT("no riscv vector register support yet");
2167 inline void Registers_riscv::setVectorRegister(int, v128) {
2168 _LIBUNWIND_ABORT("no riscv vector register support yet");
2170 #endif // _LIBUNWIND_TARGET_RISCV
2171 } // namespace libunwind
2173 #endif // __REGISTERS_HPP__